projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: FBC_CONTROL2 is gen4 only
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
101 u32 fbc_ctl;
102
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113
114 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
116 I915_WRITE(FBC_TAG + (i * 4), 0);
117
118 if (IS_GEN4(dev)) {
119 u32 fbc_ctl2;
120
121 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane;
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 }
127
128 /* enable it... */
129 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
139 }
140
141 static bool i8xx_fbc_enabled(struct drm_device *dev)
142 {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146 }
147
148 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
149 {
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_framebuffer *fb = crtc->fb;
153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
156 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
157 unsigned long stall_watermark = 200;
158 u32 dpfc_ctl;
159
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163
164 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
165 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
166 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
167 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
168
169 /* enable it... */
170 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
171
172 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
173 }
174
175 static void g4x_disable_fbc(struct drm_device *dev)
176 {
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 dpfc_ctl;
179
180 /* Disable compression */
181 dpfc_ctl = I915_READ(DPFC_CONTROL);
182 if (dpfc_ctl & DPFC_CTL_EN) {
183 dpfc_ctl &= ~DPFC_CTL_EN;
184 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
185
186 DRM_DEBUG_KMS("disabled FBC\n");
187 }
188 }
189
190 static bool g4x_fbc_enabled(struct drm_device *dev)
191 {
192 struct drm_i915_private *dev_priv = dev->dev_private;
193
194 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
195 }
196
197 static void sandybridge_blit_fbc_update(struct drm_device *dev)
198 {
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 u32 blt_ecoskpd;
201
202 /* Make sure blitter notifies FBC of writes */
203
204 /* Blitter is part of Media powerwell on VLV. No impact of
205 * his param in other platforms for now */
206 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
207
208 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
209 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
210 GEN6_BLITTER_LOCK_SHIFT;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
213 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
214 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
215 GEN6_BLITTER_LOCK_SHIFT);
216 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
217 POSTING_READ(GEN6_BLITTER_ECOSKPD);
218
219 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
220 }
221
222 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
223 {
224 struct drm_device *dev = crtc->dev;
225 struct drm_i915_private *dev_priv = dev->dev_private;
226 struct drm_framebuffer *fb = crtc->fb;
227 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
228 struct drm_i915_gem_object *obj = intel_fb->obj;
229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
230 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
231 unsigned long stall_watermark = 200;
232 u32 dpfc_ctl;
233
234 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
235 dpfc_ctl &= DPFC_RESERVED;
236 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
237 /* Set persistent mode for front-buffer rendering, ala X. */
238 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
239 dpfc_ctl |= DPFC_CTL_FENCE_EN;
240 if (IS_GEN5(dev))
241 dpfc_ctl |= obj->fence_reg;
242 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
243
244 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
245 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
246 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
260 }
261
262 static void ironlake_disable_fbc(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275 }
276
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282 }
283
284 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
285 {
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->fb;
289 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
290 struct drm_i915_gem_object *obj = intel_fb->obj;
291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
292
293 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
294
295 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
296 IVB_DPFC_CTL_FENCE_EN |
297 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
298
299 if (IS_IVYBRIDGE(dev)) {
300 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
301 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
302 } else {
303 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
304 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
305 HSW_BYPASS_FBC_QUEUE);
306 }
307
308 I915_WRITE(SNB_DPFC_CTL_SA,
309 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
310 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
311
312 sandybridge_blit_fbc_update(dev);
313
314 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
315 }
316
317 bool intel_fbc_enabled(struct drm_device *dev)
318 {
319 struct drm_i915_private *dev_priv = dev->dev_private;
320
321 if (!dev_priv->display.fbc_enabled)
322 return false;
323
324 return dev_priv->display.fbc_enabled(dev);
325 }
326
327 static void intel_fbc_work_fn(struct work_struct *__work)
328 {
329 struct intel_fbc_work *work =
330 container_of(to_delayed_work(__work),
331 struct intel_fbc_work, work);
332 struct drm_device *dev = work->crtc->dev;
333 struct drm_i915_private *dev_priv = dev->dev_private;
334
335 mutex_lock(&dev->struct_mutex);
336 if (work == dev_priv->fbc.fbc_work) {
337 /* Double check that we haven't switched fb without cancelling
338 * the prior work.
339 */
340 if (work->crtc->fb == work->fb) {
341 dev_priv->display.enable_fbc(work->crtc,
342 work->interval);
343
344 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
345 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
346 dev_priv->fbc.y = work->crtc->y;
347 }
348
349 dev_priv->fbc.fbc_work = NULL;
350 }
351 mutex_unlock(&dev->struct_mutex);
352
353 kfree(work);
354 }
355
356 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
357 {
358 if (dev_priv->fbc.fbc_work == NULL)
359 return;
360
361 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
362
363 /* Synchronisation is provided by struct_mutex and checking of
364 * dev_priv->fbc.fbc_work, so we can perform the cancellation
365 * entirely asynchronously.
366 */
367 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
368 /* tasklet was killed before being run, clean up */
369 kfree(dev_priv->fbc.fbc_work);
370
371 /* Mark the work as no longer wanted so that if it does
372 * wake-up (because the work was already running and waiting
373 * for our mutex), it will discover that is no longer
374 * necessary to run.
375 */
376 dev_priv->fbc.fbc_work = NULL;
377 }
378
379 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
380 {
381 struct intel_fbc_work *work;
382 struct drm_device *dev = crtc->dev;
383 struct drm_i915_private *dev_priv = dev->dev_private;
384
385 if (!dev_priv->display.enable_fbc)
386 return;
387
388 intel_cancel_fbc_work(dev_priv);
389
390 work = kzalloc(sizeof(*work), GFP_KERNEL);
391 if (work == NULL) {
392 DRM_ERROR("Failed to allocate FBC work structure\n");
393 dev_priv->display.enable_fbc(crtc, interval);
394 return;
395 }
396
397 work->crtc = crtc;
398 work->fb = crtc->fb;
399 work->interval = interval;
400 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
401
402 dev_priv->fbc.fbc_work = work;
403
404 /* Delay the actual enabling to let pageflipping cease and the
405 * display to settle before starting the compression. Note that
406 * this delay also serves a second purpose: it allows for a
407 * vblank to pass after disabling the FBC before we attempt
408 * to modify the control registers.
409 *
410 * A more complicated solution would involve tracking vblanks
411 * following the termination of the page-flipping sequence
412 * and indeed performing the enable as a co-routine and not
413 * waiting synchronously upon the vblank.
414 *
415 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
416 */
417 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
418 }
419
420 void intel_disable_fbc(struct drm_device *dev)
421 {
422 struct drm_i915_private *dev_priv = dev->dev_private;
423
424 intel_cancel_fbc_work(dev_priv);
425
426 if (!dev_priv->display.disable_fbc)
427 return;
428
429 dev_priv->display.disable_fbc(dev);
430 dev_priv->fbc.plane = -1;
431 }
432
433 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
434 enum no_fbc_reason reason)
435 {
436 if (dev_priv->fbc.no_fbc_reason == reason)
437 return false;
438
439 dev_priv->fbc.no_fbc_reason = reason;
440 return true;
441 }
442
443 /**
444 * intel_update_fbc - enable/disable FBC as needed
445 * @dev: the drm_device
446 *
447 * Set up the framebuffer compression hardware at mode set time. We
448 * enable it if possible:
449 * - plane A only (on pre-965)
450 * - no pixel mulitply/line duplication
451 * - no alpha buffer discard
452 * - no dual wide
453 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
454 *
455 * We can't assume that any compression will take place (worst case),
456 * so the compressed buffer has to be the same size as the uncompressed
457 * one. It also must reside (along with the line length buffer) in
458 * stolen memory.
459 *
460 * We need to enable/disable FBC on a global basis.
461 */
462 void intel_update_fbc(struct drm_device *dev)
463 {
464 struct drm_i915_private *dev_priv = dev->dev_private;
465 struct drm_crtc *crtc = NULL, *tmp_crtc;
466 struct intel_crtc *intel_crtc;
467 struct drm_framebuffer *fb;
468 struct intel_framebuffer *intel_fb;
469 struct drm_i915_gem_object *obj;
470 const struct drm_display_mode *adjusted_mode;
471 unsigned int max_width, max_height;
472
473 if (!I915_HAS_FBC(dev)) {
474 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
475 return;
476 }
477
478 if (!i915_powersave) {
479 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
480 DRM_DEBUG_KMS("fbc disabled per module param\n");
481 return;
482 }
483
484 /*
485 * If FBC is already on, we just have to verify that we can
486 * keep it that way...
487 * Need to disable if:
488 * - more than one pipe is active
489 * - changing FBC params (stride, fence, mode)
490 * - new fb is too large to fit in compressed buffer
491 * - going to an unsupported config (interlace, pixel multiply, etc.)
492 */
493 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
494 if (intel_crtc_active(tmp_crtc) &&
495 to_intel_crtc(tmp_crtc)->primary_enabled) {
496 if (crtc) {
497 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
498 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
499 goto out_disable;
500 }
501 crtc = tmp_crtc;
502 }
503 }
504
505 if (!crtc || crtc->fb == NULL) {
506 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
507 DRM_DEBUG_KMS("no output, disabling\n");
508 goto out_disable;
509 }
510
511 intel_crtc = to_intel_crtc(crtc);
512 fb = crtc->fb;
513 intel_fb = to_intel_framebuffer(fb);
514 obj = intel_fb->obj;
515 adjusted_mode = &intel_crtc->config.adjusted_mode;
516
517 if (i915_enable_fbc < 0 &&
518 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
519 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
520 DRM_DEBUG_KMS("disabled per chip default\n");
521 goto out_disable;
522 }
523 if (!i915_enable_fbc) {
524 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
525 DRM_DEBUG_KMS("fbc disabled per module param\n");
526 goto out_disable;
527 }
528 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
529 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
530 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
531 DRM_DEBUG_KMS("mode incompatible with compression, "
532 "disabling\n");
533 goto out_disable;
534 }
535
536 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
537 max_width = 4096;
538 max_height = 2048;
539 } else {
540 max_width = 2048;
541 max_height = 1536;
542 }
543 if (intel_crtc->config.pipe_src_w > max_width ||
544 intel_crtc->config.pipe_src_h > max_height) {
545 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
546 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
547 goto out_disable;
548 }
549 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
550 intel_crtc->plane != PLANE_A) {
551 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
552 DRM_DEBUG_KMS("plane not A, disabling compression\n");
553 goto out_disable;
554 }
555
556 /* The use of a CPU fence is mandatory in order to detect writes
557 * by the CPU to the scanout and trigger updates to the FBC.
558 */
559 if (obj->tiling_mode != I915_TILING_X ||
560 obj->fence_reg == I915_FENCE_REG_NONE) {
561 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
562 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
563 goto out_disable;
564 }
565
566 /* If the kernel debugger is active, always disable compression */
567 if (in_dbg_master())
568 goto out_disable;
569
570 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
571 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
572 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
573 goto out_disable;
574 }
575
576 /* If the scanout has not changed, don't modify the FBC settings.
577 * Note that we make the fundamental assumption that the fb->obj
578 * cannot be unpinned (and have its GTT offset and fence revoked)
579 * without first being decoupled from the scanout and FBC disabled.
580 */
581 if (dev_priv->fbc.plane == intel_crtc->plane &&
582 dev_priv->fbc.fb_id == fb->base.id &&
583 dev_priv->fbc.y == crtc->y)
584 return;
585
586 if (intel_fbc_enabled(dev)) {
587 /* We update FBC along two paths, after changing fb/crtc
588 * configuration (modeswitching) and after page-flipping
589 * finishes. For the latter, we know that not only did
590 * we disable the FBC at the start of the page-flip
591 * sequence, but also more than one vblank has passed.
592 *
593 * For the former case of modeswitching, it is possible
594 * to switch between two FBC valid configurations
595 * instantaneously so we do need to disable the FBC
596 * before we can modify its control registers. We also
597 * have to wait for the next vblank for that to take
598 * effect. However, since we delay enabling FBC we can
599 * assume that a vblank has passed since disabling and
600 * that we can safely alter the registers in the deferred
601 * callback.
602 *
603 * In the scenario that we go from a valid to invalid
604 * and then back to valid FBC configuration we have
605 * no strict enforcement that a vblank occurred since
606 * disabling the FBC. However, along all current pipe
607 * disabling paths we do need to wait for a vblank at
608 * some point. And we wait before enabling FBC anyway.
609 */
610 DRM_DEBUG_KMS("disabling active FBC for update\n");
611 intel_disable_fbc(dev);
612 }
613
614 intel_enable_fbc(crtc, 500);
615 dev_priv->fbc.no_fbc_reason = FBC_OK;
616 return;
617
618 out_disable:
619 /* Multiple disables should be harmless */
620 if (intel_fbc_enabled(dev)) {
621 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
622 intel_disable_fbc(dev);
623 }
624 i915_gem_stolen_cleanup_compression(dev);
625 }
626
627 static void i915_pineview_get_mem_freq(struct drm_device *dev)
628 {
629 drm_i915_private_t *dev_priv = dev->dev_private;
630 u32 tmp;
631
632 tmp = I915_READ(CLKCFG);
633
634 switch (tmp & CLKCFG_FSB_MASK) {
635 case CLKCFG_FSB_533:
636 dev_priv->fsb_freq = 533; /* 133*4 */
637 break;
638 case CLKCFG_FSB_800:
639 dev_priv->fsb_freq = 800; /* 200*4 */
640 break;
641 case CLKCFG_FSB_667:
642 dev_priv->fsb_freq = 667; /* 167*4 */
643 break;
644 case CLKCFG_FSB_400:
645 dev_priv->fsb_freq = 400; /* 100*4 */
646 break;
647 }
648
649 switch (tmp & CLKCFG_MEM_MASK) {
650 case CLKCFG_MEM_533:
651 dev_priv->mem_freq = 533;
652 break;
653 case CLKCFG_MEM_667:
654 dev_priv->mem_freq = 667;
655 break;
656 case CLKCFG_MEM_800:
657 dev_priv->mem_freq = 800;
658 break;
659 }
660
661 /* detect pineview DDR3 setting */
662 tmp = I915_READ(CSHRDDR3CTL);
663 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
664 }
665
666 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
667 {
668 drm_i915_private_t *dev_priv = dev->dev_private;
669 u16 ddrpll, csipll;
670
671 ddrpll = I915_READ16(DDRMPLL1);
672 csipll = I915_READ16(CSIPLL0);
673
674 switch (ddrpll & 0xff) {
675 case 0xc:
676 dev_priv->mem_freq = 800;
677 break;
678 case 0x10:
679 dev_priv->mem_freq = 1066;
680 break;
681 case 0x14:
682 dev_priv->mem_freq = 1333;
683 break;
684 case 0x18:
685 dev_priv->mem_freq = 1600;
686 break;
687 default:
688 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
689 ddrpll & 0xff);
690 dev_priv->mem_freq = 0;
691 break;
692 }
693
694 dev_priv->ips.r_t = dev_priv->mem_freq;
695
696 switch (csipll & 0x3ff) {
697 case 0x00c:
698 dev_priv->fsb_freq = 3200;
699 break;
700 case 0x00e:
701 dev_priv->fsb_freq = 3733;
702 break;
703 case 0x010:
704 dev_priv->fsb_freq = 4266;
705 break;
706 case 0x012:
707 dev_priv->fsb_freq = 4800;
708 break;
709 case 0x014:
710 dev_priv->fsb_freq = 5333;
711 break;
712 case 0x016:
713 dev_priv->fsb_freq = 5866;
714 break;
715 case 0x018:
716 dev_priv->fsb_freq = 6400;
717 break;
718 default:
719 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
720 csipll & 0x3ff);
721 dev_priv->fsb_freq = 0;
722 break;
723 }
724
725 if (dev_priv->fsb_freq == 3200) {
726 dev_priv->ips.c_m = 0;
727 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
728 dev_priv->ips.c_m = 1;
729 } else {
730 dev_priv->ips.c_m = 2;
731 }
732 }
733
734 static const struct cxsr_latency cxsr_latency_table[] = {
735 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
736 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
737 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
738 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
739 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
740
741 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
742 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
743 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
744 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
745 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
746
747 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
748 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
749 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
750 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
751 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
752
753 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
754 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
755 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
756 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
757 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
758
759 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
760 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
761 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
762 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
763 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
764
765 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
766 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
767 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
768 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
769 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
770 };
771
772 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
773 int is_ddr3,
774 int fsb,
775 int mem)
776 {
777 const struct cxsr_latency *latency;
778 int i;
779
780 if (fsb == 0 || mem == 0)
781 return NULL;
782
783 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
784 latency = &cxsr_latency_table[i];
785 if (is_desktop == latency->is_desktop &&
786 is_ddr3 == latency->is_ddr3 &&
787 fsb == latency->fsb_freq && mem == latency->mem_freq)
788 return latency;
789 }
790
791 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
792
793 return NULL;
794 }
795
796 static void pineview_disable_cxsr(struct drm_device *dev)
797 {
798 struct drm_i915_private *dev_priv = dev->dev_private;
799
800 /* deactivate cxsr */
801 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
802 }
803
804 /*
805 * Latency for FIFO fetches is dependent on several factors:
806 * - memory configuration (speed, channels)
807 * - chipset
808 * - current MCH state
809 * It can be fairly high in some situations, so here we assume a fairly
810 * pessimal value. It's a tradeoff between extra memory fetches (if we
811 * set this value too high, the FIFO will fetch frequently to stay full)
812 * and power consumption (set it too low to save power and we might see
813 * FIFO underruns and display "flicker").
814 *
815 * A value of 5us seems to be a good balance; safe for very low end
816 * platforms but not overly aggressive on lower latency configs.
817 */
818 static const int latency_ns = 5000;
819
820 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
821 {
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t dsparb = I915_READ(DSPARB);
824 int size;
825
826 size = dsparb & 0x7f;
827 if (plane)
828 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
829
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
832
833 return size;
834 }
835
836 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
837 {
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
840 int size;
841
842 size = dsparb & 0x1ff;
843 if (plane)
844 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
845 size >>= 1; /* Convert to cachelines */
846
847 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
848 plane ? "B" : "A", size);
849
850 return size;
851 }
852
853 static int i845_get_fifo_size(struct drm_device *dev, int plane)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 uint32_t dsparb = I915_READ(DSPARB);
857 int size;
858
859 size = dsparb & 0x7f;
860 size >>= 2; /* Convert to cachelines */
861
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
863 plane ? "B" : "A",
864 size);
865
866 return size;
867 }
868
869 static int i830_get_fifo_size(struct drm_device *dev, int plane)
870 {
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 uint32_t dsparb = I915_READ(DSPARB);
873 int size;
874
875 size = dsparb & 0x7f;
876 size >>= 1; /* Convert to cachelines */
877
878 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
879 plane ? "B" : "A", size);
880
881 return size;
882 }
883
884 /* Pineview has different values for various configs */
885 static const struct intel_watermark_params pineview_display_wm = {
886 PINEVIEW_DISPLAY_FIFO,
887 PINEVIEW_MAX_WM,
888 PINEVIEW_DFT_WM,
889 PINEVIEW_GUARD_WM,
890 PINEVIEW_FIFO_LINE_SIZE
891 };
892 static const struct intel_watermark_params pineview_display_hplloff_wm = {
893 PINEVIEW_DISPLAY_FIFO,
894 PINEVIEW_MAX_WM,
895 PINEVIEW_DFT_HPLLOFF_WM,
896 PINEVIEW_GUARD_WM,
897 PINEVIEW_FIFO_LINE_SIZE
898 };
899 static const struct intel_watermark_params pineview_cursor_wm = {
900 PINEVIEW_CURSOR_FIFO,
901 PINEVIEW_CURSOR_MAX_WM,
902 PINEVIEW_CURSOR_DFT_WM,
903 PINEVIEW_CURSOR_GUARD_WM,
904 PINEVIEW_FIFO_LINE_SIZE,
905 };
906 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
907 PINEVIEW_CURSOR_FIFO,
908 PINEVIEW_CURSOR_MAX_WM,
909 PINEVIEW_CURSOR_DFT_WM,
910 PINEVIEW_CURSOR_GUARD_WM,
911 PINEVIEW_FIFO_LINE_SIZE
912 };
913 static const struct intel_watermark_params g4x_wm_info = {
914 G4X_FIFO_SIZE,
915 G4X_MAX_WM,
916 G4X_MAX_WM,
917 2,
918 G4X_FIFO_LINE_SIZE,
919 };
920 static const struct intel_watermark_params g4x_cursor_wm_info = {
921 I965_CURSOR_FIFO,
922 I965_CURSOR_MAX_WM,
923 I965_CURSOR_DFT_WM,
924 2,
925 G4X_FIFO_LINE_SIZE,
926 };
927 static const struct intel_watermark_params valleyview_wm_info = {
928 VALLEYVIEW_FIFO_SIZE,
929 VALLEYVIEW_MAX_WM,
930 VALLEYVIEW_MAX_WM,
931 2,
932 G4X_FIFO_LINE_SIZE,
933 };
934 static const struct intel_watermark_params valleyview_cursor_wm_info = {
935 I965_CURSOR_FIFO,
936 VALLEYVIEW_CURSOR_MAX_WM,
937 I965_CURSOR_DFT_WM,
938 2,
939 G4X_FIFO_LINE_SIZE,
940 };
941 static const struct intel_watermark_params i965_cursor_wm_info = {
942 I965_CURSOR_FIFO,
943 I965_CURSOR_MAX_WM,
944 I965_CURSOR_DFT_WM,
945 2,
946 I915_FIFO_LINE_SIZE,
947 };
948 static const struct intel_watermark_params i945_wm_info = {
949 I945_FIFO_SIZE,
950 I915_MAX_WM,
951 1,
952 2,
953 I915_FIFO_LINE_SIZE
954 };
955 static const struct intel_watermark_params i915_wm_info = {
956 I915_FIFO_SIZE,
957 I915_MAX_WM,
958 1,
959 2,
960 I915_FIFO_LINE_SIZE
961 };
962 static const struct intel_watermark_params i855_wm_info = {
963 I855GM_FIFO_SIZE,
964 I915_MAX_WM,
965 1,
966 2,
967 I830_FIFO_LINE_SIZE
968 };
969 static const struct intel_watermark_params i830_wm_info = {
970 I830_FIFO_SIZE,
971 I915_MAX_WM,
972 1,
973 2,
974 I830_FIFO_LINE_SIZE
975 };
976
977 static const struct intel_watermark_params ironlake_display_wm_info = {
978 ILK_DISPLAY_FIFO,
979 ILK_DISPLAY_MAXWM,
980 ILK_DISPLAY_DFTWM,
981 2,
982 ILK_FIFO_LINE_SIZE
983 };
984 static const struct intel_watermark_params ironlake_cursor_wm_info = {
985 ILK_CURSOR_FIFO,
986 ILK_CURSOR_MAXWM,
987 ILK_CURSOR_DFTWM,
988 2,
989 ILK_FIFO_LINE_SIZE
990 };
991 static const struct intel_watermark_params ironlake_display_srwm_info = {
992 ILK_DISPLAY_SR_FIFO,
993 ILK_DISPLAY_MAX_SRWM,
994 ILK_DISPLAY_DFT_SRWM,
995 2,
996 ILK_FIFO_LINE_SIZE
997 };
998 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
999 ILK_CURSOR_SR_FIFO,
1000 ILK_CURSOR_MAX_SRWM,
1001 ILK_CURSOR_DFT_SRWM,
1002 2,
1003 ILK_FIFO_LINE_SIZE
1004 };
1005
1006 static const struct intel_watermark_params sandybridge_display_wm_info = {
1007 SNB_DISPLAY_FIFO,
1008 SNB_DISPLAY_MAXWM,
1009 SNB_DISPLAY_DFTWM,
1010 2,
1011 SNB_FIFO_LINE_SIZE
1012 };
1013 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1014 SNB_CURSOR_FIFO,
1015 SNB_CURSOR_MAXWM,
1016 SNB_CURSOR_DFTWM,
1017 2,
1018 SNB_FIFO_LINE_SIZE
1019 };
1020 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1021 SNB_DISPLAY_SR_FIFO,
1022 SNB_DISPLAY_MAX_SRWM,
1023 SNB_DISPLAY_DFT_SRWM,
1024 2,
1025 SNB_FIFO_LINE_SIZE
1026 };
1027 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1028 SNB_CURSOR_SR_FIFO,
1029 SNB_CURSOR_MAX_SRWM,
1030 SNB_CURSOR_DFT_SRWM,
1031 2,
1032 SNB_FIFO_LINE_SIZE
1033 };
1034
1035
1036 /**
1037 * intel_calculate_wm - calculate watermark level
1038 * @clock_in_khz: pixel clock
1039 * @wm: chip FIFO params
1040 * @pixel_size: display pixel size
1041 * @latency_ns: memory latency for the platform
1042 *
1043 * Calculate the watermark level (the level at which the display plane will
1044 * start fetching from memory again). Each chip has a different display
1045 * FIFO size and allocation, so the caller needs to figure that out and pass
1046 * in the correct intel_watermark_params structure.
1047 *
1048 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1049 * on the pixel size. When it reaches the watermark level, it'll start
1050 * fetching FIFO line sized based chunks from memory until the FIFO fills
1051 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1052 * will occur, and a display engine hang could result.
1053 */
1054 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1055 const struct intel_watermark_params *wm,
1056 int fifo_size,
1057 int pixel_size,
1058 unsigned long latency_ns)
1059 {
1060 long entries_required, wm_size;
1061
1062 /*
1063 * Note: we need to make sure we don't overflow for various clock &
1064 * latency values.
1065 * clocks go from a few thousand to several hundred thousand.
1066 * latency is usually a few thousand
1067 */
1068 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1069 1000;
1070 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1071
1072 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1073
1074 wm_size = fifo_size - (entries_required + wm->guard_size);
1075
1076 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1077
1078 /* Don't promote wm_size to unsigned... */
1079 if (wm_size > (long)wm->max_wm)
1080 wm_size = wm->max_wm;
1081 if (wm_size <= 0)
1082 wm_size = wm->default_wm;
1083 return wm_size;
1084 }
1085
1086 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1087 {
1088 struct drm_crtc *crtc, *enabled = NULL;
1089
1090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1091 if (intel_crtc_active(crtc)) {
1092 if (enabled)
1093 return NULL;
1094 enabled = crtc;
1095 }
1096 }
1097
1098 return enabled;
1099 }
1100
1101 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1102 {
1103 struct drm_device *dev = unused_crtc->dev;
1104 struct drm_i915_private *dev_priv = dev->dev_private;
1105 struct drm_crtc *crtc;
1106 const struct cxsr_latency *latency;
1107 u32 reg;
1108 unsigned long wm;
1109
1110 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1111 dev_priv->fsb_freq, dev_priv->mem_freq);
1112 if (!latency) {
1113 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1114 pineview_disable_cxsr(dev);
1115 return;
1116 }
1117
1118 crtc = single_enabled_crtc(dev);
1119 if (crtc) {
1120 const struct drm_display_mode *adjusted_mode;
1121 int pixel_size = crtc->fb->bits_per_pixel / 8;
1122 int clock;
1123
1124 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1125 clock = adjusted_mode->crtc_clock;
1126
1127 /* Display SR */
1128 wm = intel_calculate_wm(clock, &pineview_display_wm,
1129 pineview_display_wm.fifo_size,
1130 pixel_size, latency->display_sr);
1131 reg = I915_READ(DSPFW1);
1132 reg &= ~DSPFW_SR_MASK;
1133 reg |= wm << DSPFW_SR_SHIFT;
1134 I915_WRITE(DSPFW1, reg);
1135 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1136
1137 /* cursor SR */
1138 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1139 pineview_display_wm.fifo_size,
1140 pixel_size, latency->cursor_sr);
1141 reg = I915_READ(DSPFW3);
1142 reg &= ~DSPFW_CURSOR_SR_MASK;
1143 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1144 I915_WRITE(DSPFW3, reg);
1145
1146 /* Display HPLL off SR */
1147 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1148 pineview_display_hplloff_wm.fifo_size,
1149 pixel_size, latency->display_hpll_disable);
1150 reg = I915_READ(DSPFW3);
1151 reg &= ~DSPFW_HPLL_SR_MASK;
1152 reg |= wm & DSPFW_HPLL_SR_MASK;
1153 I915_WRITE(DSPFW3, reg);
1154
1155 /* cursor HPLL off SR */
1156 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1157 pineview_display_hplloff_wm.fifo_size,
1158 pixel_size, latency->cursor_hpll_disable);
1159 reg = I915_READ(DSPFW3);
1160 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1161 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1162 I915_WRITE(DSPFW3, reg);
1163 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1164
1165 /* activate cxsr */
1166 I915_WRITE(DSPFW3,
1167 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1168 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1169 } else {
1170 pineview_disable_cxsr(dev);
1171 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1172 }
1173 }
1174
1175 static bool g4x_compute_wm0(struct drm_device *dev,
1176 int plane,
1177 const struct intel_watermark_params *display,
1178 int display_latency_ns,
1179 const struct intel_watermark_params *cursor,
1180 int cursor_latency_ns,
1181 int *plane_wm,
1182 int *cursor_wm)
1183 {
1184 struct drm_crtc *crtc;
1185 const struct drm_display_mode *adjusted_mode;
1186 int htotal, hdisplay, clock, pixel_size;
1187 int line_time_us, line_count;
1188 int entries, tlb_miss;
1189
1190 crtc = intel_get_crtc_for_plane(dev, plane);
1191 if (!intel_crtc_active(crtc)) {
1192 *cursor_wm = cursor->guard_size;
1193 *plane_wm = display->guard_size;
1194 return false;
1195 }
1196
1197 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1198 clock = adjusted_mode->crtc_clock;
1199 htotal = adjusted_mode->htotal;
1200 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1201 pixel_size = crtc->fb->bits_per_pixel / 8;
1202
1203 /* Use the small buffer method to calculate plane watermark */
1204 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1205 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1206 if (tlb_miss > 0)
1207 entries += tlb_miss;
1208 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1209 *plane_wm = entries + display->guard_size;
1210 if (*plane_wm > (int)display->max_wm)
1211 *plane_wm = display->max_wm;
1212
1213 /* Use the large buffer method to calculate cursor watermark */
1214 line_time_us = ((htotal * 1000) / clock);
1215 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1216 entries = line_count * 64 * pixel_size;
1217 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1218 if (tlb_miss > 0)
1219 entries += tlb_miss;
1220 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1221 *cursor_wm = entries + cursor->guard_size;
1222 if (*cursor_wm > (int)cursor->max_wm)
1223 *cursor_wm = (int)cursor->max_wm;
1224
1225 return true;
1226 }
1227
1228 /*
1229 * Check the wm result.
1230 *
1231 * If any calculated watermark values is larger than the maximum value that
1232 * can be programmed into the associated watermark register, that watermark
1233 * must be disabled.
1234 */
1235 static bool g4x_check_srwm(struct drm_device *dev,
1236 int display_wm, int cursor_wm,
1237 const struct intel_watermark_params *display,
1238 const struct intel_watermark_params *cursor)
1239 {
1240 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1241 display_wm, cursor_wm);
1242
1243 if (display_wm > display->max_wm) {
1244 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1245 display_wm, display->max_wm);
1246 return false;
1247 }
1248
1249 if (cursor_wm > cursor->max_wm) {
1250 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1251 cursor_wm, cursor->max_wm);
1252 return false;
1253 }
1254
1255 if (!(display_wm || cursor_wm)) {
1256 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1257 return false;
1258 }
1259
1260 return true;
1261 }
1262
1263 static bool g4x_compute_srwm(struct drm_device *dev,
1264 int plane,
1265 int latency_ns,
1266 const struct intel_watermark_params *display,
1267 const struct intel_watermark_params *cursor,
1268 int *display_wm, int *cursor_wm)
1269 {
1270 struct drm_crtc *crtc;
1271 const struct drm_display_mode *adjusted_mode;
1272 int hdisplay, htotal, pixel_size, clock;
1273 unsigned long line_time_us;
1274 int line_count, line_size;
1275 int small, large;
1276 int entries;
1277
1278 if (!latency_ns) {
1279 *display_wm = *cursor_wm = 0;
1280 return false;
1281 }
1282
1283 crtc = intel_get_crtc_for_plane(dev, plane);
1284 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1285 clock = adjusted_mode->crtc_clock;
1286 htotal = adjusted_mode->htotal;
1287 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1288 pixel_size = crtc->fb->bits_per_pixel / 8;
1289
1290 line_time_us = (htotal * 1000) / clock;
1291 line_count = (latency_ns / line_time_us + 1000) / 1000;
1292 line_size = hdisplay * pixel_size;
1293
1294 /* Use the minimum of the small and large buffer method for primary */
1295 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1296 large = line_count * line_size;
1297
1298 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1299 *display_wm = entries + display->guard_size;
1300
1301 /* calculate the self-refresh watermark for display cursor */
1302 entries = line_count * pixel_size * 64;
1303 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1304 *cursor_wm = entries + cursor->guard_size;
1305
1306 return g4x_check_srwm(dev,
1307 *display_wm, *cursor_wm,
1308 display, cursor);
1309 }
1310
1311 static bool vlv_compute_drain_latency(struct drm_device *dev,
1312 int plane,
1313 int *plane_prec_mult,
1314 int *plane_dl,
1315 int *cursor_prec_mult,
1316 int *cursor_dl)
1317 {
1318 struct drm_crtc *crtc;
1319 int clock, pixel_size;
1320 int entries;
1321
1322 crtc = intel_get_crtc_for_plane(dev, plane);
1323 if (!intel_crtc_active(crtc))
1324 return false;
1325
1326 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1327 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1328
1329 entries = (clock / 1000) * pixel_size;
1330 *plane_prec_mult = (entries > 256) ?
1331 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1332 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1333 pixel_size);
1334
1335 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1336 *cursor_prec_mult = (entries > 256) ?
1337 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1338 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1339
1340 return true;
1341 }
1342
1343 /*
1344 * Update drain latency registers of memory arbiter
1345 *
1346 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1347 * to be programmed. Each plane has a drain latency multiplier and a drain
1348 * latency value.
1349 */
1350
1351 static void vlv_update_drain_latency(struct drm_device *dev)
1352 {
1353 struct drm_i915_private *dev_priv = dev->dev_private;
1354 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1355 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1356 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1357 either 16 or 32 */
1358
1359 /* For plane A, Cursor A */
1360 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1361 &cursor_prec_mult, &cursora_dl)) {
1362 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1363 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1364 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1365 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1366
1367 I915_WRITE(VLV_DDL1, cursora_prec |
1368 (cursora_dl << DDL_CURSORA_SHIFT) |
1369 planea_prec | planea_dl);
1370 }
1371
1372 /* For plane B, Cursor B */
1373 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1374 &cursor_prec_mult, &cursorb_dl)) {
1375 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1376 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1377 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1378 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1379
1380 I915_WRITE(VLV_DDL2, cursorb_prec |
1381 (cursorb_dl << DDL_CURSORB_SHIFT) |
1382 planeb_prec | planeb_dl);
1383 }
1384 }
1385
1386 #define single_plane_enabled(mask) is_power_of_2(mask)
1387
1388 static void valleyview_update_wm(struct drm_crtc *crtc)
1389 {
1390 struct drm_device *dev = crtc->dev;
1391 static const int sr_latency_ns = 12000;
1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1394 int plane_sr, cursor_sr;
1395 int ignore_plane_sr, ignore_cursor_sr;
1396 unsigned int enabled = 0;
1397
1398 vlv_update_drain_latency(dev);
1399
1400 if (g4x_compute_wm0(dev, PIPE_A,
1401 &valleyview_wm_info, latency_ns,
1402 &valleyview_cursor_wm_info, latency_ns,
1403 &planea_wm, &cursora_wm))
1404 enabled |= 1 << PIPE_A;
1405
1406 if (g4x_compute_wm0(dev, PIPE_B,
1407 &valleyview_wm_info, latency_ns,
1408 &valleyview_cursor_wm_info, latency_ns,
1409 &planeb_wm, &cursorb_wm))
1410 enabled |= 1 << PIPE_B;
1411
1412 if (single_plane_enabled(enabled) &&
1413 g4x_compute_srwm(dev, ffs(enabled) - 1,
1414 sr_latency_ns,
1415 &valleyview_wm_info,
1416 &valleyview_cursor_wm_info,
1417 &plane_sr, &ignore_cursor_sr) &&
1418 g4x_compute_srwm(dev, ffs(enabled) - 1,
1419 2*sr_latency_ns,
1420 &valleyview_wm_info,
1421 &valleyview_cursor_wm_info,
1422 &ignore_plane_sr, &cursor_sr)) {
1423 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1424 } else {
1425 I915_WRITE(FW_BLC_SELF_VLV,
1426 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1427 plane_sr = cursor_sr = 0;
1428 }
1429
1430 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1431 planea_wm, cursora_wm,
1432 planeb_wm, cursorb_wm,
1433 plane_sr, cursor_sr);
1434
1435 I915_WRITE(DSPFW1,
1436 (plane_sr << DSPFW_SR_SHIFT) |
1437 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1438 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1439 planea_wm);
1440 I915_WRITE(DSPFW2,
1441 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1442 (cursora_wm << DSPFW_CURSORA_SHIFT));
1443 I915_WRITE(DSPFW3,
1444 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1445 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1446 }
1447
1448 static void g4x_update_wm(struct drm_crtc *crtc)
1449 {
1450 struct drm_device *dev = crtc->dev;
1451 static const int sr_latency_ns = 12000;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1454 int plane_sr, cursor_sr;
1455 unsigned int enabled = 0;
1456
1457 if (g4x_compute_wm0(dev, PIPE_A,
1458 &g4x_wm_info, latency_ns,
1459 &g4x_cursor_wm_info, latency_ns,
1460 &planea_wm, &cursora_wm))
1461 enabled |= 1 << PIPE_A;
1462
1463 if (g4x_compute_wm0(dev, PIPE_B,
1464 &g4x_wm_info, latency_ns,
1465 &g4x_cursor_wm_info, latency_ns,
1466 &planeb_wm, &cursorb_wm))
1467 enabled |= 1 << PIPE_B;
1468
1469 if (single_plane_enabled(enabled) &&
1470 g4x_compute_srwm(dev, ffs(enabled) - 1,
1471 sr_latency_ns,
1472 &g4x_wm_info,
1473 &g4x_cursor_wm_info,
1474 &plane_sr, &cursor_sr)) {
1475 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1476 } else {
1477 I915_WRITE(FW_BLC_SELF,
1478 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1479 plane_sr = cursor_sr = 0;
1480 }
1481
1482 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1483 planea_wm, cursora_wm,
1484 planeb_wm, cursorb_wm,
1485 plane_sr, cursor_sr);
1486
1487 I915_WRITE(DSPFW1,
1488 (plane_sr << DSPFW_SR_SHIFT) |
1489 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1490 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1491 planea_wm);
1492 I915_WRITE(DSPFW2,
1493 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1494 (cursora_wm << DSPFW_CURSORA_SHIFT));
1495 /* HPLL off in SR has some issues on G4x... disable it */
1496 I915_WRITE(DSPFW3,
1497 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1498 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1499 }
1500
1501 static void i965_update_wm(struct drm_crtc *unused_crtc)
1502 {
1503 struct drm_device *dev = unused_crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_crtc *crtc;
1506 int srwm = 1;
1507 int cursor_sr = 16;
1508
1509 /* Calc sr entries for one plane configs */
1510 crtc = single_enabled_crtc(dev);
1511 if (crtc) {
1512 /* self-refresh has much higher latency */
1513 static const int sr_latency_ns = 12000;
1514 const struct drm_display_mode *adjusted_mode =
1515 &to_intel_crtc(crtc)->config.adjusted_mode;
1516 int clock = adjusted_mode->crtc_clock;
1517 int htotal = adjusted_mode->htotal;
1518 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1519 int pixel_size = crtc->fb->bits_per_pixel / 8;
1520 unsigned long line_time_us;
1521 int entries;
1522
1523 line_time_us = ((htotal * 1000) / clock);
1524
1525 /* Use ns/us then divide to preserve precision */
1526 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1527 pixel_size * hdisplay;
1528 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1529 srwm = I965_FIFO_SIZE - entries;
1530 if (srwm < 0)
1531 srwm = 1;
1532 srwm &= 0x1ff;
1533 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1534 entries, srwm);
1535
1536 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1537 pixel_size * 64;
1538 entries = DIV_ROUND_UP(entries,
1539 i965_cursor_wm_info.cacheline_size);
1540 cursor_sr = i965_cursor_wm_info.fifo_size -
1541 (entries + i965_cursor_wm_info.guard_size);
1542
1543 if (cursor_sr > i965_cursor_wm_info.max_wm)
1544 cursor_sr = i965_cursor_wm_info.max_wm;
1545
1546 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1547 "cursor %d\n", srwm, cursor_sr);
1548
1549 if (IS_CRESTLINE(dev))
1550 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1551 } else {
1552 /* Turn off self refresh if both pipes are enabled */
1553 if (IS_CRESTLINE(dev))
1554 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1555 & ~FW_BLC_SELF_EN);
1556 }
1557
1558 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1559 srwm);
1560
1561 /* 965 has limitations... */
1562 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1563 (8 << 16) | (8 << 8) | (8 << 0));
1564 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1565 /* update cursor SR watermark */
1566 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1567 }
1568
1569 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1570 {
1571 struct drm_device *dev = unused_crtc->dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 const struct intel_watermark_params *wm_info;
1574 uint32_t fwater_lo;
1575 uint32_t fwater_hi;
1576 int cwm, srwm = 1;
1577 int fifo_size;
1578 int planea_wm, planeb_wm;
1579 struct drm_crtc *crtc, *enabled = NULL;
1580
1581 if (IS_I945GM(dev))
1582 wm_info = &i945_wm_info;
1583 else if (!IS_GEN2(dev))
1584 wm_info = &i915_wm_info;
1585 else
1586 wm_info = &i855_wm_info;
1587
1588 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1589 crtc = intel_get_crtc_for_plane(dev, 0);
1590 if (intel_crtc_active(crtc)) {
1591 const struct drm_display_mode *adjusted_mode;
1592 int cpp = crtc->fb->bits_per_pixel / 8;
1593 if (IS_GEN2(dev))
1594 cpp = 4;
1595
1596 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1597 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1598 wm_info, fifo_size, cpp,
1599 latency_ns);
1600 enabled = crtc;
1601 } else
1602 planea_wm = fifo_size - wm_info->guard_size;
1603
1604 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1605 crtc = intel_get_crtc_for_plane(dev, 1);
1606 if (intel_crtc_active(crtc)) {
1607 const struct drm_display_mode *adjusted_mode;
1608 int cpp = crtc->fb->bits_per_pixel / 8;
1609 if (IS_GEN2(dev))
1610 cpp = 4;
1611
1612 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1613 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1614 wm_info, fifo_size, cpp,
1615 latency_ns);
1616 if (enabled == NULL)
1617 enabled = crtc;
1618 else
1619 enabled = NULL;
1620 } else
1621 planeb_wm = fifo_size - wm_info->guard_size;
1622
1623 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1624
1625 /*
1626 * Overlay gets an aggressive default since video jitter is bad.
1627 */
1628 cwm = 2;
1629
1630 /* Play safe and disable self-refresh before adjusting watermarks. */
1631 if (IS_I945G(dev) || IS_I945GM(dev))
1632 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1633 else if (IS_I915GM(dev))
1634 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1635
1636 /* Calc sr entries for one plane configs */
1637 if (HAS_FW_BLC(dev) && enabled) {
1638 /* self-refresh has much higher latency */
1639 static const int sr_latency_ns = 6000;
1640 const struct drm_display_mode *adjusted_mode =
1641 &to_intel_crtc(enabled)->config.adjusted_mode;
1642 int clock = adjusted_mode->crtc_clock;
1643 int htotal = adjusted_mode->htotal;
1644 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1645 int pixel_size = enabled->fb->bits_per_pixel / 8;
1646 unsigned long line_time_us;
1647 int entries;
1648
1649 line_time_us = (htotal * 1000) / clock;
1650
1651 /* Use ns/us then divide to preserve precision */
1652 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1653 pixel_size * hdisplay;
1654 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1655 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1656 srwm = wm_info->fifo_size - entries;
1657 if (srwm < 0)
1658 srwm = 1;
1659
1660 if (IS_I945G(dev) || IS_I945GM(dev))
1661 I915_WRITE(FW_BLC_SELF,
1662 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1663 else if (IS_I915GM(dev))
1664 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1665 }
1666
1667 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1668 planea_wm, planeb_wm, cwm, srwm);
1669
1670 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1671 fwater_hi = (cwm & 0x1f);
1672
1673 /* Set request length to 8 cachelines per fetch */
1674 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1675 fwater_hi = fwater_hi | (1 << 8);
1676
1677 I915_WRITE(FW_BLC, fwater_lo);
1678 I915_WRITE(FW_BLC2, fwater_hi);
1679
1680 if (HAS_FW_BLC(dev)) {
1681 if (enabled) {
1682 if (IS_I945G(dev) || IS_I945GM(dev))
1683 I915_WRITE(FW_BLC_SELF,
1684 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1685 else if (IS_I915GM(dev))
1686 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1687 DRM_DEBUG_KMS("memory self refresh enabled\n");
1688 } else
1689 DRM_DEBUG_KMS("memory self refresh disabled\n");
1690 }
1691 }
1692
1693 static void i830_update_wm(struct drm_crtc *unused_crtc)
1694 {
1695 struct drm_device *dev = unused_crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 struct drm_crtc *crtc;
1698 const struct drm_display_mode *adjusted_mode;
1699 uint32_t fwater_lo;
1700 int planea_wm;
1701
1702 crtc = single_enabled_crtc(dev);
1703 if (crtc == NULL)
1704 return;
1705
1706 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1707 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1708 &i830_wm_info,
1709 dev_priv->display.get_fifo_size(dev, 0),
1710 4, latency_ns);
1711 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1712 fwater_lo |= (3<<8) | planea_wm;
1713
1714 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1715
1716 I915_WRITE(FW_BLC, fwater_lo);
1717 }
1718
1719 /*
1720 * Check the wm result.
1721 *
1722 * If any calculated watermark values is larger than the maximum value that
1723 * can be programmed into the associated watermark register, that watermark
1724 * must be disabled.
1725 */
1726 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1727 int fbc_wm, int display_wm, int cursor_wm,
1728 const struct intel_watermark_params *display,
1729 const struct intel_watermark_params *cursor)
1730 {
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732
1733 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1734 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1735
1736 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1737 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1738 fbc_wm, SNB_FBC_MAX_SRWM, level);
1739
1740 /* fbc has it's own way to disable FBC WM */
1741 I915_WRITE(DISP_ARB_CTL,
1742 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1743 return false;
1744 } else if (INTEL_INFO(dev)->gen >= 6) {
1745 /* enable FBC WM (except on ILK, where it must remain off) */
1746 I915_WRITE(DISP_ARB_CTL,
1747 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1748 }
1749
1750 if (display_wm > display->max_wm) {
1751 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1752 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1753 return false;
1754 }
1755
1756 if (cursor_wm > cursor->max_wm) {
1757 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1758 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1759 return false;
1760 }
1761
1762 if (!(fbc_wm || display_wm || cursor_wm)) {
1763 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1764 return false;
1765 }
1766
1767 return true;
1768 }
1769
1770 /*
1771 * Compute watermark values of WM[1-3],
1772 */
1773 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1774 int latency_ns,
1775 const struct intel_watermark_params *display,
1776 const struct intel_watermark_params *cursor,
1777 int *fbc_wm, int *display_wm, int *cursor_wm)
1778 {
1779 struct drm_crtc *crtc;
1780 const struct drm_display_mode *adjusted_mode;
1781 unsigned long line_time_us;
1782 int hdisplay, htotal, pixel_size, clock;
1783 int line_count, line_size;
1784 int small, large;
1785 int entries;
1786
1787 if (!latency_ns) {
1788 *fbc_wm = *display_wm = *cursor_wm = 0;
1789 return false;
1790 }
1791
1792 crtc = intel_get_crtc_for_plane(dev, plane);
1793 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1794 clock = adjusted_mode->crtc_clock;
1795 htotal = adjusted_mode->htotal;
1796 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1797 pixel_size = crtc->fb->bits_per_pixel / 8;
1798
1799 line_time_us = (htotal * 1000) / clock;
1800 line_count = (latency_ns / line_time_us + 1000) / 1000;
1801 line_size = hdisplay * pixel_size;
1802
1803 /* Use the minimum of the small and large buffer method for primary */
1804 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1805 large = line_count * line_size;
1806
1807 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1808 *display_wm = entries + display->guard_size;
1809
1810 /*
1811 * Spec says:
1812 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1813 */
1814 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1815
1816 /* calculate the self-refresh watermark for display cursor */
1817 entries = line_count * pixel_size * 64;
1818 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1819 *cursor_wm = entries + cursor->guard_size;
1820
1821 return ironlake_check_srwm(dev, level,
1822 *fbc_wm, *display_wm, *cursor_wm,
1823 display, cursor);
1824 }
1825
1826 static void ironlake_update_wm(struct drm_crtc *crtc)
1827 {
1828 struct drm_device *dev = crtc->dev;
1829 struct drm_i915_private *dev_priv = dev->dev_private;
1830 int fbc_wm, plane_wm, cursor_wm;
1831 unsigned int enabled;
1832
1833 enabled = 0;
1834 if (g4x_compute_wm0(dev, PIPE_A,
1835 &ironlake_display_wm_info,
1836 dev_priv->wm.pri_latency[0] * 100,
1837 &ironlake_cursor_wm_info,
1838 dev_priv->wm.cur_latency[0] * 100,
1839 &plane_wm, &cursor_wm)) {
1840 I915_WRITE(WM0_PIPEA_ILK,
1841 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1842 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1843 " plane %d, " "cursor: %d\n",
1844 plane_wm, cursor_wm);
1845 enabled |= 1 << PIPE_A;
1846 }
1847
1848 if (g4x_compute_wm0(dev, PIPE_B,
1849 &ironlake_display_wm_info,
1850 dev_priv->wm.pri_latency[0] * 100,
1851 &ironlake_cursor_wm_info,
1852 dev_priv->wm.cur_latency[0] * 100,
1853 &plane_wm, &cursor_wm)) {
1854 I915_WRITE(WM0_PIPEB_ILK,
1855 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1856 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1857 " plane %d, cursor: %d\n",
1858 plane_wm, cursor_wm);
1859 enabled |= 1 << PIPE_B;
1860 }
1861
1862 /*
1863 * Calculate and update the self-refresh watermark only when one
1864 * display plane is used.
1865 */
1866 I915_WRITE(WM3_LP_ILK, 0);
1867 I915_WRITE(WM2_LP_ILK, 0);
1868 I915_WRITE(WM1_LP_ILK, 0);
1869
1870 if (!single_plane_enabled(enabled))
1871 return;
1872 enabled = ffs(enabled) - 1;
1873
1874 /* WM1 */
1875 if (!ironlake_compute_srwm(dev, 1, enabled,
1876 dev_priv->wm.pri_latency[1] * 500,
1877 &ironlake_display_srwm_info,
1878 &ironlake_cursor_srwm_info,
1879 &fbc_wm, &plane_wm, &cursor_wm))
1880 return;
1881
1882 I915_WRITE(WM1_LP_ILK,
1883 WM1_LP_SR_EN |
1884 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1885 (fbc_wm << WM1_LP_FBC_SHIFT) |
1886 (plane_wm << WM1_LP_SR_SHIFT) |
1887 cursor_wm);
1888
1889 /* WM2 */
1890 if (!ironlake_compute_srwm(dev, 2, enabled,
1891 dev_priv->wm.pri_latency[2] * 500,
1892 &ironlake_display_srwm_info,
1893 &ironlake_cursor_srwm_info,
1894 &fbc_wm, &plane_wm, &cursor_wm))
1895 return;
1896
1897 I915_WRITE(WM2_LP_ILK,
1898 WM2_LP_EN |
1899 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1900 (fbc_wm << WM1_LP_FBC_SHIFT) |
1901 (plane_wm << WM1_LP_SR_SHIFT) |
1902 cursor_wm);
1903
1904 /*
1905 * WM3 is unsupported on ILK, probably because we don't have latency
1906 * data for that power state
1907 */
1908 }
1909
1910 static void sandybridge_update_wm(struct drm_crtc *crtc)
1911 {
1912 struct drm_device *dev = crtc->dev;
1913 struct drm_i915_private *dev_priv = dev->dev_private;
1914 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1915 u32 val;
1916 int fbc_wm, plane_wm, cursor_wm;
1917 unsigned int enabled;
1918
1919 enabled = 0;
1920 if (g4x_compute_wm0(dev, PIPE_A,
1921 &sandybridge_display_wm_info, latency,
1922 &sandybridge_cursor_wm_info, latency,
1923 &plane_wm, &cursor_wm)) {
1924 val = I915_READ(WM0_PIPEA_ILK);
1925 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1926 I915_WRITE(WM0_PIPEA_ILK, val |
1927 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1928 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1929 " plane %d, " "cursor: %d\n",
1930 plane_wm, cursor_wm);
1931 enabled |= 1 << PIPE_A;
1932 }
1933
1934 if (g4x_compute_wm0(dev, PIPE_B,
1935 &sandybridge_display_wm_info, latency,
1936 &sandybridge_cursor_wm_info, latency,
1937 &plane_wm, &cursor_wm)) {
1938 val = I915_READ(WM0_PIPEB_ILK);
1939 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1940 I915_WRITE(WM0_PIPEB_ILK, val |
1941 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1942 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1943 " plane %d, cursor: %d\n",
1944 plane_wm, cursor_wm);
1945 enabled |= 1 << PIPE_B;
1946 }
1947
1948 /*
1949 * Calculate and update the self-refresh watermark only when one
1950 * display plane is used.
1951 *
1952 * SNB support 3 levels of watermark.
1953 *
1954 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1955 * and disabled in the descending order
1956 *
1957 */
1958 I915_WRITE(WM3_LP_ILK, 0);
1959 I915_WRITE(WM2_LP_ILK, 0);
1960 I915_WRITE(WM1_LP_ILK, 0);
1961
1962 if (!single_plane_enabled(enabled) ||
1963 dev_priv->sprite_scaling_enabled)
1964 return;
1965 enabled = ffs(enabled) - 1;
1966
1967 /* WM1 */
1968 if (!ironlake_compute_srwm(dev, 1, enabled,
1969 dev_priv->wm.pri_latency[1] * 500,
1970 &sandybridge_display_srwm_info,
1971 &sandybridge_cursor_srwm_info,
1972 &fbc_wm, &plane_wm, &cursor_wm))
1973 return;
1974
1975 I915_WRITE(WM1_LP_ILK,
1976 WM1_LP_SR_EN |
1977 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1978 (fbc_wm << WM1_LP_FBC_SHIFT) |
1979 (plane_wm << WM1_LP_SR_SHIFT) |
1980 cursor_wm);
1981
1982 /* WM2 */
1983 if (!ironlake_compute_srwm(dev, 2, enabled,
1984 dev_priv->wm.pri_latency[2] * 500,
1985 &sandybridge_display_srwm_info,
1986 &sandybridge_cursor_srwm_info,
1987 &fbc_wm, &plane_wm, &cursor_wm))
1988 return;
1989
1990 I915_WRITE(WM2_LP_ILK,
1991 WM2_LP_EN |
1992 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1993 (fbc_wm << WM1_LP_FBC_SHIFT) |
1994 (plane_wm << WM1_LP_SR_SHIFT) |
1995 cursor_wm);
1996
1997 /* WM3 */
1998 if (!ironlake_compute_srwm(dev, 3, enabled,
1999 dev_priv->wm.pri_latency[3] * 500,
2000 &sandybridge_display_srwm_info,
2001 &sandybridge_cursor_srwm_info,
2002 &fbc_wm, &plane_wm, &cursor_wm))
2003 return;
2004
2005 I915_WRITE(WM3_LP_ILK,
2006 WM3_LP_EN |
2007 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2008 (fbc_wm << WM1_LP_FBC_SHIFT) |
2009 (plane_wm << WM1_LP_SR_SHIFT) |
2010 cursor_wm);
2011 }
2012
2013 static void ivybridge_update_wm(struct drm_crtc *crtc)
2014 {
2015 struct drm_device *dev = crtc->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2018 u32 val;
2019 int fbc_wm, plane_wm, cursor_wm;
2020 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2021 unsigned int enabled;
2022
2023 enabled = 0;
2024 if (g4x_compute_wm0(dev, PIPE_A,
2025 &sandybridge_display_wm_info, latency,
2026 &sandybridge_cursor_wm_info, latency,
2027 &plane_wm, &cursor_wm)) {
2028 val = I915_READ(WM0_PIPEA_ILK);
2029 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2030 I915_WRITE(WM0_PIPEA_ILK, val |
2031 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2032 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2033 " plane %d, " "cursor: %d\n",
2034 plane_wm, cursor_wm);
2035 enabled |= 1 << PIPE_A;
2036 }
2037
2038 if (g4x_compute_wm0(dev, PIPE_B,
2039 &sandybridge_display_wm_info, latency,
2040 &sandybridge_cursor_wm_info, latency,
2041 &plane_wm, &cursor_wm)) {
2042 val = I915_READ(WM0_PIPEB_ILK);
2043 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2044 I915_WRITE(WM0_PIPEB_ILK, val |
2045 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2046 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2047 " plane %d, cursor: %d\n",
2048 plane_wm, cursor_wm);
2049 enabled |= 1 << PIPE_B;
2050 }
2051
2052 if (g4x_compute_wm0(dev, PIPE_C,
2053 &sandybridge_display_wm_info, latency,
2054 &sandybridge_cursor_wm_info, latency,
2055 &plane_wm, &cursor_wm)) {
2056 val = I915_READ(WM0_PIPEC_IVB);
2057 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2058 I915_WRITE(WM0_PIPEC_IVB, val |
2059 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2060 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2061 " plane %d, cursor: %d\n",
2062 plane_wm, cursor_wm);
2063 enabled |= 1 << PIPE_C;
2064 }
2065
2066 /*
2067 * Calculate and update the self-refresh watermark only when one
2068 * display plane is used.
2069 *
2070 * SNB support 3 levels of watermark.
2071 *
2072 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2073 * and disabled in the descending order
2074 *
2075 */
2076 I915_WRITE(WM3_LP_ILK, 0);
2077 I915_WRITE(WM2_LP_ILK, 0);
2078 I915_WRITE(WM1_LP_ILK, 0);
2079
2080 if (!single_plane_enabled(enabled) ||
2081 dev_priv->sprite_scaling_enabled)
2082 return;
2083 enabled = ffs(enabled) - 1;
2084
2085 /* WM1 */
2086 if (!ironlake_compute_srwm(dev, 1, enabled,
2087 dev_priv->wm.pri_latency[1] * 500,
2088 &sandybridge_display_srwm_info,
2089 &sandybridge_cursor_srwm_info,
2090 &fbc_wm, &plane_wm, &cursor_wm))
2091 return;
2092
2093 I915_WRITE(WM1_LP_ILK,
2094 WM1_LP_SR_EN |
2095 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2096 (fbc_wm << WM1_LP_FBC_SHIFT) |
2097 (plane_wm << WM1_LP_SR_SHIFT) |
2098 cursor_wm);
2099
2100 /* WM2 */
2101 if (!ironlake_compute_srwm(dev, 2, enabled,
2102 dev_priv->wm.pri_latency[2] * 500,
2103 &sandybridge_display_srwm_info,
2104 &sandybridge_cursor_srwm_info,
2105 &fbc_wm, &plane_wm, &cursor_wm))
2106 return;
2107
2108 I915_WRITE(WM2_LP_ILK,
2109 WM2_LP_EN |
2110 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2111 (fbc_wm << WM1_LP_FBC_SHIFT) |
2112 (plane_wm << WM1_LP_SR_SHIFT) |
2113 cursor_wm);
2114
2115 /* WM3, note we have to correct the cursor latency */
2116 if (!ironlake_compute_srwm(dev, 3, enabled,
2117 dev_priv->wm.pri_latency[3] * 500,
2118 &sandybridge_display_srwm_info,
2119 &sandybridge_cursor_srwm_info,
2120 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2121 !ironlake_compute_srwm(dev, 3, enabled,
2122 dev_priv->wm.cur_latency[3] * 500,
2123 &sandybridge_display_srwm_info,
2124 &sandybridge_cursor_srwm_info,
2125 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2126 return;
2127
2128 I915_WRITE(WM3_LP_ILK,
2129 WM3_LP_EN |
2130 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2131 (fbc_wm << WM1_LP_FBC_SHIFT) |
2132 (plane_wm << WM1_LP_SR_SHIFT) |
2133 cursor_wm);
2134 }
2135
2136 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2137 struct drm_crtc *crtc)
2138 {
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140 uint32_t pixel_rate;
2141
2142 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2143
2144 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2145 * adjust the pixel_rate here. */
2146
2147 if (intel_crtc->config.pch_pfit.enabled) {
2148 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2149 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2150
2151 pipe_w = intel_crtc->config.pipe_src_w;
2152 pipe_h = intel_crtc->config.pipe_src_h;
2153 pfit_w = (pfit_size >> 16) & 0xFFFF;
2154 pfit_h = pfit_size & 0xFFFF;
2155 if (pipe_w < pfit_w)
2156 pipe_w = pfit_w;
2157 if (pipe_h < pfit_h)
2158 pipe_h = pfit_h;
2159
2160 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2161 pfit_w * pfit_h);
2162 }
2163
2164 return pixel_rate;
2165 }
2166
2167 /* latency must be in 0.1us units. */
2168 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2169 uint32_t latency)
2170 {
2171 uint64_t ret;
2172
2173 if (WARN(latency == 0, "Latency value missing\n"))
2174 return UINT_MAX;
2175
2176 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2177 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2178
2179 return ret;
2180 }
2181
2182 /* latency must be in 0.1us units. */
2183 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2184 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2185 uint32_t latency)
2186 {
2187 uint32_t ret;
2188
2189 if (WARN(latency == 0, "Latency value missing\n"))
2190 return UINT_MAX;
2191
2192 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2193 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2194 ret = DIV_ROUND_UP(ret, 64) + 2;
2195 return ret;
2196 }
2197
2198 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2199 uint8_t bytes_per_pixel)
2200 {
2201 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2202 }
2203
2204 struct hsw_pipe_wm_parameters {
2205 bool active;
2206 uint32_t pipe_htotal;
2207 uint32_t pixel_rate;
2208 struct intel_plane_wm_parameters pri;
2209 struct intel_plane_wm_parameters spr;
2210 struct intel_plane_wm_parameters cur;
2211 };
2212
2213 struct hsw_wm_maximums {
2214 uint16_t pri;
2215 uint16_t spr;
2216 uint16_t cur;
2217 uint16_t fbc;
2218 };
2219
2220 /* used in computing the new watermarks state */
2221 struct intel_wm_config {
2222 unsigned int num_pipes_active;
2223 bool sprites_enabled;
2224 bool sprites_scaled;
2225 };
2226
2227 /*
2228 * For both WM_PIPE and WM_LP.
2229 * mem_value must be in 0.1us units.
2230 */
2231 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2232 uint32_t mem_value,
2233 bool is_lp)
2234 {
2235 uint32_t method1, method2;
2236
2237 if (!params->active || !params->pri.enabled)
2238 return 0;
2239
2240 method1 = ilk_wm_method1(params->pixel_rate,
2241 params->pri.bytes_per_pixel,
2242 mem_value);
2243
2244 if (!is_lp)
2245 return method1;
2246
2247 method2 = ilk_wm_method2(params->pixel_rate,
2248 params->pipe_htotal,
2249 params->pri.horiz_pixels,
2250 params->pri.bytes_per_pixel,
2251 mem_value);
2252
2253 return min(method1, method2);
2254 }
2255
2256 /*
2257 * For both WM_PIPE and WM_LP.
2258 * mem_value must be in 0.1us units.
2259 */
2260 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2261 uint32_t mem_value)
2262 {
2263 uint32_t method1, method2;
2264
2265 if (!params->active || !params->spr.enabled)
2266 return 0;
2267
2268 method1 = ilk_wm_method1(params->pixel_rate,
2269 params->spr.bytes_per_pixel,
2270 mem_value);
2271 method2 = ilk_wm_method2(params->pixel_rate,
2272 params->pipe_htotal,
2273 params->spr.horiz_pixels,
2274 params->spr.bytes_per_pixel,
2275 mem_value);
2276 return min(method1, method2);
2277 }
2278
2279 /*
2280 * For both WM_PIPE and WM_LP.
2281 * mem_value must be in 0.1us units.
2282 */
2283 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2284 uint32_t mem_value)
2285 {
2286 if (!params->active || !params->cur.enabled)
2287 return 0;
2288
2289 return ilk_wm_method2(params->pixel_rate,
2290 params->pipe_htotal,
2291 params->cur.horiz_pixels,
2292 params->cur.bytes_per_pixel,
2293 mem_value);
2294 }
2295
2296 /* Only for WM_LP. */
2297 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2298 uint32_t pri_val)
2299 {
2300 if (!params->active || !params->pri.enabled)
2301 return 0;
2302
2303 return ilk_wm_fbc(pri_val,
2304 params->pri.horiz_pixels,
2305 params->pri.bytes_per_pixel);
2306 }
2307
2308 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2309 {
2310 if (INTEL_INFO(dev)->gen >= 8)
2311 return 3072;
2312 else if (INTEL_INFO(dev)->gen >= 7)
2313 return 768;
2314 else
2315 return 512;
2316 }
2317
2318 /* Calculate the maximum primary/sprite plane watermark */
2319 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2320 int level,
2321 const struct intel_wm_config *config,
2322 enum intel_ddb_partitioning ddb_partitioning,
2323 bool is_sprite)
2324 {
2325 unsigned int fifo_size = ilk_display_fifo_size(dev);
2326 unsigned int max;
2327
2328 /* if sprites aren't enabled, sprites get nothing */
2329 if (is_sprite && !config->sprites_enabled)
2330 return 0;
2331
2332 /* HSW allows LP1+ watermarks even with multiple pipes */
2333 if (level == 0 || config->num_pipes_active > 1) {
2334 fifo_size /= INTEL_INFO(dev)->num_pipes;
2335
2336 /*
2337 * For some reason the non self refresh
2338 * FIFO size is only half of the self
2339 * refresh FIFO size on ILK/SNB.
2340 */
2341 if (INTEL_INFO(dev)->gen <= 6)
2342 fifo_size /= 2;
2343 }
2344
2345 if (config->sprites_enabled) {
2346 /* level 0 is always calculated with 1:1 split */
2347 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2348 if (is_sprite)
2349 fifo_size *= 5;
2350 fifo_size /= 6;
2351 } else {
2352 fifo_size /= 2;
2353 }
2354 }
2355
2356 /* clamp to max that the registers can hold */
2357 if (INTEL_INFO(dev)->gen >= 8)
2358 max = level == 0 ? 255 : 2047;
2359 else if (INTEL_INFO(dev)->gen >= 7)
2360 /* IVB/HSW primary/sprite plane watermarks */
2361 max = level == 0 ? 127 : 1023;
2362 else if (!is_sprite)
2363 /* ILK/SNB primary plane watermarks */
2364 max = level == 0 ? 127 : 511;
2365 else
2366 /* ILK/SNB sprite plane watermarks */
2367 max = level == 0 ? 63 : 255;
2368
2369 return min(fifo_size, max);
2370 }
2371
2372 /* Calculate the maximum cursor plane watermark */
2373 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2374 int level,
2375 const struct intel_wm_config *config)
2376 {
2377 /* HSW LP1+ watermarks w/ multiple pipes */
2378 if (level > 0 && config->num_pipes_active > 1)
2379 return 64;
2380
2381 /* otherwise just report max that registers can hold */
2382 if (INTEL_INFO(dev)->gen >= 7)
2383 return level == 0 ? 63 : 255;
2384 else
2385 return level == 0 ? 31 : 63;
2386 }
2387
2388 /* Calculate the maximum FBC watermark */
2389 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
2390 {
2391 /* max that registers can hold */
2392 if (INTEL_INFO(dev)->gen >= 8)
2393 return 31;
2394 else
2395 return 15;
2396 }
2397
2398 static void ilk_compute_wm_maximums(struct drm_device *dev,
2399 int level,
2400 const struct intel_wm_config *config,
2401 enum intel_ddb_partitioning ddb_partitioning,
2402 struct hsw_wm_maximums *max)
2403 {
2404 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2405 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2406 max->cur = ilk_cursor_wm_max(dev, level, config);
2407 max->fbc = ilk_fbc_wm_max(dev);
2408 }
2409
2410 static bool ilk_validate_wm_level(int level,
2411 const struct hsw_wm_maximums *max,
2412 struct intel_wm_level *result)
2413 {
2414 bool ret;
2415
2416 /* already determined to be invalid? */
2417 if (!result->enable)
2418 return false;
2419
2420 result->enable = result->pri_val <= max->pri &&
2421 result->spr_val <= max->spr &&
2422 result->cur_val <= max->cur;
2423
2424 ret = result->enable;
2425
2426 /*
2427 * HACK until we can pre-compute everything,
2428 * and thus fail gracefully if LP0 watermarks
2429 * are exceeded...
2430 */
2431 if (level == 0 && !result->enable) {
2432 if (result->pri_val > max->pri)
2433 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2434 level, result->pri_val, max->pri);
2435 if (result->spr_val > max->spr)
2436 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2437 level, result->spr_val, max->spr);
2438 if (result->cur_val > max->cur)
2439 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2440 level, result->cur_val, max->cur);
2441
2442 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2443 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2444 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2445 result->enable = true;
2446 }
2447
2448 return ret;
2449 }
2450
2451 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2452 int level,
2453 const struct hsw_pipe_wm_parameters *p,
2454 struct intel_wm_level *result)
2455 {
2456 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2457 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2458 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2459
2460 /* WM1+ latency values stored in 0.5us units */
2461 if (level > 0) {
2462 pri_latency *= 5;
2463 spr_latency *= 5;
2464 cur_latency *= 5;
2465 }
2466
2467 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2468 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2469 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2470 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2471 result->enable = true;
2472 }
2473
2474 static uint32_t
2475 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2476 {
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2479 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2480 u32 linetime, ips_linetime;
2481
2482 if (!intel_crtc_active(crtc))
2483 return 0;
2484
2485 /* The WM are computed with base on how long it takes to fill a single
2486 * row at the given clock rate, multiplied by 8.
2487 * */
2488 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2489 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2490 intel_ddi_get_cdclk_freq(dev_priv));
2491
2492 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2493 PIPE_WM_LINETIME_TIME(linetime);
2494 }
2495
2496 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2497 {
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499
2500 if (IS_HASWELL(dev)) {
2501 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2502
2503 wm[0] = (sskpd >> 56) & 0xFF;
2504 if (wm[0] == 0)
2505 wm[0] = sskpd & 0xF;
2506 wm[1] = (sskpd >> 4) & 0xFF;
2507 wm[2] = (sskpd >> 12) & 0xFF;
2508 wm[3] = (sskpd >> 20) & 0x1FF;
2509 wm[4] = (sskpd >> 32) & 0x1FF;
2510 } else if (INTEL_INFO(dev)->gen >= 6) {
2511 uint32_t sskpd = I915_READ(MCH_SSKPD);
2512
2513 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2514 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2515 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2516 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2517 } else if (INTEL_INFO(dev)->gen >= 5) {
2518 uint32_t mltr = I915_READ(MLTR_ILK);
2519
2520 /* ILK primary LP0 latency is 700 ns */
2521 wm[0] = 7;
2522 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2523 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2524 }
2525 }
2526
2527 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2528 {
2529 /* ILK sprite LP0 latency is 1300 ns */
2530 if (INTEL_INFO(dev)->gen == 5)
2531 wm[0] = 13;
2532 }
2533
2534 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2535 {
2536 /* ILK cursor LP0 latency is 1300 ns */
2537 if (INTEL_INFO(dev)->gen == 5)
2538 wm[0] = 13;
2539
2540 /* WaDoubleCursorLP3Latency:ivb */
2541 if (IS_IVYBRIDGE(dev))
2542 wm[3] *= 2;
2543 }
2544
2545 static int ilk_wm_max_level(const struct drm_device *dev)
2546 {
2547 /* how many WM levels are we expecting */
2548 if (IS_HASWELL(dev))
2549 return 4;
2550 else if (INTEL_INFO(dev)->gen >= 6)
2551 return 3;
2552 else
2553 return 2;
2554 }
2555
2556 static void intel_print_wm_latency(struct drm_device *dev,
2557 const char *name,
2558 const uint16_t wm[5])
2559 {
2560 int level, max_level = ilk_wm_max_level(dev);
2561
2562 for (level = 0; level <= max_level; level++) {
2563 unsigned int latency = wm[level];
2564
2565 if (latency == 0) {
2566 DRM_ERROR("%s WM%d latency not provided\n",
2567 name, level);
2568 continue;
2569 }
2570
2571 /* WM1+ latency values in 0.5us units */
2572 if (level > 0)
2573 latency *= 5;
2574
2575 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2576 name, level, wm[level],
2577 latency / 10, latency % 10);
2578 }
2579 }
2580
2581 static void intel_setup_wm_latency(struct drm_device *dev)
2582 {
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584
2585 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2586
2587 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2588 sizeof(dev_priv->wm.pri_latency));
2589 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2590 sizeof(dev_priv->wm.pri_latency));
2591
2592 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2593 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2594
2595 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2596 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2597 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2598 }
2599
2600 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2601 struct hsw_pipe_wm_parameters *p,
2602 struct intel_wm_config *config)
2603 {
2604 struct drm_device *dev = crtc->dev;
2605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606 enum pipe pipe = intel_crtc->pipe;
2607 struct drm_plane *plane;
2608
2609 p->active = intel_crtc_active(crtc);
2610 if (p->active) {
2611 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2612 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2613 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2614 p->cur.bytes_per_pixel = 4;
2615 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2616 p->cur.horiz_pixels = 64;
2617 /* TODO: for now, assume primary and cursor planes are always enabled. */
2618 p->pri.enabled = true;
2619 p->cur.enabled = true;
2620 }
2621
2622 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2623 config->num_pipes_active += intel_crtc_active(crtc);
2624
2625 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2626 struct intel_plane *intel_plane = to_intel_plane(plane);
2627
2628 if (intel_plane->pipe == pipe)
2629 p->spr = intel_plane->wm;
2630
2631 config->sprites_enabled |= intel_plane->wm.enabled;
2632 config->sprites_scaled |= intel_plane->wm.scaled;
2633 }
2634 }
2635
2636 /* Compute new watermarks for the pipe */
2637 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2638 const struct hsw_pipe_wm_parameters *params,
2639 struct intel_pipe_wm *pipe_wm)
2640 {
2641 struct drm_device *dev = crtc->dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 int level, max_level = ilk_wm_max_level(dev);
2644 /* LP0 watermark maximums depend on this pipe alone */
2645 struct intel_wm_config config = {
2646 .num_pipes_active = 1,
2647 .sprites_enabled = params->spr.enabled,
2648 .sprites_scaled = params->spr.scaled,
2649 };
2650 struct hsw_wm_maximums max;
2651
2652 /* LP0 watermarks always use 1/2 DDB partitioning */
2653 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2654
2655 for (level = 0; level <= max_level; level++)
2656 ilk_compute_wm_level(dev_priv, level, params,
2657 &pipe_wm->wm[level]);
2658
2659 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2660
2661 /* At least LP0 must be valid */
2662 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2663 }
2664
2665 /*
2666 * Merge the watermarks from all active pipes for a specific level.
2667 */
2668 static void ilk_merge_wm_level(struct drm_device *dev,
2669 int level,
2670 struct intel_wm_level *ret_wm)
2671 {
2672 const struct intel_crtc *intel_crtc;
2673
2674 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2675 const struct intel_wm_level *wm =
2676 &intel_crtc->wm.active.wm[level];
2677
2678 if (!wm->enable)
2679 return;
2680
2681 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2682 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2683 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2684 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2685 }
2686
2687 ret_wm->enable = true;
2688 }
2689
2690 /*
2691 * Merge all low power watermarks for all active pipes.
2692 */
2693 static void ilk_wm_merge(struct drm_device *dev,
2694 const struct hsw_wm_maximums *max,
2695 struct intel_pipe_wm *merged)
2696 {
2697 int level, max_level = ilk_wm_max_level(dev);
2698
2699 merged->fbc_wm_enabled = true;
2700
2701 /* merge each WM1+ level */
2702 for (level = 1; level <= max_level; level++) {
2703 struct intel_wm_level *wm = &merged->wm[level];
2704
2705 ilk_merge_wm_level(dev, level, wm);
2706
2707 if (!ilk_validate_wm_level(level, max, wm))
2708 break;
2709
2710 /*
2711 * The spec says it is preferred to disable
2712 * FBC WMs instead of disabling a WM level.
2713 */
2714 if (wm->fbc_val > max->fbc) {
2715 merged->fbc_wm_enabled = false;
2716 wm->fbc_val = 0;
2717 }
2718 }
2719 }
2720
2721 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2722 {
2723 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2724 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2725 }
2726
2727 static void hsw_compute_wm_results(struct drm_device *dev,
2728 const struct intel_pipe_wm *merged,
2729 enum intel_ddb_partitioning partitioning,
2730 struct hsw_wm_values *results)
2731 {
2732 struct intel_crtc *intel_crtc;
2733 int level, wm_lp;
2734
2735 results->enable_fbc_wm = merged->fbc_wm_enabled;
2736 results->partitioning = partitioning;
2737
2738 /* LP1+ register values */
2739 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2740 const struct intel_wm_level *r;
2741
2742 level = ilk_wm_lp_to_level(wm_lp, merged);
2743
2744 r = &merged->wm[level];
2745 if (!r->enable)
2746 break;
2747
2748 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2749 ((level * 2) << WM1_LP_LATENCY_SHIFT) |
2750 (r->pri_val << WM1_LP_SR_SHIFT) |
2751 r->cur_val;
2752
2753 if (INTEL_INFO(dev)->gen >= 8)
2754 results->wm_lp[wm_lp - 1] |=
2755 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2756 else
2757 results->wm_lp[wm_lp - 1] |=
2758 r->fbc_val << WM1_LP_FBC_SHIFT;
2759
2760 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2761 }
2762
2763 /* LP0 register values */
2764 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2765 enum pipe pipe = intel_crtc->pipe;
2766 const struct intel_wm_level *r =
2767 &intel_crtc->wm.active.wm[0];
2768
2769 if (WARN_ON(!r->enable))
2770 continue;
2771
2772 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2773
2774 results->wm_pipe[pipe] =
2775 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2776 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2777 r->cur_val;
2778 }
2779 }
2780
2781 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2782 * case both are at the same level. Prefer r1 in case they're the same. */
2783 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2784 struct intel_pipe_wm *r1,
2785 struct intel_pipe_wm *r2)
2786 {
2787 int level, max_level = ilk_wm_max_level(dev);
2788 int level1 = 0, level2 = 0;
2789
2790 for (level = 1; level <= max_level; level++) {
2791 if (r1->wm[level].enable)
2792 level1 = level;
2793 if (r2->wm[level].enable)
2794 level2 = level;
2795 }
2796
2797 if (level1 == level2) {
2798 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2799 return r2;
2800 else
2801 return r1;
2802 } else if (level1 > level2) {
2803 return r1;
2804 } else {
2805 return r2;
2806 }
2807 }
2808
2809 /* dirty bits used to track which watermarks need changes */
2810 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2811 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2812 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2813 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2814 #define WM_DIRTY_FBC (1 << 24)
2815 #define WM_DIRTY_DDB (1 << 25)
2816
2817 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2818 const struct hsw_wm_values *old,
2819 const struct hsw_wm_values *new)
2820 {
2821 unsigned int dirty = 0;
2822 enum pipe pipe;
2823 int wm_lp;
2824
2825 for_each_pipe(pipe) {
2826 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2827 dirty |= WM_DIRTY_LINETIME(pipe);
2828 /* Must disable LP1+ watermarks too */
2829 dirty |= WM_DIRTY_LP_ALL;
2830 }
2831
2832 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2833 dirty |= WM_DIRTY_PIPE(pipe);
2834 /* Must disable LP1+ watermarks too */
2835 dirty |= WM_DIRTY_LP_ALL;
2836 }
2837 }
2838
2839 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2840 dirty |= WM_DIRTY_FBC;
2841 /* Must disable LP1+ watermarks too */
2842 dirty |= WM_DIRTY_LP_ALL;
2843 }
2844
2845 if (old->partitioning != new->partitioning) {
2846 dirty |= WM_DIRTY_DDB;
2847 /* Must disable LP1+ watermarks too */
2848 dirty |= WM_DIRTY_LP_ALL;
2849 }
2850
2851 /* LP1+ watermarks already deemed dirty, no need to continue */
2852 if (dirty & WM_DIRTY_LP_ALL)
2853 return dirty;
2854
2855 /* Find the lowest numbered LP1+ watermark in need of an update... */
2856 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2857 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2858 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2859 break;
2860 }
2861
2862 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2863 for (; wm_lp <= 3; wm_lp++)
2864 dirty |= WM_DIRTY_LP(wm_lp);
2865
2866 return dirty;
2867 }
2868
2869 /*
2870 * The spec says we shouldn't write when we don't need, because every write
2871 * causes WMs to be re-evaluated, expending some power.
2872 */
2873 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2874 struct hsw_wm_values *results)
2875 {
2876 struct hsw_wm_values *previous = &dev_priv->wm.hw;
2877 unsigned int dirty;
2878 uint32_t val;
2879
2880 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2881 if (!dirty)
2882 return;
2883
2884 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2885 I915_WRITE(WM3_LP_ILK, 0);
2886 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2887 I915_WRITE(WM2_LP_ILK, 0);
2888 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2889 I915_WRITE(WM1_LP_ILK, 0);
2890
2891 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2892 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2893 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2894 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2895 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2896 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2897
2898 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2899 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2900 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2901 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2902 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2903 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2904
2905 if (dirty & WM_DIRTY_DDB) {
2906 val = I915_READ(WM_MISC);
2907 if (results->partitioning == INTEL_DDB_PART_1_2)
2908 val &= ~WM_MISC_DATA_PARTITION_5_6;
2909 else
2910 val |= WM_MISC_DATA_PARTITION_5_6;
2911 I915_WRITE(WM_MISC, val);
2912 }
2913
2914 if (dirty & WM_DIRTY_FBC) {
2915 val = I915_READ(DISP_ARB_CTL);
2916 if (results->enable_fbc_wm)
2917 val &= ~DISP_FBC_WM_DIS;
2918 else
2919 val |= DISP_FBC_WM_DIS;
2920 I915_WRITE(DISP_ARB_CTL, val);
2921 }
2922
2923 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2924 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2925 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2926 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2927 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2928 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2929
2930 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2931 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2932 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2933 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2934 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2935 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2936
2937 dev_priv->wm.hw = *results;
2938 }
2939
2940 static void haswell_update_wm(struct drm_crtc *crtc)
2941 {
2942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct hsw_wm_maximums max;
2946 struct hsw_pipe_wm_parameters params = {};
2947 struct hsw_wm_values results = {};
2948 enum intel_ddb_partitioning partitioning;
2949 struct intel_pipe_wm pipe_wm = {};
2950 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2951 struct intel_wm_config config = {};
2952
2953 hsw_compute_wm_parameters(crtc, &params, &config);
2954
2955 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2956
2957 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2958 return;
2959
2960 intel_crtc->wm.active = pipe_wm;
2961
2962 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2963 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2964
2965 /* 5/6 split only in single pipe config on IVB+ */
2966 if (INTEL_INFO(dev)->gen >= 7 &&
2967 config.num_pipes_active == 1 && config.sprites_enabled) {
2968 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2969 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2970
2971 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2972 } else {
2973 best_lp_wm = &lp_wm_1_2;
2974 }
2975
2976 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2977 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2978
2979 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2980
2981 hsw_write_wm_values(dev_priv, &results);
2982 }
2983
2984 static void haswell_update_sprite_wm(struct drm_plane *plane,
2985 struct drm_crtc *crtc,
2986 uint32_t sprite_width, int pixel_size,
2987 bool enabled, bool scaled)
2988 {
2989 struct intel_plane *intel_plane = to_intel_plane(plane);
2990
2991 intel_plane->wm.enabled = enabled;
2992 intel_plane->wm.scaled = scaled;
2993 intel_plane->wm.horiz_pixels = sprite_width;
2994 intel_plane->wm.bytes_per_pixel = pixel_size;
2995
2996 haswell_update_wm(crtc);
2997 }
2998
2999 static bool
3000 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
3001 uint32_t sprite_width, int pixel_size,
3002 const struct intel_watermark_params *display,
3003 int display_latency_ns, int *sprite_wm)
3004 {
3005 struct drm_crtc *crtc;
3006 int clock;
3007 int entries, tlb_miss;
3008
3009 crtc = intel_get_crtc_for_plane(dev, plane);
3010 if (!intel_crtc_active(crtc)) {
3011 *sprite_wm = display->guard_size;
3012 return false;
3013 }
3014
3015 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3016
3017 /* Use the small buffer method to calculate the sprite watermark */
3018 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3019 tlb_miss = display->fifo_size*display->cacheline_size -
3020 sprite_width * 8;
3021 if (tlb_miss > 0)
3022 entries += tlb_miss;
3023 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3024 *sprite_wm = entries + display->guard_size;
3025 if (*sprite_wm > (int)display->max_wm)
3026 *sprite_wm = display->max_wm;
3027
3028 return true;
3029 }
3030
3031 static bool
3032 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3033 uint32_t sprite_width, int pixel_size,
3034 const struct intel_watermark_params *display,
3035 int latency_ns, int *sprite_wm)
3036 {
3037 struct drm_crtc *crtc;
3038 unsigned long line_time_us;
3039 int clock;
3040 int line_count, line_size;
3041 int small, large;
3042 int entries;
3043
3044 if (!latency_ns) {
3045 *sprite_wm = 0;
3046 return false;
3047 }
3048
3049 crtc = intel_get_crtc_for_plane(dev, plane);
3050 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3051 if (!clock) {
3052 *sprite_wm = 0;
3053 return false;
3054 }
3055
3056 line_time_us = (sprite_width * 1000) / clock;
3057 if (!line_time_us) {
3058 *sprite_wm = 0;
3059 return false;
3060 }
3061
3062 line_count = (latency_ns / line_time_us + 1000) / 1000;
3063 line_size = sprite_width * pixel_size;
3064
3065 /* Use the minimum of the small and large buffer method for primary */
3066 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3067 large = line_count * line_size;
3068
3069 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3070 *sprite_wm = entries + display->guard_size;
3071
3072 return *sprite_wm > 0x3ff ? false : true;
3073 }
3074
3075 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3076 struct drm_crtc *crtc,
3077 uint32_t sprite_width, int pixel_size,
3078 bool enabled, bool scaled)
3079 {
3080 struct drm_device *dev = plane->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 int pipe = to_intel_plane(plane)->pipe;
3083 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
3084 u32 val;
3085 int sprite_wm, reg;
3086 int ret;
3087
3088 if (!enabled)
3089 return;
3090
3091 switch (pipe) {
3092 case 0:
3093 reg = WM0_PIPEA_ILK;
3094 break;
3095 case 1:
3096 reg = WM0_PIPEB_ILK;
3097 break;
3098 case 2:
3099 reg = WM0_PIPEC_IVB;
3100 break;
3101 default:
3102 return; /* bad pipe */
3103 }
3104
3105 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3106 &sandybridge_display_wm_info,
3107 latency, &sprite_wm);
3108 if (!ret) {
3109 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3110 pipe_name(pipe));
3111 return;
3112 }
3113
3114 val = I915_READ(reg);
3115 val &= ~WM0_PIPE_SPRITE_MASK;
3116 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3117 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3118
3119
3120 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3121 pixel_size,
3122 &sandybridge_display_srwm_info,
3123 dev_priv->wm.spr_latency[1] * 500,
3124 &sprite_wm);
3125 if (!ret) {
3126 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3127 pipe_name(pipe));
3128 return;
3129 }
3130 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3131
3132 /* Only IVB has two more LP watermarks for sprite */
3133 if (!IS_IVYBRIDGE(dev))
3134 return;
3135
3136 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3137 pixel_size,
3138 &sandybridge_display_srwm_info,
3139 dev_priv->wm.spr_latency[2] * 500,
3140 &sprite_wm);
3141 if (!ret) {
3142 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3143 pipe_name(pipe));
3144 return;
3145 }
3146 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3147
3148 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3149 pixel_size,
3150 &sandybridge_display_srwm_info,
3151 dev_priv->wm.spr_latency[3] * 500,
3152 &sprite_wm);
3153 if (!ret) {
3154 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3155 pipe_name(pipe));
3156 return;
3157 }
3158 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3159 }
3160
3161 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3162 {
3163 struct drm_device *dev = crtc->dev;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3168 enum pipe pipe = intel_crtc->pipe;
3169 static const unsigned int wm0_pipe_reg[] = {
3170 [PIPE_A] = WM0_PIPEA_ILK,
3171 [PIPE_B] = WM0_PIPEB_ILK,
3172 [PIPE_C] = WM0_PIPEC_IVB,
3173 };
3174
3175 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3176 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3177
3178 if (intel_crtc_active(crtc)) {
3179 u32 tmp = hw->wm_pipe[pipe];
3180
3181 /*
3182 * For active pipes LP0 watermark is marked as
3183 * enabled, and LP1+ watermaks as disabled since
3184 * we can't really reverse compute them in case
3185 * multiple pipes are active.
3186 */
3187 active->wm[0].enable = true;
3188 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3189 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3190 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3191 active->linetime = hw->wm_linetime[pipe];
3192 } else {
3193 int level, max_level = ilk_wm_max_level(dev);
3194
3195 /*
3196 * For inactive pipes, all watermark levels
3197 * should be marked as enabled but zeroed,
3198 * which is what we'd compute them to.
3199 */
3200 for (level = 0; level <= max_level; level++)
3201 active->wm[level].enable = true;
3202 }
3203 }
3204
3205 void ilk_wm_get_hw_state(struct drm_device *dev)
3206 {
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3209 struct drm_crtc *crtc;
3210
3211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3212 ilk_pipe_wm_get_hw_state(crtc);
3213
3214 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3215 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3216 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3217
3218 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3219 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3220 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3221
3222 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3223 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3224
3225 hw->enable_fbc_wm =
3226 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3227 }
3228
3229 /**
3230 * intel_update_watermarks - update FIFO watermark values based on current modes
3231 *
3232 * Calculate watermark values for the various WM regs based on current mode
3233 * and plane configuration.
3234 *
3235 * There are several cases to deal with here:
3236 * - normal (i.e. non-self-refresh)
3237 * - self-refresh (SR) mode
3238 * - lines are large relative to FIFO size (buffer can hold up to 2)
3239 * - lines are small relative to FIFO size (buffer can hold more than 2
3240 * lines), so need to account for TLB latency
3241 *
3242 * The normal calculation is:
3243 * watermark = dotclock * bytes per pixel * latency
3244 * where latency is platform & configuration dependent (we assume pessimal
3245 * values here).
3246 *
3247 * The SR calculation is:
3248 * watermark = (trunc(latency/line time)+1) * surface width *
3249 * bytes per pixel
3250 * where
3251 * line time = htotal / dotclock
3252 * surface width = hdisplay for normal plane and 64 for cursor
3253 * and latency is assumed to be high, as above.
3254 *
3255 * The final value programmed to the register should always be rounded up,
3256 * and include an extra 2 entries to account for clock crossings.
3257 *
3258 * We don't use the sprite, so we can ignore that. And on Crestline we have
3259 * to set the non-SR watermarks to 8.
3260 */
3261 void intel_update_watermarks(struct drm_crtc *crtc)
3262 {
3263 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3264
3265 if (dev_priv->display.update_wm)
3266 dev_priv->display.update_wm(crtc);
3267 }
3268
3269 void intel_update_sprite_watermarks(struct drm_plane *plane,
3270 struct drm_crtc *crtc,
3271 uint32_t sprite_width, int pixel_size,
3272 bool enabled, bool scaled)
3273 {
3274 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3275
3276 if (dev_priv->display.update_sprite_wm)
3277 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3278 pixel_size, enabled, scaled);
3279 }
3280
3281 static struct drm_i915_gem_object *
3282 intel_alloc_context_page(struct drm_device *dev)
3283 {
3284 struct drm_i915_gem_object *ctx;
3285 int ret;
3286
3287 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3288
3289 ctx = i915_gem_alloc_object(dev, 4096);
3290 if (!ctx) {
3291 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3292 return NULL;
3293 }
3294
3295 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3296 if (ret) {
3297 DRM_ERROR("failed to pin power context: %d\n", ret);
3298 goto err_unref;
3299 }
3300
3301 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3302 if (ret) {
3303 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3304 goto err_unpin;
3305 }
3306
3307 return ctx;
3308
3309 err_unpin:
3310 i915_gem_object_unpin(ctx);
3311 err_unref:
3312 drm_gem_object_unreference(&ctx->base);
3313 return NULL;
3314 }
3315
3316 /**
3317 * Lock protecting IPS related data structures
3318 */
3319 DEFINE_SPINLOCK(mchdev_lock);
3320
3321 /* Global for IPS driver to get at the current i915 device. Protected by
3322 * mchdev_lock. */
3323 static struct drm_i915_private *i915_mch_dev;
3324
3325 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3326 {
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 u16 rgvswctl;
3329
3330 assert_spin_locked(&mchdev_lock);
3331
3332 rgvswctl = I915_READ16(MEMSWCTL);
3333 if (rgvswctl & MEMCTL_CMD_STS) {
3334 DRM_DEBUG("gpu busy, RCS change rejected\n");
3335 return false; /* still busy with another command */
3336 }
3337
3338 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3339 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3340 I915_WRITE16(MEMSWCTL, rgvswctl);
3341 POSTING_READ16(MEMSWCTL);
3342
3343 rgvswctl |= MEMCTL_CMD_STS;
3344 I915_WRITE16(MEMSWCTL, rgvswctl);
3345
3346 return true;
3347 }
3348
3349 static void ironlake_enable_drps(struct drm_device *dev)
3350 {
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352 u32 rgvmodectl = I915_READ(MEMMODECTL);
3353 u8 fmax, fmin, fstart, vstart;
3354
3355 spin_lock_irq(&mchdev_lock);
3356
3357 /* Enable temp reporting */
3358 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3359 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3360
3361 /* 100ms RC evaluation intervals */
3362 I915_WRITE(RCUPEI, 100000);
3363 I915_WRITE(RCDNEI, 100000);
3364
3365 /* Set max/min thresholds to 90ms and 80ms respectively */
3366 I915_WRITE(RCBMAXAVG, 90000);
3367 I915_WRITE(RCBMINAVG, 80000);
3368
3369 I915_WRITE(MEMIHYST, 1);
3370
3371 /* Set up min, max, and cur for interrupt handling */
3372 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3373 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3374 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3375 MEMMODE_FSTART_SHIFT;
3376
3377 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3378 PXVFREQ_PX_SHIFT;
3379
3380 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3381 dev_priv->ips.fstart = fstart;
3382
3383 dev_priv->ips.max_delay = fstart;
3384 dev_priv->ips.min_delay = fmin;
3385 dev_priv->ips.cur_delay = fstart;
3386
3387 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3388 fmax, fmin, fstart);
3389
3390 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3391
3392 /*
3393 * Interrupts will be enabled in ironlake_irq_postinstall
3394 */
3395
3396 I915_WRITE(VIDSTART, vstart);
3397 POSTING_READ(VIDSTART);
3398
3399 rgvmodectl |= MEMMODE_SWMODE_EN;
3400 I915_WRITE(MEMMODECTL, rgvmodectl);
3401
3402 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3403 DRM_ERROR("stuck trying to change perf mode\n");
3404 mdelay(1);
3405
3406 ironlake_set_drps(dev, fstart);
3407
3408 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3409 I915_READ(0x112e0);
3410 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3411 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3412 getrawmonotonic(&dev_priv->ips.last_time2);
3413
3414 spin_unlock_irq(&mchdev_lock);
3415 }
3416
3417 static void ironlake_disable_drps(struct drm_device *dev)
3418 {
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 u16 rgvswctl;
3421
3422 spin_lock_irq(&mchdev_lock);
3423
3424 rgvswctl = I915_READ16(MEMSWCTL);
3425
3426 /* Ack interrupts, disable EFC interrupt */
3427 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3428 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3429 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3430 I915_WRITE(DEIIR, DE_PCU_EVENT);
3431 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3432
3433 /* Go back to the starting frequency */
3434 ironlake_set_drps(dev, dev_priv->ips.fstart);
3435 mdelay(1);
3436 rgvswctl |= MEMCTL_CMD_STS;
3437 I915_WRITE(MEMSWCTL, rgvswctl);
3438 mdelay(1);
3439
3440 spin_unlock_irq(&mchdev_lock);
3441 }
3442
3443 /* There's a funny hw issue where the hw returns all 0 when reading from
3444 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3445 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3446 * all limits and the gpu stuck at whatever frequency it is at atm).
3447 */
3448 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3449 {
3450 u32 limits;
3451
3452 /* Only set the down limit when we've reached the lowest level to avoid
3453 * getting more interrupts, otherwise leave this clear. This prevents a
3454 * race in the hw when coming out of rc6: There's a tiny window where
3455 * the hw runs at the minimal clock before selecting the desired
3456 * frequency, if the down threshold expires in that window we will not
3457 * receive a down interrupt. */
3458 limits = dev_priv->rps.max_delay << 24;
3459 if (val <= dev_priv->rps.min_delay)
3460 limits |= dev_priv->rps.min_delay << 16;
3461
3462 return limits;
3463 }
3464
3465 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3466 {
3467 int new_power;
3468
3469 new_power = dev_priv->rps.power;
3470 switch (dev_priv->rps.power) {
3471 case LOW_POWER:
3472 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3473 new_power = BETWEEN;
3474 break;
3475
3476 case BETWEEN:
3477 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3478 new_power = LOW_POWER;
3479 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3480 new_power = HIGH_POWER;
3481 break;
3482
3483 case HIGH_POWER:
3484 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3485 new_power = BETWEEN;
3486 break;
3487 }
3488 /* Max/min bins are special */
3489 if (val == dev_priv->rps.min_delay)
3490 new_power = LOW_POWER;
3491 if (val == dev_priv->rps.max_delay)
3492 new_power = HIGH_POWER;
3493 if (new_power == dev_priv->rps.power)
3494 return;
3495
3496 /* Note the units here are not exactly 1us, but 1280ns. */
3497 switch (new_power) {
3498 case LOW_POWER:
3499 /* Upclock if more than 95% busy over 16ms */
3500 I915_WRITE(GEN6_RP_UP_EI, 12500);
3501 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3502
3503 /* Downclock if less than 85% busy over 32ms */
3504 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3505 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3506
3507 I915_WRITE(GEN6_RP_CONTROL,
3508 GEN6_RP_MEDIA_TURBO |
3509 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3510 GEN6_RP_MEDIA_IS_GFX |
3511 GEN6_RP_ENABLE |
3512 GEN6_RP_UP_BUSY_AVG |
3513 GEN6_RP_DOWN_IDLE_AVG);
3514 break;
3515
3516 case BETWEEN:
3517 /* Upclock if more than 90% busy over 13ms */
3518 I915_WRITE(GEN6_RP_UP_EI, 10250);
3519 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3520
3521 /* Downclock if less than 75% busy over 32ms */
3522 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3523 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3524
3525 I915_WRITE(GEN6_RP_CONTROL,
3526 GEN6_RP_MEDIA_TURBO |
3527 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3528 GEN6_RP_MEDIA_IS_GFX |
3529 GEN6_RP_ENABLE |
3530 GEN6_RP_UP_BUSY_AVG |
3531 GEN6_RP_DOWN_IDLE_AVG);
3532 break;
3533
3534 case HIGH_POWER:
3535 /* Upclock if more than 85% busy over 10ms */
3536 I915_WRITE(GEN6_RP_UP_EI, 8000);
3537 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3538
3539 /* Downclock if less than 60% busy over 32ms */
3540 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3541 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3542
3543 I915_WRITE(GEN6_RP_CONTROL,
3544 GEN6_RP_MEDIA_TURBO |
3545 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3546 GEN6_RP_MEDIA_IS_GFX |
3547 GEN6_RP_ENABLE |
3548 GEN6_RP_UP_BUSY_AVG |
3549 GEN6_RP_DOWN_IDLE_AVG);
3550 break;
3551 }
3552
3553 dev_priv->rps.power = new_power;
3554 dev_priv->rps.last_adj = 0;
3555 }
3556
3557 void gen6_set_rps(struct drm_device *dev, u8 val)
3558 {
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560
3561 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3562 WARN_ON(val > dev_priv->rps.max_delay);
3563 WARN_ON(val < dev_priv->rps.min_delay);
3564
3565 if (val == dev_priv->rps.cur_delay)
3566 return;
3567
3568 gen6_set_rps_thresholds(dev_priv, val);
3569
3570 if (IS_HASWELL(dev))
3571 I915_WRITE(GEN6_RPNSWREQ,
3572 HSW_FREQUENCY(val));
3573 else
3574 I915_WRITE(GEN6_RPNSWREQ,
3575 GEN6_FREQUENCY(val) |
3576 GEN6_OFFSET(0) |
3577 GEN6_AGGRESSIVE_TURBO);
3578
3579 /* Make sure we continue to get interrupts
3580 * until we hit the minimum or maximum frequencies.
3581 */
3582 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3583 gen6_rps_limits(dev_priv, val));
3584
3585 POSTING_READ(GEN6_RPNSWREQ);
3586
3587 dev_priv->rps.cur_delay = val;
3588
3589 trace_intel_gpu_freq_change(val * 50);
3590 }
3591
3592 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3593 {
3594 mutex_lock(&dev_priv->rps.hw_lock);
3595 if (dev_priv->rps.enabled) {
3596 if (dev_priv->info->is_valleyview)
3597 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3598 else
3599 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3600 dev_priv->rps.last_adj = 0;
3601 }
3602 mutex_unlock(&dev_priv->rps.hw_lock);
3603 }
3604
3605 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3606 {
3607 mutex_lock(&dev_priv->rps.hw_lock);
3608 if (dev_priv->rps.enabled) {
3609 if (dev_priv->info->is_valleyview)
3610 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3611 else
3612 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3613 dev_priv->rps.last_adj = 0;
3614 }
3615 mutex_unlock(&dev_priv->rps.hw_lock);
3616 }
3617
3618 void valleyview_set_rps(struct drm_device *dev, u8 val)
3619 {
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621
3622 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3623 WARN_ON(val > dev_priv->rps.max_delay);
3624 WARN_ON(val < dev_priv->rps.min_delay);
3625
3626 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3627 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3628 dev_priv->rps.cur_delay,
3629 vlv_gpu_freq(dev_priv, val), val);
3630
3631 if (val == dev_priv->rps.cur_delay)
3632 return;
3633
3634 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3635
3636 dev_priv->rps.cur_delay = val;
3637
3638 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3639 }
3640
3641 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3642 {
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644
3645 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3646 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3647 /* Complete PM interrupt masking here doesn't race with the rps work
3648 * item again unmasking PM interrupts because that is using a different
3649 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3650 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3651
3652 spin_lock_irq(&dev_priv->irq_lock);
3653 dev_priv->rps.pm_iir = 0;
3654 spin_unlock_irq(&dev_priv->irq_lock);
3655
3656 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3657 }
3658
3659 static void gen6_disable_rps(struct drm_device *dev)
3660 {
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662
3663 I915_WRITE(GEN6_RC_CONTROL, 0);
3664 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3665
3666 gen6_disable_rps_interrupts(dev);
3667 }
3668
3669 static void valleyview_disable_rps(struct drm_device *dev)
3670 {
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672
3673 I915_WRITE(GEN6_RC_CONTROL, 0);
3674
3675 gen6_disable_rps_interrupts(dev);
3676
3677 if (dev_priv->vlv_pctx) {
3678 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3679 dev_priv->vlv_pctx = NULL;
3680 }
3681 }
3682
3683 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3684 {
3685 if (IS_GEN6(dev))
3686 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3687
3688 if (IS_HASWELL(dev))
3689 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3690
3691 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3692 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3693 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3694 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3695 }
3696
3697 int intel_enable_rc6(const struct drm_device *dev)
3698 {
3699 /* No RC6 before Ironlake */
3700 if (INTEL_INFO(dev)->gen < 5)
3701 return 0;
3702
3703 /* Respect the kernel parameter if it is set */
3704 if (i915_enable_rc6 >= 0)
3705 return i915_enable_rc6;
3706
3707 /* Disable RC6 on Ironlake */
3708 if (INTEL_INFO(dev)->gen == 5)
3709 return 0;
3710
3711 if (IS_HASWELL(dev))
3712 return INTEL_RC6_ENABLE;
3713
3714 /* snb/ivb have more than one rc6 state. */
3715 if (INTEL_INFO(dev)->gen == 6)
3716 return INTEL_RC6_ENABLE;
3717
3718 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3719 }
3720
3721 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3722 {
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 u32 enabled_intrs;
3725
3726 spin_lock_irq(&dev_priv->irq_lock);
3727 WARN_ON(dev_priv->rps.pm_iir);
3728 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3729 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3730 spin_unlock_irq(&dev_priv->irq_lock);
3731
3732 /* only unmask PM interrupts we need. Mask all others. */
3733 enabled_intrs = GEN6_PM_RPS_EVENTS;
3734
3735 /* IVB and SNB hard hangs on looping batchbuffer
3736 * if GEN6_PM_UP_EI_EXPIRED is masked.
3737 */
3738 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3739 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3740
3741 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3742 }
3743
3744 static void gen8_enable_rps(struct drm_device *dev)
3745 {
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 struct intel_ring_buffer *ring;
3748 uint32_t rc6_mask = 0, rp_state_cap;
3749 int unused;
3750
3751 /* 1a: Software RC state - RC0 */
3752 I915_WRITE(GEN6_RC_STATE, 0);
3753
3754 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3755 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3756 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3757
3758 /* 2a: Disable RC states. */
3759 I915_WRITE(GEN6_RC_CONTROL, 0);
3760
3761 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3762
3763 /* 2b: Program RC6 thresholds.*/
3764 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3765 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3766 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3767 for_each_ring(ring, dev_priv, unused)
3768 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3769 I915_WRITE(GEN6_RC_SLEEP, 0);
3770 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3771
3772 /* 3: Enable RC6 */
3773 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3774 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3775 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3776 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3777 GEN6_RC_CTL_EI_MODE(1) |
3778 rc6_mask);
3779
3780 /* 4 Program defaults and thresholds for RPS*/
3781 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3782 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3783 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3784 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3785
3786 /* Docs recommend 900MHz, and 300 MHz respectively */
3787 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3788 dev_priv->rps.max_delay << 24 |
3789 dev_priv->rps.min_delay << 16);
3790
3791 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3792 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3793 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3794 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3795
3796 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3797
3798 /* 5: Enable RPS */
3799 I915_WRITE(GEN6_RP_CONTROL,
3800 GEN6_RP_MEDIA_TURBO |
3801 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3802 GEN6_RP_MEDIA_IS_GFX |
3803 GEN6_RP_ENABLE |
3804 GEN6_RP_UP_BUSY_AVG |
3805 GEN6_RP_DOWN_IDLE_AVG);
3806
3807 /* 6: Ring frequency + overclocking (our driver does this later */
3808
3809 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3810
3811 gen6_enable_rps_interrupts(dev);
3812
3813 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3814 }
3815
3816 static void gen6_enable_rps(struct drm_device *dev)
3817 {
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 struct intel_ring_buffer *ring;
3820 u32 rp_state_cap;
3821 u32 gt_perf_status;
3822 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3823 u32 gtfifodbg;
3824 int rc6_mode;
3825 int i, ret;
3826
3827 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3828
3829 /* Here begins a magic sequence of register writes to enable
3830 * auto-downclocking.
3831 *
3832 * Perhaps there might be some value in exposing these to
3833 * userspace...
3834 */
3835 I915_WRITE(GEN6_RC_STATE, 0);
3836
3837 /* Clear the DBG now so we don't confuse earlier errors */
3838 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3839 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3840 I915_WRITE(GTFIFODBG, gtfifodbg);
3841 }
3842
3843 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3844
3845 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3846 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3847
3848 /* In units of 50MHz */
3849 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3850 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3851 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3852 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3853 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3854 dev_priv->rps.cur_delay = 0;
3855
3856 /* disable the counters and set deterministic thresholds */
3857 I915_WRITE(GEN6_RC_CONTROL, 0);
3858
3859 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3860 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3861 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3862 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3863 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3864
3865 for_each_ring(ring, dev_priv, i)
3866 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3867
3868 I915_WRITE(GEN6_RC_SLEEP, 0);
3869 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3870 if (IS_IVYBRIDGE(dev))
3871 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3872 else
3873 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3874 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3875 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3876
3877 /* Check if we are enabling RC6 */
3878 rc6_mode = intel_enable_rc6(dev_priv->dev);
3879 if (rc6_mode & INTEL_RC6_ENABLE)
3880 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3881
3882 /* We don't use those on Haswell */
3883 if (!IS_HASWELL(dev)) {
3884 if (rc6_mode & INTEL_RC6p_ENABLE)
3885 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3886
3887 if (rc6_mode & INTEL_RC6pp_ENABLE)
3888 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3889 }
3890
3891 intel_print_rc6_info(dev, rc6_mask);
3892
3893 I915_WRITE(GEN6_RC_CONTROL,
3894 rc6_mask |
3895 GEN6_RC_CTL_EI_MODE(1) |
3896 GEN6_RC_CTL_HW_ENABLE);
3897
3898 /* Power down if completely idle for over 50ms */
3899 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3900 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3901
3902 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3903 if (!ret) {
3904 pcu_mbox = 0;
3905 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3906 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3907 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3908 (dev_priv->rps.max_delay & 0xff) * 50,
3909 (pcu_mbox & 0xff) * 50);
3910 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3911 }
3912 } else {
3913 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3914 }
3915
3916 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3917 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3918
3919 gen6_enable_rps_interrupts(dev);
3920
3921 rc6vids = 0;
3922 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3923 if (IS_GEN6(dev) && ret) {
3924 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3925 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3926 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3927 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3928 rc6vids &= 0xffff00;
3929 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3930 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3931 if (ret)
3932 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3933 }
3934
3935 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3936 }
3937
3938 void gen6_update_ring_freq(struct drm_device *dev)
3939 {
3940 struct drm_i915_private *dev_priv = dev->dev_private;
3941 int min_freq = 15;
3942 unsigned int gpu_freq;
3943 unsigned int max_ia_freq, min_ring_freq;
3944 int scaling_factor = 180;
3945 struct cpufreq_policy *policy;
3946
3947 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3948
3949 policy = cpufreq_cpu_get(0);
3950 if (policy) {
3951 max_ia_freq = policy->cpuinfo.max_freq;
3952 cpufreq_cpu_put(policy);
3953 } else {
3954 /*
3955 * Default to measured freq if none found, PCU will ensure we
3956 * don't go over
3957 */
3958 max_ia_freq = tsc_khz;
3959 }
3960
3961 /* Convert from kHz to MHz */
3962 max_ia_freq /= 1000;
3963
3964 min_ring_freq = I915_READ(DCLK) & 0xf;
3965 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3966 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3967
3968 /*
3969 * For each potential GPU frequency, load a ring frequency we'd like
3970 * to use for memory access. We do this by specifying the IA frequency
3971 * the PCU should use as a reference to determine the ring frequency.
3972 */
3973 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3974 gpu_freq--) {
3975 int diff = dev_priv->rps.max_delay - gpu_freq;
3976 unsigned int ia_freq = 0, ring_freq = 0;
3977
3978 if (INTEL_INFO(dev)->gen >= 8) {
3979 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3980 ring_freq = max(min_ring_freq, gpu_freq);
3981 } else if (IS_HASWELL(dev)) {
3982 ring_freq = mult_frac(gpu_freq, 5, 4);
3983 ring_freq = max(min_ring_freq, ring_freq);
3984 /* leave ia_freq as the default, chosen by cpufreq */
3985 } else {
3986 /* On older processors, there is no separate ring
3987 * clock domain, so in order to boost the bandwidth
3988 * of the ring, we need to upclock the CPU (ia_freq).
3989 *
3990 * For GPU frequencies less than 750MHz,
3991 * just use the lowest ring freq.
3992 */
3993 if (gpu_freq < min_freq)
3994 ia_freq = 800;
3995 else
3996 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3997 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3998 }
3999
4000 sandybridge_pcode_write(dev_priv,
4001 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4002 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4003 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4004 gpu_freq);
4005 }
4006 }
4007
4008 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4009 {
4010 u32 val, rp0;
4011
4012 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4013
4014 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4015 /* Clamp to max */
4016 rp0 = min_t(u32, rp0, 0xea);
4017
4018 return rp0;
4019 }
4020
4021 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4022 {
4023 u32 val, rpe;
4024
4025 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4026 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4027 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4028 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4029
4030 return rpe;
4031 }
4032
4033 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4034 {
4035 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4036 }
4037
4038 static void valleyview_setup_pctx(struct drm_device *dev)
4039 {
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 struct drm_i915_gem_object *pctx;
4042 unsigned long pctx_paddr;
4043 u32 pcbr;
4044 int pctx_size = 24*1024;
4045
4046 pcbr = I915_READ(VLV_PCBR);
4047 if (pcbr) {
4048 /* BIOS set it up already, grab the pre-alloc'd space */
4049 int pcbr_offset;
4050
4051 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4052 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4053 pcbr_offset,
4054 I915_GTT_OFFSET_NONE,
4055 pctx_size);
4056 goto out;
4057 }
4058
4059 /*
4060 * From the Gunit register HAS:
4061 * The Gfx driver is expected to program this register and ensure
4062 * proper allocation within Gfx stolen memory. For example, this
4063 * register should be programmed such than the PCBR range does not
4064 * overlap with other ranges, such as the frame buffer, protected
4065 * memory, or any other relevant ranges.
4066 */
4067 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4068 if (!pctx) {
4069 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4070 return;
4071 }
4072
4073 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4074 I915_WRITE(VLV_PCBR, pctx_paddr);
4075
4076 out:
4077 dev_priv->vlv_pctx = pctx;
4078 }
4079
4080 static void valleyview_enable_rps(struct drm_device *dev)
4081 {
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083 struct intel_ring_buffer *ring;
4084 u32 gtfifodbg, val, rc6_mode = 0;
4085 int i;
4086
4087 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4088
4089 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4090 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4091 gtfifodbg);
4092 I915_WRITE(GTFIFODBG, gtfifodbg);
4093 }
4094
4095 valleyview_setup_pctx(dev);
4096
4097 /* If VLV, Forcewake all wells, else re-direct to regular path */
4098 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4099
4100 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4101 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4102 I915_WRITE(GEN6_RP_UP_EI, 66000);
4103 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4104
4105 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4106
4107 I915_WRITE(GEN6_RP_CONTROL,
4108 GEN6_RP_MEDIA_TURBO |
4109 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4110 GEN6_RP_MEDIA_IS_GFX |
4111 GEN6_RP_ENABLE |
4112 GEN6_RP_UP_BUSY_AVG |
4113 GEN6_RP_DOWN_IDLE_CONT);
4114
4115 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4116 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4117 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4118
4119 for_each_ring(ring, dev_priv, i)
4120 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4121
4122 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4123
4124 /* allows RC6 residency counter to work */
4125 I915_WRITE(VLV_COUNTER_CONTROL,
4126 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4127 VLV_MEDIA_RC6_COUNT_EN |
4128 VLV_RENDER_RC6_COUNT_EN));
4129 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4130 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4131
4132 intel_print_rc6_info(dev, rc6_mode);
4133
4134 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4135
4136 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4137
4138 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4139 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4140
4141 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4142 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4143 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4144 dev_priv->rps.cur_delay);
4145
4146 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4147 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4148 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4149 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4150 dev_priv->rps.max_delay);
4151
4152 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4153 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4154 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4155 dev_priv->rps.rpe_delay);
4156
4157 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4158 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4159 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4160 dev_priv->rps.min_delay);
4161
4162 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4163 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4164 dev_priv->rps.rpe_delay);
4165
4166 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4167
4168 gen6_enable_rps_interrupts(dev);
4169
4170 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4171 }
4172
4173 void ironlake_teardown_rc6(struct drm_device *dev)
4174 {
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176
4177 if (dev_priv->ips.renderctx) {
4178 i915_gem_object_unpin(dev_priv->ips.renderctx);
4179 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4180 dev_priv->ips.renderctx = NULL;
4181 }
4182
4183 if (dev_priv->ips.pwrctx) {
4184 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4185 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4186 dev_priv->ips.pwrctx = NULL;
4187 }
4188 }
4189
4190 static void ironlake_disable_rc6(struct drm_device *dev)
4191 {
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193
4194 if (I915_READ(PWRCTXA)) {
4195 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4196 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4197 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4198 50);
4199
4200 I915_WRITE(PWRCTXA, 0);
4201 POSTING_READ(PWRCTXA);
4202
4203 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4204 POSTING_READ(RSTDBYCTL);
4205 }
4206 }
4207
4208 static int ironlake_setup_rc6(struct drm_device *dev)
4209 {
4210 struct drm_i915_private *dev_priv = dev->dev_private;
4211
4212 if (dev_priv->ips.renderctx == NULL)
4213 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4214 if (!dev_priv->ips.renderctx)
4215 return -ENOMEM;
4216
4217 if (dev_priv->ips.pwrctx == NULL)
4218 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4219 if (!dev_priv->ips.pwrctx) {
4220 ironlake_teardown_rc6(dev);
4221 return -ENOMEM;
4222 }
4223
4224 return 0;
4225 }
4226
4227 static void ironlake_enable_rc6(struct drm_device *dev)
4228 {
4229 struct drm_i915_private *dev_priv = dev->dev_private;
4230 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4231 bool was_interruptible;
4232 int ret;
4233
4234 /* rc6 disabled by default due to repeated reports of hanging during
4235 * boot and resume.
4236 */
4237 if (!intel_enable_rc6(dev))
4238 return;
4239
4240 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4241
4242 ret = ironlake_setup_rc6(dev);
4243 if (ret)
4244 return;
4245
4246 was_interruptible = dev_priv->mm.interruptible;
4247 dev_priv->mm.interruptible = false;
4248
4249 /*
4250 * GPU can automatically power down the render unit if given a page
4251 * to save state.
4252 */
4253 ret = intel_ring_begin(ring, 6);
4254 if (ret) {
4255 ironlake_teardown_rc6(dev);
4256 dev_priv->mm.interruptible = was_interruptible;
4257 return;
4258 }
4259
4260 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4261 intel_ring_emit(ring, MI_SET_CONTEXT);
4262 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4263 MI_MM_SPACE_GTT |
4264 MI_SAVE_EXT_STATE_EN |
4265 MI_RESTORE_EXT_STATE_EN |
4266 MI_RESTORE_INHIBIT);
4267 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4268 intel_ring_emit(ring, MI_NOOP);
4269 intel_ring_emit(ring, MI_FLUSH);
4270 intel_ring_advance(ring);
4271
4272 /*
4273 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4274 * does an implicit flush, combined with MI_FLUSH above, it should be
4275 * safe to assume that renderctx is valid
4276 */
4277 ret = intel_ring_idle(ring);
4278 dev_priv->mm.interruptible = was_interruptible;
4279 if (ret) {
4280 DRM_ERROR("failed to enable ironlake power savings\n");
4281 ironlake_teardown_rc6(dev);
4282 return;
4283 }
4284
4285 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4286 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4287
4288 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4289 }
4290
4291 static unsigned long intel_pxfreq(u32 vidfreq)
4292 {
4293 unsigned long freq;
4294 int div = (vidfreq & 0x3f0000) >> 16;
4295 int post = (vidfreq & 0x3000) >> 12;
4296 int pre = (vidfreq & 0x7);
4297
4298 if (!pre)
4299 return 0;
4300
4301 freq = ((div * 133333) / ((1<<post) * pre));
4302
4303 return freq;
4304 }
4305
4306 static const struct cparams {
4307 u16 i;
4308 u16 t;
4309 u16 m;
4310 u16 c;
4311 } cparams[] = {
4312 { 1, 1333, 301, 28664 },
4313 { 1, 1066, 294, 24460 },
4314 { 1, 800, 294, 25192 },
4315 { 0, 1333, 276, 27605 },
4316 { 0, 1066, 276, 27605 },
4317 { 0, 800, 231, 23784 },
4318 };
4319
4320 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4321 {
4322 u64 total_count, diff, ret;
4323 u32 count1, count2, count3, m = 0, c = 0;
4324 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4325 int i;
4326
4327 assert_spin_locked(&mchdev_lock);
4328
4329 diff1 = now - dev_priv->ips.last_time1;
4330
4331 /* Prevent division-by-zero if we are asking too fast.
4332 * Also, we don't get interesting results if we are polling
4333 * faster than once in 10ms, so just return the saved value
4334 * in such cases.
4335 */
4336 if (diff1 <= 10)
4337 return dev_priv->ips.chipset_power;
4338
4339 count1 = I915_READ(DMIEC);
4340 count2 = I915_READ(DDREC);
4341 count3 = I915_READ(CSIEC);
4342
4343 total_count = count1 + count2 + count3;
4344
4345 /* FIXME: handle per-counter overflow */
4346 if (total_count < dev_priv->ips.last_count1) {
4347 diff = ~0UL - dev_priv->ips.last_count1;
4348 diff += total_count;
4349 } else {
4350 diff = total_count - dev_priv->ips.last_count1;
4351 }
4352
4353 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4354 if (cparams[i].i == dev_priv->ips.c_m &&
4355 cparams[i].t == dev_priv->ips.r_t) {
4356 m = cparams[i].m;
4357 c = cparams[i].c;
4358 break;
4359 }
4360 }
4361
4362 diff = div_u64(diff, diff1);
4363 ret = ((m * diff) + c);
4364 ret = div_u64(ret, 10);
4365
4366 dev_priv->ips.last_count1 = total_count;
4367 dev_priv->ips.last_time1 = now;
4368
4369 dev_priv->ips.chipset_power = ret;
4370
4371 return ret;
4372 }
4373
4374 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4375 {
4376 unsigned long val;
4377
4378 if (dev_priv->info->gen != 5)
4379 return 0;
4380
4381 spin_lock_irq(&mchdev_lock);
4382
4383 val = __i915_chipset_val(dev_priv);
4384
4385 spin_unlock_irq(&mchdev_lock);
4386
4387 return val;
4388 }
4389
4390 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4391 {
4392 unsigned long m, x, b;
4393 u32 tsfs;
4394
4395 tsfs = I915_READ(TSFS);
4396
4397 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4398 x = I915_READ8(TR1);
4399
4400 b = tsfs & TSFS_INTR_MASK;
4401
4402 return ((m * x) / 127) - b;
4403 }
4404
4405 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4406 {
4407 static const struct v_table {
4408 u16 vd; /* in .1 mil */
4409 u16 vm; /* in .1 mil */
4410 } v_table[] = {
4411 { 0, 0, },
4412 { 375, 0, },
4413 { 500, 0, },
4414 { 625, 0, },
4415 { 750, 0, },
4416 { 875, 0, },
4417 { 1000, 0, },
4418 { 1125, 0, },
4419 { 4125, 3000, },
4420 { 4125, 3000, },
4421 { 4125, 3000, },
4422 { 4125, 3000, },
4423 { 4125, 3000, },
4424 { 4125, 3000, },
4425 { 4125, 3000, },
4426 { 4125, 3000, },
4427 { 4125, 3000, },
4428 { 4125, 3000, },
4429 { 4125, 3000, },
4430 { 4125, 3000, },
4431 { 4125, 3000, },
4432 { 4125, 3000, },
4433 { 4125, 3000, },
4434 { 4125, 3000, },
4435 { 4125, 3000, },
4436 { 4125, 3000, },
4437 { 4125, 3000, },
4438 { 4125, 3000, },
4439 { 4125, 3000, },
4440 { 4125, 3000, },
4441 { 4125, 3000, },
4442 { 4125, 3000, },
4443 { 4250, 3125, },
4444 { 4375, 3250, },
4445 { 4500, 3375, },
4446 { 4625, 3500, },
4447 { 4750, 3625, },
4448 { 4875, 3750, },
4449 { 5000, 3875, },
4450 { 5125, 4000, },
4451 { 5250, 4125, },
4452 { 5375, 4250, },
4453 { 5500, 4375, },
4454 { 5625, 4500, },
4455 { 5750, 4625, },
4456 { 5875, 4750, },
4457 { 6000, 4875, },
4458 { 6125, 5000, },
4459 { 6250, 5125, },
4460 { 6375, 5250, },
4461 { 6500, 5375, },
4462 { 6625, 5500, },
4463 { 6750, 5625, },
4464 { 6875, 5750, },
4465 { 7000, 5875, },
4466 { 7125, 6000, },
4467 { 7250, 6125, },
4468 { 7375, 6250, },
4469 { 7500, 6375, },
4470 { 7625, 6500, },
4471 { 7750, 6625, },
4472 { 7875, 6750, },
4473 { 8000, 6875, },
4474 { 8125, 7000, },
4475 { 8250, 7125, },
4476 { 8375, 7250, },
4477 { 8500, 7375, },
4478 { 8625, 7500, },
4479 { 8750, 7625, },
4480 { 8875, 7750, },
4481 { 9000, 7875, },
4482 { 9125, 8000, },
4483 { 9250, 8125, },
4484 { 9375, 8250, },
4485 { 9500, 8375, },
4486 { 9625, 8500, },
4487 { 9750, 8625, },
4488 { 9875, 8750, },
4489 { 10000, 8875, },
4490 { 10125, 9000, },
4491 { 10250, 9125, },
4492 { 10375, 9250, },
4493 { 10500, 9375, },
4494 { 10625, 9500, },
4495 { 10750, 9625, },
4496 { 10875, 9750, },
4497 { 11000, 9875, },
4498 { 11125, 10000, },
4499 { 11250, 10125, },
4500 { 11375, 10250, },
4501 { 11500, 10375, },
4502 { 11625, 10500, },
4503 { 11750, 10625, },
4504 { 11875, 10750, },
4505 { 12000, 10875, },
4506 { 12125, 11000, },
4507 { 12250, 11125, },
4508 { 12375, 11250, },
4509 { 12500, 11375, },
4510 { 12625, 11500, },
4511 { 12750, 11625, },
4512 { 12875, 11750, },
4513 { 13000, 11875, },
4514 { 13125, 12000, },
4515 { 13250, 12125, },
4516 { 13375, 12250, },
4517 { 13500, 12375, },
4518 { 13625, 12500, },
4519 { 13750, 12625, },
4520 { 13875, 12750, },
4521 { 14000, 12875, },
4522 { 14125, 13000, },
4523 { 14250, 13125, },
4524 { 14375, 13250, },
4525 { 14500, 13375, },
4526 { 14625, 13500, },
4527 { 14750, 13625, },
4528 { 14875, 13750, },
4529 { 15000, 13875, },
4530 { 15125, 14000, },
4531 { 15250, 14125, },
4532 { 15375, 14250, },
4533 { 15500, 14375, },
4534 { 15625, 14500, },
4535 { 15750, 14625, },
4536 { 15875, 14750, },
4537 { 16000, 14875, },
4538 { 16125, 15000, },
4539 };
4540 if (dev_priv->info->is_mobile)
4541 return v_table[pxvid].vm;
4542 else
4543 return v_table[pxvid].vd;
4544 }
4545
4546 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4547 {
4548 struct timespec now, diff1;
4549 u64 diff;
4550 unsigned long diffms;
4551 u32 count;
4552
4553 assert_spin_locked(&mchdev_lock);
4554
4555 getrawmonotonic(&now);
4556 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4557
4558 /* Don't divide by 0 */
4559 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4560 if (!diffms)
4561 return;
4562
4563 count = I915_READ(GFXEC);
4564
4565 if (count < dev_priv->ips.last_count2) {
4566 diff = ~0UL - dev_priv->ips.last_count2;
4567 diff += count;
4568 } else {
4569 diff = count - dev_priv->ips.last_count2;
4570 }
4571
4572 dev_priv->ips.last_count2 = count;
4573 dev_priv->ips.last_time2 = now;
4574
4575 /* More magic constants... */
4576 diff = diff * 1181;
4577 diff = div_u64(diff, diffms * 10);
4578 dev_priv->ips.gfx_power = diff;
4579 }
4580
4581 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4582 {
4583 if (dev_priv->info->gen != 5)
4584 return;
4585
4586 spin_lock_irq(&mchdev_lock);
4587
4588 __i915_update_gfx_val(dev_priv);
4589
4590 spin_unlock_irq(&mchdev_lock);
4591 }
4592
4593 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4594 {
4595 unsigned long t, corr, state1, corr2, state2;
4596 u32 pxvid, ext_v;
4597
4598 assert_spin_locked(&mchdev_lock);
4599
4600 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4601 pxvid = (pxvid >> 24) & 0x7f;
4602 ext_v = pvid_to_extvid(dev_priv, pxvid);
4603
4604 state1 = ext_v;
4605
4606 t = i915_mch_val(dev_priv);
4607
4608 /* Revel in the empirically derived constants */
4609
4610 /* Correction factor in 1/100000 units */
4611 if (t > 80)
4612 corr = ((t * 2349) + 135940);
4613 else if (t >= 50)
4614 corr = ((t * 964) + 29317);
4615 else /* < 50 */
4616 corr = ((t * 301) + 1004);
4617
4618 corr = corr * ((150142 * state1) / 10000 - 78642);
4619 corr /= 100000;
4620 corr2 = (corr * dev_priv->ips.corr);
4621
4622 state2 = (corr2 * state1) / 10000;
4623 state2 /= 100; /* convert to mW */
4624
4625 __i915_update_gfx_val(dev_priv);
4626
4627 return dev_priv->ips.gfx_power + state2;
4628 }
4629
4630 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4631 {
4632 unsigned long val;
4633
4634 if (dev_priv->info->gen != 5)
4635 return 0;
4636
4637 spin_lock_irq(&mchdev_lock);
4638
4639 val = __i915_gfx_val(dev_priv);
4640
4641 spin_unlock_irq(&mchdev_lock);
4642
4643 return val;
4644 }
4645
4646 /**
4647 * i915_read_mch_val - return value for IPS use
4648 *
4649 * Calculate and return a value for the IPS driver to use when deciding whether
4650 * we have thermal and power headroom to increase CPU or GPU power budget.
4651 */
4652 unsigned long i915_read_mch_val(void)
4653 {
4654 struct drm_i915_private *dev_priv;
4655 unsigned long chipset_val, graphics_val, ret = 0;
4656
4657 spin_lock_irq(&mchdev_lock);
4658 if (!i915_mch_dev)
4659 goto out_unlock;
4660 dev_priv = i915_mch_dev;
4661
4662 chipset_val = __i915_chipset_val(dev_priv);
4663 graphics_val = __i915_gfx_val(dev_priv);
4664
4665 ret = chipset_val + graphics_val;
4666
4667 out_unlock:
4668 spin_unlock_irq(&mchdev_lock);
4669
4670 return ret;
4671 }
4672 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4673
4674 /**
4675 * i915_gpu_raise - raise GPU frequency limit
4676 *
4677 * Raise the limit; IPS indicates we have thermal headroom.
4678 */
4679 bool i915_gpu_raise(void)
4680 {
4681 struct drm_i915_private *dev_priv;
4682 bool ret = true;
4683
4684 spin_lock_irq(&mchdev_lock);
4685 if (!i915_mch_dev) {
4686 ret = false;
4687 goto out_unlock;
4688 }
4689 dev_priv = i915_mch_dev;
4690
4691 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4692 dev_priv->ips.max_delay--;
4693
4694 out_unlock:
4695 spin_unlock_irq(&mchdev_lock);
4696
4697 return ret;
4698 }
4699 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4700
4701 /**
4702 * i915_gpu_lower - lower GPU frequency limit
4703 *
4704 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4705 * frequency maximum.
4706 */
4707 bool i915_gpu_lower(void)
4708 {
4709 struct drm_i915_private *dev_priv;
4710 bool ret = true;
4711
4712 spin_lock_irq(&mchdev_lock);
4713 if (!i915_mch_dev) {
4714 ret = false;
4715 goto out_unlock;
4716 }
4717 dev_priv = i915_mch_dev;
4718
4719 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4720 dev_priv->ips.max_delay++;
4721
4722 out_unlock:
4723 spin_unlock_irq(&mchdev_lock);
4724
4725 return ret;
4726 }
4727 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4728
4729 /**
4730 * i915_gpu_busy - indicate GPU business to IPS
4731 *
4732 * Tell the IPS driver whether or not the GPU is busy.
4733 */
4734 bool i915_gpu_busy(void)
4735 {
4736 struct drm_i915_private *dev_priv;
4737 struct intel_ring_buffer *ring;
4738 bool ret = false;
4739 int i;
4740
4741 spin_lock_irq(&mchdev_lock);
4742 if (!i915_mch_dev)
4743 goto out_unlock;
4744 dev_priv = i915_mch_dev;
4745
4746 for_each_ring(ring, dev_priv, i)
4747 ret |= !list_empty(&ring->request_list);
4748
4749 out_unlock:
4750 spin_unlock_irq(&mchdev_lock);
4751
4752 return ret;
4753 }
4754 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4755
4756 /**
4757 * i915_gpu_turbo_disable - disable graphics turbo
4758 *
4759 * Disable graphics turbo by resetting the max frequency and setting the
4760 * current frequency to the default.
4761 */
4762 bool i915_gpu_turbo_disable(void)
4763 {
4764 struct drm_i915_private *dev_priv;
4765 bool ret = true;
4766
4767 spin_lock_irq(&mchdev_lock);
4768 if (!i915_mch_dev) {
4769 ret = false;
4770 goto out_unlock;
4771 }
4772 dev_priv = i915_mch_dev;
4773
4774 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4775
4776 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4777 ret = false;
4778
4779 out_unlock:
4780 spin_unlock_irq(&mchdev_lock);
4781
4782 return ret;
4783 }
4784 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4785
4786 /**
4787 * Tells the intel_ips driver that the i915 driver is now loaded, if
4788 * IPS got loaded first.
4789 *
4790 * This awkward dance is so that neither module has to depend on the
4791 * other in order for IPS to do the appropriate communication of
4792 * GPU turbo limits to i915.
4793 */
4794 static void
4795 ips_ping_for_i915_load(void)
4796 {
4797 void (*link)(void);
4798
4799 link = symbol_get(ips_link_to_i915_driver);
4800 if (link) {
4801 link();
4802 symbol_put(ips_link_to_i915_driver);
4803 }
4804 }
4805
4806 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4807 {
4808 /* We only register the i915 ips part with intel-ips once everything is
4809 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4810 spin_lock_irq(&mchdev_lock);
4811 i915_mch_dev = dev_priv;
4812 spin_unlock_irq(&mchdev_lock);
4813
4814 ips_ping_for_i915_load();
4815 }
4816
4817 void intel_gpu_ips_teardown(void)
4818 {
4819 spin_lock_irq(&mchdev_lock);
4820 i915_mch_dev = NULL;
4821 spin_unlock_irq(&mchdev_lock);
4822 }
4823 static void intel_init_emon(struct drm_device *dev)
4824 {
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 u32 lcfuse;
4827 u8 pxw[16];
4828 int i;
4829
4830 /* Disable to program */
4831 I915_WRITE(ECR, 0);
4832 POSTING_READ(ECR);
4833
4834 /* Program energy weights for various events */
4835 I915_WRITE(SDEW, 0x15040d00);
4836 I915_WRITE(CSIEW0, 0x007f0000);
4837 I915_WRITE(CSIEW1, 0x1e220004);
4838 I915_WRITE(CSIEW2, 0x04000004);
4839
4840 for (i = 0; i < 5; i++)
4841 I915_WRITE(PEW + (i * 4), 0);
4842 for (i = 0; i < 3; i++)
4843 I915_WRITE(DEW + (i * 4), 0);
4844
4845 /* Program P-state weights to account for frequency power adjustment */
4846 for (i = 0; i < 16; i++) {
4847 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4848 unsigned long freq = intel_pxfreq(pxvidfreq);
4849 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4850 PXVFREQ_PX_SHIFT;
4851 unsigned long val;
4852
4853 val = vid * vid;
4854 val *= (freq / 1000);
4855 val *= 255;
4856 val /= (127*127*900);
4857 if (val > 0xff)
4858 DRM_ERROR("bad pxval: %ld\n", val);
4859 pxw[i] = val;
4860 }
4861 /* Render standby states get 0 weight */
4862 pxw[14] = 0;
4863 pxw[15] = 0;
4864
4865 for (i = 0; i < 4; i++) {
4866 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4867 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4868 I915_WRITE(PXW + (i * 4), val);
4869 }
4870
4871 /* Adjust magic regs to magic values (more experimental results) */
4872 I915_WRITE(OGW0, 0);
4873 I915_WRITE(OGW1, 0);
4874 I915_WRITE(EG0, 0x00007f00);
4875 I915_WRITE(EG1, 0x0000000e);
4876 I915_WRITE(EG2, 0x000e0000);
4877 I915_WRITE(EG3, 0x68000300);
4878 I915_WRITE(EG4, 0x42000000);
4879 I915_WRITE(EG5, 0x00140031);
4880 I915_WRITE(EG6, 0);
4881 I915_WRITE(EG7, 0);
4882
4883 for (i = 0; i < 8; i++)
4884 I915_WRITE(PXWL + (i * 4), 0);
4885
4886 /* Enable PMON + select events */
4887 I915_WRITE(ECR, 0x80000019);
4888
4889 lcfuse = I915_READ(LCFUSE02);
4890
4891 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4892 }
4893
4894 void intel_disable_gt_powersave(struct drm_device *dev)
4895 {
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897
4898 /* Interrupts should be disabled already to avoid re-arming. */
4899 WARN_ON(dev->irq_enabled);
4900
4901 if (IS_IRONLAKE_M(dev)) {
4902 ironlake_disable_drps(dev);
4903 ironlake_disable_rc6(dev);
4904 } else if (INTEL_INFO(dev)->gen >= 6) {
4905 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4906 cancel_work_sync(&dev_priv->rps.work);
4907 mutex_lock(&dev_priv->rps.hw_lock);
4908 if (IS_VALLEYVIEW(dev))
4909 valleyview_disable_rps(dev);
4910 else
4911 gen6_disable_rps(dev);
4912 dev_priv->rps.enabled = false;
4913 mutex_unlock(&dev_priv->rps.hw_lock);
4914 }
4915 }
4916
4917 static void intel_gen6_powersave_work(struct work_struct *work)
4918 {
4919 struct drm_i915_private *dev_priv =
4920 container_of(work, struct drm_i915_private,
4921 rps.delayed_resume_work.work);
4922 struct drm_device *dev = dev_priv->dev;
4923
4924 mutex_lock(&dev_priv->rps.hw_lock);
4925
4926 if (IS_VALLEYVIEW(dev)) {
4927 valleyview_enable_rps(dev);
4928 } else if (IS_BROADWELL(dev)) {
4929 gen8_enable_rps(dev);
4930 gen6_update_ring_freq(dev);
4931 } else {
4932 gen6_enable_rps(dev);
4933 gen6_update_ring_freq(dev);
4934 }
4935 dev_priv->rps.enabled = true;
4936 mutex_unlock(&dev_priv->rps.hw_lock);
4937 }
4938
4939 void intel_enable_gt_powersave(struct drm_device *dev)
4940 {
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942
4943 if (IS_IRONLAKE_M(dev)) {
4944 ironlake_enable_drps(dev);
4945 ironlake_enable_rc6(dev);
4946 intel_init_emon(dev);
4947 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4948 /*
4949 * PCU communication is slow and this doesn't need to be
4950 * done at any specific time, so do this out of our fast path
4951 * to make resume and init faster.
4952 */
4953 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4954 round_jiffies_up_relative(HZ));
4955 }
4956 }
4957
4958 static void ibx_init_clock_gating(struct drm_device *dev)
4959 {
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961
4962 /*
4963 * On Ibex Peak and Cougar Point, we need to disable clock
4964 * gating for the panel power sequencer or it will fail to
4965 * start up when no ports are active.
4966 */
4967 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4968 }
4969
4970 static void g4x_disable_trickle_feed(struct drm_device *dev)
4971 {
4972 struct drm_i915_private *dev_priv = dev->dev_private;
4973 int pipe;
4974
4975 for_each_pipe(pipe) {
4976 I915_WRITE(DSPCNTR(pipe),
4977 I915_READ(DSPCNTR(pipe)) |
4978 DISPPLANE_TRICKLE_FEED_DISABLE);
4979 intel_flush_primary_plane(dev_priv, pipe);
4980 }
4981 }
4982
4983 static void ironlake_init_clock_gating(struct drm_device *dev)
4984 {
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4987
4988 /*
4989 * Required for FBC
4990 * WaFbcDisableDpfcClockGating:ilk
4991 */
4992 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4993 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4994 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4995
4996 I915_WRITE(PCH_3DCGDIS0,
4997 MARIUNIT_CLOCK_GATE_DISABLE |
4998 SVSMUNIT_CLOCK_GATE_DISABLE);
4999 I915_WRITE(PCH_3DCGDIS1,
5000 VFMUNIT_CLOCK_GATE_DISABLE);
5001
5002 /*
5003 * According to the spec the following bits should be set in
5004 * order to enable memory self-refresh
5005 * The bit 22/21 of 0x42004
5006 * The bit 5 of 0x42020
5007 * The bit 15 of 0x45000
5008 */
5009 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5010 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5011 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5012 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5013 I915_WRITE(DISP_ARB_CTL,
5014 (I915_READ(DISP_ARB_CTL) |
5015 DISP_FBC_WM_DIS));
5016 I915_WRITE(WM3_LP_ILK, 0);
5017 I915_WRITE(WM2_LP_ILK, 0);
5018 I915_WRITE(WM1_LP_ILK, 0);
5019
5020 /*
5021 * Based on the document from hardware guys the following bits
5022 * should be set unconditionally in order to enable FBC.
5023 * The bit 22 of 0x42000
5024 * The bit 22 of 0x42004
5025 * The bit 7,8,9 of 0x42020.
5026 */
5027 if (IS_IRONLAKE_M(dev)) {
5028 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5029 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5030 I915_READ(ILK_DISPLAY_CHICKEN1) |
5031 ILK_FBCQ_DIS);
5032 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5033 I915_READ(ILK_DISPLAY_CHICKEN2) |
5034 ILK_DPARB_GATE);
5035 }
5036
5037 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5038
5039 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5040 I915_READ(ILK_DISPLAY_CHICKEN2) |
5041 ILK_ELPIN_409_SELECT);
5042 I915_WRITE(_3D_CHICKEN2,
5043 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5044 _3D_CHICKEN2_WM_READ_PIPELINED);
5045
5046 /* WaDisableRenderCachePipelinedFlush:ilk */
5047 I915_WRITE(CACHE_MODE_0,
5048 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5049
5050 g4x_disable_trickle_feed(dev);
5051
5052 ibx_init_clock_gating(dev);
5053 }
5054
5055 static void cpt_init_clock_gating(struct drm_device *dev)
5056 {
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 int pipe;
5059 uint32_t val;
5060
5061 /*
5062 * On Ibex Peak and Cougar Point, we need to disable clock
5063 * gating for the panel power sequencer or it will fail to
5064 * start up when no ports are active.
5065 */
5066 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5067 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5068 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5069 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5070 DPLS_EDP_PPS_FIX_DIS);
5071 /* The below fixes the weird display corruption, a few pixels shifted
5072 * downward, on (only) LVDS of some HP laptops with IVY.
5073 */
5074 for_each_pipe(pipe) {
5075 val = I915_READ(TRANS_CHICKEN2(pipe));
5076 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5077 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5078 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5079 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5080 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5081 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5082 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5083 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5084 }
5085 /* WADP0ClockGatingDisable */
5086 for_each_pipe(pipe) {
5087 I915_WRITE(TRANS_CHICKEN1(pipe),
5088 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5089 }
5090 }
5091
5092 static void gen6_check_mch_setup(struct drm_device *dev)
5093 {
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 uint32_t tmp;
5096
5097 tmp = I915_READ(MCH_SSKPD);
5098 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5099 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5100 DRM_INFO("This can cause pipe underruns and display issues.\n");
5101 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5102 }
5103 }
5104
5105 static void gen6_init_clock_gating(struct drm_device *dev)
5106 {
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5109
5110 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5111
5112 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5113 I915_READ(ILK_DISPLAY_CHICKEN2) |
5114 ILK_ELPIN_409_SELECT);
5115
5116 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5117 I915_WRITE(_3D_CHICKEN,
5118 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5119
5120 /* WaSetupGtModeTdRowDispatch:snb */
5121 if (IS_SNB_GT1(dev))
5122 I915_WRITE(GEN6_GT_MODE,
5123 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5124
5125 I915_WRITE(WM3_LP_ILK, 0);
5126 I915_WRITE(WM2_LP_ILK, 0);
5127 I915_WRITE(WM1_LP_ILK, 0);
5128
5129 I915_WRITE(CACHE_MODE_0,
5130 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5131
5132 I915_WRITE(GEN6_UCGCTL1,
5133 I915_READ(GEN6_UCGCTL1) |
5134 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5135 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5136
5137 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5138 * gating disable must be set. Failure to set it results in
5139 * flickering pixels due to Z write ordering failures after
5140 * some amount of runtime in the Mesa "fire" demo, and Unigine
5141 * Sanctuary and Tropics, and apparently anything else with
5142 * alpha test or pixel discard.
5143 *
5144 * According to the spec, bit 11 (RCCUNIT) must also be set,
5145 * but we didn't debug actual testcases to find it out.
5146 *
5147 * Also apply WaDisableVDSUnitClockGating:snb and
5148 * WaDisableRCPBUnitClockGating:snb.
5149 */
5150 I915_WRITE(GEN6_UCGCTL2,
5151 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5152 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5153 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5154
5155 /* Bspec says we need to always set all mask bits. */
5156 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5157 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5158
5159 /*
5160 * According to the spec the following bits should be
5161 * set in order to enable memory self-refresh and fbc:
5162 * The bit21 and bit22 of 0x42000
5163 * The bit21 and bit22 of 0x42004
5164 * The bit5 and bit7 of 0x42020
5165 * The bit14 of 0x70180
5166 * The bit14 of 0x71180
5167 *
5168 * WaFbcAsynchFlipDisableFbcQueue:snb
5169 */
5170 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5171 I915_READ(ILK_DISPLAY_CHICKEN1) |
5172 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5173 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5174 I915_READ(ILK_DISPLAY_CHICKEN2) |
5175 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5176 I915_WRITE(ILK_DSPCLK_GATE_D,
5177 I915_READ(ILK_DSPCLK_GATE_D) |
5178 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5179 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5180
5181 g4x_disable_trickle_feed(dev);
5182
5183 /* The default value should be 0x200 according to docs, but the two
5184 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5185 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5186 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5187
5188 cpt_init_clock_gating(dev);
5189
5190 gen6_check_mch_setup(dev);
5191 }
5192
5193 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5194 {
5195 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5196
5197 reg &= ~GEN7_FF_SCHED_MASK;
5198 reg |= GEN7_FF_TS_SCHED_HW;
5199 reg |= GEN7_FF_VS_SCHED_HW;
5200 reg |= GEN7_FF_DS_SCHED_HW;
5201
5202 if (IS_HASWELL(dev_priv->dev))
5203 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5204
5205 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5206 }
5207
5208 static void lpt_init_clock_gating(struct drm_device *dev)
5209 {
5210 struct drm_i915_private *dev_priv = dev->dev_private;
5211
5212 /*
5213 * TODO: this bit should only be enabled when really needed, then
5214 * disabled when not needed anymore in order to save power.
5215 */
5216 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5217 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5218 I915_READ(SOUTH_DSPCLK_GATE_D) |
5219 PCH_LP_PARTITION_LEVEL_DISABLE);
5220
5221 /* WADPOClockGatingDisable:hsw */
5222 I915_WRITE(_TRANSA_CHICKEN1,
5223 I915_READ(_TRANSA_CHICKEN1) |
5224 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5225 }
5226
5227 static void lpt_suspend_hw(struct drm_device *dev)
5228 {
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5230
5231 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5232 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5233
5234 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5235 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5236 }
5237 }
5238
5239 static void gen8_init_clock_gating(struct drm_device *dev)
5240 {
5241 struct drm_i915_private *dev_priv = dev->dev_private;
5242 enum pipe i;
5243
5244 I915_WRITE(WM3_LP_ILK, 0);
5245 I915_WRITE(WM2_LP_ILK, 0);
5246 I915_WRITE(WM1_LP_ILK, 0);
5247
5248 /* FIXME(BDW): Check all the w/a, some might only apply to
5249 * pre-production hw. */
5250
5251 WARN(!i915_preliminary_hw_support,
5252 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5253 I915_WRITE(HALF_SLICE_CHICKEN3,
5254 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5255 I915_WRITE(HALF_SLICE_CHICKEN3,
5256 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5257 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5258
5259 I915_WRITE(_3D_CHICKEN3,
5260 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5261
5262 I915_WRITE(COMMON_SLICE_CHICKEN2,
5263 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5264
5265 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5266 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5267
5268 /* WaSwitchSolVfFArbitrationPriority */
5269 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5270
5271 /* WaPsrDPAMaskVBlankInSRD */
5272 I915_WRITE(CHICKEN_PAR1_1,
5273 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5274
5275 /* WaPsrDPRSUnmaskVBlankInSRD */
5276 for_each_pipe(i) {
5277 I915_WRITE(CHICKEN_PIPESL_1(i),
5278 I915_READ(CHICKEN_PIPESL_1(i) |
5279 DPRS_MASK_VBLANK_SRD));
5280 }
5281 }
5282
5283 static void haswell_init_clock_gating(struct drm_device *dev)
5284 {
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286
5287 I915_WRITE(WM3_LP_ILK, 0);
5288 I915_WRITE(WM2_LP_ILK, 0);
5289 I915_WRITE(WM1_LP_ILK, 0);
5290
5291 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5292 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5293 */
5294 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5295
5296 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5297 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5298 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5299
5300 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5301 I915_WRITE(GEN7_L3CNTLREG1,
5302 GEN7_WA_FOR_GEN7_L3_CONTROL);
5303 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5304 GEN7_WA_L3_CHICKEN_MODE);
5305
5306 /* L3 caching of data atomics doesn't work -- disable it. */
5307 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5308 I915_WRITE(HSW_ROW_CHICKEN3,
5309 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5310
5311 /* This is required by WaCatErrorRejectionIssue:hsw */
5312 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5313 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5314 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5315
5316 /* WaVSRefCountFullforceMissDisable:hsw */
5317 gen7_setup_fixed_func_scheduler(dev_priv);
5318
5319 /* WaDisable4x2SubspanOptimization:hsw */
5320 I915_WRITE(CACHE_MODE_1,
5321 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5322
5323 /* WaSwitchSolVfFArbitrationPriority:hsw */
5324 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5325
5326 /* WaRsPkgCStateDisplayPMReq:hsw */
5327 I915_WRITE(CHICKEN_PAR1_1,
5328 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5329
5330 lpt_init_clock_gating(dev);
5331 }
5332
5333 static void ivybridge_init_clock_gating(struct drm_device *dev)
5334 {
5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 uint32_t snpcr;
5337
5338 I915_WRITE(WM3_LP_ILK, 0);
5339 I915_WRITE(WM2_LP_ILK, 0);
5340 I915_WRITE(WM1_LP_ILK, 0);
5341
5342 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5343
5344 /* WaDisableEarlyCull:ivb */
5345 I915_WRITE(_3D_CHICKEN3,
5346 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5347
5348 /* WaDisableBackToBackFlipFix:ivb */
5349 I915_WRITE(IVB_CHICKEN3,
5350 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5351 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5352
5353 /* WaDisablePSDDualDispatchEnable:ivb */
5354 if (IS_IVB_GT1(dev))
5355 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5356 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5357 else
5358 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5359 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5360
5361 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5362 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5363 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5364
5365 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5366 I915_WRITE(GEN7_L3CNTLREG1,
5367 GEN7_WA_FOR_GEN7_L3_CONTROL);
5368 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5369 GEN7_WA_L3_CHICKEN_MODE);
5370 if (IS_IVB_GT1(dev))
5371 I915_WRITE(GEN7_ROW_CHICKEN2,
5372 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5373 else
5374 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5375 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5376
5377
5378 /* WaForceL3Serialization:ivb */
5379 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5380 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5381
5382 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5383 * gating disable must be set. Failure to set it results in
5384 * flickering pixels due to Z write ordering failures after
5385 * some amount of runtime in the Mesa "fire" demo, and Unigine
5386 * Sanctuary and Tropics, and apparently anything else with
5387 * alpha test or pixel discard.
5388 *
5389 * According to the spec, bit 11 (RCCUNIT) must also be set,
5390 * but we didn't debug actual testcases to find it out.
5391 *
5392 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5393 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5394 */
5395 I915_WRITE(GEN6_UCGCTL2,
5396 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5397 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5398
5399 /* This is required by WaCatErrorRejectionIssue:ivb */
5400 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5401 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5402 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5403
5404 g4x_disable_trickle_feed(dev);
5405
5406 /* WaVSRefCountFullforceMissDisable:ivb */
5407 gen7_setup_fixed_func_scheduler(dev_priv);
5408
5409 /* WaDisable4x2SubspanOptimization:ivb */
5410 I915_WRITE(CACHE_MODE_1,
5411 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5412
5413 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5414 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5415 snpcr |= GEN6_MBC_SNPCR_MED;
5416 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5417
5418 if (!HAS_PCH_NOP(dev))
5419 cpt_init_clock_gating(dev);
5420
5421 gen6_check_mch_setup(dev);
5422 }
5423
5424 static void valleyview_init_clock_gating(struct drm_device *dev)
5425 {
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 u32 val;
5428
5429 mutex_lock(&dev_priv->rps.hw_lock);
5430 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5431 mutex_unlock(&dev_priv->rps.hw_lock);
5432 switch ((val >> 6) & 3) {
5433 case 0:
5434 dev_priv->mem_freq = 800;
5435 break;
5436 case 1:
5437 dev_priv->mem_freq = 1066;
5438 break;
5439 case 2:
5440 dev_priv->mem_freq = 1333;
5441 break;
5442 case 3:
5443 dev_priv->mem_freq = 1333;
5444 break;
5445 }
5446 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5447
5448 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5449
5450 /* WaDisableEarlyCull:vlv */
5451 I915_WRITE(_3D_CHICKEN3,
5452 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5453
5454 /* WaDisableBackToBackFlipFix:vlv */
5455 I915_WRITE(IVB_CHICKEN3,
5456 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5457 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5458
5459 /* WaDisablePSDDualDispatchEnable:vlv */
5460 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5461 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5462 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5463
5464 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5465 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5466 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5467
5468 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5469 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5470 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5471
5472 /* WaForceL3Serialization:vlv */
5473 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5474 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5475
5476 /* WaDisableDopClockGating:vlv */
5477 I915_WRITE(GEN7_ROW_CHICKEN2,
5478 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5479
5480 /* This is required by WaCatErrorRejectionIssue:vlv */
5481 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5482 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5483 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5484
5485 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5486 * gating disable must be set. Failure to set it results in
5487 * flickering pixels due to Z write ordering failures after
5488 * some amount of runtime in the Mesa "fire" demo, and Unigine
5489 * Sanctuary and Tropics, and apparently anything else with
5490 * alpha test or pixel discard.
5491 *
5492 * According to the spec, bit 11 (RCCUNIT) must also be set,
5493 * but we didn't debug actual testcases to find it out.
5494 *
5495 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5496 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5497 *
5498 * Also apply WaDisableVDSUnitClockGating:vlv and
5499 * WaDisableRCPBUnitClockGating:vlv.
5500 */
5501 I915_WRITE(GEN6_UCGCTL2,
5502 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5503 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5504 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5505 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5506 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5507
5508 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5509
5510 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5511
5512 I915_WRITE(CACHE_MODE_1,
5513 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5514
5515 /*
5516 * WaDisableVLVClockGating_VBIIssue:vlv
5517 * Disable clock gating on th GCFG unit to prevent a delay
5518 * in the reporting of vblank events.
5519 */
5520 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5521
5522 /* Conservative clock gating settings for now */
5523 I915_WRITE(0x9400, 0xffffffff);
5524 I915_WRITE(0x9404, 0xffffffff);
5525 I915_WRITE(0x9408, 0xffffffff);
5526 I915_WRITE(0x940c, 0xffffffff);
5527 I915_WRITE(0x9410, 0xffffffff);
5528 I915_WRITE(0x9414, 0xffffffff);
5529 I915_WRITE(0x9418, 0xffffffff);
5530 }
5531
5532 static void g4x_init_clock_gating(struct drm_device *dev)
5533 {
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 uint32_t dspclk_gate;
5536
5537 I915_WRITE(RENCLK_GATE_D1, 0);
5538 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5539 GS_UNIT_CLOCK_GATE_DISABLE |
5540 CL_UNIT_CLOCK_GATE_DISABLE);
5541 I915_WRITE(RAMCLK_GATE_D, 0);
5542 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5543 OVRUNIT_CLOCK_GATE_DISABLE |
5544 OVCUNIT_CLOCK_GATE_DISABLE;
5545 if (IS_GM45(dev))
5546 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5547 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5548
5549 /* WaDisableRenderCachePipelinedFlush */
5550 I915_WRITE(CACHE_MODE_0,
5551 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5552
5553 g4x_disable_trickle_feed(dev);
5554 }
5555
5556 static void crestline_init_clock_gating(struct drm_device *dev)
5557 {
5558 struct drm_i915_private *dev_priv = dev->dev_private;
5559
5560 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5561 I915_WRITE(RENCLK_GATE_D2, 0);
5562 I915_WRITE(DSPCLK_GATE_D, 0);
5563 I915_WRITE(RAMCLK_GATE_D, 0);
5564 I915_WRITE16(DEUC, 0);
5565 I915_WRITE(MI_ARB_STATE,
5566 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5567 }
5568
5569 static void broadwater_init_clock_gating(struct drm_device *dev)
5570 {
5571 struct drm_i915_private *dev_priv = dev->dev_private;
5572
5573 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5574 I965_RCC_CLOCK_GATE_DISABLE |
5575 I965_RCPB_CLOCK_GATE_DISABLE |
5576 I965_ISC_CLOCK_GATE_DISABLE |
5577 I965_FBC_CLOCK_GATE_DISABLE);
5578 I915_WRITE(RENCLK_GATE_D2, 0);
5579 I915_WRITE(MI_ARB_STATE,
5580 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5581 }
5582
5583 static void gen3_init_clock_gating(struct drm_device *dev)
5584 {
5585 struct drm_i915_private *dev_priv = dev->dev_private;
5586 u32 dstate = I915_READ(D_STATE);
5587
5588 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5589 DSTATE_DOT_CLOCK_GATING;
5590 I915_WRITE(D_STATE, dstate);
5591
5592 if (IS_PINEVIEW(dev))
5593 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5594
5595 /* IIR "flip pending" means done if this bit is set */
5596 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5597 }
5598
5599 static void i85x_init_clock_gating(struct drm_device *dev)
5600 {
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602
5603 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5604 }
5605
5606 static void i830_init_clock_gating(struct drm_device *dev)
5607 {
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609
5610 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5611 }
5612
5613 void intel_init_clock_gating(struct drm_device *dev)
5614 {
5615 struct drm_i915_private *dev_priv = dev->dev_private;
5616
5617 dev_priv->display.init_clock_gating(dev);
5618 }
5619
5620 void intel_suspend_hw(struct drm_device *dev)
5621 {
5622 if (HAS_PCH_LPT(dev))
5623 lpt_suspend_hw(dev);
5624 }
5625
5626 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5627 for (i = 0; \
5628 i < (power_domains)->power_well_count && \
5629 ((power_well) = &(power_domains)->power_wells[i]); \
5630 i++) \
5631 if ((power_well)->domains & (domain_mask))
5632
5633 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5634 for (i = (power_domains)->power_well_count - 1; \
5635 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5636 i--) \
5637 if ((power_well)->domains & (domain_mask))
5638
5639 /**
5640 * We should only use the power well if we explicitly asked the hardware to
5641 * enable it, so check if it's enabled and also check if we've requested it to
5642 * be enabled.
5643 */
5644 static bool hsw_power_well_enabled(struct drm_device *dev,
5645 struct i915_power_well *power_well)
5646 {
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648
5649 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5650 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5651 }
5652
5653 bool intel_display_power_enabled_sw(struct drm_device *dev,
5654 enum intel_display_power_domain domain)
5655 {
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 struct i915_power_domains *power_domains;
5658
5659 power_domains = &dev_priv->power_domains;
5660
5661 return power_domains->domain_use_count[domain];
5662 }
5663
5664 bool intel_display_power_enabled(struct drm_device *dev,
5665 enum intel_display_power_domain domain)
5666 {
5667 struct drm_i915_private *dev_priv = dev->dev_private;
5668 struct i915_power_domains *power_domains;
5669 struct i915_power_well *power_well;
5670 bool is_enabled;
5671 int i;
5672
5673 power_domains = &dev_priv->power_domains;
5674
5675 is_enabled = true;
5676
5677 mutex_lock(&power_domains->lock);
5678 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5679 if (power_well->always_on)
5680 continue;
5681
5682 if (!power_well->is_enabled(dev, power_well)) {
5683 is_enabled = false;
5684 break;
5685 }
5686 }
5687 mutex_unlock(&power_domains->lock);
5688
5689 return is_enabled;
5690 }
5691
5692 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5693 {
5694 struct drm_device *dev = dev_priv->dev;
5695 unsigned long irqflags;
5696
5697 /*
5698 * After we re-enable the power well, if we touch VGA register 0x3d5
5699 * we'll get unclaimed register interrupts. This stops after we write
5700 * anything to the VGA MSR register. The vgacon module uses this
5701 * register all the time, so if we unbind our driver and, as a
5702 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5703 * console_unlock(). So make here we touch the VGA MSR register, making
5704 * sure vgacon can keep working normally without triggering interrupts
5705 * and error messages.
5706 */
5707 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5708 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5709 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5710
5711 if (IS_BROADWELL(dev)) {
5712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5713 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5714 dev_priv->de_irq_mask[PIPE_B]);
5715 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5716 ~dev_priv->de_irq_mask[PIPE_B] |
5717 GEN8_PIPE_VBLANK);
5718 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5719 dev_priv->de_irq_mask[PIPE_C]);
5720 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5721 ~dev_priv->de_irq_mask[PIPE_C] |
5722 GEN8_PIPE_VBLANK);
5723 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5725 }
5726 }
5727
5728 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5729 {
5730 struct drm_device *dev = dev_priv->dev;
5731 enum pipe p;
5732 unsigned long irqflags;
5733
5734 /*
5735 * After this, the registers on the pipes that are part of the power
5736 * well will become zero, so we have to adjust our counters according to
5737 * that.
5738 *
5739 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5740 */
5741 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5742 for_each_pipe(p)
5743 if (p != PIPE_A)
5744 dev->vblank[p].last = 0;
5745 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5746 }
5747
5748 static void hsw_set_power_well(struct drm_device *dev,
5749 struct i915_power_well *power_well, bool enable)
5750 {
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 bool is_enabled, enable_requested;
5753 uint32_t tmp;
5754
5755 WARN_ON(dev_priv->pc8.enabled);
5756
5757 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5758 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5759 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5760
5761 if (enable) {
5762 if (!enable_requested)
5763 I915_WRITE(HSW_PWR_WELL_DRIVER,
5764 HSW_PWR_WELL_ENABLE_REQUEST);
5765
5766 if (!is_enabled) {
5767 DRM_DEBUG_KMS("Enabling power well\n");
5768 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5769 HSW_PWR_WELL_STATE_ENABLED), 20))
5770 DRM_ERROR("Timeout enabling power well\n");
5771 }
5772
5773 hsw_power_well_post_enable(dev_priv);
5774 } else {
5775 if (enable_requested) {
5776 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5777 POSTING_READ(HSW_PWR_WELL_DRIVER);
5778 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5779
5780 hsw_power_well_post_disable(dev_priv);
5781 }
5782 }
5783 }
5784
5785 static void __intel_power_well_get(struct drm_device *dev,
5786 struct i915_power_well *power_well)
5787 {
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789
5790 if (!power_well->count++ && power_well->set) {
5791 hsw_disable_package_c8(dev_priv);
5792 power_well->set(dev, power_well, true);
5793 }
5794 }
5795
5796 static void __intel_power_well_put(struct drm_device *dev,
5797 struct i915_power_well *power_well)
5798 {
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800
5801 WARN_ON(!power_well->count);
5802
5803 if (!--power_well->count && power_well->set &&
5804 i915_disable_power_well) {
5805 power_well->set(dev, power_well, false);
5806 hsw_enable_package_c8(dev_priv);
5807 }
5808 }
5809
5810 void intel_display_power_get(struct drm_device *dev,
5811 enum intel_display_power_domain domain)
5812 {
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 struct i915_power_domains *power_domains;
5815 struct i915_power_well *power_well;
5816 int i;
5817
5818 power_domains = &dev_priv->power_domains;
5819
5820 mutex_lock(&power_domains->lock);
5821
5822 for_each_power_well(i, power_well, BIT(domain), power_domains)
5823 __intel_power_well_get(dev, power_well);
5824
5825 power_domains->domain_use_count[domain]++;
5826
5827 mutex_unlock(&power_domains->lock);
5828 }
5829
5830 void intel_display_power_put(struct drm_device *dev,
5831 enum intel_display_power_domain domain)
5832 {
5833 struct drm_i915_private *dev_priv = dev->dev_private;
5834 struct i915_power_domains *power_domains;
5835 struct i915_power_well *power_well;
5836 int i;
5837
5838 power_domains = &dev_priv->power_domains;
5839
5840 mutex_lock(&power_domains->lock);
5841
5842 WARN_ON(!power_domains->domain_use_count[domain]);
5843 power_domains->domain_use_count[domain]--;
5844
5845 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5846 __intel_power_well_put(dev, power_well);
5847
5848 mutex_unlock(&power_domains->lock);
5849 }
5850
5851 static struct i915_power_domains *hsw_pwr;
5852
5853 /* Display audio driver power well request */
5854 void i915_request_power_well(void)
5855 {
5856 struct drm_i915_private *dev_priv;
5857
5858 if (WARN_ON(!hsw_pwr))
5859 return;
5860
5861 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5862 power_domains);
5863 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5864 }
5865 EXPORT_SYMBOL_GPL(i915_request_power_well);
5866
5867 /* Display audio driver power well release */
5868 void i915_release_power_well(void)
5869 {
5870 struct drm_i915_private *dev_priv;
5871
5872 if (WARN_ON(!hsw_pwr))
5873 return;
5874
5875 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5876 power_domains);
5877 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5878 }
5879 EXPORT_SYMBOL_GPL(i915_release_power_well);
5880
5881 static struct i915_power_well i9xx_always_on_power_well[] = {
5882 {
5883 .name = "always-on",
5884 .always_on = 1,
5885 .domains = POWER_DOMAIN_MASK,
5886 },
5887 };
5888
5889 static struct i915_power_well hsw_power_wells[] = {
5890 {
5891 .name = "always-on",
5892 .always_on = 1,
5893 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5894 },
5895 {
5896 .name = "display",
5897 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5898 .is_enabled = hsw_power_well_enabled,
5899 .set = hsw_set_power_well,
5900 },
5901 };
5902
5903 static struct i915_power_well bdw_power_wells[] = {
5904 {
5905 .name = "always-on",
5906 .always_on = 1,
5907 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5908 },
5909 {
5910 .name = "display",
5911 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5912 .is_enabled = hsw_power_well_enabled,
5913 .set = hsw_set_power_well,
5914 },
5915 };
5916
5917 #define set_power_wells(power_domains, __power_wells) ({ \
5918 (power_domains)->power_wells = (__power_wells); \
5919 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5920 })
5921
5922 int intel_power_domains_init(struct drm_device *dev)
5923 {
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5926
5927 mutex_init(&power_domains->lock);
5928
5929 /*
5930 * The enabling order will be from lower to higher indexed wells,
5931 * the disabling order is reversed.
5932 */
5933 if (IS_HASWELL(dev)) {
5934 set_power_wells(power_domains, hsw_power_wells);
5935 hsw_pwr = power_domains;
5936 } else if (IS_BROADWELL(dev)) {
5937 set_power_wells(power_domains, bdw_power_wells);
5938 hsw_pwr = power_domains;
5939 } else {
5940 set_power_wells(power_domains, i9xx_always_on_power_well);
5941 }
5942
5943 return 0;
5944 }
5945
5946 void intel_power_domains_remove(struct drm_device *dev)
5947 {
5948 hsw_pwr = NULL;
5949 }
5950
5951 static void intel_power_domains_resume(struct drm_device *dev)
5952 {
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5955 struct i915_power_well *power_well;
5956 int i;
5957
5958 mutex_lock(&power_domains->lock);
5959 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5960 if (power_well->set)
5961 power_well->set(dev, power_well, power_well->count > 0);
5962 }
5963 mutex_unlock(&power_domains->lock);
5964 }
5965
5966 /*
5967 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5968 * when not needed anymore. We have 4 registers that can request the power well
5969 * to be enabled, and it will only be disabled if none of the registers is
5970 * requesting it to be enabled.
5971 */
5972 void intel_power_domains_init_hw(struct drm_device *dev)
5973 {
5974 struct drm_i915_private *dev_priv = dev->dev_private;
5975
5976 /* For now, we need the power well to be always enabled. */
5977 intel_display_set_init_power(dev, true);
5978 intel_power_domains_resume(dev);
5979
5980 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5981 return;
5982
5983 /* We're taking over the BIOS, so clear any requests made by it since
5984 * the driver is in charge now. */
5985 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5986 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5987 }
5988
5989 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5990 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5991 {
5992 hsw_disable_package_c8(dev_priv);
5993 }
5994
5995 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5996 {
5997 hsw_enable_package_c8(dev_priv);
5998 }
5999
6000 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6001 {
6002 struct drm_device *dev = dev_priv->dev;
6003 struct device *device = &dev->pdev->dev;
6004
6005 if (!HAS_RUNTIME_PM(dev))
6006 return;
6007
6008 pm_runtime_get_sync(device);
6009 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6010 }
6011
6012 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6013 {
6014 struct drm_device *dev = dev_priv->dev;
6015 struct device *device = &dev->pdev->dev;
6016
6017 if (!HAS_RUNTIME_PM(dev))
6018 return;
6019
6020 pm_runtime_mark_last_busy(device);
6021 pm_runtime_put_autosuspend(device);
6022 }
6023
6024 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6025 {
6026 struct drm_device *dev = dev_priv->dev;
6027 struct device *device = &dev->pdev->dev;
6028
6029 dev_priv->pm.suspended = false;
6030
6031 if (!HAS_RUNTIME_PM(dev))
6032 return;
6033
6034 pm_runtime_set_active(device);
6035
6036 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6037 pm_runtime_mark_last_busy(device);
6038 pm_runtime_use_autosuspend(device);
6039 }
6040
6041 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6042 {
6043 struct drm_device *dev = dev_priv->dev;
6044 struct device *device = &dev->pdev->dev;
6045
6046 if (!HAS_RUNTIME_PM(dev))
6047 return;
6048
6049 /* Make sure we're not suspended first. */
6050 pm_runtime_get_sync(device);
6051 pm_runtime_disable(device);
6052 }
6053
6054 /* Set up chip specific power management-related functions */
6055 void intel_init_pm(struct drm_device *dev)
6056 {
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058
6059 if (I915_HAS_FBC(dev)) {
6060 if (INTEL_INFO(dev)->gen >= 7) {
6061 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6062 dev_priv->display.enable_fbc = gen7_enable_fbc;
6063 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6064 } else if (INTEL_INFO(dev)->gen >= 5) {
6065 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6066 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6067 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6068 } else if (IS_GM45(dev)) {
6069 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6070 dev_priv->display.enable_fbc = g4x_enable_fbc;
6071 dev_priv->display.disable_fbc = g4x_disable_fbc;
6072 } else {
6073 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6074 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6075 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6076 }
6077 }
6078
6079 /* For cxsr */
6080 if (IS_PINEVIEW(dev))
6081 i915_pineview_get_mem_freq(dev);
6082 else if (IS_GEN5(dev))
6083 i915_ironlake_get_mem_freq(dev);
6084
6085 /* For FIFO watermark updates */
6086 if (HAS_PCH_SPLIT(dev)) {
6087 intel_setup_wm_latency(dev);
6088
6089 if (IS_GEN5(dev)) {
6090 if (dev_priv->wm.pri_latency[1] &&
6091 dev_priv->wm.spr_latency[1] &&
6092 dev_priv->wm.cur_latency[1])
6093 dev_priv->display.update_wm = ironlake_update_wm;
6094 else {
6095 DRM_DEBUG_KMS("Failed to get proper latency. "
6096 "Disable CxSR\n");
6097 dev_priv->display.update_wm = NULL;
6098 }
6099 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6100 } else if (IS_GEN6(dev)) {
6101 if (dev_priv->wm.pri_latency[0] &&
6102 dev_priv->wm.spr_latency[0] &&
6103 dev_priv->wm.cur_latency[0]) {
6104 dev_priv->display.update_wm = sandybridge_update_wm;
6105 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6106 } else {
6107 DRM_DEBUG_KMS("Failed to read display plane latency. "
6108 "Disable CxSR\n");
6109 dev_priv->display.update_wm = NULL;
6110 }
6111 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6112 } else if (IS_IVYBRIDGE(dev)) {
6113 if (dev_priv->wm.pri_latency[0] &&
6114 dev_priv->wm.spr_latency[0] &&
6115 dev_priv->wm.cur_latency[0]) {
6116 dev_priv->display.update_wm = ivybridge_update_wm;
6117 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6118 } else {
6119 DRM_DEBUG_KMS("Failed to read display plane latency. "
6120 "Disable CxSR\n");
6121 dev_priv->display.update_wm = NULL;
6122 }
6123 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6124 } else if (IS_HASWELL(dev)) {
6125 if (dev_priv->wm.pri_latency[0] &&
6126 dev_priv->wm.spr_latency[0] &&
6127 dev_priv->wm.cur_latency[0]) {
6128 dev_priv->display.update_wm = haswell_update_wm;
6129 dev_priv->display.update_sprite_wm =
6130 haswell_update_sprite_wm;
6131 } else {
6132 DRM_DEBUG_KMS("Failed to read display plane latency. "
6133 "Disable CxSR\n");
6134 dev_priv->display.update_wm = NULL;
6135 }
6136 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6137 } else if (INTEL_INFO(dev)->gen == 8) {
6138 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6139 } else
6140 dev_priv->display.update_wm = NULL;
6141 } else if (IS_VALLEYVIEW(dev)) {
6142 dev_priv->display.update_wm = valleyview_update_wm;
6143 dev_priv->display.init_clock_gating =
6144 valleyview_init_clock_gating;
6145 } else if (IS_PINEVIEW(dev)) {
6146 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6147 dev_priv->is_ddr3,
6148 dev_priv->fsb_freq,
6149 dev_priv->mem_freq)) {
6150 DRM_INFO("failed to find known CxSR latency "
6151 "(found ddr%s fsb freq %d, mem freq %d), "
6152 "disabling CxSR\n",
6153 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6154 dev_priv->fsb_freq, dev_priv->mem_freq);
6155 /* Disable CxSR and never update its watermark again */
6156 pineview_disable_cxsr(dev);
6157 dev_priv->display.update_wm = NULL;
6158 } else
6159 dev_priv->display.update_wm = pineview_update_wm;
6160 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6161 } else if (IS_G4X(dev)) {
6162 dev_priv->display.update_wm = g4x_update_wm;
6163 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6164 } else if (IS_GEN4(dev)) {
6165 dev_priv->display.update_wm = i965_update_wm;
6166 if (IS_CRESTLINE(dev))
6167 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6168 else if (IS_BROADWATER(dev))
6169 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6170 } else if (IS_GEN3(dev)) {
6171 dev_priv->display.update_wm = i9xx_update_wm;
6172 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6173 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6174 } else if (IS_I865G(dev)) {
6175 dev_priv->display.update_wm = i830_update_wm;
6176 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6177 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6178 } else if (IS_I85X(dev)) {
6179 dev_priv->display.update_wm = i9xx_update_wm;
6180 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6181 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6182 } else {
6183 dev_priv->display.update_wm = i830_update_wm;
6184 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6185 if (IS_845G(dev))
6186 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6187 else
6188 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6189 }
6190 }
6191
6192 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6193 {
6194 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6195
6196 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6197 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6198 return -EAGAIN;
6199 }
6200
6201 I915_WRITE(GEN6_PCODE_DATA, *val);
6202 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6203
6204 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6205 500)) {
6206 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6207 return -ETIMEDOUT;
6208 }
6209
6210 *val = I915_READ(GEN6_PCODE_DATA);
6211 I915_WRITE(GEN6_PCODE_DATA, 0);
6212
6213 return 0;
6214 }
6215
6216 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6217 {
6218 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6219
6220 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6221 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6222 return -EAGAIN;
6223 }
6224
6225 I915_WRITE(GEN6_PCODE_DATA, val);
6226 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6227
6228 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6229 500)) {
6230 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6231 return -ETIMEDOUT;
6232 }
6233
6234 I915_WRITE(GEN6_PCODE_DATA, 0);
6235
6236 return 0;
6237 }
6238
6239 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6240 {
6241 int div;
6242
6243 /* 4 x czclk */
6244 switch (dev_priv->mem_freq) {
6245 case 800:
6246 div = 10;
6247 break;
6248 case 1066:
6249 div = 12;
6250 break;
6251 case 1333:
6252 div = 16;
6253 break;
6254 default:
6255 return -1;
6256 }
6257
6258 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6259 }
6260
6261 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6262 {
6263 int mul;
6264
6265 /* 4 x czclk */
6266 switch (dev_priv->mem_freq) {
6267 case 800:
6268 mul = 10;
6269 break;
6270 case 1066:
6271 mul = 12;
6272 break;
6273 case 1333:
6274 mul = 16;
6275 break;
6276 default:
6277 return -1;
6278 }
6279
6280 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6281 }
6282
6283 void intel_pm_init(struct drm_device *dev)
6284 {
6285 struct drm_i915_private *dev_priv = dev->dev_private;
6286
6287 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6288 intel_gen6_powersave_work);
6289 }
Linux kernel - Deliverables
This page took 0.180094 seconds and 6 git commands to generate.