2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
36 * RC6 is a special power stage which allows the GPU to enter an very
37 * low-voltage mode when idle, using down to 0V while at this stage. This
38 * stage is entered automatically when the GPU is idle when RC6 support is
39 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 * There are different RC6 modes available in Intel GPU, which differentiate
42 * among each other with the latency required to enter and leave RC6 and
43 * voltage consumed by the GPU in different states.
45 * The combination of the following flags define which states GPU is allowed
46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
47 * RC6pp is deepest RC6. Their support by hardware varies according to the
48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
49 * which brings the most power savings; deeper states save more power, but
50 * require higher latency to switch to and wake up.
52 #define INTEL_RC6_ENABLE (1<<0)
53 #define INTEL_RC6p_ENABLE (1<<1)
54 #define INTEL_RC6pp_ENABLE (1<<2)
56 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
57 * framebuffer contents in-memory, aiming at reducing the required bandwidth
58 * during in-memory transfers and, therefore, reduce the power packet.
60 * The benefits of FBC are mostly visible with solid backgrounds and
61 * variation-less patterns.
63 * FBC-related functionality can be enabled by the means of the
64 * i915.i915_enable_fbc parameter
67 static void i8xx_disable_fbc(struct drm_device
*dev
)
69 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
72 /* Disable compression */
73 fbc_ctl
= I915_READ(FBC_CONTROL
);
74 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
77 fbc_ctl
&= ~FBC_CTL_EN
;
78 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
80 /* Wait for compressing bit to clear */
81 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
82 DRM_DEBUG_KMS("FBC idle timed out\n");
86 DRM_DEBUG_KMS("disabled FBC\n");
89 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
91 struct drm_device
*dev
= crtc
->dev
;
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct drm_framebuffer
*fb
= crtc
->fb
;
94 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
95 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
96 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
99 u32 fbc_ctl
, fbc_ctl2
;
101 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
102 if (fb
->pitches
[0] < cfb_pitch
)
103 cfb_pitch
= fb
->pitches
[0];
105 /* FBC_CTL wants 64B units */
106 cfb_pitch
= (cfb_pitch
/ 64) - 1;
107 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
110 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
111 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
114 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
116 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
117 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
120 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
122 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
123 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
124 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
125 fbc_ctl
|= obj
->fence_reg
;
126 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
128 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
129 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
132 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
136 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
139 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
141 struct drm_device
*dev
= crtc
->dev
;
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 struct drm_framebuffer
*fb
= crtc
->fb
;
144 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
145 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
147 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
148 unsigned long stall_watermark
= 200;
151 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
152 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
153 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
155 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
156 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
157 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
158 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
161 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
163 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
166 static void g4x_disable_fbc(struct drm_device
*dev
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
171 /* Disable compression */
172 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
173 if (dpfc_ctl
& DPFC_CTL_EN
) {
174 dpfc_ctl
&= ~DPFC_CTL_EN
;
175 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
177 DRM_DEBUG_KMS("disabled FBC\n");
181 static bool g4x_fbc_enabled(struct drm_device
*dev
)
183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
185 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
188 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
193 /* Make sure blitter notifies FBC of writes */
194 gen6_gt_force_wake_get(dev_priv
);
195 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
196 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
197 GEN6_BLITTER_LOCK_SHIFT
;
198 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
199 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
200 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
201 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
202 GEN6_BLITTER_LOCK_SHIFT
);
203 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
204 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
205 gen6_gt_force_wake_put(dev_priv
);
208 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
210 struct drm_device
*dev
= crtc
->dev
;
211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
212 struct drm_framebuffer
*fb
= crtc
->fb
;
213 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
214 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
216 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
217 unsigned long stall_watermark
= 200;
220 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
221 dpfc_ctl
&= DPFC_RESERVED
;
222 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
223 /* Set persistent mode for front-buffer rendering, ala X. */
224 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
225 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
226 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
228 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
229 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
230 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
231 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
232 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
234 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
237 I915_WRITE(SNB_DPFC_CTL_SA
,
238 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
239 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
240 sandybridge_blit_fbc_update(dev
);
243 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
246 static void ironlake_disable_fbc(struct drm_device
*dev
)
248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
251 /* Disable compression */
252 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
253 if (dpfc_ctl
& DPFC_CTL_EN
) {
254 dpfc_ctl
&= ~DPFC_CTL_EN
;
255 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
257 DRM_DEBUG_KMS("disabled FBC\n");
261 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
265 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
268 static void gen7_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
270 struct drm_device
*dev
= crtc
->dev
;
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
272 struct drm_framebuffer
*fb
= crtc
->fb
;
273 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
274 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
277 I915_WRITE(IVB_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
));
279 I915_WRITE(ILK_DPFC_CONTROL
, DPFC_CTL_EN
| DPFC_CTL_LIMIT_1X
|
280 IVB_DPFC_CTL_FENCE_EN
|
281 intel_crtc
->plane
<< IVB_DPFC_CTL_PLANE_SHIFT
);
283 if (IS_IVYBRIDGE(dev
)) {
284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
285 I915_WRITE(ILK_DISPLAY_CHICKEN1
, ILK_FBCQ_DIS
);
287 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
288 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc
->pipe
),
289 HSW_BYPASS_FBC_QUEUE
);
292 I915_WRITE(SNB_DPFC_CTL_SA
,
293 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
294 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
296 sandybridge_blit_fbc_update(dev
);
298 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
301 bool intel_fbc_enabled(struct drm_device
*dev
)
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
305 if (!dev_priv
->display
.fbc_enabled
)
308 return dev_priv
->display
.fbc_enabled(dev
);
311 static void intel_fbc_work_fn(struct work_struct
*__work
)
313 struct intel_fbc_work
*work
=
314 container_of(to_delayed_work(__work
),
315 struct intel_fbc_work
, work
);
316 struct drm_device
*dev
= work
->crtc
->dev
;
317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
319 mutex_lock(&dev
->struct_mutex
);
320 if (work
== dev_priv
->fbc
.fbc_work
) {
321 /* Double check that we haven't switched fb without cancelling
324 if (work
->crtc
->fb
== work
->fb
) {
325 dev_priv
->display
.enable_fbc(work
->crtc
,
328 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
329 dev_priv
->fbc
.fb_id
= work
->crtc
->fb
->base
.id
;
330 dev_priv
->fbc
.y
= work
->crtc
->y
;
333 dev_priv
->fbc
.fbc_work
= NULL
;
335 mutex_unlock(&dev
->struct_mutex
);
340 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
342 if (dev_priv
->fbc
.fbc_work
== NULL
)
345 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
347 /* Synchronisation is provided by struct_mutex and checking of
348 * dev_priv->fbc.fbc_work, so we can perform the cancellation
349 * entirely asynchronously.
351 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
352 /* tasklet was killed before being run, clean up */
353 kfree(dev_priv
->fbc
.fbc_work
);
355 /* Mark the work as no longer wanted so that if it does
356 * wake-up (because the work was already running and waiting
357 * for our mutex), it will discover that is no longer
360 dev_priv
->fbc
.fbc_work
= NULL
;
363 static void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
365 struct intel_fbc_work
*work
;
366 struct drm_device
*dev
= crtc
->dev
;
367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
369 if (!dev_priv
->display
.enable_fbc
)
372 intel_cancel_fbc_work(dev_priv
);
374 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
376 DRM_ERROR("Failed to allocate FBC work structure\n");
377 dev_priv
->display
.enable_fbc(crtc
, interval
);
383 work
->interval
= interval
;
384 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
386 dev_priv
->fbc
.fbc_work
= work
;
388 /* Delay the actual enabling to let pageflipping cease and the
389 * display to settle before starting the compression. Note that
390 * this delay also serves a second purpose: it allows for a
391 * vblank to pass after disabling the FBC before we attempt
392 * to modify the control registers.
394 * A more complicated solution would involve tracking vblanks
395 * following the termination of the page-flipping sequence
396 * and indeed performing the enable as a co-routine and not
397 * waiting synchronously upon the vblank.
399 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
401 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
404 void intel_disable_fbc(struct drm_device
*dev
)
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
408 intel_cancel_fbc_work(dev_priv
);
410 if (!dev_priv
->display
.disable_fbc
)
413 dev_priv
->display
.disable_fbc(dev
);
414 dev_priv
->fbc
.plane
= -1;
417 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
418 enum no_fbc_reason reason
)
420 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
423 dev_priv
->fbc
.no_fbc_reason
= reason
;
428 * intel_update_fbc - enable/disable FBC as needed
429 * @dev: the drm_device
431 * Set up the framebuffer compression hardware at mode set time. We
432 * enable it if possible:
433 * - plane A only (on pre-965)
434 * - no pixel mulitply/line duplication
435 * - no alpha buffer discard
437 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
439 * We can't assume that any compression will take place (worst case),
440 * so the compressed buffer has to be the same size as the uncompressed
441 * one. It also must reside (along with the line length buffer) in
444 * We need to enable/disable FBC on a global basis.
446 void intel_update_fbc(struct drm_device
*dev
)
448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
449 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
450 struct intel_crtc
*intel_crtc
;
451 struct drm_framebuffer
*fb
;
452 struct intel_framebuffer
*intel_fb
;
453 struct drm_i915_gem_object
*obj
;
454 const struct drm_display_mode
*adjusted_mode
;
455 unsigned int max_width
, max_height
;
457 if (!I915_HAS_FBC(dev
)) {
458 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
462 if (!i915_powersave
) {
463 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
464 DRM_DEBUG_KMS("fbc disabled per module param\n");
469 * If FBC is already on, we just have to verify that we can
470 * keep it that way...
471 * Need to disable if:
472 * - more than one pipe is active
473 * - changing FBC params (stride, fence, mode)
474 * - new fb is too large to fit in compressed buffer
475 * - going to an unsupported config (interlace, pixel multiply, etc.)
477 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
478 if (intel_crtc_active(tmp_crtc
) &&
479 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
481 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
482 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
489 if (!crtc
|| crtc
->fb
== NULL
) {
490 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
491 DRM_DEBUG_KMS("no output, disabling\n");
495 intel_crtc
= to_intel_crtc(crtc
);
497 intel_fb
= to_intel_framebuffer(fb
);
499 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
501 if (i915_enable_fbc
< 0 &&
502 INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
)) {
503 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
504 DRM_DEBUG_KMS("disabled per chip default\n");
507 if (!i915_enable_fbc
) {
508 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
509 DRM_DEBUG_KMS("fbc disabled per module param\n");
512 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
513 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
514 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
515 DRM_DEBUG_KMS("mode incompatible with compression, "
520 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
527 if (intel_crtc
->config
.pipe_src_w
> max_width
||
528 intel_crtc
->config
.pipe_src_h
> max_height
) {
529 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
530 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
533 if ((IS_I915GM(dev
) || IS_I945GM(dev
) || IS_HASWELL(dev
)) &&
534 intel_crtc
->plane
!= 0) {
535 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
536 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
540 /* The use of a CPU fence is mandatory in order to detect writes
541 * by the CPU to the scanout and trigger updates to the FBC.
543 if (obj
->tiling_mode
!= I915_TILING_X
||
544 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
545 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
546 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
550 /* If the kernel debugger is active, always disable compression */
554 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
555 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
556 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
560 /* If the scanout has not changed, don't modify the FBC settings.
561 * Note that we make the fundamental assumption that the fb->obj
562 * cannot be unpinned (and have its GTT offset and fence revoked)
563 * without first being decoupled from the scanout and FBC disabled.
565 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
566 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
567 dev_priv
->fbc
.y
== crtc
->y
)
570 if (intel_fbc_enabled(dev
)) {
571 /* We update FBC along two paths, after changing fb/crtc
572 * configuration (modeswitching) and after page-flipping
573 * finishes. For the latter, we know that not only did
574 * we disable the FBC at the start of the page-flip
575 * sequence, but also more than one vblank has passed.
577 * For the former case of modeswitching, it is possible
578 * to switch between two FBC valid configurations
579 * instantaneously so we do need to disable the FBC
580 * before we can modify its control registers. We also
581 * have to wait for the next vblank for that to take
582 * effect. However, since we delay enabling FBC we can
583 * assume that a vblank has passed since disabling and
584 * that we can safely alter the registers in the deferred
587 * In the scenario that we go from a valid to invalid
588 * and then back to valid FBC configuration we have
589 * no strict enforcement that a vblank occurred since
590 * disabling the FBC. However, along all current pipe
591 * disabling paths we do need to wait for a vblank at
592 * some point. And we wait before enabling FBC anyway.
594 DRM_DEBUG_KMS("disabling active FBC for update\n");
595 intel_disable_fbc(dev
);
598 intel_enable_fbc(crtc
, 500);
599 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
603 /* Multiple disables should be harmless */
604 if (intel_fbc_enabled(dev
)) {
605 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
606 intel_disable_fbc(dev
);
608 i915_gem_stolen_cleanup_compression(dev
);
611 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
613 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
616 tmp
= I915_READ(CLKCFG
);
618 switch (tmp
& CLKCFG_FSB_MASK
) {
620 dev_priv
->fsb_freq
= 533; /* 133*4 */
623 dev_priv
->fsb_freq
= 800; /* 200*4 */
626 dev_priv
->fsb_freq
= 667; /* 167*4 */
629 dev_priv
->fsb_freq
= 400; /* 100*4 */
633 switch (tmp
& CLKCFG_MEM_MASK
) {
635 dev_priv
->mem_freq
= 533;
638 dev_priv
->mem_freq
= 667;
641 dev_priv
->mem_freq
= 800;
645 /* detect pineview DDR3 setting */
646 tmp
= I915_READ(CSHRDDR3CTL
);
647 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
650 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
655 ddrpll
= I915_READ16(DDRMPLL1
);
656 csipll
= I915_READ16(CSIPLL0
);
658 switch (ddrpll
& 0xff) {
660 dev_priv
->mem_freq
= 800;
663 dev_priv
->mem_freq
= 1066;
666 dev_priv
->mem_freq
= 1333;
669 dev_priv
->mem_freq
= 1600;
672 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
674 dev_priv
->mem_freq
= 0;
678 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
680 switch (csipll
& 0x3ff) {
682 dev_priv
->fsb_freq
= 3200;
685 dev_priv
->fsb_freq
= 3733;
688 dev_priv
->fsb_freq
= 4266;
691 dev_priv
->fsb_freq
= 4800;
694 dev_priv
->fsb_freq
= 5333;
697 dev_priv
->fsb_freq
= 5866;
700 dev_priv
->fsb_freq
= 6400;
703 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
705 dev_priv
->fsb_freq
= 0;
709 if (dev_priv
->fsb_freq
== 3200) {
710 dev_priv
->ips
.c_m
= 0;
711 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
712 dev_priv
->ips
.c_m
= 1;
714 dev_priv
->ips
.c_m
= 2;
718 static const struct cxsr_latency cxsr_latency_table
[] = {
719 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
720 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
721 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
722 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
723 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
725 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
726 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
727 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
728 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
729 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
731 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
732 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
733 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
734 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
735 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
737 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
738 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
739 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
740 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
741 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
743 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
744 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
745 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
746 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
747 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
749 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
750 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
751 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
752 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
753 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
756 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
761 const struct cxsr_latency
*latency
;
764 if (fsb
== 0 || mem
== 0)
767 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
768 latency
= &cxsr_latency_table
[i
];
769 if (is_desktop
== latency
->is_desktop
&&
770 is_ddr3
== latency
->is_ddr3
&&
771 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
775 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
780 static void pineview_disable_cxsr(struct drm_device
*dev
)
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 /* deactivate cxsr */
785 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
789 * Latency for FIFO fetches is dependent on several factors:
790 * - memory configuration (speed, channels)
792 * - current MCH state
793 * It can be fairly high in some situations, so here we assume a fairly
794 * pessimal value. It's a tradeoff between extra memory fetches (if we
795 * set this value too high, the FIFO will fetch frequently to stay full)
796 * and power consumption (set it too low to save power and we might see
797 * FIFO underruns and display "flicker").
799 * A value of 5us seems to be a good balance; safe for very low end
800 * platforms but not overly aggressive on lower latency configs.
802 static const int latency_ns
= 5000;
804 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
807 uint32_t dsparb
= I915_READ(DSPARB
);
810 size
= dsparb
& 0x7f;
812 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
814 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
815 plane
? "B" : "A", size
);
820 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
823 uint32_t dsparb
= I915_READ(DSPARB
);
826 size
= dsparb
& 0x1ff;
828 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
829 size
>>= 1; /* Convert to cachelines */
831 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
832 plane
? "B" : "A", size
);
837 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
840 uint32_t dsparb
= I915_READ(DSPARB
);
843 size
= dsparb
& 0x7f;
844 size
>>= 2; /* Convert to cachelines */
846 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
853 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
856 uint32_t dsparb
= I915_READ(DSPARB
);
859 size
= dsparb
& 0x7f;
860 size
>>= 1; /* Convert to cachelines */
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
863 plane
? "B" : "A", size
);
868 /* Pineview has different values for various configs */
869 static const struct intel_watermark_params pineview_display_wm
= {
870 PINEVIEW_DISPLAY_FIFO
,
874 PINEVIEW_FIFO_LINE_SIZE
876 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
877 PINEVIEW_DISPLAY_FIFO
,
879 PINEVIEW_DFT_HPLLOFF_WM
,
881 PINEVIEW_FIFO_LINE_SIZE
883 static const struct intel_watermark_params pineview_cursor_wm
= {
884 PINEVIEW_CURSOR_FIFO
,
885 PINEVIEW_CURSOR_MAX_WM
,
886 PINEVIEW_CURSOR_DFT_WM
,
887 PINEVIEW_CURSOR_GUARD_WM
,
888 PINEVIEW_FIFO_LINE_SIZE
,
890 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
891 PINEVIEW_CURSOR_FIFO
,
892 PINEVIEW_CURSOR_MAX_WM
,
893 PINEVIEW_CURSOR_DFT_WM
,
894 PINEVIEW_CURSOR_GUARD_WM
,
895 PINEVIEW_FIFO_LINE_SIZE
897 static const struct intel_watermark_params g4x_wm_info
= {
904 static const struct intel_watermark_params g4x_cursor_wm_info
= {
911 static const struct intel_watermark_params valleyview_wm_info
= {
912 VALLEYVIEW_FIFO_SIZE
,
918 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
920 VALLEYVIEW_CURSOR_MAX_WM
,
925 static const struct intel_watermark_params i965_cursor_wm_info
= {
932 static const struct intel_watermark_params i945_wm_info
= {
939 static const struct intel_watermark_params i915_wm_info
= {
946 static const struct intel_watermark_params i855_wm_info
= {
953 static const struct intel_watermark_params i830_wm_info
= {
961 static const struct intel_watermark_params ironlake_display_wm_info
= {
968 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
975 static const struct intel_watermark_params ironlake_display_srwm_info
= {
977 ILK_DISPLAY_MAX_SRWM
,
978 ILK_DISPLAY_DFT_SRWM
,
982 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
990 static const struct intel_watermark_params sandybridge_display_wm_info
= {
997 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
1004 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
1005 SNB_DISPLAY_SR_FIFO
,
1006 SNB_DISPLAY_MAX_SRWM
,
1007 SNB_DISPLAY_DFT_SRWM
,
1011 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
1013 SNB_CURSOR_MAX_SRWM
,
1014 SNB_CURSOR_DFT_SRWM
,
1021 * intel_calculate_wm - calculate watermark level
1022 * @clock_in_khz: pixel clock
1023 * @wm: chip FIFO params
1024 * @pixel_size: display pixel size
1025 * @latency_ns: memory latency for the platform
1027 * Calculate the watermark level (the level at which the display plane will
1028 * start fetching from memory again). Each chip has a different display
1029 * FIFO size and allocation, so the caller needs to figure that out and pass
1030 * in the correct intel_watermark_params structure.
1032 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1033 * on the pixel size. When it reaches the watermark level, it'll start
1034 * fetching FIFO line sized based chunks from memory until the FIFO fills
1035 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1036 * will occur, and a display engine hang could result.
1038 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1039 const struct intel_watermark_params
*wm
,
1042 unsigned long latency_ns
)
1044 long entries_required
, wm_size
;
1047 * Note: we need to make sure we don't overflow for various clock &
1049 * clocks go from a few thousand to several hundred thousand.
1050 * latency is usually a few thousand
1052 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1054 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1056 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1058 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1060 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1062 /* Don't promote wm_size to unsigned... */
1063 if (wm_size
> (long)wm
->max_wm
)
1064 wm_size
= wm
->max_wm
;
1066 wm_size
= wm
->default_wm
;
1070 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1072 struct drm_crtc
*crtc
, *enabled
= NULL
;
1074 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1075 if (intel_crtc_active(crtc
)) {
1085 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1087 struct drm_device
*dev
= unused_crtc
->dev
;
1088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1089 struct drm_crtc
*crtc
;
1090 const struct cxsr_latency
*latency
;
1094 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1095 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1097 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1098 pineview_disable_cxsr(dev
);
1102 crtc
= single_enabled_crtc(dev
);
1104 const struct drm_display_mode
*adjusted_mode
;
1105 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1108 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1109 clock
= adjusted_mode
->crtc_clock
;
1112 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1113 pineview_display_wm
.fifo_size
,
1114 pixel_size
, latency
->display_sr
);
1115 reg
= I915_READ(DSPFW1
);
1116 reg
&= ~DSPFW_SR_MASK
;
1117 reg
|= wm
<< DSPFW_SR_SHIFT
;
1118 I915_WRITE(DSPFW1
, reg
);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1122 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1123 pineview_display_wm
.fifo_size
,
1124 pixel_size
, latency
->cursor_sr
);
1125 reg
= I915_READ(DSPFW3
);
1126 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1127 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1128 I915_WRITE(DSPFW3
, reg
);
1130 /* Display HPLL off SR */
1131 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1132 pineview_display_hplloff_wm
.fifo_size
,
1133 pixel_size
, latency
->display_hpll_disable
);
1134 reg
= I915_READ(DSPFW3
);
1135 reg
&= ~DSPFW_HPLL_SR_MASK
;
1136 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1137 I915_WRITE(DSPFW3
, reg
);
1139 /* cursor HPLL off SR */
1140 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1141 pineview_display_hplloff_wm
.fifo_size
,
1142 pixel_size
, latency
->cursor_hpll_disable
);
1143 reg
= I915_READ(DSPFW3
);
1144 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1145 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1146 I915_WRITE(DSPFW3
, reg
);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1151 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1154 pineview_disable_cxsr(dev
);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1159 static bool g4x_compute_wm0(struct drm_device
*dev
,
1161 const struct intel_watermark_params
*display
,
1162 int display_latency_ns
,
1163 const struct intel_watermark_params
*cursor
,
1164 int cursor_latency_ns
,
1168 struct drm_crtc
*crtc
;
1169 const struct drm_display_mode
*adjusted_mode
;
1170 int htotal
, hdisplay
, clock
, pixel_size
;
1171 int line_time_us
, line_count
;
1172 int entries
, tlb_miss
;
1174 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1175 if (!intel_crtc_active(crtc
)) {
1176 *cursor_wm
= cursor
->guard_size
;
1177 *plane_wm
= display
->guard_size
;
1181 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1182 clock
= adjusted_mode
->crtc_clock
;
1183 htotal
= adjusted_mode
->crtc_htotal
;
1184 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1185 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1187 /* Use the small buffer method to calculate plane watermark */
1188 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1189 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1191 entries
+= tlb_miss
;
1192 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1193 *plane_wm
= entries
+ display
->guard_size
;
1194 if (*plane_wm
> (int)display
->max_wm
)
1195 *plane_wm
= display
->max_wm
;
1197 /* Use the large buffer method to calculate cursor watermark */
1198 line_time_us
= ((htotal
* 1000) / clock
);
1199 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1200 entries
= line_count
* 64 * pixel_size
;
1201 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1203 entries
+= tlb_miss
;
1204 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1205 *cursor_wm
= entries
+ cursor
->guard_size
;
1206 if (*cursor_wm
> (int)cursor
->max_wm
)
1207 *cursor_wm
= (int)cursor
->max_wm
;
1213 * Check the wm result.
1215 * If any calculated watermark values is larger than the maximum value that
1216 * can be programmed into the associated watermark register, that watermark
1219 static bool g4x_check_srwm(struct drm_device
*dev
,
1220 int display_wm
, int cursor_wm
,
1221 const struct intel_watermark_params
*display
,
1222 const struct intel_watermark_params
*cursor
)
1224 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1225 display_wm
, cursor_wm
);
1227 if (display_wm
> display
->max_wm
) {
1228 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1229 display_wm
, display
->max_wm
);
1233 if (cursor_wm
> cursor
->max_wm
) {
1234 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1235 cursor_wm
, cursor
->max_wm
);
1239 if (!(display_wm
|| cursor_wm
)) {
1240 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1247 static bool g4x_compute_srwm(struct drm_device
*dev
,
1250 const struct intel_watermark_params
*display
,
1251 const struct intel_watermark_params
*cursor
,
1252 int *display_wm
, int *cursor_wm
)
1254 struct drm_crtc
*crtc
;
1255 const struct drm_display_mode
*adjusted_mode
;
1256 int hdisplay
, htotal
, pixel_size
, clock
;
1257 unsigned long line_time_us
;
1258 int line_count
, line_size
;
1263 *display_wm
= *cursor_wm
= 0;
1267 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1268 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1269 clock
= adjusted_mode
->crtc_clock
;
1270 htotal
= adjusted_mode
->crtc_htotal
;
1271 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1272 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1274 line_time_us
= (htotal
* 1000) / clock
;
1275 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1276 line_size
= hdisplay
* pixel_size
;
1278 /* Use the minimum of the small and large buffer method for primary */
1279 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1280 large
= line_count
* line_size
;
1282 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1283 *display_wm
= entries
+ display
->guard_size
;
1285 /* calculate the self-refresh watermark for display cursor */
1286 entries
= line_count
* pixel_size
* 64;
1287 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1288 *cursor_wm
= entries
+ cursor
->guard_size
;
1290 return g4x_check_srwm(dev
,
1291 *display_wm
, *cursor_wm
,
1295 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1297 int *plane_prec_mult
,
1299 int *cursor_prec_mult
,
1302 struct drm_crtc
*crtc
;
1303 int clock
, pixel_size
;
1306 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1307 if (!intel_crtc_active(crtc
))
1310 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1311 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1313 entries
= (clock
/ 1000) * pixel_size
;
1314 *plane_prec_mult
= (entries
> 256) ?
1315 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1316 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1319 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1320 *cursor_prec_mult
= (entries
> 256) ?
1321 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1322 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1328 * Update drain latency registers of memory arbiter
1330 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1331 * to be programmed. Each plane has a drain latency multiplier and a drain
1335 static void vlv_update_drain_latency(struct drm_device
*dev
)
1337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1338 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1339 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1340 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1343 /* For plane A, Cursor A */
1344 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1345 &cursor_prec_mult
, &cursora_dl
)) {
1346 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1347 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1348 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1349 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1351 I915_WRITE(VLV_DDL1
, cursora_prec
|
1352 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1353 planea_prec
| planea_dl
);
1356 /* For plane B, Cursor B */
1357 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1358 &cursor_prec_mult
, &cursorb_dl
)) {
1359 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1360 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1361 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1362 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1364 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1365 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1366 planeb_prec
| planeb_dl
);
1370 #define single_plane_enabled(mask) is_power_of_2(mask)
1372 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1374 struct drm_device
*dev
= crtc
->dev
;
1375 static const int sr_latency_ns
= 12000;
1376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1377 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1378 int plane_sr
, cursor_sr
;
1379 int ignore_plane_sr
, ignore_cursor_sr
;
1380 unsigned int enabled
= 0;
1382 vlv_update_drain_latency(dev
);
1384 if (g4x_compute_wm0(dev
, PIPE_A
,
1385 &valleyview_wm_info
, latency_ns
,
1386 &valleyview_cursor_wm_info
, latency_ns
,
1387 &planea_wm
, &cursora_wm
))
1388 enabled
|= 1 << PIPE_A
;
1390 if (g4x_compute_wm0(dev
, PIPE_B
,
1391 &valleyview_wm_info
, latency_ns
,
1392 &valleyview_cursor_wm_info
, latency_ns
,
1393 &planeb_wm
, &cursorb_wm
))
1394 enabled
|= 1 << PIPE_B
;
1396 if (single_plane_enabled(enabled
) &&
1397 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1399 &valleyview_wm_info
,
1400 &valleyview_cursor_wm_info
,
1401 &plane_sr
, &ignore_cursor_sr
) &&
1402 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1404 &valleyview_wm_info
,
1405 &valleyview_cursor_wm_info
,
1406 &ignore_plane_sr
, &cursor_sr
)) {
1407 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1409 I915_WRITE(FW_BLC_SELF_VLV
,
1410 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1411 plane_sr
= cursor_sr
= 0;
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm
, cursora_wm
,
1416 planeb_wm
, cursorb_wm
,
1417 plane_sr
, cursor_sr
);
1420 (plane_sr
<< DSPFW_SR_SHIFT
) |
1421 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1422 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1425 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1426 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1428 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1429 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1432 static void g4x_update_wm(struct drm_crtc
*crtc
)
1434 struct drm_device
*dev
= crtc
->dev
;
1435 static const int sr_latency_ns
= 12000;
1436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1437 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1438 int plane_sr
, cursor_sr
;
1439 unsigned int enabled
= 0;
1441 if (g4x_compute_wm0(dev
, PIPE_A
,
1442 &g4x_wm_info
, latency_ns
,
1443 &g4x_cursor_wm_info
, latency_ns
,
1444 &planea_wm
, &cursora_wm
))
1445 enabled
|= 1 << PIPE_A
;
1447 if (g4x_compute_wm0(dev
, PIPE_B
,
1448 &g4x_wm_info
, latency_ns
,
1449 &g4x_cursor_wm_info
, latency_ns
,
1450 &planeb_wm
, &cursorb_wm
))
1451 enabled
|= 1 << PIPE_B
;
1453 if (single_plane_enabled(enabled
) &&
1454 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1457 &g4x_cursor_wm_info
,
1458 &plane_sr
, &cursor_sr
)) {
1459 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1461 I915_WRITE(FW_BLC_SELF
,
1462 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1463 plane_sr
= cursor_sr
= 0;
1466 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1467 planea_wm
, cursora_wm
,
1468 planeb_wm
, cursorb_wm
,
1469 plane_sr
, cursor_sr
);
1472 (plane_sr
<< DSPFW_SR_SHIFT
) |
1473 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1474 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1477 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1478 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1479 /* HPLL off in SR has some issues on G4x... disable it */
1481 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1482 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1485 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1487 struct drm_device
*dev
= unused_crtc
->dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 struct drm_crtc
*crtc
;
1493 /* Calc sr entries for one plane configs */
1494 crtc
= single_enabled_crtc(dev
);
1496 /* self-refresh has much higher latency */
1497 static const int sr_latency_ns
= 12000;
1498 const struct drm_display_mode
*adjusted_mode
=
1499 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1500 int clock
= adjusted_mode
->crtc_clock
;
1501 int htotal
= adjusted_mode
->crtc_htotal
;
1502 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1503 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1504 unsigned long line_time_us
;
1507 line_time_us
= ((htotal
* 1000) / clock
);
1509 /* Use ns/us then divide to preserve precision */
1510 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1511 pixel_size
* hdisplay
;
1512 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1513 srwm
= I965_FIFO_SIZE
- entries
;
1517 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1520 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1522 entries
= DIV_ROUND_UP(entries
,
1523 i965_cursor_wm_info
.cacheline_size
);
1524 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1525 (entries
+ i965_cursor_wm_info
.guard_size
);
1527 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1528 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1530 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1531 "cursor %d\n", srwm
, cursor_sr
);
1533 if (IS_CRESTLINE(dev
))
1534 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1536 /* Turn off self refresh if both pipes are enabled */
1537 if (IS_CRESTLINE(dev
))
1538 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1542 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1545 /* 965 has limitations... */
1546 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1547 (8 << 16) | (8 << 8) | (8 << 0));
1548 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1549 /* update cursor SR watermark */
1550 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1553 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1555 struct drm_device
*dev
= unused_crtc
->dev
;
1556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1557 const struct intel_watermark_params
*wm_info
;
1562 int planea_wm
, planeb_wm
;
1563 struct drm_crtc
*crtc
, *enabled
= NULL
;
1566 wm_info
= &i945_wm_info
;
1567 else if (!IS_GEN2(dev
))
1568 wm_info
= &i915_wm_info
;
1570 wm_info
= &i855_wm_info
;
1572 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1573 crtc
= intel_get_crtc_for_plane(dev
, 0);
1574 if (intel_crtc_active(crtc
)) {
1575 const struct drm_display_mode
*adjusted_mode
;
1576 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1580 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1581 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1582 wm_info
, fifo_size
, cpp
,
1586 planea_wm
= fifo_size
- wm_info
->guard_size
;
1588 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1589 crtc
= intel_get_crtc_for_plane(dev
, 1);
1590 if (intel_crtc_active(crtc
)) {
1591 const struct drm_display_mode
*adjusted_mode
;
1592 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1596 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1597 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1598 wm_info
, fifo_size
, cpp
,
1600 if (enabled
== NULL
)
1605 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1607 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1610 * Overlay gets an aggressive default since video jitter is bad.
1614 /* Play safe and disable self-refresh before adjusting watermarks. */
1615 if (IS_I945G(dev
) || IS_I945GM(dev
))
1616 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1617 else if (IS_I915GM(dev
))
1618 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1620 /* Calc sr entries for one plane configs */
1621 if (HAS_FW_BLC(dev
) && enabled
) {
1622 /* self-refresh has much higher latency */
1623 static const int sr_latency_ns
= 6000;
1624 const struct drm_display_mode
*adjusted_mode
=
1625 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1626 int clock
= adjusted_mode
->crtc_clock
;
1627 int htotal
= adjusted_mode
->crtc_htotal
;
1628 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1629 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1630 unsigned long line_time_us
;
1633 line_time_us
= (htotal
* 1000) / clock
;
1635 /* Use ns/us then divide to preserve precision */
1636 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1637 pixel_size
* hdisplay
;
1638 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1639 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1640 srwm
= wm_info
->fifo_size
- entries
;
1644 if (IS_I945G(dev
) || IS_I945GM(dev
))
1645 I915_WRITE(FW_BLC_SELF
,
1646 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1647 else if (IS_I915GM(dev
))
1648 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1651 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1652 planea_wm
, planeb_wm
, cwm
, srwm
);
1654 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1655 fwater_hi
= (cwm
& 0x1f);
1657 /* Set request length to 8 cachelines per fetch */
1658 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1659 fwater_hi
= fwater_hi
| (1 << 8);
1661 I915_WRITE(FW_BLC
, fwater_lo
);
1662 I915_WRITE(FW_BLC2
, fwater_hi
);
1664 if (HAS_FW_BLC(dev
)) {
1666 if (IS_I945G(dev
) || IS_I945GM(dev
))
1667 I915_WRITE(FW_BLC_SELF
,
1668 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1669 else if (IS_I915GM(dev
))
1670 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1671 DRM_DEBUG_KMS("memory self refresh enabled\n");
1673 DRM_DEBUG_KMS("memory self refresh disabled\n");
1677 static void i830_update_wm(struct drm_crtc
*unused_crtc
)
1679 struct drm_device
*dev
= unused_crtc
->dev
;
1680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1681 struct drm_crtc
*crtc
;
1682 const struct drm_display_mode
*adjusted_mode
;
1686 crtc
= single_enabled_crtc(dev
);
1690 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1691 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1693 dev_priv
->display
.get_fifo_size(dev
, 0),
1695 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1696 fwater_lo
|= (3<<8) | planea_wm
;
1698 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1700 I915_WRITE(FW_BLC
, fwater_lo
);
1704 * Check the wm result.
1706 * If any calculated watermark values is larger than the maximum value that
1707 * can be programmed into the associated watermark register, that watermark
1710 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1711 int fbc_wm
, int display_wm
, int cursor_wm
,
1712 const struct intel_watermark_params
*display
,
1713 const struct intel_watermark_params
*cursor
)
1715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1717 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1718 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1720 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1721 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1722 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1724 /* fbc has it's own way to disable FBC WM */
1725 I915_WRITE(DISP_ARB_CTL
,
1726 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1728 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1729 /* enable FBC WM (except on ILK, where it must remain off) */
1730 I915_WRITE(DISP_ARB_CTL
,
1731 I915_READ(DISP_ARB_CTL
) & ~DISP_FBC_WM_DIS
);
1734 if (display_wm
> display
->max_wm
) {
1735 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1736 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1740 if (cursor_wm
> cursor
->max_wm
) {
1741 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1742 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1746 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1747 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1755 * Compute watermark values of WM[1-3],
1757 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1759 const struct intel_watermark_params
*display
,
1760 const struct intel_watermark_params
*cursor
,
1761 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1763 struct drm_crtc
*crtc
;
1764 const struct drm_display_mode
*adjusted_mode
;
1765 unsigned long line_time_us
;
1766 int hdisplay
, htotal
, pixel_size
, clock
;
1767 int line_count
, line_size
;
1772 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1776 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1777 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1778 clock
= adjusted_mode
->crtc_clock
;
1779 htotal
= adjusted_mode
->crtc_htotal
;
1780 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1781 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1783 line_time_us
= (htotal
* 1000) / clock
;
1784 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1785 line_size
= hdisplay
* pixel_size
;
1787 /* Use the minimum of the small and large buffer method for primary */
1788 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1789 large
= line_count
* line_size
;
1791 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1792 *display_wm
= entries
+ display
->guard_size
;
1796 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1798 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1800 /* calculate the self-refresh watermark for display cursor */
1801 entries
= line_count
* pixel_size
* 64;
1802 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1803 *cursor_wm
= entries
+ cursor
->guard_size
;
1805 return ironlake_check_srwm(dev
, level
,
1806 *fbc_wm
, *display_wm
, *cursor_wm
,
1810 static void ironlake_update_wm(struct drm_crtc
*crtc
)
1812 struct drm_device
*dev
= crtc
->dev
;
1813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1814 int fbc_wm
, plane_wm
, cursor_wm
;
1815 unsigned int enabled
;
1818 if (g4x_compute_wm0(dev
, PIPE_A
,
1819 &ironlake_display_wm_info
,
1820 dev_priv
->wm
.pri_latency
[0] * 100,
1821 &ironlake_cursor_wm_info
,
1822 dev_priv
->wm
.cur_latency
[0] * 100,
1823 &plane_wm
, &cursor_wm
)) {
1824 I915_WRITE(WM0_PIPEA_ILK
,
1825 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1826 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1827 " plane %d, " "cursor: %d\n",
1828 plane_wm
, cursor_wm
);
1829 enabled
|= 1 << PIPE_A
;
1832 if (g4x_compute_wm0(dev
, PIPE_B
,
1833 &ironlake_display_wm_info
,
1834 dev_priv
->wm
.pri_latency
[0] * 100,
1835 &ironlake_cursor_wm_info
,
1836 dev_priv
->wm
.cur_latency
[0] * 100,
1837 &plane_wm
, &cursor_wm
)) {
1838 I915_WRITE(WM0_PIPEB_ILK
,
1839 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1840 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1841 " plane %d, cursor: %d\n",
1842 plane_wm
, cursor_wm
);
1843 enabled
|= 1 << PIPE_B
;
1847 * Calculate and update the self-refresh watermark only when one
1848 * display plane is used.
1850 I915_WRITE(WM3_LP_ILK
, 0);
1851 I915_WRITE(WM2_LP_ILK
, 0);
1852 I915_WRITE(WM1_LP_ILK
, 0);
1854 if (!single_plane_enabled(enabled
))
1856 enabled
= ffs(enabled
) - 1;
1859 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1860 dev_priv
->wm
.pri_latency
[1] * 500,
1861 &ironlake_display_srwm_info
,
1862 &ironlake_cursor_srwm_info
,
1863 &fbc_wm
, &plane_wm
, &cursor_wm
))
1866 I915_WRITE(WM1_LP_ILK
,
1868 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
1869 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1870 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1874 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1875 dev_priv
->wm
.pri_latency
[2] * 500,
1876 &ironlake_display_srwm_info
,
1877 &ironlake_cursor_srwm_info
,
1878 &fbc_wm
, &plane_wm
, &cursor_wm
))
1881 I915_WRITE(WM2_LP_ILK
,
1883 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
1884 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1885 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1889 * WM3 is unsupported on ILK, probably because we don't have latency
1890 * data for that power state
1894 static void sandybridge_update_wm(struct drm_crtc
*crtc
)
1896 struct drm_device
*dev
= crtc
->dev
;
1897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1898 int latency
= dev_priv
->wm
.pri_latency
[0] * 100; /* In unit 0.1us */
1900 int fbc_wm
, plane_wm
, cursor_wm
;
1901 unsigned int enabled
;
1904 if (g4x_compute_wm0(dev
, PIPE_A
,
1905 &sandybridge_display_wm_info
, latency
,
1906 &sandybridge_cursor_wm_info
, latency
,
1907 &plane_wm
, &cursor_wm
)) {
1908 val
= I915_READ(WM0_PIPEA_ILK
);
1909 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1910 I915_WRITE(WM0_PIPEA_ILK
, val
|
1911 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1912 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1913 " plane %d, " "cursor: %d\n",
1914 plane_wm
, cursor_wm
);
1915 enabled
|= 1 << PIPE_A
;
1918 if (g4x_compute_wm0(dev
, PIPE_B
,
1919 &sandybridge_display_wm_info
, latency
,
1920 &sandybridge_cursor_wm_info
, latency
,
1921 &plane_wm
, &cursor_wm
)) {
1922 val
= I915_READ(WM0_PIPEB_ILK
);
1923 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1924 I915_WRITE(WM0_PIPEB_ILK
, val
|
1925 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1926 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1927 " plane %d, cursor: %d\n",
1928 plane_wm
, cursor_wm
);
1929 enabled
|= 1 << PIPE_B
;
1933 * Calculate and update the self-refresh watermark only when one
1934 * display plane is used.
1936 * SNB support 3 levels of watermark.
1938 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1939 * and disabled in the descending order
1942 I915_WRITE(WM3_LP_ILK
, 0);
1943 I915_WRITE(WM2_LP_ILK
, 0);
1944 I915_WRITE(WM1_LP_ILK
, 0);
1946 if (!single_plane_enabled(enabled
) ||
1947 dev_priv
->sprite_scaling_enabled
)
1949 enabled
= ffs(enabled
) - 1;
1952 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1953 dev_priv
->wm
.pri_latency
[1] * 500,
1954 &sandybridge_display_srwm_info
,
1955 &sandybridge_cursor_srwm_info
,
1956 &fbc_wm
, &plane_wm
, &cursor_wm
))
1959 I915_WRITE(WM1_LP_ILK
,
1961 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
1962 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1963 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1967 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1968 dev_priv
->wm
.pri_latency
[2] * 500,
1969 &sandybridge_display_srwm_info
,
1970 &sandybridge_cursor_srwm_info
,
1971 &fbc_wm
, &plane_wm
, &cursor_wm
))
1974 I915_WRITE(WM2_LP_ILK
,
1976 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
1977 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1978 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1982 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1983 dev_priv
->wm
.pri_latency
[3] * 500,
1984 &sandybridge_display_srwm_info
,
1985 &sandybridge_cursor_srwm_info
,
1986 &fbc_wm
, &plane_wm
, &cursor_wm
))
1989 I915_WRITE(WM3_LP_ILK
,
1991 (dev_priv
->wm
.pri_latency
[3] << WM1_LP_LATENCY_SHIFT
) |
1992 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1993 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1997 static void ivybridge_update_wm(struct drm_crtc
*crtc
)
1999 struct drm_device
*dev
= crtc
->dev
;
2000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 int latency
= dev_priv
->wm
.pri_latency
[0] * 100; /* In unit 0.1us */
2003 int fbc_wm
, plane_wm
, cursor_wm
;
2004 int ignore_fbc_wm
, ignore_plane_wm
, ignore_cursor_wm
;
2005 unsigned int enabled
;
2008 if (g4x_compute_wm0(dev
, PIPE_A
,
2009 &sandybridge_display_wm_info
, latency
,
2010 &sandybridge_cursor_wm_info
, latency
,
2011 &plane_wm
, &cursor_wm
)) {
2012 val
= I915_READ(WM0_PIPEA_ILK
);
2013 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2014 I915_WRITE(WM0_PIPEA_ILK
, val
|
2015 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2016 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2017 " plane %d, " "cursor: %d\n",
2018 plane_wm
, cursor_wm
);
2019 enabled
|= 1 << PIPE_A
;
2022 if (g4x_compute_wm0(dev
, PIPE_B
,
2023 &sandybridge_display_wm_info
, latency
,
2024 &sandybridge_cursor_wm_info
, latency
,
2025 &plane_wm
, &cursor_wm
)) {
2026 val
= I915_READ(WM0_PIPEB_ILK
);
2027 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2028 I915_WRITE(WM0_PIPEB_ILK
, val
|
2029 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2030 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2031 " plane %d, cursor: %d\n",
2032 plane_wm
, cursor_wm
);
2033 enabled
|= 1 << PIPE_B
;
2036 if (g4x_compute_wm0(dev
, PIPE_C
,
2037 &sandybridge_display_wm_info
, latency
,
2038 &sandybridge_cursor_wm_info
, latency
,
2039 &plane_wm
, &cursor_wm
)) {
2040 val
= I915_READ(WM0_PIPEC_IVB
);
2041 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2042 I915_WRITE(WM0_PIPEC_IVB
, val
|
2043 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2044 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2045 " plane %d, cursor: %d\n",
2046 plane_wm
, cursor_wm
);
2047 enabled
|= 1 << PIPE_C
;
2051 * Calculate and update the self-refresh watermark only when one
2052 * display plane is used.
2054 * SNB support 3 levels of watermark.
2056 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2057 * and disabled in the descending order
2060 I915_WRITE(WM3_LP_ILK
, 0);
2061 I915_WRITE(WM2_LP_ILK
, 0);
2062 I915_WRITE(WM1_LP_ILK
, 0);
2064 if (!single_plane_enabled(enabled
) ||
2065 dev_priv
->sprite_scaling_enabled
)
2067 enabled
= ffs(enabled
) - 1;
2070 if (!ironlake_compute_srwm(dev
, 1, enabled
,
2071 dev_priv
->wm
.pri_latency
[1] * 500,
2072 &sandybridge_display_srwm_info
,
2073 &sandybridge_cursor_srwm_info
,
2074 &fbc_wm
, &plane_wm
, &cursor_wm
))
2077 I915_WRITE(WM1_LP_ILK
,
2079 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
2080 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2081 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2085 if (!ironlake_compute_srwm(dev
, 2, enabled
,
2086 dev_priv
->wm
.pri_latency
[2] * 500,
2087 &sandybridge_display_srwm_info
,
2088 &sandybridge_cursor_srwm_info
,
2089 &fbc_wm
, &plane_wm
, &cursor_wm
))
2092 I915_WRITE(WM2_LP_ILK
,
2094 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
2095 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2096 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2099 /* WM3, note we have to correct the cursor latency */
2100 if (!ironlake_compute_srwm(dev
, 3, enabled
,
2101 dev_priv
->wm
.pri_latency
[3] * 500,
2102 &sandybridge_display_srwm_info
,
2103 &sandybridge_cursor_srwm_info
,
2104 &fbc_wm
, &plane_wm
, &ignore_cursor_wm
) ||
2105 !ironlake_compute_srwm(dev
, 3, enabled
,
2106 dev_priv
->wm
.cur_latency
[3] * 500,
2107 &sandybridge_display_srwm_info
,
2108 &sandybridge_cursor_srwm_info
,
2109 &ignore_fbc_wm
, &ignore_plane_wm
, &cursor_wm
))
2112 I915_WRITE(WM3_LP_ILK
,
2114 (dev_priv
->wm
.pri_latency
[3] << WM1_LP_LATENCY_SHIFT
) |
2115 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2116 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2120 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
2121 struct drm_crtc
*crtc
)
2123 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2124 uint32_t pixel_rate
;
2126 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
2128 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2129 * adjust the pixel_rate here. */
2131 if (intel_crtc
->config
.pch_pfit
.enabled
) {
2132 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
2133 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
2135 pipe_w
= intel_crtc
->config
.pipe_src_w
;
2136 pipe_h
= intel_crtc
->config
.pipe_src_h
;
2137 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
2138 pfit_h
= pfit_size
& 0xFFFF;
2139 if (pipe_w
< pfit_w
)
2141 if (pipe_h
< pfit_h
)
2144 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
2151 /* latency must be in 0.1us units. */
2152 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2157 if (WARN(latency
== 0, "Latency value missing\n"))
2160 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
2161 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
2166 /* latency must be in 0.1us units. */
2167 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2168 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2173 if (WARN(latency
== 0, "Latency value missing\n"))
2176 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
2177 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
2178 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2182 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2183 uint8_t bytes_per_pixel
)
2185 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
2188 struct hsw_pipe_wm_parameters
{
2190 uint32_t pipe_htotal
;
2191 uint32_t pixel_rate
;
2192 struct intel_plane_wm_parameters pri
;
2193 struct intel_plane_wm_parameters spr
;
2194 struct intel_plane_wm_parameters cur
;
2197 struct hsw_wm_maximums
{
2204 /* used in computing the new watermarks state */
2205 struct intel_wm_config
{
2206 unsigned int num_pipes_active
;
2207 bool sprites_enabled
;
2208 bool sprites_scaled
;
2212 * For both WM_PIPE and WM_LP.
2213 * mem_value must be in 0.1us units.
2215 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters
*params
,
2219 uint32_t method1
, method2
;
2221 if (!params
->active
|| !params
->pri
.enabled
)
2224 method1
= ilk_wm_method1(params
->pixel_rate
,
2225 params
->pri
.bytes_per_pixel
,
2231 method2
= ilk_wm_method2(params
->pixel_rate
,
2232 params
->pipe_htotal
,
2233 params
->pri
.horiz_pixels
,
2234 params
->pri
.bytes_per_pixel
,
2237 return min(method1
, method2
);
2241 * For both WM_PIPE and WM_LP.
2242 * mem_value must be in 0.1us units.
2244 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters
*params
,
2247 uint32_t method1
, method2
;
2249 if (!params
->active
|| !params
->spr
.enabled
)
2252 method1
= ilk_wm_method1(params
->pixel_rate
,
2253 params
->spr
.bytes_per_pixel
,
2255 method2
= ilk_wm_method2(params
->pixel_rate
,
2256 params
->pipe_htotal
,
2257 params
->spr
.horiz_pixels
,
2258 params
->spr
.bytes_per_pixel
,
2260 return min(method1
, method2
);
2264 * For both WM_PIPE and WM_LP.
2265 * mem_value must be in 0.1us units.
2267 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters
*params
,
2270 if (!params
->active
|| !params
->cur
.enabled
)
2273 return ilk_wm_method2(params
->pixel_rate
,
2274 params
->pipe_htotal
,
2275 params
->cur
.horiz_pixels
,
2276 params
->cur
.bytes_per_pixel
,
2280 /* Only for WM_LP. */
2281 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters
*params
,
2284 if (!params
->active
|| !params
->pri
.enabled
)
2287 return ilk_wm_fbc(pri_val
,
2288 params
->pri
.horiz_pixels
,
2289 params
->pri
.bytes_per_pixel
);
2292 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
2294 if (INTEL_INFO(dev
)->gen
>= 8)
2296 else if (INTEL_INFO(dev
)->gen
>= 7)
2302 /* Calculate the maximum primary/sprite plane watermark */
2303 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2305 const struct intel_wm_config
*config
,
2306 enum intel_ddb_partitioning ddb_partitioning
,
2309 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
2312 /* if sprites aren't enabled, sprites get nothing */
2313 if (is_sprite
&& !config
->sprites_enabled
)
2316 /* HSW allows LP1+ watermarks even with multiple pipes */
2317 if (level
== 0 || config
->num_pipes_active
> 1) {
2318 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
2321 * For some reason the non self refresh
2322 * FIFO size is only half of the self
2323 * refresh FIFO size on ILK/SNB.
2325 if (INTEL_INFO(dev
)->gen
<= 6)
2329 if (config
->sprites_enabled
) {
2330 /* level 0 is always calculated with 1:1 split */
2331 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2340 /* clamp to max that the registers can hold */
2341 if (INTEL_INFO(dev
)->gen
>= 8)
2342 max
= level
== 0 ? 255 : 2047;
2343 else if (INTEL_INFO(dev
)->gen
>= 7)
2344 /* IVB/HSW primary/sprite plane watermarks */
2345 max
= level
== 0 ? 127 : 1023;
2346 else if (!is_sprite
)
2347 /* ILK/SNB primary plane watermarks */
2348 max
= level
== 0 ? 127 : 511;
2350 /* ILK/SNB sprite plane watermarks */
2351 max
= level
== 0 ? 63 : 255;
2353 return min(fifo_size
, max
);
2356 /* Calculate the maximum cursor plane watermark */
2357 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2359 const struct intel_wm_config
*config
)
2361 /* HSW LP1+ watermarks w/ multiple pipes */
2362 if (level
> 0 && config
->num_pipes_active
> 1)
2365 /* otherwise just report max that registers can hold */
2366 if (INTEL_INFO(dev
)->gen
>= 7)
2367 return level
== 0 ? 63 : 255;
2369 return level
== 0 ? 31 : 63;
2372 /* Calculate the maximum FBC watermark */
2373 static unsigned int ilk_fbc_wm_max(struct drm_device
*dev
)
2375 /* max that registers can hold */
2376 if (INTEL_INFO(dev
)->gen
>= 8)
2382 static void ilk_compute_wm_maximums(struct drm_device
*dev
,
2384 const struct intel_wm_config
*config
,
2385 enum intel_ddb_partitioning ddb_partitioning
,
2386 struct hsw_wm_maximums
*max
)
2388 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2389 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2390 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2391 max
->fbc
= ilk_fbc_wm_max(dev
);
2394 static bool ilk_validate_wm_level(int level
,
2395 const struct hsw_wm_maximums
*max
,
2396 struct intel_wm_level
*result
)
2400 /* already determined to be invalid? */
2401 if (!result
->enable
)
2404 result
->enable
= result
->pri_val
<= max
->pri
&&
2405 result
->spr_val
<= max
->spr
&&
2406 result
->cur_val
<= max
->cur
;
2408 ret
= result
->enable
;
2411 * HACK until we can pre-compute everything,
2412 * and thus fail gracefully if LP0 watermarks
2415 if (level
== 0 && !result
->enable
) {
2416 if (result
->pri_val
> max
->pri
)
2417 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2418 level
, result
->pri_val
, max
->pri
);
2419 if (result
->spr_val
> max
->spr
)
2420 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2421 level
, result
->spr_val
, max
->spr
);
2422 if (result
->cur_val
> max
->cur
)
2423 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2424 level
, result
->cur_val
, max
->cur
);
2426 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2427 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2428 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2429 result
->enable
= true;
2435 static void ilk_compute_wm_level(struct drm_i915_private
*dev_priv
,
2437 const struct hsw_pipe_wm_parameters
*p
,
2438 struct intel_wm_level
*result
)
2440 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2441 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2442 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2444 /* WM1+ latency values stored in 0.5us units */
2451 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2452 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2453 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2454 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2455 result
->enable
= true;
2459 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2463 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2464 u32 linetime
, ips_linetime
;
2466 if (!intel_crtc_active(crtc
))
2469 /* The WM are computed with base on how long it takes to fill a single
2470 * row at the given clock rate, multiplied by 8.
2472 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2474 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2475 intel_ddi_get_cdclk_freq(dev_priv
));
2477 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2478 PIPE_WM_LINETIME_TIME(linetime
);
2481 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2485 if (IS_HASWELL(dev
)) {
2486 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2488 wm
[0] = (sskpd
>> 56) & 0xFF;
2490 wm
[0] = sskpd
& 0xF;
2491 wm
[1] = (sskpd
>> 4) & 0xFF;
2492 wm
[2] = (sskpd
>> 12) & 0xFF;
2493 wm
[3] = (sskpd
>> 20) & 0x1FF;
2494 wm
[4] = (sskpd
>> 32) & 0x1FF;
2495 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2496 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2498 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2499 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2500 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2501 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2502 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2503 uint32_t mltr
= I915_READ(MLTR_ILK
);
2505 /* ILK primary LP0 latency is 700 ns */
2507 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2508 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2512 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2514 /* ILK sprite LP0 latency is 1300 ns */
2515 if (INTEL_INFO(dev
)->gen
== 5)
2519 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2521 /* ILK cursor LP0 latency is 1300 ns */
2522 if (INTEL_INFO(dev
)->gen
== 5)
2525 /* WaDoubleCursorLP3Latency:ivb */
2526 if (IS_IVYBRIDGE(dev
))
2530 static int ilk_wm_max_level(const struct drm_device
*dev
)
2532 /* how many WM levels are we expecting */
2533 if (IS_HASWELL(dev
))
2535 else if (INTEL_INFO(dev
)->gen
>= 6)
2541 static void intel_print_wm_latency(struct drm_device
*dev
,
2543 const uint16_t wm
[5])
2545 int level
, max_level
= ilk_wm_max_level(dev
);
2547 for (level
= 0; level
<= max_level
; level
++) {
2548 unsigned int latency
= wm
[level
];
2551 DRM_ERROR("%s WM%d latency not provided\n",
2556 /* WM1+ latency values in 0.5us units */
2560 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2561 name
, level
, wm
[level
],
2562 latency
/ 10, latency
% 10);
2566 static void intel_setup_wm_latency(struct drm_device
*dev
)
2568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2570 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2572 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2573 sizeof(dev_priv
->wm
.pri_latency
));
2574 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2575 sizeof(dev_priv
->wm
.pri_latency
));
2577 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2578 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2580 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2581 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2582 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2585 static void hsw_compute_wm_parameters(struct drm_crtc
*crtc
,
2586 struct hsw_pipe_wm_parameters
*p
,
2587 struct intel_wm_config
*config
)
2589 struct drm_device
*dev
= crtc
->dev
;
2590 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2591 enum pipe pipe
= intel_crtc
->pipe
;
2592 struct drm_plane
*plane
;
2594 p
->active
= intel_crtc_active(crtc
);
2596 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.htotal
;
2597 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2598 p
->pri
.bytes_per_pixel
= crtc
->fb
->bits_per_pixel
/ 8;
2599 p
->cur
.bytes_per_pixel
= 4;
2600 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2601 p
->cur
.horiz_pixels
= 64;
2602 /* TODO: for now, assume primary and cursor planes are always enabled. */
2603 p
->pri
.enabled
= true;
2604 p
->cur
.enabled
= true;
2607 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
2608 config
->num_pipes_active
+= intel_crtc_active(crtc
);
2610 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2611 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2613 if (intel_plane
->pipe
== pipe
)
2614 p
->spr
= intel_plane
->wm
;
2616 config
->sprites_enabled
|= intel_plane
->wm
.enabled
;
2617 config
->sprites_scaled
|= intel_plane
->wm
.scaled
;
2621 /* Compute new watermarks for the pipe */
2622 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2623 const struct hsw_pipe_wm_parameters
*params
,
2624 struct intel_pipe_wm
*pipe_wm
)
2626 struct drm_device
*dev
= crtc
->dev
;
2627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2628 int level
, max_level
= ilk_wm_max_level(dev
);
2629 /* LP0 watermark maximums depend on this pipe alone */
2630 struct intel_wm_config config
= {
2631 .num_pipes_active
= 1,
2632 .sprites_enabled
= params
->spr
.enabled
,
2633 .sprites_scaled
= params
->spr
.scaled
,
2635 struct hsw_wm_maximums max
;
2637 /* LP0 watermarks always use 1/2 DDB partitioning */
2638 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2640 for (level
= 0; level
<= max_level
; level
++)
2641 ilk_compute_wm_level(dev_priv
, level
, params
,
2642 &pipe_wm
->wm
[level
]);
2644 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2646 /* At least LP0 must be valid */
2647 return ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]);
2651 * Merge the watermarks from all active pipes for a specific level.
2653 static void ilk_merge_wm_level(struct drm_device
*dev
,
2655 struct intel_wm_level
*ret_wm
)
2657 const struct intel_crtc
*intel_crtc
;
2659 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2660 const struct intel_wm_level
*wm
=
2661 &intel_crtc
->wm
.active
.wm
[level
];
2666 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2667 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2668 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2669 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2672 ret_wm
->enable
= true;
2676 * Merge all low power watermarks for all active pipes.
2678 static void ilk_wm_merge(struct drm_device
*dev
,
2679 const struct hsw_wm_maximums
*max
,
2680 struct intel_pipe_wm
*merged
)
2682 int level
, max_level
= ilk_wm_max_level(dev
);
2684 merged
->fbc_wm_enabled
= true;
2686 /* merge each WM1+ level */
2687 for (level
= 1; level
<= max_level
; level
++) {
2688 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2690 ilk_merge_wm_level(dev
, level
, wm
);
2692 if (!ilk_validate_wm_level(level
, max
, wm
))
2696 * The spec says it is preferred to disable
2697 * FBC WMs instead of disabling a WM level.
2699 if (wm
->fbc_val
> max
->fbc
) {
2700 merged
->fbc_wm_enabled
= false;
2706 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2708 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2709 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2712 static void hsw_compute_wm_results(struct drm_device
*dev
,
2713 const struct intel_pipe_wm
*merged
,
2714 enum intel_ddb_partitioning partitioning
,
2715 struct hsw_wm_values
*results
)
2717 struct intel_crtc
*intel_crtc
;
2720 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2721 results
->partitioning
= partitioning
;
2723 /* LP1+ register values */
2724 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2725 const struct intel_wm_level
*r
;
2727 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2729 r
= &merged
->wm
[level
];
2733 results
->wm_lp
[wm_lp
- 1] = WM3_LP_EN
|
2734 ((level
* 2) << WM1_LP_LATENCY_SHIFT
) |
2735 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2738 if (INTEL_INFO(dev
)->gen
>= 8)
2739 results
->wm_lp
[wm_lp
- 1] |=
2740 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2742 results
->wm_lp
[wm_lp
- 1] |=
2743 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2745 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2748 /* LP0 register values */
2749 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2750 enum pipe pipe
= intel_crtc
->pipe
;
2751 const struct intel_wm_level
*r
=
2752 &intel_crtc
->wm
.active
.wm
[0];
2754 if (WARN_ON(!r
->enable
))
2757 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2759 results
->wm_pipe
[pipe
] =
2760 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2761 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2766 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2767 * case both are at the same level. Prefer r1 in case they're the same. */
2768 static struct intel_pipe_wm
*hsw_find_best_result(struct drm_device
*dev
,
2769 struct intel_pipe_wm
*r1
,
2770 struct intel_pipe_wm
*r2
)
2772 int level
, max_level
= ilk_wm_max_level(dev
);
2773 int level1
= 0, level2
= 0;
2775 for (level
= 1; level
<= max_level
; level
++) {
2776 if (r1
->wm
[level
].enable
)
2778 if (r2
->wm
[level
].enable
)
2782 if (level1
== level2
) {
2783 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2787 } else if (level1
> level2
) {
2794 /* dirty bits used to track which watermarks need changes */
2795 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2796 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2797 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2798 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2799 #define WM_DIRTY_FBC (1 << 24)
2800 #define WM_DIRTY_DDB (1 << 25)
2802 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2803 const struct hsw_wm_values
*old
,
2804 const struct hsw_wm_values
*new)
2806 unsigned int dirty
= 0;
2810 for_each_pipe(pipe
) {
2811 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2812 dirty
|= WM_DIRTY_LINETIME(pipe
);
2813 /* Must disable LP1+ watermarks too */
2814 dirty
|= WM_DIRTY_LP_ALL
;
2817 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2818 dirty
|= WM_DIRTY_PIPE(pipe
);
2819 /* Must disable LP1+ watermarks too */
2820 dirty
|= WM_DIRTY_LP_ALL
;
2824 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2825 dirty
|= WM_DIRTY_FBC
;
2826 /* Must disable LP1+ watermarks too */
2827 dirty
|= WM_DIRTY_LP_ALL
;
2830 if (old
->partitioning
!= new->partitioning
) {
2831 dirty
|= WM_DIRTY_DDB
;
2832 /* Must disable LP1+ watermarks too */
2833 dirty
|= WM_DIRTY_LP_ALL
;
2836 /* LP1+ watermarks already deemed dirty, no need to continue */
2837 if (dirty
& WM_DIRTY_LP_ALL
)
2840 /* Find the lowest numbered LP1+ watermark in need of an update... */
2841 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2842 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2843 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2847 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2848 for (; wm_lp
<= 3; wm_lp
++)
2849 dirty
|= WM_DIRTY_LP(wm_lp
);
2855 * The spec says we shouldn't write when we don't need, because every write
2856 * causes WMs to be re-evaluated, expending some power.
2858 static void hsw_write_wm_values(struct drm_i915_private
*dev_priv
,
2859 struct hsw_wm_values
*results
)
2861 struct hsw_wm_values
*previous
= &dev_priv
->wm
.hw
;
2865 dirty
= ilk_compute_wm_dirty(dev_priv
->dev
, previous
, results
);
2869 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != 0)
2870 I915_WRITE(WM3_LP_ILK
, 0);
2871 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != 0)
2872 I915_WRITE(WM2_LP_ILK
, 0);
2873 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != 0)
2874 I915_WRITE(WM1_LP_ILK
, 0);
2876 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2877 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2878 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2879 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2880 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2881 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2883 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2884 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2885 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2886 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2887 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2888 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2890 if (dirty
& WM_DIRTY_DDB
) {
2891 val
= I915_READ(WM_MISC
);
2892 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2893 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2895 val
|= WM_MISC_DATA_PARTITION_5_6
;
2896 I915_WRITE(WM_MISC
, val
);
2899 if (dirty
& WM_DIRTY_FBC
) {
2900 val
= I915_READ(DISP_ARB_CTL
);
2901 if (results
->enable_fbc_wm
)
2902 val
&= ~DISP_FBC_WM_DIS
;
2904 val
|= DISP_FBC_WM_DIS
;
2905 I915_WRITE(DISP_ARB_CTL
, val
);
2908 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2909 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2910 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2911 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2912 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2913 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2915 if (dirty
& WM_DIRTY_LP(1) && results
->wm_lp
[0] != 0)
2916 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2917 if (dirty
& WM_DIRTY_LP(2) && results
->wm_lp
[1] != 0)
2918 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2919 if (dirty
& WM_DIRTY_LP(3) && results
->wm_lp
[2] != 0)
2920 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2922 dev_priv
->wm
.hw
= *results
;
2925 static void haswell_update_wm(struct drm_crtc
*crtc
)
2927 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2928 struct drm_device
*dev
= crtc
->dev
;
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 struct hsw_wm_maximums max
;
2931 struct hsw_pipe_wm_parameters params
= {};
2932 struct hsw_wm_values results
= {};
2933 enum intel_ddb_partitioning partitioning
;
2934 struct intel_pipe_wm pipe_wm
= {};
2935 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2936 struct intel_wm_config config
= {};
2938 hsw_compute_wm_parameters(crtc
, ¶ms
, &config
);
2940 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2942 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2945 intel_crtc
->wm
.active
= pipe_wm
;
2947 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2948 ilk_wm_merge(dev
, &max
, &lp_wm_1_2
);
2950 /* 5/6 split only in single pipe config on IVB+ */
2951 if (INTEL_INFO(dev
)->gen
>= 7 &&
2952 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2953 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2954 ilk_wm_merge(dev
, &max
, &lp_wm_5_6
);
2956 best_lp_wm
= hsw_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2958 best_lp_wm
= &lp_wm_1_2
;
2961 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2962 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2964 hsw_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2966 hsw_write_wm_values(dev_priv
, &results
);
2969 static void haswell_update_sprite_wm(struct drm_plane
*plane
,
2970 struct drm_crtc
*crtc
,
2971 uint32_t sprite_width
, int pixel_size
,
2972 bool enabled
, bool scaled
)
2974 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2976 intel_plane
->wm
.enabled
= enabled
;
2977 intel_plane
->wm
.scaled
= scaled
;
2978 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2979 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2981 haswell_update_wm(crtc
);
2985 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
2986 uint32_t sprite_width
, int pixel_size
,
2987 const struct intel_watermark_params
*display
,
2988 int display_latency_ns
, int *sprite_wm
)
2990 struct drm_crtc
*crtc
;
2992 int entries
, tlb_miss
;
2994 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2995 if (!intel_crtc_active(crtc
)) {
2996 *sprite_wm
= display
->guard_size
;
3000 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3002 /* Use the small buffer method to calculate the sprite watermark */
3003 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
3004 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
3007 entries
+= tlb_miss
;
3008 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
3009 *sprite_wm
= entries
+ display
->guard_size
;
3010 if (*sprite_wm
> (int)display
->max_wm
)
3011 *sprite_wm
= display
->max_wm
;
3017 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
3018 uint32_t sprite_width
, int pixel_size
,
3019 const struct intel_watermark_params
*display
,
3020 int latency_ns
, int *sprite_wm
)
3022 struct drm_crtc
*crtc
;
3023 unsigned long line_time_us
;
3025 int line_count
, line_size
;
3034 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3035 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3041 line_time_us
= (sprite_width
* 1000) / clock
;
3042 if (!line_time_us
) {
3047 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
3048 line_size
= sprite_width
* pixel_size
;
3050 /* Use the minimum of the small and large buffer method for primary */
3051 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
3052 large
= line_count
* line_size
;
3054 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
3055 *sprite_wm
= entries
+ display
->guard_size
;
3057 return *sprite_wm
> 0x3ff ? false : true;
3060 static void sandybridge_update_sprite_wm(struct drm_plane
*plane
,
3061 struct drm_crtc
*crtc
,
3062 uint32_t sprite_width
, int pixel_size
,
3063 bool enabled
, bool scaled
)
3065 struct drm_device
*dev
= plane
->dev
;
3066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3067 int pipe
= to_intel_plane(plane
)->pipe
;
3068 int latency
= dev_priv
->wm
.spr_latency
[0] * 100; /* In unit 0.1us */
3078 reg
= WM0_PIPEA_ILK
;
3081 reg
= WM0_PIPEB_ILK
;
3084 reg
= WM0_PIPEC_IVB
;
3087 return; /* bad pipe */
3090 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
3091 &sandybridge_display_wm_info
,
3092 latency
, &sprite_wm
);
3094 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3099 val
= I915_READ(reg
);
3100 val
&= ~WM0_PIPE_SPRITE_MASK
;
3101 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
3102 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe
), sprite_wm
);
3105 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3107 &sandybridge_display_srwm_info
,
3108 dev_priv
->wm
.spr_latency
[1] * 500,
3111 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3115 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
3117 /* Only IVB has two more LP watermarks for sprite */
3118 if (!IS_IVYBRIDGE(dev
))
3121 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3123 &sandybridge_display_srwm_info
,
3124 dev_priv
->wm
.spr_latency
[2] * 500,
3127 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3131 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
3133 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3135 &sandybridge_display_srwm_info
,
3136 dev_priv
->wm
.spr_latency
[3] * 500,
3139 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3143 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
3146 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3148 struct drm_device
*dev
= crtc
->dev
;
3149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3150 struct hsw_wm_values
*hw
= &dev_priv
->wm
.hw
;
3151 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3152 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
3153 enum pipe pipe
= intel_crtc
->pipe
;
3154 static const unsigned int wm0_pipe_reg
[] = {
3155 [PIPE_A
] = WM0_PIPEA_ILK
,
3156 [PIPE_B
] = WM0_PIPEB_ILK
,
3157 [PIPE_C
] = WM0_PIPEC_IVB
,
3160 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3161 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3163 if (intel_crtc_active(crtc
)) {
3164 u32 tmp
= hw
->wm_pipe
[pipe
];
3167 * For active pipes LP0 watermark is marked as
3168 * enabled, and LP1+ watermaks as disabled since
3169 * we can't really reverse compute them in case
3170 * multiple pipes are active.
3172 active
->wm
[0].enable
= true;
3173 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3174 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3175 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3176 active
->linetime
= hw
->wm_linetime
[pipe
];
3178 int level
, max_level
= ilk_wm_max_level(dev
);
3181 * For inactive pipes, all watermark levels
3182 * should be marked as enabled but zeroed,
3183 * which is what we'd compute them to.
3185 for (level
= 0; level
<= max_level
; level
++)
3186 active
->wm
[level
].enable
= true;
3190 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3193 struct hsw_wm_values
*hw
= &dev_priv
->wm
.hw
;
3194 struct drm_crtc
*crtc
;
3196 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3197 ilk_pipe_wm_get_hw_state(crtc
);
3199 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3200 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3201 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3203 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3204 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3205 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3207 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3208 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3211 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3215 * intel_update_watermarks - update FIFO watermark values based on current modes
3217 * Calculate watermark values for the various WM regs based on current mode
3218 * and plane configuration.
3220 * There are several cases to deal with here:
3221 * - normal (i.e. non-self-refresh)
3222 * - self-refresh (SR) mode
3223 * - lines are large relative to FIFO size (buffer can hold up to 2)
3224 * - lines are small relative to FIFO size (buffer can hold more than 2
3225 * lines), so need to account for TLB latency
3227 * The normal calculation is:
3228 * watermark = dotclock * bytes per pixel * latency
3229 * where latency is platform & configuration dependent (we assume pessimal
3232 * The SR calculation is:
3233 * watermark = (trunc(latency/line time)+1) * surface width *
3236 * line time = htotal / dotclock
3237 * surface width = hdisplay for normal plane and 64 for cursor
3238 * and latency is assumed to be high, as above.
3240 * The final value programmed to the register should always be rounded up,
3241 * and include an extra 2 entries to account for clock crossings.
3243 * We don't use the sprite, so we can ignore that. And on Crestline we have
3244 * to set the non-SR watermarks to 8.
3246 void intel_update_watermarks(struct drm_crtc
*crtc
)
3248 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3250 if (dev_priv
->display
.update_wm
)
3251 dev_priv
->display
.update_wm(crtc
);
3254 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
3255 struct drm_crtc
*crtc
,
3256 uint32_t sprite_width
, int pixel_size
,
3257 bool enabled
, bool scaled
)
3259 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
3261 if (dev_priv
->display
.update_sprite_wm
)
3262 dev_priv
->display
.update_sprite_wm(plane
, crtc
, sprite_width
,
3263 pixel_size
, enabled
, scaled
);
3266 static struct drm_i915_gem_object
*
3267 intel_alloc_context_page(struct drm_device
*dev
)
3269 struct drm_i915_gem_object
*ctx
;
3272 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3274 ctx
= i915_gem_alloc_object(dev
, 4096);
3276 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3280 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, true, false);
3282 DRM_ERROR("failed to pin power context: %d\n", ret
);
3286 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
3288 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
3295 i915_gem_object_unpin(ctx
);
3297 drm_gem_object_unreference(&ctx
->base
);
3302 * Lock protecting IPS related data structures
3304 DEFINE_SPINLOCK(mchdev_lock
);
3306 /* Global for IPS driver to get at the current i915 device. Protected by
3308 static struct drm_i915_private
*i915_mch_dev
;
3310 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3315 assert_spin_locked(&mchdev_lock
);
3317 rgvswctl
= I915_READ16(MEMSWCTL
);
3318 if (rgvswctl
& MEMCTL_CMD_STS
) {
3319 DRM_DEBUG("gpu busy, RCS change rejected\n");
3320 return false; /* still busy with another command */
3323 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3324 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3325 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3326 POSTING_READ16(MEMSWCTL
);
3328 rgvswctl
|= MEMCTL_CMD_STS
;
3329 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3334 static void ironlake_enable_drps(struct drm_device
*dev
)
3336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3337 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3338 u8 fmax
, fmin
, fstart
, vstart
;
3340 spin_lock_irq(&mchdev_lock
);
3342 /* Enable temp reporting */
3343 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3344 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3346 /* 100ms RC evaluation intervals */
3347 I915_WRITE(RCUPEI
, 100000);
3348 I915_WRITE(RCDNEI
, 100000);
3350 /* Set max/min thresholds to 90ms and 80ms respectively */
3351 I915_WRITE(RCBMAXAVG
, 90000);
3352 I915_WRITE(RCBMINAVG
, 80000);
3354 I915_WRITE(MEMIHYST
, 1);
3356 /* Set up min, max, and cur for interrupt handling */
3357 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3358 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3359 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3360 MEMMODE_FSTART_SHIFT
;
3362 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3365 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3366 dev_priv
->ips
.fstart
= fstart
;
3368 dev_priv
->ips
.max_delay
= fstart
;
3369 dev_priv
->ips
.min_delay
= fmin
;
3370 dev_priv
->ips
.cur_delay
= fstart
;
3372 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3373 fmax
, fmin
, fstart
);
3375 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3378 * Interrupts will be enabled in ironlake_irq_postinstall
3381 I915_WRITE(VIDSTART
, vstart
);
3382 POSTING_READ(VIDSTART
);
3384 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3385 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3387 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3388 DRM_ERROR("stuck trying to change perf mode\n");
3391 ironlake_set_drps(dev
, fstart
);
3393 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3395 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3396 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3397 getrawmonotonic(&dev_priv
->ips
.last_time2
);
3399 spin_unlock_irq(&mchdev_lock
);
3402 static void ironlake_disable_drps(struct drm_device
*dev
)
3404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3407 spin_lock_irq(&mchdev_lock
);
3409 rgvswctl
= I915_READ16(MEMSWCTL
);
3411 /* Ack interrupts, disable EFC interrupt */
3412 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3413 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3414 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3415 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3416 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3418 /* Go back to the starting frequency */
3419 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3421 rgvswctl
|= MEMCTL_CMD_STS
;
3422 I915_WRITE(MEMSWCTL
, rgvswctl
);
3425 spin_unlock_irq(&mchdev_lock
);
3428 /* There's a funny hw issue where the hw returns all 0 when reading from
3429 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3430 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3431 * all limits and the gpu stuck at whatever frequency it is at atm).
3433 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8
*val
)
3439 if (*val
>= dev_priv
->rps
.max_delay
)
3440 *val
= dev_priv
->rps
.max_delay
;
3441 limits
|= dev_priv
->rps
.max_delay
<< 24;
3443 /* Only set the down limit when we've reached the lowest level to avoid
3444 * getting more interrupts, otherwise leave this clear. This prevents a
3445 * race in the hw when coming out of rc6: There's a tiny window where
3446 * the hw runs at the minimal clock before selecting the desired
3447 * frequency, if the down threshold expires in that window we will not
3448 * receive a down interrupt. */
3449 if (*val
<= dev_priv
->rps
.min_delay
) {
3450 *val
= dev_priv
->rps
.min_delay
;
3451 limits
|= dev_priv
->rps
.min_delay
<< 16;
3457 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3461 new_power
= dev_priv
->rps
.power
;
3462 switch (dev_priv
->rps
.power
) {
3464 if (val
> dev_priv
->rps
.rpe_delay
+ 1 && val
> dev_priv
->rps
.cur_delay
)
3465 new_power
= BETWEEN
;
3469 if (val
<= dev_priv
->rps
.rpe_delay
&& val
< dev_priv
->rps
.cur_delay
)
3470 new_power
= LOW_POWER
;
3471 else if (val
>= dev_priv
->rps
.rp0_delay
&& val
> dev_priv
->rps
.cur_delay
)
3472 new_power
= HIGH_POWER
;
3476 if (val
< (dev_priv
->rps
.rp1_delay
+ dev_priv
->rps
.rp0_delay
) >> 1 && val
< dev_priv
->rps
.cur_delay
)
3477 new_power
= BETWEEN
;
3480 /* Max/min bins are special */
3481 if (val
== dev_priv
->rps
.min_delay
)
3482 new_power
= LOW_POWER
;
3483 if (val
== dev_priv
->rps
.max_delay
)
3484 new_power
= HIGH_POWER
;
3485 if (new_power
== dev_priv
->rps
.power
)
3488 /* Note the units here are not exactly 1us, but 1280ns. */
3489 switch (new_power
) {
3491 /* Upclock if more than 95% busy over 16ms */
3492 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3493 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3495 /* Downclock if less than 85% busy over 32ms */
3496 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3497 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3499 I915_WRITE(GEN6_RP_CONTROL
,
3500 GEN6_RP_MEDIA_TURBO
|
3501 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3502 GEN6_RP_MEDIA_IS_GFX
|
3504 GEN6_RP_UP_BUSY_AVG
|
3505 GEN6_RP_DOWN_IDLE_AVG
);
3509 /* Upclock if more than 90% busy over 13ms */
3510 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3511 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3513 /* Downclock if less than 75% busy over 32ms */
3514 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3515 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3517 I915_WRITE(GEN6_RP_CONTROL
,
3518 GEN6_RP_MEDIA_TURBO
|
3519 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3520 GEN6_RP_MEDIA_IS_GFX
|
3522 GEN6_RP_UP_BUSY_AVG
|
3523 GEN6_RP_DOWN_IDLE_AVG
);
3527 /* Upclock if more than 85% busy over 10ms */
3528 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3529 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3531 /* Downclock if less than 60% busy over 32ms */
3532 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3533 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3535 I915_WRITE(GEN6_RP_CONTROL
,
3536 GEN6_RP_MEDIA_TURBO
|
3537 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3538 GEN6_RP_MEDIA_IS_GFX
|
3540 GEN6_RP_UP_BUSY_AVG
|
3541 GEN6_RP_DOWN_IDLE_AVG
);
3545 dev_priv
->rps
.power
= new_power
;
3546 dev_priv
->rps
.last_adj
= 0;
3549 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3552 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
3554 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3555 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3556 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3558 if (val
== dev_priv
->rps
.cur_delay
)
3561 gen6_set_rps_thresholds(dev_priv
, val
);
3563 if (IS_HASWELL(dev
))
3564 I915_WRITE(GEN6_RPNSWREQ
,
3565 HSW_FREQUENCY(val
));
3567 I915_WRITE(GEN6_RPNSWREQ
,
3568 GEN6_FREQUENCY(val
) |
3570 GEN6_AGGRESSIVE_TURBO
);
3572 /* Make sure we continue to get interrupts
3573 * until we hit the minimum or maximum frequencies.
3575 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
3577 POSTING_READ(GEN6_RPNSWREQ
);
3579 dev_priv
->rps
.cur_delay
= val
;
3581 trace_intel_gpu_freq_change(val
* 50);
3584 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3586 mutex_lock(&dev_priv
->rps
.hw_lock
);
3587 if (dev_priv
->rps
.enabled
) {
3588 if (dev_priv
->info
->is_valleyview
)
3589 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3591 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3592 dev_priv
->rps
.last_adj
= 0;
3594 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3597 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3599 mutex_lock(&dev_priv
->rps
.hw_lock
);
3600 if (dev_priv
->rps
.enabled
) {
3601 if (dev_priv
->info
->is_valleyview
)
3602 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_delay
);
3604 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_delay
);
3605 dev_priv
->rps
.last_adj
= 0;
3607 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3611 * Wait until the previous freq change has completed,
3612 * or the timeout elapsed, and then update our notion
3613 * of the current GPU frequency.
3615 static void vlv_update_rps_cur_delay(struct drm_i915_private
*dev_priv
)
3619 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3621 if (wait_for(((pval
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
)) & GENFREQSTATUS
) == 0, 10))
3622 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3626 if (pval
!= dev_priv
->rps
.cur_delay
)
3627 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3628 vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.cur_delay
),
3629 dev_priv
->rps
.cur_delay
,
3630 vlv_gpu_freq(dev_priv
->mem_freq
, pval
), pval
);
3632 dev_priv
->rps
.cur_delay
= pval
;
3635 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3639 gen6_rps_limits(dev_priv
, &val
);
3641 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3642 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3643 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3645 vlv_update_rps_cur_delay(dev_priv
);
3647 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3648 vlv_gpu_freq(dev_priv
->mem_freq
,
3649 dev_priv
->rps
.cur_delay
),
3650 dev_priv
->rps
.cur_delay
,
3651 vlv_gpu_freq(dev_priv
->mem_freq
, val
), val
);
3653 if (val
== dev_priv
->rps
.cur_delay
)
3656 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3658 dev_priv
->rps
.cur_delay
= val
;
3660 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
->mem_freq
, val
));
3663 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3667 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3668 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) & ~GEN6_PM_RPS_EVENTS
);
3669 /* Complete PM interrupt masking here doesn't race with the rps work
3670 * item again unmasking PM interrupts because that is using a different
3671 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3672 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3674 spin_lock_irq(&dev_priv
->irq_lock
);
3675 dev_priv
->rps
.pm_iir
= 0;
3676 spin_unlock_irq(&dev_priv
->irq_lock
);
3678 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3681 static void gen6_disable_rps(struct drm_device
*dev
)
3683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3685 I915_WRITE(GEN6_RC_CONTROL
, 0);
3686 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3688 gen6_disable_rps_interrupts(dev
);
3691 static void valleyview_disable_rps(struct drm_device
*dev
)
3693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 I915_WRITE(GEN6_RC_CONTROL
, 0);
3697 gen6_disable_rps_interrupts(dev
);
3699 if (dev_priv
->vlv_pctx
) {
3700 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3701 dev_priv
->vlv_pctx
= NULL
;
3705 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3708 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3710 if (IS_HASWELL(dev
))
3711 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3713 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3714 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3715 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3716 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3719 int intel_enable_rc6(const struct drm_device
*dev
)
3721 /* No RC6 before Ironlake */
3722 if (INTEL_INFO(dev
)->gen
< 5)
3725 /* Respect the kernel parameter if it is set */
3726 if (i915_enable_rc6
>= 0)
3727 return i915_enable_rc6
;
3729 /* Disable RC6 on Ironlake */
3730 if (INTEL_INFO(dev
)->gen
== 5)
3733 if (IS_HASWELL(dev
))
3734 return INTEL_RC6_ENABLE
;
3736 /* snb/ivb have more than one rc6 state. */
3737 if (INTEL_INFO(dev
)->gen
== 6)
3738 return INTEL_RC6_ENABLE
;
3740 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3743 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3748 spin_lock_irq(&dev_priv
->irq_lock
);
3749 WARN_ON(dev_priv
->rps
.pm_iir
);
3750 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
3751 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3752 spin_unlock_irq(&dev_priv
->irq_lock
);
3754 /* only unmask PM interrupts we need. Mask all others. */
3755 enabled_intrs
= GEN6_PM_RPS_EVENTS
;
3757 /* IVB and SNB hard hangs on looping batchbuffer
3758 * if GEN6_PM_UP_EI_EXPIRED is masked.
3760 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
3761 enabled_intrs
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3763 I915_WRITE(GEN6_PMINTRMSK
, ~enabled_intrs
);
3766 static void gen8_enable_rps(struct drm_device
*dev
)
3768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3769 struct intel_ring_buffer
*ring
;
3770 uint32_t rc6_mask
= 0, rp_state_cap
;
3773 /* 1a: Software RC state - RC0 */
3774 I915_WRITE(GEN6_RC_STATE
, 0);
3776 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3777 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3778 gen6_gt_force_wake_get(dev_priv
);
3780 /* 2a: Disable RC states. */
3781 I915_WRITE(GEN6_RC_CONTROL
, 0);
3783 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3785 /* 2b: Program RC6 thresholds.*/
3786 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3787 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3788 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3789 for_each_ring(ring
, dev_priv
, unused
)
3790 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3791 I915_WRITE(GEN6_RC_SLEEP
, 0);
3792 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3795 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3796 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3797 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
3798 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3799 GEN6_RC_CTL_EI_MODE(1) |
3802 /* 4 Program defaults and thresholds for RPS*/
3803 I915_WRITE(GEN6_RPNSWREQ
, HSW_FREQUENCY(10)); /* Request 500 MHz */
3804 I915_WRITE(GEN6_RC_VIDEO_FREQ
, HSW_FREQUENCY(12)); /* Request 600 MHz */
3805 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3806 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3808 /* Docs recommend 900MHz, and 300 MHz respectively */
3809 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3810 dev_priv
->rps
.max_delay
<< 24 |
3811 dev_priv
->rps
.min_delay
<< 16);
3813 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3814 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3815 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3816 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3818 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3821 I915_WRITE(GEN6_RP_CONTROL
,
3822 GEN6_RP_MEDIA_TURBO
|
3823 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3824 GEN6_RP_MEDIA_IS_GFX
|
3826 GEN6_RP_UP_BUSY_AVG
|
3827 GEN6_RP_DOWN_IDLE_AVG
);
3829 /* 6: Ring frequency + overclocking (our driver does this later */
3831 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3833 gen6_enable_rps_interrupts(dev
);
3835 gen6_gt_force_wake_put(dev_priv
);
3838 static void gen6_enable_rps(struct drm_device
*dev
)
3840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3841 struct intel_ring_buffer
*ring
;
3844 u32 rc6vids
, pcu_mbox
, rc6_mask
= 0;
3849 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3851 /* Here begins a magic sequence of register writes to enable
3852 * auto-downclocking.
3854 * Perhaps there might be some value in exposing these to
3857 I915_WRITE(GEN6_RC_STATE
, 0);
3859 /* Clear the DBG now so we don't confuse earlier errors */
3860 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3861 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3862 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3865 gen6_gt_force_wake_get(dev_priv
);
3867 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3868 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3870 /* In units of 50MHz */
3871 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
3872 dev_priv
->rps
.min_delay
= (rp_state_cap
>> 16) & 0xff;
3873 dev_priv
->rps
.rp1_delay
= (rp_state_cap
>> 8) & 0xff;
3874 dev_priv
->rps
.rp0_delay
= (rp_state_cap
>> 0) & 0xff;
3875 dev_priv
->rps
.rpe_delay
= dev_priv
->rps
.rp1_delay
;
3876 dev_priv
->rps
.cur_delay
= 0;
3878 /* disable the counters and set deterministic thresholds */
3879 I915_WRITE(GEN6_RC_CONTROL
, 0);
3881 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3882 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3883 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3884 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3885 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3887 for_each_ring(ring
, dev_priv
, i
)
3888 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3890 I915_WRITE(GEN6_RC_SLEEP
, 0);
3891 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3892 if (IS_IVYBRIDGE(dev
))
3893 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3895 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3896 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3897 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3899 /* Check if we are enabling RC6 */
3900 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3901 if (rc6_mode
& INTEL_RC6_ENABLE
)
3902 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3904 /* We don't use those on Haswell */
3905 if (!IS_HASWELL(dev
)) {
3906 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3907 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3909 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3910 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3913 intel_print_rc6_info(dev
, rc6_mask
);
3915 I915_WRITE(GEN6_RC_CONTROL
,
3917 GEN6_RC_CTL_EI_MODE(1) |
3918 GEN6_RC_CTL_HW_ENABLE
);
3920 /* Power down if completely idle for over 50ms */
3921 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3922 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3924 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3927 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3928 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3929 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3930 (dev_priv
->rps
.max_delay
& 0xff) * 50,
3931 (pcu_mbox
& 0xff) * 50);
3932 dev_priv
->rps
.hw_max
= pcu_mbox
& 0xff;
3935 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3938 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3939 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3941 gen6_enable_rps_interrupts(dev
);
3944 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3945 if (IS_GEN6(dev
) && ret
) {
3946 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3947 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3948 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3949 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3950 rc6vids
&= 0xffff00;
3951 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3952 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3954 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3957 gen6_gt_force_wake_put(dev_priv
);
3960 void gen6_update_ring_freq(struct drm_device
*dev
)
3962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3964 unsigned int gpu_freq
;
3965 unsigned int max_ia_freq
, min_ring_freq
;
3966 int scaling_factor
= 180;
3967 struct cpufreq_policy
*policy
;
3969 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3971 policy
= cpufreq_cpu_get(0);
3973 max_ia_freq
= policy
->cpuinfo
.max_freq
;
3974 cpufreq_cpu_put(policy
);
3977 * Default to measured freq if none found, PCU will ensure we
3980 max_ia_freq
= tsc_khz
;
3983 /* Convert from kHz to MHz */
3984 max_ia_freq
/= 1000;
3986 min_ring_freq
= I915_READ(DCLK
) & 0xf;
3987 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3988 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
3991 * For each potential GPU frequency, load a ring frequency we'd like
3992 * to use for memory access. We do this by specifying the IA frequency
3993 * the PCU should use as a reference to determine the ring frequency.
3995 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
3997 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
3998 unsigned int ia_freq
= 0, ring_freq
= 0;
4000 if (INTEL_INFO(dev
)->gen
>= 8) {
4001 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4002 ring_freq
= max(min_ring_freq
, gpu_freq
);
4003 } else if (IS_HASWELL(dev
)) {
4004 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4005 ring_freq
= max(min_ring_freq
, ring_freq
);
4006 /* leave ia_freq as the default, chosen by cpufreq */
4008 /* On older processors, there is no separate ring
4009 * clock domain, so in order to boost the bandwidth
4010 * of the ring, we need to upclock the CPU (ia_freq).
4012 * For GPU frequencies less than 750MHz,
4013 * just use the lowest ring freq.
4015 if (gpu_freq
< min_freq
)
4018 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4019 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4022 sandybridge_pcode_write(dev_priv
,
4023 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4024 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4025 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4030 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4034 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4036 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
4038 rp0
= min_t(u32
, rp0
, 0xea);
4043 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4047 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
4048 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
4049 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
4050 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
4055 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4057 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
4060 static void valleyview_setup_pctx(struct drm_device
*dev
)
4062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4063 struct drm_i915_gem_object
*pctx
;
4064 unsigned long pctx_paddr
;
4066 int pctx_size
= 24*1024;
4068 pcbr
= I915_READ(VLV_PCBR
);
4070 /* BIOS set it up already, grab the pre-alloc'd space */
4073 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4074 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4076 I915_GTT_OFFSET_NONE
,
4082 * From the Gunit register HAS:
4083 * The Gfx driver is expected to program this register and ensure
4084 * proper allocation within Gfx stolen memory. For example, this
4085 * register should be programmed such than the PCBR range does not
4086 * overlap with other ranges, such as the frame buffer, protected
4087 * memory, or any other relevant ranges.
4089 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4091 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4095 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4096 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4099 dev_priv
->vlv_pctx
= pctx
;
4102 static void valleyview_enable_rps(struct drm_device
*dev
)
4104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4105 struct intel_ring_buffer
*ring
;
4106 u32 gtfifodbg
, val
, rc6_mode
= 0;
4109 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4111 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4112 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4114 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4117 valleyview_setup_pctx(dev
);
4119 gen6_gt_force_wake_get(dev_priv
);
4121 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4122 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4123 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4124 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4126 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4128 I915_WRITE(GEN6_RP_CONTROL
,
4129 GEN6_RP_MEDIA_TURBO
|
4130 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4131 GEN6_RP_MEDIA_IS_GFX
|
4133 GEN6_RP_UP_BUSY_AVG
|
4134 GEN6_RP_DOWN_IDLE_CONT
);
4136 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4137 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4138 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4140 for_each_ring(ring
, dev_priv
, i
)
4141 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4143 I915_WRITE(GEN6_RC6_THRESHOLD
, 0xc350);
4145 /* allows RC6 residency counter to work */
4146 I915_WRITE(VLV_COUNTER_CONTROL
,
4147 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4148 VLV_MEDIA_RC6_COUNT_EN
|
4149 VLV_RENDER_RC6_COUNT_EN
));
4150 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4151 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
4153 intel_print_rc6_info(dev
, rc6_mode
);
4155 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4157 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4158 switch ((val
>> 6) & 3) {
4161 dev_priv
->mem_freq
= 800;
4164 dev_priv
->mem_freq
= 1066;
4167 dev_priv
->mem_freq
= 1333;
4170 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
4172 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4173 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4175 dev_priv
->rps
.cur_delay
= (val
>> 8) & 0xff;
4176 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4177 vlv_gpu_freq(dev_priv
->mem_freq
,
4178 dev_priv
->rps
.cur_delay
),
4179 dev_priv
->rps
.cur_delay
);
4181 dev_priv
->rps
.max_delay
= valleyview_rps_max_freq(dev_priv
);
4182 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
;
4183 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4184 vlv_gpu_freq(dev_priv
->mem_freq
,
4185 dev_priv
->rps
.max_delay
),
4186 dev_priv
->rps
.max_delay
);
4188 dev_priv
->rps
.rpe_delay
= valleyview_rps_rpe_freq(dev_priv
);
4189 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4190 vlv_gpu_freq(dev_priv
->mem_freq
,
4191 dev_priv
->rps
.rpe_delay
),
4192 dev_priv
->rps
.rpe_delay
);
4194 dev_priv
->rps
.min_delay
= valleyview_rps_min_freq(dev_priv
);
4195 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4196 vlv_gpu_freq(dev_priv
->mem_freq
,
4197 dev_priv
->rps
.min_delay
),
4198 dev_priv
->rps
.min_delay
);
4200 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4201 vlv_gpu_freq(dev_priv
->mem_freq
,
4202 dev_priv
->rps
.rpe_delay
),
4203 dev_priv
->rps
.rpe_delay
);
4205 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.rpe_delay
);
4207 gen6_enable_rps_interrupts(dev
);
4209 gen6_gt_force_wake_put(dev_priv
);
4212 void ironlake_teardown_rc6(struct drm_device
*dev
)
4214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4216 if (dev_priv
->ips
.renderctx
) {
4217 i915_gem_object_unpin(dev_priv
->ips
.renderctx
);
4218 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4219 dev_priv
->ips
.renderctx
= NULL
;
4222 if (dev_priv
->ips
.pwrctx
) {
4223 i915_gem_object_unpin(dev_priv
->ips
.pwrctx
);
4224 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4225 dev_priv
->ips
.pwrctx
= NULL
;
4229 static void ironlake_disable_rc6(struct drm_device
*dev
)
4231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4233 if (I915_READ(PWRCTXA
)) {
4234 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4235 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4236 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4239 I915_WRITE(PWRCTXA
, 0);
4240 POSTING_READ(PWRCTXA
);
4242 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4243 POSTING_READ(RSTDBYCTL
);
4247 static int ironlake_setup_rc6(struct drm_device
*dev
)
4249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4251 if (dev_priv
->ips
.renderctx
== NULL
)
4252 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4253 if (!dev_priv
->ips
.renderctx
)
4256 if (dev_priv
->ips
.pwrctx
== NULL
)
4257 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4258 if (!dev_priv
->ips
.pwrctx
) {
4259 ironlake_teardown_rc6(dev
);
4266 static void ironlake_enable_rc6(struct drm_device
*dev
)
4268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4269 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
4270 bool was_interruptible
;
4273 /* rc6 disabled by default due to repeated reports of hanging during
4276 if (!intel_enable_rc6(dev
))
4279 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4281 ret
= ironlake_setup_rc6(dev
);
4285 was_interruptible
= dev_priv
->mm
.interruptible
;
4286 dev_priv
->mm
.interruptible
= false;
4289 * GPU can automatically power down the render unit if given a page
4292 ret
= intel_ring_begin(ring
, 6);
4294 ironlake_teardown_rc6(dev
);
4295 dev_priv
->mm
.interruptible
= was_interruptible
;
4299 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4300 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4301 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4303 MI_SAVE_EXT_STATE_EN
|
4304 MI_RESTORE_EXT_STATE_EN
|
4305 MI_RESTORE_INHIBIT
);
4306 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4307 intel_ring_emit(ring
, MI_NOOP
);
4308 intel_ring_emit(ring
, MI_FLUSH
);
4309 intel_ring_advance(ring
);
4312 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4313 * does an implicit flush, combined with MI_FLUSH above, it should be
4314 * safe to assume that renderctx is valid
4316 ret
= intel_ring_idle(ring
);
4317 dev_priv
->mm
.interruptible
= was_interruptible
;
4319 DRM_ERROR("failed to enable ironlake power savings\n");
4320 ironlake_teardown_rc6(dev
);
4324 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4325 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4327 intel_print_rc6_info(dev
, INTEL_RC6_ENABLE
);
4330 static unsigned long intel_pxfreq(u32 vidfreq
)
4333 int div
= (vidfreq
& 0x3f0000) >> 16;
4334 int post
= (vidfreq
& 0x3000) >> 12;
4335 int pre
= (vidfreq
& 0x7);
4340 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4345 static const struct cparams
{
4351 { 1, 1333, 301, 28664 },
4352 { 1, 1066, 294, 24460 },
4353 { 1, 800, 294, 25192 },
4354 { 0, 1333, 276, 27605 },
4355 { 0, 1066, 276, 27605 },
4356 { 0, 800, 231, 23784 },
4359 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4361 u64 total_count
, diff
, ret
;
4362 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4363 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4366 assert_spin_locked(&mchdev_lock
);
4368 diff1
= now
- dev_priv
->ips
.last_time1
;
4370 /* Prevent division-by-zero if we are asking too fast.
4371 * Also, we don't get interesting results if we are polling
4372 * faster than once in 10ms, so just return the saved value
4376 return dev_priv
->ips
.chipset_power
;
4378 count1
= I915_READ(DMIEC
);
4379 count2
= I915_READ(DDREC
);
4380 count3
= I915_READ(CSIEC
);
4382 total_count
= count1
+ count2
+ count3
;
4384 /* FIXME: handle per-counter overflow */
4385 if (total_count
< dev_priv
->ips
.last_count1
) {
4386 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4387 diff
+= total_count
;
4389 diff
= total_count
- dev_priv
->ips
.last_count1
;
4392 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4393 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4394 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4401 diff
= div_u64(diff
, diff1
);
4402 ret
= ((m
* diff
) + c
);
4403 ret
= div_u64(ret
, 10);
4405 dev_priv
->ips
.last_count1
= total_count
;
4406 dev_priv
->ips
.last_time1
= now
;
4408 dev_priv
->ips
.chipset_power
= ret
;
4413 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4417 if (dev_priv
->info
->gen
!= 5)
4420 spin_lock_irq(&mchdev_lock
);
4422 val
= __i915_chipset_val(dev_priv
);
4424 spin_unlock_irq(&mchdev_lock
);
4429 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4431 unsigned long m
, x
, b
;
4434 tsfs
= I915_READ(TSFS
);
4436 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4437 x
= I915_READ8(TR1
);
4439 b
= tsfs
& TSFS_INTR_MASK
;
4441 return ((m
* x
) / 127) - b
;
4444 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4446 static const struct v_table
{
4447 u16 vd
; /* in .1 mil */
4448 u16 vm
; /* in .1 mil */
4579 if (dev_priv
->info
->is_mobile
)
4580 return v_table
[pxvid
].vm
;
4582 return v_table
[pxvid
].vd
;
4585 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4587 struct timespec now
, diff1
;
4589 unsigned long diffms
;
4592 assert_spin_locked(&mchdev_lock
);
4594 getrawmonotonic(&now
);
4595 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4597 /* Don't divide by 0 */
4598 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4602 count
= I915_READ(GFXEC
);
4604 if (count
< dev_priv
->ips
.last_count2
) {
4605 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4608 diff
= count
- dev_priv
->ips
.last_count2
;
4611 dev_priv
->ips
.last_count2
= count
;
4612 dev_priv
->ips
.last_time2
= now
;
4614 /* More magic constants... */
4616 diff
= div_u64(diff
, diffms
* 10);
4617 dev_priv
->ips
.gfx_power
= diff
;
4620 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4622 if (dev_priv
->info
->gen
!= 5)
4625 spin_lock_irq(&mchdev_lock
);
4627 __i915_update_gfx_val(dev_priv
);
4629 spin_unlock_irq(&mchdev_lock
);
4632 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4634 unsigned long t
, corr
, state1
, corr2
, state2
;
4637 assert_spin_locked(&mchdev_lock
);
4639 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
4640 pxvid
= (pxvid
>> 24) & 0x7f;
4641 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4645 t
= i915_mch_val(dev_priv
);
4647 /* Revel in the empirically derived constants */
4649 /* Correction factor in 1/100000 units */
4651 corr
= ((t
* 2349) + 135940);
4653 corr
= ((t
* 964) + 29317);
4655 corr
= ((t
* 301) + 1004);
4657 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4659 corr2
= (corr
* dev_priv
->ips
.corr
);
4661 state2
= (corr2
* state1
) / 10000;
4662 state2
/= 100; /* convert to mW */
4664 __i915_update_gfx_val(dev_priv
);
4666 return dev_priv
->ips
.gfx_power
+ state2
;
4669 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4673 if (dev_priv
->info
->gen
!= 5)
4676 spin_lock_irq(&mchdev_lock
);
4678 val
= __i915_gfx_val(dev_priv
);
4680 spin_unlock_irq(&mchdev_lock
);
4686 * i915_read_mch_val - return value for IPS use
4688 * Calculate and return a value for the IPS driver to use when deciding whether
4689 * we have thermal and power headroom to increase CPU or GPU power budget.
4691 unsigned long i915_read_mch_val(void)
4693 struct drm_i915_private
*dev_priv
;
4694 unsigned long chipset_val
, graphics_val
, ret
= 0;
4696 spin_lock_irq(&mchdev_lock
);
4699 dev_priv
= i915_mch_dev
;
4701 chipset_val
= __i915_chipset_val(dev_priv
);
4702 graphics_val
= __i915_gfx_val(dev_priv
);
4704 ret
= chipset_val
+ graphics_val
;
4707 spin_unlock_irq(&mchdev_lock
);
4711 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4714 * i915_gpu_raise - raise GPU frequency limit
4716 * Raise the limit; IPS indicates we have thermal headroom.
4718 bool i915_gpu_raise(void)
4720 struct drm_i915_private
*dev_priv
;
4723 spin_lock_irq(&mchdev_lock
);
4724 if (!i915_mch_dev
) {
4728 dev_priv
= i915_mch_dev
;
4730 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4731 dev_priv
->ips
.max_delay
--;
4734 spin_unlock_irq(&mchdev_lock
);
4738 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4741 * i915_gpu_lower - lower GPU frequency limit
4743 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4744 * frequency maximum.
4746 bool i915_gpu_lower(void)
4748 struct drm_i915_private
*dev_priv
;
4751 spin_lock_irq(&mchdev_lock
);
4752 if (!i915_mch_dev
) {
4756 dev_priv
= i915_mch_dev
;
4758 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4759 dev_priv
->ips
.max_delay
++;
4762 spin_unlock_irq(&mchdev_lock
);
4766 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4769 * i915_gpu_busy - indicate GPU business to IPS
4771 * Tell the IPS driver whether or not the GPU is busy.
4773 bool i915_gpu_busy(void)
4775 struct drm_i915_private
*dev_priv
;
4776 struct intel_ring_buffer
*ring
;
4780 spin_lock_irq(&mchdev_lock
);
4783 dev_priv
= i915_mch_dev
;
4785 for_each_ring(ring
, dev_priv
, i
)
4786 ret
|= !list_empty(&ring
->request_list
);
4789 spin_unlock_irq(&mchdev_lock
);
4793 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4796 * i915_gpu_turbo_disable - disable graphics turbo
4798 * Disable graphics turbo by resetting the max frequency and setting the
4799 * current frequency to the default.
4801 bool i915_gpu_turbo_disable(void)
4803 struct drm_i915_private
*dev_priv
;
4806 spin_lock_irq(&mchdev_lock
);
4807 if (!i915_mch_dev
) {
4811 dev_priv
= i915_mch_dev
;
4813 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4815 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4819 spin_unlock_irq(&mchdev_lock
);
4823 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4826 * Tells the intel_ips driver that the i915 driver is now loaded, if
4827 * IPS got loaded first.
4829 * This awkward dance is so that neither module has to depend on the
4830 * other in order for IPS to do the appropriate communication of
4831 * GPU turbo limits to i915.
4834 ips_ping_for_i915_load(void)
4838 link
= symbol_get(ips_link_to_i915_driver
);
4841 symbol_put(ips_link_to_i915_driver
);
4845 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4847 /* We only register the i915 ips part with intel-ips once everything is
4848 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4849 spin_lock_irq(&mchdev_lock
);
4850 i915_mch_dev
= dev_priv
;
4851 spin_unlock_irq(&mchdev_lock
);
4853 ips_ping_for_i915_load();
4856 void intel_gpu_ips_teardown(void)
4858 spin_lock_irq(&mchdev_lock
);
4859 i915_mch_dev
= NULL
;
4860 spin_unlock_irq(&mchdev_lock
);
4862 static void intel_init_emon(struct drm_device
*dev
)
4864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4869 /* Disable to program */
4873 /* Program energy weights for various events */
4874 I915_WRITE(SDEW
, 0x15040d00);
4875 I915_WRITE(CSIEW0
, 0x007f0000);
4876 I915_WRITE(CSIEW1
, 0x1e220004);
4877 I915_WRITE(CSIEW2
, 0x04000004);
4879 for (i
= 0; i
< 5; i
++)
4880 I915_WRITE(PEW
+ (i
* 4), 0);
4881 for (i
= 0; i
< 3; i
++)
4882 I915_WRITE(DEW
+ (i
* 4), 0);
4884 /* Program P-state weights to account for frequency power adjustment */
4885 for (i
= 0; i
< 16; i
++) {
4886 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4887 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4888 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4893 val
*= (freq
/ 1000);
4895 val
/= (127*127*900);
4897 DRM_ERROR("bad pxval: %ld\n", val
);
4900 /* Render standby states get 0 weight */
4904 for (i
= 0; i
< 4; i
++) {
4905 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4906 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4907 I915_WRITE(PXW
+ (i
* 4), val
);
4910 /* Adjust magic regs to magic values (more experimental results) */
4911 I915_WRITE(OGW0
, 0);
4912 I915_WRITE(OGW1
, 0);
4913 I915_WRITE(EG0
, 0x00007f00);
4914 I915_WRITE(EG1
, 0x0000000e);
4915 I915_WRITE(EG2
, 0x000e0000);
4916 I915_WRITE(EG3
, 0x68000300);
4917 I915_WRITE(EG4
, 0x42000000);
4918 I915_WRITE(EG5
, 0x00140031);
4922 for (i
= 0; i
< 8; i
++)
4923 I915_WRITE(PXWL
+ (i
* 4), 0);
4925 /* Enable PMON + select events */
4926 I915_WRITE(ECR
, 0x80000019);
4928 lcfuse
= I915_READ(LCFUSE02
);
4930 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4933 void intel_disable_gt_powersave(struct drm_device
*dev
)
4935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4937 /* Interrupts should be disabled already to avoid re-arming. */
4938 WARN_ON(dev
->irq_enabled
);
4940 if (IS_IRONLAKE_M(dev
)) {
4941 ironlake_disable_drps(dev
);
4942 ironlake_disable_rc6(dev
);
4943 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4944 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
4945 cancel_work_sync(&dev_priv
->rps
.work
);
4946 mutex_lock(&dev_priv
->rps
.hw_lock
);
4947 if (IS_VALLEYVIEW(dev
))
4948 valleyview_disable_rps(dev
);
4950 gen6_disable_rps(dev
);
4951 dev_priv
->rps
.enabled
= false;
4952 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4956 static void intel_gen6_powersave_work(struct work_struct
*work
)
4958 struct drm_i915_private
*dev_priv
=
4959 container_of(work
, struct drm_i915_private
,
4960 rps
.delayed_resume_work
.work
);
4961 struct drm_device
*dev
= dev_priv
->dev
;
4963 mutex_lock(&dev_priv
->rps
.hw_lock
);
4965 if (IS_VALLEYVIEW(dev
)) {
4966 valleyview_enable_rps(dev
);
4967 } else if (IS_BROADWELL(dev
)) {
4968 gen8_enable_rps(dev
);
4969 gen6_update_ring_freq(dev
);
4971 gen6_enable_rps(dev
);
4972 gen6_update_ring_freq(dev
);
4974 dev_priv
->rps
.enabled
= true;
4975 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4978 void intel_enable_gt_powersave(struct drm_device
*dev
)
4980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4982 if (IS_IRONLAKE_M(dev
)) {
4983 ironlake_enable_drps(dev
);
4984 ironlake_enable_rc6(dev
);
4985 intel_init_emon(dev
);
4986 } else if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
4988 * PCU communication is slow and this doesn't need to be
4989 * done at any specific time, so do this out of our fast path
4990 * to make resume and init faster.
4992 schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
4993 round_jiffies_up_relative(HZ
));
4997 static void ibx_init_clock_gating(struct drm_device
*dev
)
4999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5002 * On Ibex Peak and Cougar Point, we need to disable clock
5003 * gating for the panel power sequencer or it will fail to
5004 * start up when no ports are active.
5006 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5009 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5014 for_each_pipe(pipe
) {
5015 I915_WRITE(DSPCNTR(pipe
),
5016 I915_READ(DSPCNTR(pipe
)) |
5017 DISPPLANE_TRICKLE_FEED_DISABLE
);
5018 intel_flush_primary_plane(dev_priv
, pipe
);
5022 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5025 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5029 * WaFbcDisableDpfcClockGating:ilk
5031 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5032 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5033 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5035 I915_WRITE(PCH_3DCGDIS0
,
5036 MARIUNIT_CLOCK_GATE_DISABLE
|
5037 SVSMUNIT_CLOCK_GATE_DISABLE
);
5038 I915_WRITE(PCH_3DCGDIS1
,
5039 VFMUNIT_CLOCK_GATE_DISABLE
);
5042 * According to the spec the following bits should be set in
5043 * order to enable memory self-refresh
5044 * The bit 22/21 of 0x42004
5045 * The bit 5 of 0x42020
5046 * The bit 15 of 0x45000
5048 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5049 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5050 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5051 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5052 I915_WRITE(DISP_ARB_CTL
,
5053 (I915_READ(DISP_ARB_CTL
) |
5055 I915_WRITE(WM3_LP_ILK
, 0);
5056 I915_WRITE(WM2_LP_ILK
, 0);
5057 I915_WRITE(WM1_LP_ILK
, 0);
5060 * Based on the document from hardware guys the following bits
5061 * should be set unconditionally in order to enable FBC.
5062 * The bit 22 of 0x42000
5063 * The bit 22 of 0x42004
5064 * The bit 7,8,9 of 0x42020.
5066 if (IS_IRONLAKE_M(dev
)) {
5067 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5068 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5069 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5071 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5072 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5076 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5078 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5079 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5080 ILK_ELPIN_409_SELECT
);
5081 I915_WRITE(_3D_CHICKEN2
,
5082 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5083 _3D_CHICKEN2_WM_READ_PIPELINED
);
5085 /* WaDisableRenderCachePipelinedFlush:ilk */
5086 I915_WRITE(CACHE_MODE_0
,
5087 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5089 g4x_disable_trickle_feed(dev
);
5091 ibx_init_clock_gating(dev
);
5094 static void cpt_init_clock_gating(struct drm_device
*dev
)
5096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5101 * On Ibex Peak and Cougar Point, we need to disable clock
5102 * gating for the panel power sequencer or it will fail to
5103 * start up when no ports are active.
5105 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5106 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5107 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5108 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5109 DPLS_EDP_PPS_FIX_DIS
);
5110 /* The below fixes the weird display corruption, a few pixels shifted
5111 * downward, on (only) LVDS of some HP laptops with IVY.
5113 for_each_pipe(pipe
) {
5114 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5115 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5116 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5117 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5118 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5119 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5120 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5121 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5122 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5124 /* WADP0ClockGatingDisable */
5125 for_each_pipe(pipe
) {
5126 I915_WRITE(TRANS_CHICKEN1(pipe
),
5127 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5131 static void gen6_check_mch_setup(struct drm_device
*dev
)
5133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5136 tmp
= I915_READ(MCH_SSKPD
);
5137 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
5138 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
5139 DRM_INFO("This can cause pipe underruns and display issues.\n");
5140 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5144 static void gen6_init_clock_gating(struct drm_device
*dev
)
5146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5147 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5149 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5151 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5152 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5153 ILK_ELPIN_409_SELECT
);
5155 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5156 I915_WRITE(_3D_CHICKEN
,
5157 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5159 /* WaSetupGtModeTdRowDispatch:snb */
5160 if (IS_SNB_GT1(dev
))
5161 I915_WRITE(GEN6_GT_MODE
,
5162 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5164 I915_WRITE(WM3_LP_ILK
, 0);
5165 I915_WRITE(WM2_LP_ILK
, 0);
5166 I915_WRITE(WM1_LP_ILK
, 0);
5168 I915_WRITE(CACHE_MODE_0
,
5169 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5171 I915_WRITE(GEN6_UCGCTL1
,
5172 I915_READ(GEN6_UCGCTL1
) |
5173 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5174 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5176 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5177 * gating disable must be set. Failure to set it results in
5178 * flickering pixels due to Z write ordering failures after
5179 * some amount of runtime in the Mesa "fire" demo, and Unigine
5180 * Sanctuary and Tropics, and apparently anything else with
5181 * alpha test or pixel discard.
5183 * According to the spec, bit 11 (RCCUNIT) must also be set,
5184 * but we didn't debug actual testcases to find it out.
5186 * Also apply WaDisableVDSUnitClockGating:snb and
5187 * WaDisableRCPBUnitClockGating:snb.
5189 I915_WRITE(GEN6_UCGCTL2
,
5190 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
5191 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5192 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5194 /* Bspec says we need to always set all mask bits. */
5195 I915_WRITE(_3D_CHICKEN3
, (0xFFFF << 16) |
5196 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
);
5199 * According to the spec the following bits should be
5200 * set in order to enable memory self-refresh and fbc:
5201 * The bit21 and bit22 of 0x42000
5202 * The bit21 and bit22 of 0x42004
5203 * The bit5 and bit7 of 0x42020
5204 * The bit14 of 0x70180
5205 * The bit14 of 0x71180
5207 * WaFbcAsynchFlipDisableFbcQueue:snb
5209 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5210 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5211 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5212 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5213 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5214 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5215 I915_WRITE(ILK_DSPCLK_GATE_D
,
5216 I915_READ(ILK_DSPCLK_GATE_D
) |
5217 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5218 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5220 g4x_disable_trickle_feed(dev
);
5222 /* The default value should be 0x200 according to docs, but the two
5223 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5224 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_DISABLE(0xffff));
5225 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI
));
5227 cpt_init_clock_gating(dev
);
5229 gen6_check_mch_setup(dev
);
5232 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5234 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5236 reg
&= ~GEN7_FF_SCHED_MASK
;
5237 reg
|= GEN7_FF_TS_SCHED_HW
;
5238 reg
|= GEN7_FF_VS_SCHED_HW
;
5239 reg
|= GEN7_FF_DS_SCHED_HW
;
5241 if (IS_HASWELL(dev_priv
->dev
))
5242 reg
&= ~GEN7_FF_VS_REF_CNT_FFME
;
5244 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5247 static void lpt_init_clock_gating(struct drm_device
*dev
)
5249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5252 * TODO: this bit should only be enabled when really needed, then
5253 * disabled when not needed anymore in order to save power.
5255 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5256 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5257 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5258 PCH_LP_PARTITION_LEVEL_DISABLE
);
5260 /* WADPOClockGatingDisable:hsw */
5261 I915_WRITE(_TRANSA_CHICKEN1
,
5262 I915_READ(_TRANSA_CHICKEN1
) |
5263 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5266 static void lpt_suspend_hw(struct drm_device
*dev
)
5268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5270 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5271 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5273 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5274 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5278 static void gen8_init_clock_gating(struct drm_device
*dev
)
5280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5283 I915_WRITE(WM3_LP_ILK
, 0);
5284 I915_WRITE(WM2_LP_ILK
, 0);
5285 I915_WRITE(WM1_LP_ILK
, 0);
5287 /* FIXME(BDW): Check all the w/a, some might only apply to
5288 * pre-production hw. */
5290 WARN(!i915_preliminary_hw_support
,
5291 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5292 I915_WRITE(HALF_SLICE_CHICKEN3
,
5293 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5294 I915_WRITE(HALF_SLICE_CHICKEN3
,
5295 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5296 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5298 I915_WRITE(_3D_CHICKEN3
,
5299 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5301 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5302 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5304 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5305 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5307 /* WaSwitchSolVfFArbitrationPriority */
5308 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5310 /* WaPsrDPAMaskVBlankInSRD */
5311 I915_WRITE(CHICKEN_PAR1_1
,
5312 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5314 /* WaPsrDPRSUnmaskVBlankInSRD */
5316 I915_WRITE(CHICKEN_PIPESL_1(i
),
5317 I915_READ(CHICKEN_PIPESL_1(i
) |
5318 DPRS_MASK_VBLANK_SRD
));
5322 static void haswell_init_clock_gating(struct drm_device
*dev
)
5324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5326 I915_WRITE(WM3_LP_ILK
, 0);
5327 I915_WRITE(WM2_LP_ILK
, 0);
5328 I915_WRITE(WM1_LP_ILK
, 0);
5330 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5331 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5333 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5335 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5336 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5337 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5339 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5340 I915_WRITE(GEN7_L3CNTLREG1
,
5341 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5342 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5343 GEN7_WA_L3_CHICKEN_MODE
);
5345 /* L3 caching of data atomics doesn't work -- disable it. */
5346 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5347 I915_WRITE(HSW_ROW_CHICKEN3
,
5348 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5350 /* This is required by WaCatErrorRejectionIssue:hsw */
5351 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5352 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5353 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5355 /* WaVSRefCountFullforceMissDisable:hsw */
5356 gen7_setup_fixed_func_scheduler(dev_priv
);
5358 /* WaDisable4x2SubspanOptimization:hsw */
5359 I915_WRITE(CACHE_MODE_1
,
5360 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5362 /* WaSwitchSolVfFArbitrationPriority:hsw */
5363 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5365 /* WaRsPkgCStateDisplayPMReq:hsw */
5366 I915_WRITE(CHICKEN_PAR1_1
,
5367 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5369 lpt_init_clock_gating(dev
);
5372 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5377 I915_WRITE(WM3_LP_ILK
, 0);
5378 I915_WRITE(WM2_LP_ILK
, 0);
5379 I915_WRITE(WM1_LP_ILK
, 0);
5381 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5383 /* WaDisableEarlyCull:ivb */
5384 I915_WRITE(_3D_CHICKEN3
,
5385 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5387 /* WaDisableBackToBackFlipFix:ivb */
5388 I915_WRITE(IVB_CHICKEN3
,
5389 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5390 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5392 /* WaDisablePSDDualDispatchEnable:ivb */
5393 if (IS_IVB_GT1(dev
))
5394 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5395 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5397 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2
,
5398 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5400 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5401 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5402 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5404 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5405 I915_WRITE(GEN7_L3CNTLREG1
,
5406 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5407 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5408 GEN7_WA_L3_CHICKEN_MODE
);
5409 if (IS_IVB_GT1(dev
))
5410 I915_WRITE(GEN7_ROW_CHICKEN2
,
5411 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5413 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5414 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5417 /* WaForceL3Serialization:ivb */
5418 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5419 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5421 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5422 * gating disable must be set. Failure to set it results in
5423 * flickering pixels due to Z write ordering failures after
5424 * some amount of runtime in the Mesa "fire" demo, and Unigine
5425 * Sanctuary and Tropics, and apparently anything else with
5426 * alpha test or pixel discard.
5428 * According to the spec, bit 11 (RCCUNIT) must also be set,
5429 * but we didn't debug actual testcases to find it out.
5431 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5432 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5434 I915_WRITE(GEN6_UCGCTL2
,
5435 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
5436 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5438 /* This is required by WaCatErrorRejectionIssue:ivb */
5439 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5440 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5441 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5443 g4x_disable_trickle_feed(dev
);
5445 /* WaVSRefCountFullforceMissDisable:ivb */
5446 gen7_setup_fixed_func_scheduler(dev_priv
);
5448 /* WaDisable4x2SubspanOptimization:ivb */
5449 I915_WRITE(CACHE_MODE_1
,
5450 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5452 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5453 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5454 snpcr
|= GEN6_MBC_SNPCR_MED
;
5455 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5457 if (!HAS_PCH_NOP(dev
))
5458 cpt_init_clock_gating(dev
);
5460 gen6_check_mch_setup(dev
);
5463 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5467 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5469 /* WaDisableEarlyCull:vlv */
5470 I915_WRITE(_3D_CHICKEN3
,
5471 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5473 /* WaDisableBackToBackFlipFix:vlv */
5474 I915_WRITE(IVB_CHICKEN3
,
5475 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5476 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5478 /* WaDisablePSDDualDispatchEnable:vlv */
5479 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5480 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5481 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5483 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5484 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5485 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5487 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5488 I915_WRITE(GEN7_L3CNTLREG1
, I915_READ(GEN7_L3CNTLREG1
) | GEN7_L3AGDIS
);
5489 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
5491 /* WaForceL3Serialization:vlv */
5492 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5493 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5495 /* WaDisableDopClockGating:vlv */
5496 I915_WRITE(GEN7_ROW_CHICKEN2
,
5497 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5499 /* This is required by WaCatErrorRejectionIssue:vlv */
5500 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5501 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5502 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5504 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5505 * gating disable must be set. Failure to set it results in
5506 * flickering pixels due to Z write ordering failures after
5507 * some amount of runtime in the Mesa "fire" demo, and Unigine
5508 * Sanctuary and Tropics, and apparently anything else with
5509 * alpha test or pixel discard.
5511 * According to the spec, bit 11 (RCCUNIT) must also be set,
5512 * but we didn't debug actual testcases to find it out.
5514 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5515 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5517 * Also apply WaDisableVDSUnitClockGating:vlv and
5518 * WaDisableRCPBUnitClockGating:vlv.
5520 I915_WRITE(GEN6_UCGCTL2
,
5521 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
5522 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
5523 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
5524 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5525 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5527 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5529 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5531 I915_WRITE(CACHE_MODE_1
,
5532 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5535 * WaDisableVLVClockGating_VBIIssue:vlv
5536 * Disable clock gating on th GCFG unit to prevent a delay
5537 * in the reporting of vblank events.
5539 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, 0xffffffff);
5541 /* Conservative clock gating settings for now */
5542 I915_WRITE(0x9400, 0xffffffff);
5543 I915_WRITE(0x9404, 0xffffffff);
5544 I915_WRITE(0x9408, 0xffffffff);
5545 I915_WRITE(0x940c, 0xffffffff);
5546 I915_WRITE(0x9410, 0xffffffff);
5547 I915_WRITE(0x9414, 0xffffffff);
5548 I915_WRITE(0x9418, 0xffffffff);
5551 static void g4x_init_clock_gating(struct drm_device
*dev
)
5553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 uint32_t dspclk_gate
;
5556 I915_WRITE(RENCLK_GATE_D1
, 0);
5557 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5558 GS_UNIT_CLOCK_GATE_DISABLE
|
5559 CL_UNIT_CLOCK_GATE_DISABLE
);
5560 I915_WRITE(RAMCLK_GATE_D
, 0);
5561 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5562 OVRUNIT_CLOCK_GATE_DISABLE
|
5563 OVCUNIT_CLOCK_GATE_DISABLE
;
5565 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5566 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5568 /* WaDisableRenderCachePipelinedFlush */
5569 I915_WRITE(CACHE_MODE_0
,
5570 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5572 g4x_disable_trickle_feed(dev
);
5575 static void crestline_init_clock_gating(struct drm_device
*dev
)
5577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5579 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5580 I915_WRITE(RENCLK_GATE_D2
, 0);
5581 I915_WRITE(DSPCLK_GATE_D
, 0);
5582 I915_WRITE(RAMCLK_GATE_D
, 0);
5583 I915_WRITE16(DEUC
, 0);
5584 I915_WRITE(MI_ARB_STATE
,
5585 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5588 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5592 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5593 I965_RCC_CLOCK_GATE_DISABLE
|
5594 I965_RCPB_CLOCK_GATE_DISABLE
|
5595 I965_ISC_CLOCK_GATE_DISABLE
|
5596 I965_FBC_CLOCK_GATE_DISABLE
);
5597 I915_WRITE(RENCLK_GATE_D2
, 0);
5598 I915_WRITE(MI_ARB_STATE
,
5599 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5602 static void gen3_init_clock_gating(struct drm_device
*dev
)
5604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5605 u32 dstate
= I915_READ(D_STATE
);
5607 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5608 DSTATE_DOT_CLOCK_GATING
;
5609 I915_WRITE(D_STATE
, dstate
);
5611 if (IS_PINEVIEW(dev
))
5612 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5614 /* IIR "flip pending" means done if this bit is set */
5615 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5618 static void i85x_init_clock_gating(struct drm_device
*dev
)
5620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5622 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5625 static void i830_init_clock_gating(struct drm_device
*dev
)
5627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5629 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5632 void intel_init_clock_gating(struct drm_device
*dev
)
5634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5636 dev_priv
->display
.init_clock_gating(dev
);
5639 void intel_suspend_hw(struct drm_device
*dev
)
5641 if (HAS_PCH_LPT(dev
))
5642 lpt_suspend_hw(dev
);
5645 static bool is_always_on_power_domain(struct drm_device
*dev
,
5646 enum intel_display_power_domain domain
)
5648 unsigned long always_on_domains
;
5650 BUG_ON(BIT(domain
) & ~POWER_DOMAIN_MASK
);
5652 if (IS_BROADWELL(dev
)) {
5653 always_on_domains
= BDW_ALWAYS_ON_POWER_DOMAINS
;
5654 } else if (IS_HASWELL(dev
)) {
5655 always_on_domains
= HSW_ALWAYS_ON_POWER_DOMAINS
;
5661 return BIT(domain
) & always_on_domains
;
5665 * We should only use the power well if we explicitly asked the hardware to
5666 * enable it, so check if it's enabled and also check if we've requested it to
5669 bool intel_display_power_enabled(struct drm_device
*dev
,
5670 enum intel_display_power_domain domain
)
5672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5674 if (!HAS_POWER_WELL(dev
))
5677 if (is_always_on_power_domain(dev
, domain
))
5680 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5681 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
5684 static void __intel_set_power_well(struct drm_device
*dev
, bool enable
)
5686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5687 bool is_enabled
, enable_requested
;
5690 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5691 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
5692 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
5695 if (!enable_requested
)
5696 I915_WRITE(HSW_PWR_WELL_DRIVER
,
5697 HSW_PWR_WELL_ENABLE_REQUEST
);
5700 DRM_DEBUG_KMS("Enabling power well\n");
5701 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5702 HSW_PWR_WELL_STATE_ENABLED
), 20))
5703 DRM_ERROR("Timeout enabling power well\n");
5706 if (enable_requested
) {
5707 unsigned long irqflags
;
5710 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5711 POSTING_READ(HSW_PWR_WELL_DRIVER
);
5712 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5715 * After this, the registers on the pipes that are part
5716 * of the power well will become zero, so we have to
5717 * adjust our counters according to that.
5719 * FIXME: Should we do this in general in
5720 * drm_vblank_post_modeset?
5722 spin_lock_irqsave(&dev
->vbl_lock
, irqflags
);
5725 dev
->vblank
[p
].last
= 0;
5726 spin_unlock_irqrestore(&dev
->vbl_lock
, irqflags
);
5731 static void __intel_power_well_get(struct drm_device
*dev
,
5732 struct i915_power_well
*power_well
)
5734 if (!power_well
->count
++)
5735 __intel_set_power_well(dev
, true);
5738 static void __intel_power_well_put(struct drm_device
*dev
,
5739 struct i915_power_well
*power_well
)
5741 WARN_ON(!power_well
->count
);
5742 if (!--power_well
->count
&& i915_disable_power_well
)
5743 __intel_set_power_well(dev
, false);
5746 void intel_display_power_get(struct drm_device
*dev
,
5747 enum intel_display_power_domain domain
)
5749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5750 struct i915_power_domains
*power_domains
;
5752 if (!HAS_POWER_WELL(dev
))
5755 if (is_always_on_power_domain(dev
, domain
))
5758 power_domains
= &dev_priv
->power_domains
;
5760 mutex_lock(&power_domains
->lock
);
5761 __intel_power_well_get(dev
, &power_domains
->power_wells
[0]);
5762 mutex_unlock(&power_domains
->lock
);
5765 void intel_display_power_put(struct drm_device
*dev
,
5766 enum intel_display_power_domain domain
)
5768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5769 struct i915_power_domains
*power_domains
;
5771 if (!HAS_POWER_WELL(dev
))
5774 if (is_always_on_power_domain(dev
, domain
))
5777 power_domains
= &dev_priv
->power_domains
;
5779 mutex_lock(&power_domains
->lock
);
5780 __intel_power_well_put(dev
, &power_domains
->power_wells
[0]);
5781 mutex_unlock(&power_domains
->lock
);
5784 static struct i915_power_domains
*hsw_pwr
;
5786 /* Display audio driver power well request */
5787 void i915_request_power_well(void)
5789 struct drm_i915_private
*dev_priv
;
5791 if (WARN_ON(!hsw_pwr
))
5794 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
5797 mutex_lock(&hsw_pwr
->lock
);
5798 __intel_power_well_get(dev_priv
->dev
, &hsw_pwr
->power_wells
[0]);
5799 mutex_unlock(&hsw_pwr
->lock
);
5801 EXPORT_SYMBOL_GPL(i915_request_power_well
);
5803 /* Display audio driver power well release */
5804 void i915_release_power_well(void)
5806 struct drm_i915_private
*dev_priv
;
5808 if (WARN_ON(!hsw_pwr
))
5811 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
5814 mutex_lock(&hsw_pwr
->lock
);
5815 __intel_power_well_put(dev_priv
->dev
, &hsw_pwr
->power_wells
[0]);
5816 mutex_unlock(&hsw_pwr
->lock
);
5818 EXPORT_SYMBOL_GPL(i915_release_power_well
);
5820 int intel_power_domains_init(struct drm_device
*dev
)
5822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5823 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
5824 struct i915_power_well
*power_well
;
5826 mutex_init(&power_domains
->lock
);
5827 hsw_pwr
= power_domains
;
5829 power_well
= &power_domains
->power_wells
[0];
5830 power_well
->count
= 0;
5835 void intel_power_domains_remove(struct drm_device
*dev
)
5840 static void intel_power_domains_resume(struct drm_device
*dev
)
5842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5843 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
5844 struct i915_power_well
*power_well
;
5846 if (!HAS_POWER_WELL(dev
))
5849 mutex_lock(&power_domains
->lock
);
5851 power_well
= &power_domains
->power_wells
[0];
5852 __intel_set_power_well(dev
, power_well
->count
> 0);
5854 mutex_unlock(&power_domains
->lock
);
5858 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5859 * when not needed anymore. We have 4 registers that can request the power well
5860 * to be enabled, and it will only be disabled if none of the registers is
5861 * requesting it to be enabled.
5863 void intel_power_domains_init_hw(struct drm_device
*dev
)
5865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5867 if (!HAS_POWER_WELL(dev
))
5870 /* For now, we need the power well to be always enabled. */
5871 intel_display_set_init_power(dev
, true);
5872 intel_power_domains_resume(dev
);
5874 /* We're taking over the BIOS, so clear any requests made by it since
5875 * the driver is in charge now. */
5876 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
5877 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
5880 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5881 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
5883 hsw_disable_package_c8(dev_priv
);
5886 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
5888 hsw_enable_package_c8(dev_priv
);
5891 /* Set up chip specific power management-related functions */
5892 void intel_init_pm(struct drm_device
*dev
)
5894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5896 if (I915_HAS_FBC(dev
)) {
5897 if (HAS_PCH_SPLIT(dev
)) {
5898 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5899 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
5900 dev_priv
->display
.enable_fbc
=
5903 dev_priv
->display
.enable_fbc
=
5904 ironlake_enable_fbc
;
5905 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5906 } else if (IS_GM45(dev
)) {
5907 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5908 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5909 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5910 } else if (IS_CRESTLINE(dev
)) {
5911 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5912 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5913 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5915 /* 855GM needs testing */
5919 if (IS_PINEVIEW(dev
))
5920 i915_pineview_get_mem_freq(dev
);
5921 else if (IS_GEN5(dev
))
5922 i915_ironlake_get_mem_freq(dev
);
5924 /* For FIFO watermark updates */
5925 if (HAS_PCH_SPLIT(dev
)) {
5926 intel_setup_wm_latency(dev
);
5929 if (dev_priv
->wm
.pri_latency
[1] &&
5930 dev_priv
->wm
.spr_latency
[1] &&
5931 dev_priv
->wm
.cur_latency
[1])
5932 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5934 DRM_DEBUG_KMS("Failed to get proper latency. "
5936 dev_priv
->display
.update_wm
= NULL
;
5938 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
5939 } else if (IS_GEN6(dev
)) {
5940 if (dev_priv
->wm
.pri_latency
[0] &&
5941 dev_priv
->wm
.spr_latency
[0] &&
5942 dev_priv
->wm
.cur_latency
[0]) {
5943 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
5944 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5946 DRM_DEBUG_KMS("Failed to read display plane latency. "
5948 dev_priv
->display
.update_wm
= NULL
;
5950 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
5951 } else if (IS_IVYBRIDGE(dev
)) {
5952 if (dev_priv
->wm
.pri_latency
[0] &&
5953 dev_priv
->wm
.spr_latency
[0] &&
5954 dev_priv
->wm
.cur_latency
[0]) {
5955 dev_priv
->display
.update_wm
= ivybridge_update_wm
;
5956 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5958 DRM_DEBUG_KMS("Failed to read display plane latency. "
5960 dev_priv
->display
.update_wm
= NULL
;
5962 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
5963 } else if (IS_HASWELL(dev
)) {
5964 if (dev_priv
->wm
.pri_latency
[0] &&
5965 dev_priv
->wm
.spr_latency
[0] &&
5966 dev_priv
->wm
.cur_latency
[0]) {
5967 dev_priv
->display
.update_wm
= haswell_update_wm
;
5968 dev_priv
->display
.update_sprite_wm
=
5969 haswell_update_sprite_wm
;
5971 DRM_DEBUG_KMS("Failed to read display plane latency. "
5973 dev_priv
->display
.update_wm
= NULL
;
5975 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
5976 } else if (INTEL_INFO(dev
)->gen
== 8) {
5977 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
5979 dev_priv
->display
.update_wm
= NULL
;
5980 } else if (IS_VALLEYVIEW(dev
)) {
5981 dev_priv
->display
.update_wm
= valleyview_update_wm
;
5982 dev_priv
->display
.init_clock_gating
=
5983 valleyview_init_clock_gating
;
5984 } else if (IS_PINEVIEW(dev
)) {
5985 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5988 dev_priv
->mem_freq
)) {
5989 DRM_INFO("failed to find known CxSR latency "
5990 "(found ddr%s fsb freq %d, mem freq %d), "
5992 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
5993 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5994 /* Disable CxSR and never update its watermark again */
5995 pineview_disable_cxsr(dev
);
5996 dev_priv
->display
.update_wm
= NULL
;
5998 dev_priv
->display
.update_wm
= pineview_update_wm
;
5999 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6000 } else if (IS_G4X(dev
)) {
6001 dev_priv
->display
.update_wm
= g4x_update_wm
;
6002 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6003 } else if (IS_GEN4(dev
)) {
6004 dev_priv
->display
.update_wm
= i965_update_wm
;
6005 if (IS_CRESTLINE(dev
))
6006 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6007 else if (IS_BROADWATER(dev
))
6008 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6009 } else if (IS_GEN3(dev
)) {
6010 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6011 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6012 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6013 } else if (IS_I865G(dev
)) {
6014 dev_priv
->display
.update_wm
= i830_update_wm
;
6015 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6016 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6017 } else if (IS_I85X(dev
)) {
6018 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6019 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
6020 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6022 dev_priv
->display
.update_wm
= i830_update_wm
;
6023 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6025 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6027 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6031 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
6033 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6035 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6036 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6040 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6041 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6043 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6045 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6049 *val
= I915_READ(GEN6_PCODE_DATA
);
6050 I915_WRITE(GEN6_PCODE_DATA
, 0);
6055 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
6057 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6059 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6060 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6064 I915_WRITE(GEN6_PCODE_DATA
, val
);
6065 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6067 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6069 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6073 I915_WRITE(GEN6_PCODE_DATA
, 0);
6078 int vlv_gpu_freq(int ddr_freq
, int val
)
6099 return ((val
- 0xbd) * mult
) + base
;
6102 int vlv_freq_opcode(int ddr_freq
, int val
)
6133 void intel_pm_init(struct drm_device
*dev
)
6135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6137 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6138 intel_gen6_powersave_work
);