2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device
*dev
)
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 /* Disable compression */
75 fbc_ctl
= I915_READ(FBC_CONTROL
);
76 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
79 fbc_ctl
&= ~FBC_CTL_EN
;
80 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc
*crtc
)
93 struct drm_device
*dev
= crtc
->dev
;
94 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
95 struct drm_framebuffer
*fb
= crtc
->fb
;
96 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
97 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
98 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
103 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
104 if (fb
->pitches
[0] < cfb_pitch
)
105 cfb_pitch
= fb
->pitches
[0];
107 /* FBC_CTL wants 32B or 64B units */
109 cfb_pitch
= (cfb_pitch
/ 32) - 1;
111 cfb_pitch
= (cfb_pitch
/ 64) - 1;
112 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
115 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
116 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
122 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
124 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
125 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
129 fbc_ctl
= I915_READ(FBC_CONTROL
);
130 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
131 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
133 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
134 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
135 fbc_ctl
|= obj
->fence_reg
;
136 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
139 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
142 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
149 static void g4x_enable_fbc(struct drm_crtc
*crtc
)
151 struct drm_device
*dev
= crtc
->dev
;
152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
153 struct drm_framebuffer
*fb
= crtc
->fb
;
154 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
155 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
157 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
160 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
161 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
162 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
164 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
167 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
172 static void g4x_disable_fbc(struct drm_device
*dev
)
174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
177 /* Disable compression */
178 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
179 if (dpfc_ctl
& DPFC_CTL_EN
) {
180 dpfc_ctl
&= ~DPFC_CTL_EN
;
181 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
183 DRM_DEBUG_KMS("disabled FBC\n");
187 static bool g4x_fbc_enabled(struct drm_device
*dev
)
189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
194 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
199 /* Make sure blitter notifies FBC of writes */
201 /* Blitter is part of Media powerwell on VLV. No impact of
202 * his param in other platforms for now */
203 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_MEDIA
);
205 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
206 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
207 GEN6_BLITTER_LOCK_SHIFT
;
208 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
209 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
210 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
211 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
212 GEN6_BLITTER_LOCK_SHIFT
);
213 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
214 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
216 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_MEDIA
);
219 static void ironlake_enable_fbc(struct drm_crtc
*crtc
)
221 struct drm_device
*dev
= crtc
->dev
;
222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
223 struct drm_framebuffer
*fb
= crtc
->fb
;
224 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
225 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
226 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
227 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
230 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
231 dpfc_ctl
&= DPFC_RESERVED
;
232 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
233 /* Set persistent mode for front-buffer rendering, ala X. */
234 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
235 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
237 dpfc_ctl
|= obj
->fence_reg
;
238 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
240 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
241 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
243 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
246 I915_WRITE(SNB_DPFC_CTL_SA
,
247 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
249 sandybridge_blit_fbc_update(dev
);
252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
255 static void ironlake_disable_fbc(struct drm_device
*dev
)
257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
260 /* Disable compression */
261 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
262 if (dpfc_ctl
& DPFC_CTL_EN
) {
263 dpfc_ctl
&= ~DPFC_CTL_EN
;
264 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
266 DRM_DEBUG_KMS("disabled FBC\n");
270 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
274 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
277 static void gen7_enable_fbc(struct drm_crtc
*crtc
)
279 struct drm_device
*dev
= crtc
->dev
;
280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
281 struct drm_framebuffer
*fb
= crtc
->fb
;
282 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
283 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
286 I915_WRITE(IVB_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
));
288 I915_WRITE(ILK_DPFC_CONTROL
, DPFC_CTL_EN
| DPFC_CTL_LIMIT_1X
|
289 IVB_DPFC_CTL_FENCE_EN
|
290 intel_crtc
->plane
<< IVB_DPFC_CTL_PLANE_SHIFT
);
292 if (IS_IVYBRIDGE(dev
)) {
293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
294 I915_WRITE(ILK_DISPLAY_CHICKEN1
, ILK_FBCQ_DIS
);
296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc
->pipe
),
298 HSW_BYPASS_FBC_QUEUE
);
301 I915_WRITE(SNB_DPFC_CTL_SA
,
302 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
305 sandybridge_blit_fbc_update(dev
);
307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
310 bool intel_fbc_enabled(struct drm_device
*dev
)
312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 if (!dev_priv
->display
.fbc_enabled
)
317 return dev_priv
->display
.fbc_enabled(dev
);
320 static void intel_fbc_work_fn(struct work_struct
*__work
)
322 struct intel_fbc_work
*work
=
323 container_of(to_delayed_work(__work
),
324 struct intel_fbc_work
, work
);
325 struct drm_device
*dev
= work
->crtc
->dev
;
326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 mutex_lock(&dev
->struct_mutex
);
329 if (work
== dev_priv
->fbc
.fbc_work
) {
330 /* Double check that we haven't switched fb without cancelling
333 if (work
->crtc
->fb
== work
->fb
) {
334 dev_priv
->display
.enable_fbc(work
->crtc
);
336 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
337 dev_priv
->fbc
.fb_id
= work
->crtc
->fb
->base
.id
;
338 dev_priv
->fbc
.y
= work
->crtc
->y
;
341 dev_priv
->fbc
.fbc_work
= NULL
;
343 mutex_unlock(&dev
->struct_mutex
);
348 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
350 if (dev_priv
->fbc
.fbc_work
== NULL
)
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
359 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv
->fbc
.fbc_work
);
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
368 dev_priv
->fbc
.fbc_work
= NULL
;
371 static void intel_enable_fbc(struct drm_crtc
*crtc
)
373 struct intel_fbc_work
*work
;
374 struct drm_device
*dev
= crtc
->dev
;
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 if (!dev_priv
->display
.enable_fbc
)
380 intel_cancel_fbc_work(dev_priv
);
382 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
384 DRM_ERROR("Failed to allocate FBC work structure\n");
385 dev_priv
->display
.enable_fbc(crtc
);
391 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
393 dev_priv
->fbc
.fbc_work
= work
;
395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
408 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
411 void intel_disable_fbc(struct drm_device
*dev
)
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 intel_cancel_fbc_work(dev_priv
);
417 if (!dev_priv
->display
.disable_fbc
)
420 dev_priv
->display
.disable_fbc(dev
);
421 dev_priv
->fbc
.plane
= -1;
424 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
425 enum no_fbc_reason reason
)
427 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
430 dev_priv
->fbc
.no_fbc_reason
= reason
;
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
451 * We need to enable/disable FBC on a global basis.
453 void intel_update_fbc(struct drm_device
*dev
)
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
457 struct intel_crtc
*intel_crtc
;
458 struct drm_framebuffer
*fb
;
459 struct intel_framebuffer
*intel_fb
;
460 struct drm_i915_gem_object
*obj
;
461 const struct drm_display_mode
*adjusted_mode
;
462 unsigned int max_width
, max_height
;
464 if (!I915_HAS_FBC(dev
)) {
465 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
469 if (!i915_powersave
) {
470 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
484 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
485 if (intel_crtc_active(tmp_crtc
) &&
486 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
488 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
496 if (!crtc
|| crtc
->fb
== NULL
) {
497 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
498 DRM_DEBUG_KMS("no output, disabling\n");
502 intel_crtc
= to_intel_crtc(crtc
);
504 intel_fb
= to_intel_framebuffer(fb
);
506 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
508 if (i915_enable_fbc
< 0 &&
509 INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
)) {
510 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
511 DRM_DEBUG_KMS("disabled per chip default\n");
514 if (!i915_enable_fbc
) {
515 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
519 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
520 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
521 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
527 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
534 if (intel_crtc
->config
.pipe_src_w
> max_width
||
535 intel_crtc
->config
.pipe_src_h
> max_height
) {
536 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
540 if ((INTEL_INFO(dev
)->gen
< 4 || IS_HASWELL(dev
)) &&
541 intel_crtc
->plane
!= PLANE_A
) {
542 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
543 DRM_DEBUG_KMS("plane not A, disabling compression\n");
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
550 if (obj
->tiling_mode
!= I915_TILING_X
||
551 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
552 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
557 /* If the kernel debugger is active, always disable compression */
561 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
562 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
572 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
573 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
574 dev_priv
->fbc
.y
== crtc
->y
)
577 if (intel_fbc_enabled(dev
)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev
);
605 intel_enable_fbc(crtc
);
606 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev
)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev
);
615 i915_gem_stolen_cleanup_compression(dev
);
618 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
623 tmp
= I915_READ(CLKCFG
);
625 switch (tmp
& CLKCFG_FSB_MASK
) {
627 dev_priv
->fsb_freq
= 533; /* 133*4 */
630 dev_priv
->fsb_freq
= 800; /* 200*4 */
633 dev_priv
->fsb_freq
= 667; /* 167*4 */
636 dev_priv
->fsb_freq
= 400; /* 100*4 */
640 switch (tmp
& CLKCFG_MEM_MASK
) {
642 dev_priv
->mem_freq
= 533;
645 dev_priv
->mem_freq
= 667;
648 dev_priv
->mem_freq
= 800;
652 /* detect pineview DDR3 setting */
653 tmp
= I915_READ(CSHRDDR3CTL
);
654 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
657 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
659 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 ddrpll
= I915_READ16(DDRMPLL1
);
663 csipll
= I915_READ16(CSIPLL0
);
665 switch (ddrpll
& 0xff) {
667 dev_priv
->mem_freq
= 800;
670 dev_priv
->mem_freq
= 1066;
673 dev_priv
->mem_freq
= 1333;
676 dev_priv
->mem_freq
= 1600;
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
681 dev_priv
->mem_freq
= 0;
685 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
687 switch (csipll
& 0x3ff) {
689 dev_priv
->fsb_freq
= 3200;
692 dev_priv
->fsb_freq
= 3733;
695 dev_priv
->fsb_freq
= 4266;
698 dev_priv
->fsb_freq
= 4800;
701 dev_priv
->fsb_freq
= 5333;
704 dev_priv
->fsb_freq
= 5866;
707 dev_priv
->fsb_freq
= 6400;
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
712 dev_priv
->fsb_freq
= 0;
716 if (dev_priv
->fsb_freq
== 3200) {
717 dev_priv
->ips
.c_m
= 0;
718 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
719 dev_priv
->ips
.c_m
= 1;
721 dev_priv
->ips
.c_m
= 2;
725 static const struct cxsr_latency cxsr_latency_table
[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
763 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
768 const struct cxsr_latency
*latency
;
771 if (fsb
== 0 || mem
== 0)
774 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
775 latency
= &cxsr_latency_table
[i
];
776 if (is_desktop
== latency
->is_desktop
&&
777 is_ddr3
== latency
->is_ddr3
&&
778 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
787 static void pineview_disable_cxsr(struct drm_device
*dev
)
789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
809 static const int latency_ns
= 5000;
811 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 uint32_t dsparb
= I915_READ(DSPARB
);
817 size
= dsparb
& 0x7f;
819 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
822 plane
? "B" : "A", size
);
827 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
830 uint32_t dsparb
= I915_READ(DSPARB
);
833 size
= dsparb
& 0x1ff;
835 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
836 size
>>= 1; /* Convert to cachelines */
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
839 plane
? "B" : "A", size
);
844 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
847 uint32_t dsparb
= I915_READ(DSPARB
);
850 size
= dsparb
& 0x7f;
851 size
>>= 2; /* Convert to cachelines */
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
860 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
863 uint32_t dsparb
= I915_READ(DSPARB
);
866 size
= dsparb
& 0x7f;
867 size
>>= 1; /* Convert to cachelines */
869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
870 plane
? "B" : "A", size
);
875 /* Pineview has different values for various configs */
876 static const struct intel_watermark_params pineview_display_wm
= {
877 PINEVIEW_DISPLAY_FIFO
,
881 PINEVIEW_FIFO_LINE_SIZE
883 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
884 PINEVIEW_DISPLAY_FIFO
,
886 PINEVIEW_DFT_HPLLOFF_WM
,
888 PINEVIEW_FIFO_LINE_SIZE
890 static const struct intel_watermark_params pineview_cursor_wm
= {
891 PINEVIEW_CURSOR_FIFO
,
892 PINEVIEW_CURSOR_MAX_WM
,
893 PINEVIEW_CURSOR_DFT_WM
,
894 PINEVIEW_CURSOR_GUARD_WM
,
895 PINEVIEW_FIFO_LINE_SIZE
,
897 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
898 PINEVIEW_CURSOR_FIFO
,
899 PINEVIEW_CURSOR_MAX_WM
,
900 PINEVIEW_CURSOR_DFT_WM
,
901 PINEVIEW_CURSOR_GUARD_WM
,
902 PINEVIEW_FIFO_LINE_SIZE
904 static const struct intel_watermark_params g4x_wm_info
= {
911 static const struct intel_watermark_params g4x_cursor_wm_info
= {
918 static const struct intel_watermark_params valleyview_wm_info
= {
919 VALLEYVIEW_FIFO_SIZE
,
925 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
927 VALLEYVIEW_CURSOR_MAX_WM
,
932 static const struct intel_watermark_params i965_cursor_wm_info
= {
939 static const struct intel_watermark_params i945_wm_info
= {
946 static const struct intel_watermark_params i915_wm_info
= {
953 static const struct intel_watermark_params i855_wm_info
= {
960 static const struct intel_watermark_params i830_wm_info
= {
968 static const struct intel_watermark_params ironlake_display_wm_info
= {
975 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
982 static const struct intel_watermark_params ironlake_display_srwm_info
= {
984 ILK_DISPLAY_MAX_SRWM
,
985 ILK_DISPLAY_DFT_SRWM
,
989 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
997 static const struct intel_watermark_params sandybridge_display_wm_info
= {
1004 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
1011 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
1012 SNB_DISPLAY_SR_FIFO
,
1013 SNB_DISPLAY_MAX_SRWM
,
1014 SNB_DISPLAY_DFT_SRWM
,
1018 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
1020 SNB_CURSOR_MAX_SRWM
,
1021 SNB_CURSOR_DFT_SRWM
,
1028 * intel_calculate_wm - calculate watermark level
1029 * @clock_in_khz: pixel clock
1030 * @wm: chip FIFO params
1031 * @pixel_size: display pixel size
1032 * @latency_ns: memory latency for the platform
1034 * Calculate the watermark level (the level at which the display plane will
1035 * start fetching from memory again). Each chip has a different display
1036 * FIFO size and allocation, so the caller needs to figure that out and pass
1037 * in the correct intel_watermark_params structure.
1039 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1040 * on the pixel size. When it reaches the watermark level, it'll start
1041 * fetching FIFO line sized based chunks from memory until the FIFO fills
1042 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1043 * will occur, and a display engine hang could result.
1045 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1046 const struct intel_watermark_params
*wm
,
1049 unsigned long latency_ns
)
1051 long entries_required
, wm_size
;
1054 * Note: we need to make sure we don't overflow for various clock &
1056 * clocks go from a few thousand to several hundred thousand.
1057 * latency is usually a few thousand
1059 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1061 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1063 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1065 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1067 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1069 /* Don't promote wm_size to unsigned... */
1070 if (wm_size
> (long)wm
->max_wm
)
1071 wm_size
= wm
->max_wm
;
1073 wm_size
= wm
->default_wm
;
1077 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1079 struct drm_crtc
*crtc
, *enabled
= NULL
;
1081 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1082 if (intel_crtc_active(crtc
)) {
1092 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1094 struct drm_device
*dev
= unused_crtc
->dev
;
1095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1096 struct drm_crtc
*crtc
;
1097 const struct cxsr_latency
*latency
;
1101 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1102 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1104 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1105 pineview_disable_cxsr(dev
);
1109 crtc
= single_enabled_crtc(dev
);
1111 const struct drm_display_mode
*adjusted_mode
;
1112 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1115 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1116 clock
= adjusted_mode
->crtc_clock
;
1119 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1120 pineview_display_wm
.fifo_size
,
1121 pixel_size
, latency
->display_sr
);
1122 reg
= I915_READ(DSPFW1
);
1123 reg
&= ~DSPFW_SR_MASK
;
1124 reg
|= wm
<< DSPFW_SR_SHIFT
;
1125 I915_WRITE(DSPFW1
, reg
);
1126 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1129 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1130 pineview_display_wm
.fifo_size
,
1131 pixel_size
, latency
->cursor_sr
);
1132 reg
= I915_READ(DSPFW3
);
1133 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1134 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1135 I915_WRITE(DSPFW3
, reg
);
1137 /* Display HPLL off SR */
1138 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1139 pineview_display_hplloff_wm
.fifo_size
,
1140 pixel_size
, latency
->display_hpll_disable
);
1141 reg
= I915_READ(DSPFW3
);
1142 reg
&= ~DSPFW_HPLL_SR_MASK
;
1143 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1144 I915_WRITE(DSPFW3
, reg
);
1146 /* cursor HPLL off SR */
1147 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1148 pineview_display_hplloff_wm
.fifo_size
,
1149 pixel_size
, latency
->cursor_hpll_disable
);
1150 reg
= I915_READ(DSPFW3
);
1151 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1152 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1153 I915_WRITE(DSPFW3
, reg
);
1154 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1158 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1159 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1161 pineview_disable_cxsr(dev
);
1162 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1166 static bool g4x_compute_wm0(struct drm_device
*dev
,
1168 const struct intel_watermark_params
*display
,
1169 int display_latency_ns
,
1170 const struct intel_watermark_params
*cursor
,
1171 int cursor_latency_ns
,
1175 struct drm_crtc
*crtc
;
1176 const struct drm_display_mode
*adjusted_mode
;
1177 int htotal
, hdisplay
, clock
, pixel_size
;
1178 int line_time_us
, line_count
;
1179 int entries
, tlb_miss
;
1181 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1182 if (!intel_crtc_active(crtc
)) {
1183 *cursor_wm
= cursor
->guard_size
;
1184 *plane_wm
= display
->guard_size
;
1188 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1189 clock
= adjusted_mode
->crtc_clock
;
1190 htotal
= adjusted_mode
->htotal
;
1191 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1192 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1194 /* Use the small buffer method to calculate plane watermark */
1195 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1196 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1198 entries
+= tlb_miss
;
1199 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1200 *plane_wm
= entries
+ display
->guard_size
;
1201 if (*plane_wm
> (int)display
->max_wm
)
1202 *plane_wm
= display
->max_wm
;
1204 /* Use the large buffer method to calculate cursor watermark */
1205 line_time_us
= ((htotal
* 1000) / clock
);
1206 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1207 entries
= line_count
* 64 * pixel_size
;
1208 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1210 entries
+= tlb_miss
;
1211 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1212 *cursor_wm
= entries
+ cursor
->guard_size
;
1213 if (*cursor_wm
> (int)cursor
->max_wm
)
1214 *cursor_wm
= (int)cursor
->max_wm
;
1220 * Check the wm result.
1222 * If any calculated watermark values is larger than the maximum value that
1223 * can be programmed into the associated watermark register, that watermark
1226 static bool g4x_check_srwm(struct drm_device
*dev
,
1227 int display_wm
, int cursor_wm
,
1228 const struct intel_watermark_params
*display
,
1229 const struct intel_watermark_params
*cursor
)
1231 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1232 display_wm
, cursor_wm
);
1234 if (display_wm
> display
->max_wm
) {
1235 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1236 display_wm
, display
->max_wm
);
1240 if (cursor_wm
> cursor
->max_wm
) {
1241 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1242 cursor_wm
, cursor
->max_wm
);
1246 if (!(display_wm
|| cursor_wm
)) {
1247 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1254 static bool g4x_compute_srwm(struct drm_device
*dev
,
1257 const struct intel_watermark_params
*display
,
1258 const struct intel_watermark_params
*cursor
,
1259 int *display_wm
, int *cursor_wm
)
1261 struct drm_crtc
*crtc
;
1262 const struct drm_display_mode
*adjusted_mode
;
1263 int hdisplay
, htotal
, pixel_size
, clock
;
1264 unsigned long line_time_us
;
1265 int line_count
, line_size
;
1270 *display_wm
= *cursor_wm
= 0;
1274 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1275 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1276 clock
= adjusted_mode
->crtc_clock
;
1277 htotal
= adjusted_mode
->htotal
;
1278 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1279 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1281 line_time_us
= (htotal
* 1000) / clock
;
1282 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1283 line_size
= hdisplay
* pixel_size
;
1285 /* Use the minimum of the small and large buffer method for primary */
1286 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1287 large
= line_count
* line_size
;
1289 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1290 *display_wm
= entries
+ display
->guard_size
;
1292 /* calculate the self-refresh watermark for display cursor */
1293 entries
= line_count
* pixel_size
* 64;
1294 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1295 *cursor_wm
= entries
+ cursor
->guard_size
;
1297 return g4x_check_srwm(dev
,
1298 *display_wm
, *cursor_wm
,
1302 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1304 int *plane_prec_mult
,
1306 int *cursor_prec_mult
,
1309 struct drm_crtc
*crtc
;
1310 int clock
, pixel_size
;
1313 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1314 if (!intel_crtc_active(crtc
))
1317 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1318 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1320 entries
= (clock
/ 1000) * pixel_size
;
1321 *plane_prec_mult
= (entries
> 256) ?
1322 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1323 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1326 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1327 *cursor_prec_mult
= (entries
> 256) ?
1328 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1329 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1335 * Update drain latency registers of memory arbiter
1337 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1338 * to be programmed. Each plane has a drain latency multiplier and a drain
1342 static void vlv_update_drain_latency(struct drm_device
*dev
)
1344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1345 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1346 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1347 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1350 /* For plane A, Cursor A */
1351 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1352 &cursor_prec_mult
, &cursora_dl
)) {
1353 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1354 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1355 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1356 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1358 I915_WRITE(VLV_DDL1
, cursora_prec
|
1359 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1360 planea_prec
| planea_dl
);
1363 /* For plane B, Cursor B */
1364 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1365 &cursor_prec_mult
, &cursorb_dl
)) {
1366 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1367 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1368 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1369 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1371 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1372 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1373 planeb_prec
| planeb_dl
);
1377 #define single_plane_enabled(mask) is_power_of_2(mask)
1379 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1381 struct drm_device
*dev
= crtc
->dev
;
1382 static const int sr_latency_ns
= 12000;
1383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1384 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1385 int plane_sr
, cursor_sr
;
1386 int ignore_plane_sr
, ignore_cursor_sr
;
1387 unsigned int enabled
= 0;
1389 vlv_update_drain_latency(dev
);
1391 if (g4x_compute_wm0(dev
, PIPE_A
,
1392 &valleyview_wm_info
, latency_ns
,
1393 &valleyview_cursor_wm_info
, latency_ns
,
1394 &planea_wm
, &cursora_wm
))
1395 enabled
|= 1 << PIPE_A
;
1397 if (g4x_compute_wm0(dev
, PIPE_B
,
1398 &valleyview_wm_info
, latency_ns
,
1399 &valleyview_cursor_wm_info
, latency_ns
,
1400 &planeb_wm
, &cursorb_wm
))
1401 enabled
|= 1 << PIPE_B
;
1403 if (single_plane_enabled(enabled
) &&
1404 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1406 &valleyview_wm_info
,
1407 &valleyview_cursor_wm_info
,
1408 &plane_sr
, &ignore_cursor_sr
) &&
1409 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1411 &valleyview_wm_info
,
1412 &valleyview_cursor_wm_info
,
1413 &ignore_plane_sr
, &cursor_sr
)) {
1414 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1416 I915_WRITE(FW_BLC_SELF_VLV
,
1417 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1418 plane_sr
= cursor_sr
= 0;
1421 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422 planea_wm
, cursora_wm
,
1423 planeb_wm
, cursorb_wm
,
1424 plane_sr
, cursor_sr
);
1427 (plane_sr
<< DSPFW_SR_SHIFT
) |
1428 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1429 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1432 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1433 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1435 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1436 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1439 static void g4x_update_wm(struct drm_crtc
*crtc
)
1441 struct drm_device
*dev
= crtc
->dev
;
1442 static const int sr_latency_ns
= 12000;
1443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1445 int plane_sr
, cursor_sr
;
1446 unsigned int enabled
= 0;
1448 if (g4x_compute_wm0(dev
, PIPE_A
,
1449 &g4x_wm_info
, latency_ns
,
1450 &g4x_cursor_wm_info
, latency_ns
,
1451 &planea_wm
, &cursora_wm
))
1452 enabled
|= 1 << PIPE_A
;
1454 if (g4x_compute_wm0(dev
, PIPE_B
,
1455 &g4x_wm_info
, latency_ns
,
1456 &g4x_cursor_wm_info
, latency_ns
,
1457 &planeb_wm
, &cursorb_wm
))
1458 enabled
|= 1 << PIPE_B
;
1460 if (single_plane_enabled(enabled
) &&
1461 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1464 &g4x_cursor_wm_info
,
1465 &plane_sr
, &cursor_sr
)) {
1466 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1468 I915_WRITE(FW_BLC_SELF
,
1469 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1470 plane_sr
= cursor_sr
= 0;
1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1474 planea_wm
, cursora_wm
,
1475 planeb_wm
, cursorb_wm
,
1476 plane_sr
, cursor_sr
);
1479 (plane_sr
<< DSPFW_SR_SHIFT
) |
1480 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1481 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1484 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1485 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1486 /* HPLL off in SR has some issues on G4x... disable it */
1488 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1489 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1492 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1494 struct drm_device
*dev
= unused_crtc
->dev
;
1495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1496 struct drm_crtc
*crtc
;
1500 /* Calc sr entries for one plane configs */
1501 crtc
= single_enabled_crtc(dev
);
1503 /* self-refresh has much higher latency */
1504 static const int sr_latency_ns
= 12000;
1505 const struct drm_display_mode
*adjusted_mode
=
1506 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1507 int clock
= adjusted_mode
->crtc_clock
;
1508 int htotal
= adjusted_mode
->htotal
;
1509 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1510 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1511 unsigned long line_time_us
;
1514 line_time_us
= ((htotal
* 1000) / clock
);
1516 /* Use ns/us then divide to preserve precision */
1517 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1518 pixel_size
* hdisplay
;
1519 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1520 srwm
= I965_FIFO_SIZE
- entries
;
1524 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1527 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1529 entries
= DIV_ROUND_UP(entries
,
1530 i965_cursor_wm_info
.cacheline_size
);
1531 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1532 (entries
+ i965_cursor_wm_info
.guard_size
);
1534 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1535 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1537 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1538 "cursor %d\n", srwm
, cursor_sr
);
1540 if (IS_CRESTLINE(dev
))
1541 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1543 /* Turn off self refresh if both pipes are enabled */
1544 if (IS_CRESTLINE(dev
))
1545 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1549 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1552 /* 965 has limitations... */
1553 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1554 (8 << 16) | (8 << 8) | (8 << 0));
1555 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1556 /* update cursor SR watermark */
1557 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1560 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1562 struct drm_device
*dev
= unused_crtc
->dev
;
1563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1564 const struct intel_watermark_params
*wm_info
;
1569 int planea_wm
, planeb_wm
;
1570 struct drm_crtc
*crtc
, *enabled
= NULL
;
1573 wm_info
= &i945_wm_info
;
1574 else if (!IS_GEN2(dev
))
1575 wm_info
= &i915_wm_info
;
1577 wm_info
= &i855_wm_info
;
1579 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1580 crtc
= intel_get_crtc_for_plane(dev
, 0);
1581 if (intel_crtc_active(crtc
)) {
1582 const struct drm_display_mode
*adjusted_mode
;
1583 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1587 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1588 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1589 wm_info
, fifo_size
, cpp
,
1593 planea_wm
= fifo_size
- wm_info
->guard_size
;
1595 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1596 crtc
= intel_get_crtc_for_plane(dev
, 1);
1597 if (intel_crtc_active(crtc
)) {
1598 const struct drm_display_mode
*adjusted_mode
;
1599 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1603 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1604 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1605 wm_info
, fifo_size
, cpp
,
1607 if (enabled
== NULL
)
1612 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1614 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1617 * Overlay gets an aggressive default since video jitter is bad.
1621 /* Play safe and disable self-refresh before adjusting watermarks. */
1622 if (IS_I945G(dev
) || IS_I945GM(dev
))
1623 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1624 else if (IS_I915GM(dev
))
1625 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1627 /* Calc sr entries for one plane configs */
1628 if (HAS_FW_BLC(dev
) && enabled
) {
1629 /* self-refresh has much higher latency */
1630 static const int sr_latency_ns
= 6000;
1631 const struct drm_display_mode
*adjusted_mode
=
1632 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1633 int clock
= adjusted_mode
->crtc_clock
;
1634 int htotal
= adjusted_mode
->htotal
;
1635 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1636 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1637 unsigned long line_time_us
;
1640 line_time_us
= (htotal
* 1000) / clock
;
1642 /* Use ns/us then divide to preserve precision */
1643 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1644 pixel_size
* hdisplay
;
1645 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1647 srwm
= wm_info
->fifo_size
- entries
;
1651 if (IS_I945G(dev
) || IS_I945GM(dev
))
1652 I915_WRITE(FW_BLC_SELF
,
1653 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1654 else if (IS_I915GM(dev
))
1655 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm
, planeb_wm
, cwm
, srwm
);
1661 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1662 fwater_hi
= (cwm
& 0x1f);
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1666 fwater_hi
= fwater_hi
| (1 << 8);
1668 I915_WRITE(FW_BLC
, fwater_lo
);
1669 I915_WRITE(FW_BLC2
, fwater_hi
);
1671 if (HAS_FW_BLC(dev
)) {
1673 if (IS_I945G(dev
) || IS_I945GM(dev
))
1674 I915_WRITE(FW_BLC_SELF
,
1675 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1676 else if (IS_I915GM(dev
))
1677 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1678 DRM_DEBUG_KMS("memory self refresh enabled\n");
1680 DRM_DEBUG_KMS("memory self refresh disabled\n");
1684 static void i830_update_wm(struct drm_crtc
*unused_crtc
)
1686 struct drm_device
*dev
= unused_crtc
->dev
;
1687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1688 struct drm_crtc
*crtc
;
1689 const struct drm_display_mode
*adjusted_mode
;
1693 crtc
= single_enabled_crtc(dev
);
1697 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1698 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1700 dev_priv
->display
.get_fifo_size(dev
, 0),
1702 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1703 fwater_lo
|= (3<<8) | planea_wm
;
1705 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1707 I915_WRITE(FW_BLC
, fwater_lo
);
1711 * Check the wm result.
1713 * If any calculated watermark values is larger than the maximum value that
1714 * can be programmed into the associated watermark register, that watermark
1717 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1718 int fbc_wm
, int display_wm
, int cursor_wm
,
1719 const struct intel_watermark_params
*display
,
1720 const struct intel_watermark_params
*cursor
)
1722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1724 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1725 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1727 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1728 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1729 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1731 /* fbc has it's own way to disable FBC WM */
1732 I915_WRITE(DISP_ARB_CTL
,
1733 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1735 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1736 /* enable FBC WM (except on ILK, where it must remain off) */
1737 I915_WRITE(DISP_ARB_CTL
,
1738 I915_READ(DISP_ARB_CTL
) & ~DISP_FBC_WM_DIS
);
1741 if (display_wm
> display
->max_wm
) {
1742 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1743 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1747 if (cursor_wm
> cursor
->max_wm
) {
1748 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1749 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1753 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1754 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1762 * Compute watermark values of WM[1-3],
1764 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1766 const struct intel_watermark_params
*display
,
1767 const struct intel_watermark_params
*cursor
,
1768 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1770 struct drm_crtc
*crtc
;
1771 const struct drm_display_mode
*adjusted_mode
;
1772 unsigned long line_time_us
;
1773 int hdisplay
, htotal
, pixel_size
, clock
;
1774 int line_count
, line_size
;
1779 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1783 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1784 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1785 clock
= adjusted_mode
->crtc_clock
;
1786 htotal
= adjusted_mode
->htotal
;
1787 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1788 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1790 line_time_us
= (htotal
* 1000) / clock
;
1791 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1792 line_size
= hdisplay
* pixel_size
;
1794 /* Use the minimum of the small and large buffer method for primary */
1795 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1796 large
= line_count
* line_size
;
1798 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1799 *display_wm
= entries
+ display
->guard_size
;
1803 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1805 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1807 /* calculate the self-refresh watermark for display cursor */
1808 entries
= line_count
* pixel_size
* 64;
1809 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1810 *cursor_wm
= entries
+ cursor
->guard_size
;
1812 return ironlake_check_srwm(dev
, level
,
1813 *fbc_wm
, *display_wm
, *cursor_wm
,
1817 static void ironlake_update_wm(struct drm_crtc
*crtc
)
1819 struct drm_device
*dev
= crtc
->dev
;
1820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1821 int fbc_wm
, plane_wm
, cursor_wm
;
1822 unsigned int enabled
;
1825 if (g4x_compute_wm0(dev
, PIPE_A
,
1826 &ironlake_display_wm_info
,
1827 dev_priv
->wm
.pri_latency
[0] * 100,
1828 &ironlake_cursor_wm_info
,
1829 dev_priv
->wm
.cur_latency
[0] * 100,
1830 &plane_wm
, &cursor_wm
)) {
1831 I915_WRITE(WM0_PIPEA_ILK
,
1832 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1833 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1834 " plane %d, " "cursor: %d\n",
1835 plane_wm
, cursor_wm
);
1836 enabled
|= 1 << PIPE_A
;
1839 if (g4x_compute_wm0(dev
, PIPE_B
,
1840 &ironlake_display_wm_info
,
1841 dev_priv
->wm
.pri_latency
[0] * 100,
1842 &ironlake_cursor_wm_info
,
1843 dev_priv
->wm
.cur_latency
[0] * 100,
1844 &plane_wm
, &cursor_wm
)) {
1845 I915_WRITE(WM0_PIPEB_ILK
,
1846 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1847 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1848 " plane %d, cursor: %d\n",
1849 plane_wm
, cursor_wm
);
1850 enabled
|= 1 << PIPE_B
;
1854 * Calculate and update the self-refresh watermark only when one
1855 * display plane is used.
1857 I915_WRITE(WM3_LP_ILK
, 0);
1858 I915_WRITE(WM2_LP_ILK
, 0);
1859 I915_WRITE(WM1_LP_ILK
, 0);
1861 if (!single_plane_enabled(enabled
))
1863 enabled
= ffs(enabled
) - 1;
1866 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1867 dev_priv
->wm
.pri_latency
[1] * 500,
1868 &ironlake_display_srwm_info
,
1869 &ironlake_cursor_srwm_info
,
1870 &fbc_wm
, &plane_wm
, &cursor_wm
))
1873 I915_WRITE(WM1_LP_ILK
,
1875 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
1876 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1877 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1881 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1882 dev_priv
->wm
.pri_latency
[2] * 500,
1883 &ironlake_display_srwm_info
,
1884 &ironlake_cursor_srwm_info
,
1885 &fbc_wm
, &plane_wm
, &cursor_wm
))
1888 I915_WRITE(WM2_LP_ILK
,
1890 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
1891 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1892 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1896 * WM3 is unsupported on ILK, probably because we don't have latency
1897 * data for that power state
1901 static void sandybridge_update_wm(struct drm_crtc
*crtc
)
1903 struct drm_device
*dev
= crtc
->dev
;
1904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1905 int latency
= dev_priv
->wm
.pri_latency
[0] * 100; /* In unit 0.1us */
1907 int fbc_wm
, plane_wm
, cursor_wm
;
1908 unsigned int enabled
;
1911 if (g4x_compute_wm0(dev
, PIPE_A
,
1912 &sandybridge_display_wm_info
, latency
,
1913 &sandybridge_cursor_wm_info
, latency
,
1914 &plane_wm
, &cursor_wm
)) {
1915 val
= I915_READ(WM0_PIPEA_ILK
);
1916 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1917 I915_WRITE(WM0_PIPEA_ILK
, val
|
1918 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1919 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1920 " plane %d, " "cursor: %d\n",
1921 plane_wm
, cursor_wm
);
1922 enabled
|= 1 << PIPE_A
;
1925 if (g4x_compute_wm0(dev
, PIPE_B
,
1926 &sandybridge_display_wm_info
, latency
,
1927 &sandybridge_cursor_wm_info
, latency
,
1928 &plane_wm
, &cursor_wm
)) {
1929 val
= I915_READ(WM0_PIPEB_ILK
);
1930 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1931 I915_WRITE(WM0_PIPEB_ILK
, val
|
1932 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1933 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1934 " plane %d, cursor: %d\n",
1935 plane_wm
, cursor_wm
);
1936 enabled
|= 1 << PIPE_B
;
1940 * Calculate and update the self-refresh watermark only when one
1941 * display plane is used.
1943 * SNB support 3 levels of watermark.
1945 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1946 * and disabled in the descending order
1949 I915_WRITE(WM3_LP_ILK
, 0);
1950 I915_WRITE(WM2_LP_ILK
, 0);
1951 I915_WRITE(WM1_LP_ILK
, 0);
1953 if (!single_plane_enabled(enabled
) ||
1954 dev_priv
->sprite_scaling_enabled
)
1956 enabled
= ffs(enabled
) - 1;
1959 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1960 dev_priv
->wm
.pri_latency
[1] * 500,
1961 &sandybridge_display_srwm_info
,
1962 &sandybridge_cursor_srwm_info
,
1963 &fbc_wm
, &plane_wm
, &cursor_wm
))
1966 I915_WRITE(WM1_LP_ILK
,
1968 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
1969 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1970 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1974 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1975 dev_priv
->wm
.pri_latency
[2] * 500,
1976 &sandybridge_display_srwm_info
,
1977 &sandybridge_cursor_srwm_info
,
1978 &fbc_wm
, &plane_wm
, &cursor_wm
))
1981 I915_WRITE(WM2_LP_ILK
,
1983 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
1984 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1985 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1989 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1990 dev_priv
->wm
.pri_latency
[3] * 500,
1991 &sandybridge_display_srwm_info
,
1992 &sandybridge_cursor_srwm_info
,
1993 &fbc_wm
, &plane_wm
, &cursor_wm
))
1996 I915_WRITE(WM3_LP_ILK
,
1998 (dev_priv
->wm
.pri_latency
[3] << WM1_LP_LATENCY_SHIFT
) |
1999 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2000 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2004 static void ivybridge_update_wm(struct drm_crtc
*crtc
)
2006 struct drm_device
*dev
= crtc
->dev
;
2007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2008 int latency
= dev_priv
->wm
.pri_latency
[0] * 100; /* In unit 0.1us */
2010 int fbc_wm
, plane_wm
, cursor_wm
;
2011 int ignore_fbc_wm
, ignore_plane_wm
, ignore_cursor_wm
;
2012 unsigned int enabled
;
2015 if (g4x_compute_wm0(dev
, PIPE_A
,
2016 &sandybridge_display_wm_info
, latency
,
2017 &sandybridge_cursor_wm_info
, latency
,
2018 &plane_wm
, &cursor_wm
)) {
2019 val
= I915_READ(WM0_PIPEA_ILK
);
2020 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2021 I915_WRITE(WM0_PIPEA_ILK
, val
|
2022 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2023 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2024 " plane %d, " "cursor: %d\n",
2025 plane_wm
, cursor_wm
);
2026 enabled
|= 1 << PIPE_A
;
2029 if (g4x_compute_wm0(dev
, PIPE_B
,
2030 &sandybridge_display_wm_info
, latency
,
2031 &sandybridge_cursor_wm_info
, latency
,
2032 &plane_wm
, &cursor_wm
)) {
2033 val
= I915_READ(WM0_PIPEB_ILK
);
2034 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2035 I915_WRITE(WM0_PIPEB_ILK
, val
|
2036 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2037 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2038 " plane %d, cursor: %d\n",
2039 plane_wm
, cursor_wm
);
2040 enabled
|= 1 << PIPE_B
;
2043 if (g4x_compute_wm0(dev
, PIPE_C
,
2044 &sandybridge_display_wm_info
, latency
,
2045 &sandybridge_cursor_wm_info
, latency
,
2046 &plane_wm
, &cursor_wm
)) {
2047 val
= I915_READ(WM0_PIPEC_IVB
);
2048 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2049 I915_WRITE(WM0_PIPEC_IVB
, val
|
2050 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2051 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2052 " plane %d, cursor: %d\n",
2053 plane_wm
, cursor_wm
);
2054 enabled
|= 1 << PIPE_C
;
2058 * Calculate and update the self-refresh watermark only when one
2059 * display plane is used.
2061 * SNB support 3 levels of watermark.
2063 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2064 * and disabled in the descending order
2067 I915_WRITE(WM3_LP_ILK
, 0);
2068 I915_WRITE(WM2_LP_ILK
, 0);
2069 I915_WRITE(WM1_LP_ILK
, 0);
2071 if (!single_plane_enabled(enabled
) ||
2072 dev_priv
->sprite_scaling_enabled
)
2074 enabled
= ffs(enabled
) - 1;
2077 if (!ironlake_compute_srwm(dev
, 1, enabled
,
2078 dev_priv
->wm
.pri_latency
[1] * 500,
2079 &sandybridge_display_srwm_info
,
2080 &sandybridge_cursor_srwm_info
,
2081 &fbc_wm
, &plane_wm
, &cursor_wm
))
2084 I915_WRITE(WM1_LP_ILK
,
2086 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
2087 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2088 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2092 if (!ironlake_compute_srwm(dev
, 2, enabled
,
2093 dev_priv
->wm
.pri_latency
[2] * 500,
2094 &sandybridge_display_srwm_info
,
2095 &sandybridge_cursor_srwm_info
,
2096 &fbc_wm
, &plane_wm
, &cursor_wm
))
2099 I915_WRITE(WM2_LP_ILK
,
2101 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
2102 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2103 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2106 /* WM3, note we have to correct the cursor latency */
2107 if (!ironlake_compute_srwm(dev
, 3, enabled
,
2108 dev_priv
->wm
.pri_latency
[3] * 500,
2109 &sandybridge_display_srwm_info
,
2110 &sandybridge_cursor_srwm_info
,
2111 &fbc_wm
, &plane_wm
, &ignore_cursor_wm
) ||
2112 !ironlake_compute_srwm(dev
, 3, enabled
,
2113 dev_priv
->wm
.cur_latency
[3] * 500,
2114 &sandybridge_display_srwm_info
,
2115 &sandybridge_cursor_srwm_info
,
2116 &ignore_fbc_wm
, &ignore_plane_wm
, &cursor_wm
))
2119 I915_WRITE(WM3_LP_ILK
,
2121 (dev_priv
->wm
.pri_latency
[3] << WM1_LP_LATENCY_SHIFT
) |
2122 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2123 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2127 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
2128 struct drm_crtc
*crtc
)
2130 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2131 uint32_t pixel_rate
;
2133 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
2135 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2136 * adjust the pixel_rate here. */
2138 if (intel_crtc
->config
.pch_pfit
.enabled
) {
2139 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
2140 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
2142 pipe_w
= intel_crtc
->config
.pipe_src_w
;
2143 pipe_h
= intel_crtc
->config
.pipe_src_h
;
2144 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
2145 pfit_h
= pfit_size
& 0xFFFF;
2146 if (pipe_w
< pfit_w
)
2148 if (pipe_h
< pfit_h
)
2151 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
2158 /* latency must be in 0.1us units. */
2159 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2164 if (WARN(latency
== 0, "Latency value missing\n"))
2167 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
2168 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
2173 /* latency must be in 0.1us units. */
2174 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2175 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2180 if (WARN(latency
== 0, "Latency value missing\n"))
2183 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
2184 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
2185 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2189 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2190 uint8_t bytes_per_pixel
)
2192 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
2195 struct hsw_pipe_wm_parameters
{
2197 uint32_t pipe_htotal
;
2198 uint32_t pixel_rate
;
2199 struct intel_plane_wm_parameters pri
;
2200 struct intel_plane_wm_parameters spr
;
2201 struct intel_plane_wm_parameters cur
;
2204 struct hsw_wm_maximums
{
2211 /* used in computing the new watermarks state */
2212 struct intel_wm_config
{
2213 unsigned int num_pipes_active
;
2214 bool sprites_enabled
;
2215 bool sprites_scaled
;
2219 * For both WM_PIPE and WM_LP.
2220 * mem_value must be in 0.1us units.
2222 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters
*params
,
2226 uint32_t method1
, method2
;
2228 if (!params
->active
|| !params
->pri
.enabled
)
2231 method1
= ilk_wm_method1(params
->pixel_rate
,
2232 params
->pri
.bytes_per_pixel
,
2238 method2
= ilk_wm_method2(params
->pixel_rate
,
2239 params
->pipe_htotal
,
2240 params
->pri
.horiz_pixels
,
2241 params
->pri
.bytes_per_pixel
,
2244 return min(method1
, method2
);
2248 * For both WM_PIPE and WM_LP.
2249 * mem_value must be in 0.1us units.
2251 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters
*params
,
2254 uint32_t method1
, method2
;
2256 if (!params
->active
|| !params
->spr
.enabled
)
2259 method1
= ilk_wm_method1(params
->pixel_rate
,
2260 params
->spr
.bytes_per_pixel
,
2262 method2
= ilk_wm_method2(params
->pixel_rate
,
2263 params
->pipe_htotal
,
2264 params
->spr
.horiz_pixels
,
2265 params
->spr
.bytes_per_pixel
,
2267 return min(method1
, method2
);
2271 * For both WM_PIPE and WM_LP.
2272 * mem_value must be in 0.1us units.
2274 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters
*params
,
2277 if (!params
->active
|| !params
->cur
.enabled
)
2280 return ilk_wm_method2(params
->pixel_rate
,
2281 params
->pipe_htotal
,
2282 params
->cur
.horiz_pixels
,
2283 params
->cur
.bytes_per_pixel
,
2287 /* Only for WM_LP. */
2288 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters
*params
,
2291 if (!params
->active
|| !params
->pri
.enabled
)
2294 return ilk_wm_fbc(pri_val
,
2295 params
->pri
.horiz_pixels
,
2296 params
->pri
.bytes_per_pixel
);
2299 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
2301 if (INTEL_INFO(dev
)->gen
>= 8)
2303 else if (INTEL_INFO(dev
)->gen
>= 7)
2309 /* Calculate the maximum primary/sprite plane watermark */
2310 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2312 const struct intel_wm_config
*config
,
2313 enum intel_ddb_partitioning ddb_partitioning
,
2316 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
2319 /* if sprites aren't enabled, sprites get nothing */
2320 if (is_sprite
&& !config
->sprites_enabled
)
2323 /* HSW allows LP1+ watermarks even with multiple pipes */
2324 if (level
== 0 || config
->num_pipes_active
> 1) {
2325 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
2328 * For some reason the non self refresh
2329 * FIFO size is only half of the self
2330 * refresh FIFO size on ILK/SNB.
2332 if (INTEL_INFO(dev
)->gen
<= 6)
2336 if (config
->sprites_enabled
) {
2337 /* level 0 is always calculated with 1:1 split */
2338 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2347 /* clamp to max that the registers can hold */
2348 if (INTEL_INFO(dev
)->gen
>= 8)
2349 max
= level
== 0 ? 255 : 2047;
2350 else if (INTEL_INFO(dev
)->gen
>= 7)
2351 /* IVB/HSW primary/sprite plane watermarks */
2352 max
= level
== 0 ? 127 : 1023;
2353 else if (!is_sprite
)
2354 /* ILK/SNB primary plane watermarks */
2355 max
= level
== 0 ? 127 : 511;
2357 /* ILK/SNB sprite plane watermarks */
2358 max
= level
== 0 ? 63 : 255;
2360 return min(fifo_size
, max
);
2363 /* Calculate the maximum cursor plane watermark */
2364 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2366 const struct intel_wm_config
*config
)
2368 /* HSW LP1+ watermarks w/ multiple pipes */
2369 if (level
> 0 && config
->num_pipes_active
> 1)
2372 /* otherwise just report max that registers can hold */
2373 if (INTEL_INFO(dev
)->gen
>= 7)
2374 return level
== 0 ? 63 : 255;
2376 return level
== 0 ? 31 : 63;
2379 /* Calculate the maximum FBC watermark */
2380 static unsigned int ilk_fbc_wm_max(struct drm_device
*dev
)
2382 /* max that registers can hold */
2383 if (INTEL_INFO(dev
)->gen
>= 8)
2389 static void ilk_compute_wm_maximums(struct drm_device
*dev
,
2391 const struct intel_wm_config
*config
,
2392 enum intel_ddb_partitioning ddb_partitioning
,
2393 struct hsw_wm_maximums
*max
)
2395 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2396 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2397 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2398 max
->fbc
= ilk_fbc_wm_max(dev
);
2401 static bool ilk_validate_wm_level(int level
,
2402 const struct hsw_wm_maximums
*max
,
2403 struct intel_wm_level
*result
)
2407 /* already determined to be invalid? */
2408 if (!result
->enable
)
2411 result
->enable
= result
->pri_val
<= max
->pri
&&
2412 result
->spr_val
<= max
->spr
&&
2413 result
->cur_val
<= max
->cur
;
2415 ret
= result
->enable
;
2418 * HACK until we can pre-compute everything,
2419 * and thus fail gracefully if LP0 watermarks
2422 if (level
== 0 && !result
->enable
) {
2423 if (result
->pri_val
> max
->pri
)
2424 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2425 level
, result
->pri_val
, max
->pri
);
2426 if (result
->spr_val
> max
->spr
)
2427 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2428 level
, result
->spr_val
, max
->spr
);
2429 if (result
->cur_val
> max
->cur
)
2430 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2431 level
, result
->cur_val
, max
->cur
);
2433 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2434 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2435 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2436 result
->enable
= true;
2442 static void ilk_compute_wm_level(struct drm_i915_private
*dev_priv
,
2444 const struct hsw_pipe_wm_parameters
*p
,
2445 struct intel_wm_level
*result
)
2447 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2448 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2449 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2451 /* WM1+ latency values stored in 0.5us units */
2458 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2459 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2460 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2461 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2462 result
->enable
= true;
2466 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2469 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2470 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2471 u32 linetime
, ips_linetime
;
2473 if (!intel_crtc_active(crtc
))
2476 /* The WM are computed with base on how long it takes to fill a single
2477 * row at the given clock rate, multiplied by 8.
2479 linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8, mode
->clock
);
2480 ips_linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8,
2481 intel_ddi_get_cdclk_freq(dev_priv
));
2483 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2484 PIPE_WM_LINETIME_TIME(linetime
);
2487 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2491 if (IS_HASWELL(dev
)) {
2492 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2494 wm
[0] = (sskpd
>> 56) & 0xFF;
2496 wm
[0] = sskpd
& 0xF;
2497 wm
[1] = (sskpd
>> 4) & 0xFF;
2498 wm
[2] = (sskpd
>> 12) & 0xFF;
2499 wm
[3] = (sskpd
>> 20) & 0x1FF;
2500 wm
[4] = (sskpd
>> 32) & 0x1FF;
2501 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2502 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2504 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2505 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2506 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2507 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2508 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2509 uint32_t mltr
= I915_READ(MLTR_ILK
);
2511 /* ILK primary LP0 latency is 700 ns */
2513 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2514 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2518 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2520 /* ILK sprite LP0 latency is 1300 ns */
2521 if (INTEL_INFO(dev
)->gen
== 5)
2525 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2527 /* ILK cursor LP0 latency is 1300 ns */
2528 if (INTEL_INFO(dev
)->gen
== 5)
2531 /* WaDoubleCursorLP3Latency:ivb */
2532 if (IS_IVYBRIDGE(dev
))
2536 static int ilk_wm_max_level(const struct drm_device
*dev
)
2538 /* how many WM levels are we expecting */
2539 if (IS_HASWELL(dev
))
2541 else if (INTEL_INFO(dev
)->gen
>= 6)
2547 static void intel_print_wm_latency(struct drm_device
*dev
,
2549 const uint16_t wm
[5])
2551 int level
, max_level
= ilk_wm_max_level(dev
);
2553 for (level
= 0; level
<= max_level
; level
++) {
2554 unsigned int latency
= wm
[level
];
2557 DRM_ERROR("%s WM%d latency not provided\n",
2562 /* WM1+ latency values in 0.5us units */
2566 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2567 name
, level
, wm
[level
],
2568 latency
/ 10, latency
% 10);
2572 static void intel_setup_wm_latency(struct drm_device
*dev
)
2574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2576 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2578 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2579 sizeof(dev_priv
->wm
.pri_latency
));
2580 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2581 sizeof(dev_priv
->wm
.pri_latency
));
2583 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2584 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2586 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2587 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2588 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2591 static void hsw_compute_wm_parameters(struct drm_crtc
*crtc
,
2592 struct hsw_pipe_wm_parameters
*p
,
2593 struct intel_wm_config
*config
)
2595 struct drm_device
*dev
= crtc
->dev
;
2596 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2597 enum pipe pipe
= intel_crtc
->pipe
;
2598 struct drm_plane
*plane
;
2600 p
->active
= intel_crtc_active(crtc
);
2602 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.htotal
;
2603 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2604 p
->pri
.bytes_per_pixel
= crtc
->fb
->bits_per_pixel
/ 8;
2605 p
->cur
.bytes_per_pixel
= 4;
2606 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2607 p
->cur
.horiz_pixels
= 64;
2608 /* TODO: for now, assume primary and cursor planes are always enabled. */
2609 p
->pri
.enabled
= true;
2610 p
->cur
.enabled
= true;
2613 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
2614 config
->num_pipes_active
+= intel_crtc_active(crtc
);
2616 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2617 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2619 if (intel_plane
->pipe
== pipe
)
2620 p
->spr
= intel_plane
->wm
;
2622 config
->sprites_enabled
|= intel_plane
->wm
.enabled
;
2623 config
->sprites_scaled
|= intel_plane
->wm
.scaled
;
2627 /* Compute new watermarks for the pipe */
2628 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2629 const struct hsw_pipe_wm_parameters
*params
,
2630 struct intel_pipe_wm
*pipe_wm
)
2632 struct drm_device
*dev
= crtc
->dev
;
2633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2634 int level
, max_level
= ilk_wm_max_level(dev
);
2635 /* LP0 watermark maximums depend on this pipe alone */
2636 struct intel_wm_config config
= {
2637 .num_pipes_active
= 1,
2638 .sprites_enabled
= params
->spr
.enabled
,
2639 .sprites_scaled
= params
->spr
.scaled
,
2641 struct hsw_wm_maximums max
;
2643 /* LP0 watermarks always use 1/2 DDB partitioning */
2644 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2646 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2647 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2650 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2651 if (params
->spr
.scaled
)
2654 for (level
= 0; level
<= max_level
; level
++)
2655 ilk_compute_wm_level(dev_priv
, level
, params
,
2656 &pipe_wm
->wm
[level
]);
2658 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2660 /* At least LP0 must be valid */
2661 return ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]);
2665 * Merge the watermarks from all active pipes for a specific level.
2667 static void ilk_merge_wm_level(struct drm_device
*dev
,
2669 struct intel_wm_level
*ret_wm
)
2671 const struct intel_crtc
*intel_crtc
;
2673 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2674 const struct intel_wm_level
*wm
=
2675 &intel_crtc
->wm
.active
.wm
[level
];
2680 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2681 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2682 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2683 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2686 ret_wm
->enable
= true;
2690 * Merge all low power watermarks for all active pipes.
2692 static void ilk_wm_merge(struct drm_device
*dev
,
2693 const struct intel_wm_config
*config
,
2694 const struct hsw_wm_maximums
*max
,
2695 struct intel_pipe_wm
*merged
)
2697 int level
, max_level
= ilk_wm_max_level(dev
);
2699 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2700 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2701 config
->num_pipes_active
> 1)
2704 /* ILK: FBC WM must be disabled always */
2705 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2707 /* merge each WM1+ level */
2708 for (level
= 1; level
<= max_level
; level
++) {
2709 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2711 ilk_merge_wm_level(dev
, level
, wm
);
2713 if (!ilk_validate_wm_level(level
, max
, wm
))
2717 * The spec says it is preferred to disable
2718 * FBC WMs instead of disabling a WM level.
2720 if (wm
->fbc_val
> max
->fbc
) {
2721 merged
->fbc_wm_enabled
= false;
2726 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2728 * FIXME this is racy. FBC might get enabled later.
2729 * What we should check here is whether FBC can be
2730 * enabled sometime later.
2732 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2733 for (level
= 2; level
<= max_level
; level
++) {
2734 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2741 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2743 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2744 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2747 /* The value we need to program into the WM_LPx latency field */
2748 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2752 if (IS_HASWELL(dev
))
2755 return dev_priv
->wm
.pri_latency
[level
];
2758 static void hsw_compute_wm_results(struct drm_device
*dev
,
2759 const struct intel_pipe_wm
*merged
,
2760 enum intel_ddb_partitioning partitioning
,
2761 struct hsw_wm_values
*results
)
2763 struct intel_crtc
*intel_crtc
;
2766 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2767 results
->partitioning
= partitioning
;
2769 /* LP1+ register values */
2770 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2771 const struct intel_wm_level
*r
;
2773 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2775 r
= &merged
->wm
[level
];
2779 results
->wm_lp
[wm_lp
- 1] = WM3_LP_EN
|
2780 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2781 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2784 if (INTEL_INFO(dev
)->gen
>= 8)
2785 results
->wm_lp
[wm_lp
- 1] |=
2786 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2788 results
->wm_lp
[wm_lp
- 1] |=
2789 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2791 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2792 WARN_ON(wm_lp
!= 1);
2793 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2795 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2798 /* LP0 register values */
2799 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2800 enum pipe pipe
= intel_crtc
->pipe
;
2801 const struct intel_wm_level
*r
=
2802 &intel_crtc
->wm
.active
.wm
[0];
2804 if (WARN_ON(!r
->enable
))
2807 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2809 results
->wm_pipe
[pipe
] =
2810 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2811 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2816 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2817 * case both are at the same level. Prefer r1 in case they're the same. */
2818 static struct intel_pipe_wm
*hsw_find_best_result(struct drm_device
*dev
,
2819 struct intel_pipe_wm
*r1
,
2820 struct intel_pipe_wm
*r2
)
2822 int level
, max_level
= ilk_wm_max_level(dev
);
2823 int level1
= 0, level2
= 0;
2825 for (level
= 1; level
<= max_level
; level
++) {
2826 if (r1
->wm
[level
].enable
)
2828 if (r2
->wm
[level
].enable
)
2832 if (level1
== level2
) {
2833 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2837 } else if (level1
> level2
) {
2844 /* dirty bits used to track which watermarks need changes */
2845 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2846 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2847 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2848 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2849 #define WM_DIRTY_FBC (1 << 24)
2850 #define WM_DIRTY_DDB (1 << 25)
2852 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2853 const struct hsw_wm_values
*old
,
2854 const struct hsw_wm_values
*new)
2856 unsigned int dirty
= 0;
2860 for_each_pipe(pipe
) {
2861 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2862 dirty
|= WM_DIRTY_LINETIME(pipe
);
2863 /* Must disable LP1+ watermarks too */
2864 dirty
|= WM_DIRTY_LP_ALL
;
2867 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2868 dirty
|= WM_DIRTY_PIPE(pipe
);
2869 /* Must disable LP1+ watermarks too */
2870 dirty
|= WM_DIRTY_LP_ALL
;
2874 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2875 dirty
|= WM_DIRTY_FBC
;
2876 /* Must disable LP1+ watermarks too */
2877 dirty
|= WM_DIRTY_LP_ALL
;
2880 if (old
->partitioning
!= new->partitioning
) {
2881 dirty
|= WM_DIRTY_DDB
;
2882 /* Must disable LP1+ watermarks too */
2883 dirty
|= WM_DIRTY_LP_ALL
;
2886 /* LP1+ watermarks already deemed dirty, no need to continue */
2887 if (dirty
& WM_DIRTY_LP_ALL
)
2890 /* Find the lowest numbered LP1+ watermark in need of an update... */
2891 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2892 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2893 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2897 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2898 for (; wm_lp
<= 3; wm_lp
++)
2899 dirty
|= WM_DIRTY_LP(wm_lp
);
2905 * The spec says we shouldn't write when we don't need, because every write
2906 * causes WMs to be re-evaluated, expending some power.
2908 static void hsw_write_wm_values(struct drm_i915_private
*dev_priv
,
2909 struct hsw_wm_values
*results
)
2911 struct drm_device
*dev
= dev_priv
->dev
;
2912 struct hsw_wm_values
*previous
= &dev_priv
->wm
.hw
;
2916 dirty
= ilk_compute_wm_dirty(dev_priv
->dev
, previous
, results
);
2920 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2921 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2922 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2924 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2925 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2926 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2928 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2929 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2930 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2934 * Don't touch WM1S_LP_EN here.
2935 * Doing so could cause underruns.
2938 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2939 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2940 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2941 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2942 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2943 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2945 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2946 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2947 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2948 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2949 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2950 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2952 if (dirty
& WM_DIRTY_DDB
) {
2953 if (IS_HASWELL(dev
)) {
2954 val
= I915_READ(WM_MISC
);
2955 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2956 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2958 val
|= WM_MISC_DATA_PARTITION_5_6
;
2959 I915_WRITE(WM_MISC
, val
);
2961 val
= I915_READ(DISP_ARB_CTL2
);
2962 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2963 val
&= ~DISP_DATA_PARTITION_5_6
;
2965 val
|= DISP_DATA_PARTITION_5_6
;
2966 I915_WRITE(DISP_ARB_CTL2
, val
);
2970 if (dirty
& WM_DIRTY_FBC
) {
2971 val
= I915_READ(DISP_ARB_CTL
);
2972 if (results
->enable_fbc_wm
)
2973 val
&= ~DISP_FBC_WM_DIS
;
2975 val
|= DISP_FBC_WM_DIS
;
2976 I915_WRITE(DISP_ARB_CTL
, val
);
2979 if (INTEL_INFO(dev
)->gen
<= 6) {
2980 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2981 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2983 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2984 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2985 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2986 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2987 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2988 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2991 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2992 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2993 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2994 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2995 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2996 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2998 dev_priv
->wm
.hw
= *results
;
3001 static void haswell_update_wm(struct drm_crtc
*crtc
)
3003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3004 struct drm_device
*dev
= crtc
->dev
;
3005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3006 struct hsw_wm_maximums max
;
3007 struct hsw_pipe_wm_parameters params
= {};
3008 struct hsw_wm_values results
= {};
3009 enum intel_ddb_partitioning partitioning
;
3010 struct intel_pipe_wm pipe_wm
= {};
3011 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3012 struct intel_wm_config config
= {};
3014 hsw_compute_wm_parameters(crtc
, ¶ms
, &config
);
3016 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
3018 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
3021 intel_crtc
->wm
.active
= pipe_wm
;
3023 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
3024 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
3026 /* 5/6 split only in single pipe config on IVB+ */
3027 if (INTEL_INFO(dev
)->gen
>= 7 &&
3028 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
3029 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
3030 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
3032 best_lp_wm
= hsw_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3034 best_lp_wm
= &lp_wm_1_2
;
3037 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3038 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3040 hsw_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3042 hsw_write_wm_values(dev_priv
, &results
);
3045 static void haswell_update_sprite_wm(struct drm_plane
*plane
,
3046 struct drm_crtc
*crtc
,
3047 uint32_t sprite_width
, int pixel_size
,
3048 bool enabled
, bool scaled
)
3050 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3052 intel_plane
->wm
.enabled
= enabled
;
3053 intel_plane
->wm
.scaled
= scaled
;
3054 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3055 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
3057 haswell_update_wm(crtc
);
3061 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
3062 uint32_t sprite_width
, int pixel_size
,
3063 const struct intel_watermark_params
*display
,
3064 int display_latency_ns
, int *sprite_wm
)
3066 struct drm_crtc
*crtc
;
3068 int entries
, tlb_miss
;
3070 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3071 if (!intel_crtc_active(crtc
)) {
3072 *sprite_wm
= display
->guard_size
;
3076 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3078 /* Use the small buffer method to calculate the sprite watermark */
3079 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
3080 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
3083 entries
+= tlb_miss
;
3084 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
3085 *sprite_wm
= entries
+ display
->guard_size
;
3086 if (*sprite_wm
> (int)display
->max_wm
)
3087 *sprite_wm
= display
->max_wm
;
3093 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
3094 uint32_t sprite_width
, int pixel_size
,
3095 const struct intel_watermark_params
*display
,
3096 int latency_ns
, int *sprite_wm
)
3098 struct drm_crtc
*crtc
;
3099 unsigned long line_time_us
;
3101 int line_count
, line_size
;
3110 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3111 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3117 line_time_us
= (sprite_width
* 1000) / clock
;
3118 if (!line_time_us
) {
3123 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
3124 line_size
= sprite_width
* pixel_size
;
3126 /* Use the minimum of the small and large buffer method for primary */
3127 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
3128 large
= line_count
* line_size
;
3130 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
3131 *sprite_wm
= entries
+ display
->guard_size
;
3133 return *sprite_wm
> 0x3ff ? false : true;
3136 static void sandybridge_update_sprite_wm(struct drm_plane
*plane
,
3137 struct drm_crtc
*crtc
,
3138 uint32_t sprite_width
, int pixel_size
,
3139 bool enabled
, bool scaled
)
3141 struct drm_device
*dev
= plane
->dev
;
3142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3143 int pipe
= to_intel_plane(plane
)->pipe
;
3144 int latency
= dev_priv
->wm
.spr_latency
[0] * 100; /* In unit 0.1us */
3154 reg
= WM0_PIPEA_ILK
;
3157 reg
= WM0_PIPEB_ILK
;
3160 reg
= WM0_PIPEC_IVB
;
3163 return; /* bad pipe */
3166 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
3167 &sandybridge_display_wm_info
,
3168 latency
, &sprite_wm
);
3170 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3175 val
= I915_READ(reg
);
3176 val
&= ~WM0_PIPE_SPRITE_MASK
;
3177 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
3178 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe
), sprite_wm
);
3181 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3183 &sandybridge_display_srwm_info
,
3184 dev_priv
->wm
.spr_latency
[1] * 500,
3187 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3191 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
3193 /* Only IVB has two more LP watermarks for sprite */
3194 if (!IS_IVYBRIDGE(dev
))
3197 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3199 &sandybridge_display_srwm_info
,
3200 dev_priv
->wm
.spr_latency
[2] * 500,
3203 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3207 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
3209 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3211 &sandybridge_display_srwm_info
,
3212 dev_priv
->wm
.spr_latency
[3] * 500,
3215 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3219 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
3222 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3224 struct drm_device
*dev
= crtc
->dev
;
3225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3226 struct hsw_wm_values
*hw
= &dev_priv
->wm
.hw
;
3227 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3228 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
3229 enum pipe pipe
= intel_crtc
->pipe
;
3230 static const unsigned int wm0_pipe_reg
[] = {
3231 [PIPE_A
] = WM0_PIPEA_ILK
,
3232 [PIPE_B
] = WM0_PIPEB_ILK
,
3233 [PIPE_C
] = WM0_PIPEC_IVB
,
3236 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3237 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3239 if (intel_crtc_active(crtc
)) {
3240 u32 tmp
= hw
->wm_pipe
[pipe
];
3243 * For active pipes LP0 watermark is marked as
3244 * enabled, and LP1+ watermaks as disabled since
3245 * we can't really reverse compute them in case
3246 * multiple pipes are active.
3248 active
->wm
[0].enable
= true;
3249 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3250 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3251 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3252 active
->linetime
= hw
->wm_linetime
[pipe
];
3254 int level
, max_level
= ilk_wm_max_level(dev
);
3257 * For inactive pipes, all watermark levels
3258 * should be marked as enabled but zeroed,
3259 * which is what we'd compute them to.
3261 for (level
= 0; level
<= max_level
; level
++)
3262 active
->wm
[level
].enable
= true;
3266 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3269 struct hsw_wm_values
*hw
= &dev_priv
->wm
.hw
;
3270 struct drm_crtc
*crtc
;
3272 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3273 ilk_pipe_wm_get_hw_state(crtc
);
3275 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3276 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3277 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3279 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3280 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3281 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3283 if (IS_HASWELL(dev
))
3284 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3285 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3286 else if (IS_IVYBRIDGE(dev
))
3287 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
3288 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3291 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3295 * intel_update_watermarks - update FIFO watermark values based on current modes
3297 * Calculate watermark values for the various WM regs based on current mode
3298 * and plane configuration.
3300 * There are several cases to deal with here:
3301 * - normal (i.e. non-self-refresh)
3302 * - self-refresh (SR) mode
3303 * - lines are large relative to FIFO size (buffer can hold up to 2)
3304 * - lines are small relative to FIFO size (buffer can hold more than 2
3305 * lines), so need to account for TLB latency
3307 * The normal calculation is:
3308 * watermark = dotclock * bytes per pixel * latency
3309 * where latency is platform & configuration dependent (we assume pessimal
3312 * The SR calculation is:
3313 * watermark = (trunc(latency/line time)+1) * surface width *
3316 * line time = htotal / dotclock
3317 * surface width = hdisplay for normal plane and 64 for cursor
3318 * and latency is assumed to be high, as above.
3320 * The final value programmed to the register should always be rounded up,
3321 * and include an extra 2 entries to account for clock crossings.
3323 * We don't use the sprite, so we can ignore that. And on Crestline we have
3324 * to set the non-SR watermarks to 8.
3326 void intel_update_watermarks(struct drm_crtc
*crtc
)
3328 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3330 if (dev_priv
->display
.update_wm
)
3331 dev_priv
->display
.update_wm(crtc
);
3334 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
3335 struct drm_crtc
*crtc
,
3336 uint32_t sprite_width
, int pixel_size
,
3337 bool enabled
, bool scaled
)
3339 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
3341 if (dev_priv
->display
.update_sprite_wm
)
3342 dev_priv
->display
.update_sprite_wm(plane
, crtc
, sprite_width
,
3343 pixel_size
, enabled
, scaled
);
3346 static struct drm_i915_gem_object
*
3347 intel_alloc_context_page(struct drm_device
*dev
)
3349 struct drm_i915_gem_object
*ctx
;
3352 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3354 ctx
= i915_gem_alloc_object(dev
, 4096);
3356 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3360 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, true, false);
3362 DRM_ERROR("failed to pin power context: %d\n", ret
);
3366 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
3368 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
3375 i915_gem_object_unpin(ctx
);
3377 drm_gem_object_unreference(&ctx
->base
);
3382 * Lock protecting IPS related data structures
3384 DEFINE_SPINLOCK(mchdev_lock
);
3386 /* Global for IPS driver to get at the current i915 device. Protected by
3388 static struct drm_i915_private
*i915_mch_dev
;
3390 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3395 assert_spin_locked(&mchdev_lock
);
3397 rgvswctl
= I915_READ16(MEMSWCTL
);
3398 if (rgvswctl
& MEMCTL_CMD_STS
) {
3399 DRM_DEBUG("gpu busy, RCS change rejected\n");
3400 return false; /* still busy with another command */
3403 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3404 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3405 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3406 POSTING_READ16(MEMSWCTL
);
3408 rgvswctl
|= MEMCTL_CMD_STS
;
3409 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3414 static void ironlake_enable_drps(struct drm_device
*dev
)
3416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3417 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3418 u8 fmax
, fmin
, fstart
, vstart
;
3420 spin_lock_irq(&mchdev_lock
);
3422 /* Enable temp reporting */
3423 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3424 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3426 /* 100ms RC evaluation intervals */
3427 I915_WRITE(RCUPEI
, 100000);
3428 I915_WRITE(RCDNEI
, 100000);
3430 /* Set max/min thresholds to 90ms and 80ms respectively */
3431 I915_WRITE(RCBMAXAVG
, 90000);
3432 I915_WRITE(RCBMINAVG
, 80000);
3434 I915_WRITE(MEMIHYST
, 1);
3436 /* Set up min, max, and cur for interrupt handling */
3437 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3438 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3439 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3440 MEMMODE_FSTART_SHIFT
;
3442 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3445 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3446 dev_priv
->ips
.fstart
= fstart
;
3448 dev_priv
->ips
.max_delay
= fstart
;
3449 dev_priv
->ips
.min_delay
= fmin
;
3450 dev_priv
->ips
.cur_delay
= fstart
;
3452 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3453 fmax
, fmin
, fstart
);
3455 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3458 * Interrupts will be enabled in ironlake_irq_postinstall
3461 I915_WRITE(VIDSTART
, vstart
);
3462 POSTING_READ(VIDSTART
);
3464 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3465 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3467 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3468 DRM_ERROR("stuck trying to change perf mode\n");
3471 ironlake_set_drps(dev
, fstart
);
3473 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3475 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3476 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3477 getrawmonotonic(&dev_priv
->ips
.last_time2
);
3479 spin_unlock_irq(&mchdev_lock
);
3482 static void ironlake_disable_drps(struct drm_device
*dev
)
3484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 spin_lock_irq(&mchdev_lock
);
3489 rgvswctl
= I915_READ16(MEMSWCTL
);
3491 /* Ack interrupts, disable EFC interrupt */
3492 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3493 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3494 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3495 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3496 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3498 /* Go back to the starting frequency */
3499 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3501 rgvswctl
|= MEMCTL_CMD_STS
;
3502 I915_WRITE(MEMSWCTL
, rgvswctl
);
3505 spin_unlock_irq(&mchdev_lock
);
3508 /* There's a funny hw issue where the hw returns all 0 when reading from
3509 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3510 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3511 * all limits and the gpu stuck at whatever frequency it is at atm).
3513 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3517 /* Only set the down limit when we've reached the lowest level to avoid
3518 * getting more interrupts, otherwise leave this clear. This prevents a
3519 * race in the hw when coming out of rc6: There's a tiny window where
3520 * the hw runs at the minimal clock before selecting the desired
3521 * frequency, if the down threshold expires in that window we will not
3522 * receive a down interrupt. */
3523 limits
= dev_priv
->rps
.max_delay
<< 24;
3524 if (val
<= dev_priv
->rps
.min_delay
)
3525 limits
|= dev_priv
->rps
.min_delay
<< 16;
3530 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3534 new_power
= dev_priv
->rps
.power
;
3535 switch (dev_priv
->rps
.power
) {
3537 if (val
> dev_priv
->rps
.rpe_delay
+ 1 && val
> dev_priv
->rps
.cur_delay
)
3538 new_power
= BETWEEN
;
3542 if (val
<= dev_priv
->rps
.rpe_delay
&& val
< dev_priv
->rps
.cur_delay
)
3543 new_power
= LOW_POWER
;
3544 else if (val
>= dev_priv
->rps
.rp0_delay
&& val
> dev_priv
->rps
.cur_delay
)
3545 new_power
= HIGH_POWER
;
3549 if (val
< (dev_priv
->rps
.rp1_delay
+ dev_priv
->rps
.rp0_delay
) >> 1 && val
< dev_priv
->rps
.cur_delay
)
3550 new_power
= BETWEEN
;
3553 /* Max/min bins are special */
3554 if (val
== dev_priv
->rps
.min_delay
)
3555 new_power
= LOW_POWER
;
3556 if (val
== dev_priv
->rps
.max_delay
)
3557 new_power
= HIGH_POWER
;
3558 if (new_power
== dev_priv
->rps
.power
)
3561 /* Note the units here are not exactly 1us, but 1280ns. */
3562 switch (new_power
) {
3564 /* Upclock if more than 95% busy over 16ms */
3565 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3566 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3568 /* Downclock if less than 85% busy over 32ms */
3569 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3570 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3572 I915_WRITE(GEN6_RP_CONTROL
,
3573 GEN6_RP_MEDIA_TURBO
|
3574 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3575 GEN6_RP_MEDIA_IS_GFX
|
3577 GEN6_RP_UP_BUSY_AVG
|
3578 GEN6_RP_DOWN_IDLE_AVG
);
3582 /* Upclock if more than 90% busy over 13ms */
3583 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3584 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3586 /* Downclock if less than 75% busy over 32ms */
3587 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3588 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3590 I915_WRITE(GEN6_RP_CONTROL
,
3591 GEN6_RP_MEDIA_TURBO
|
3592 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3593 GEN6_RP_MEDIA_IS_GFX
|
3595 GEN6_RP_UP_BUSY_AVG
|
3596 GEN6_RP_DOWN_IDLE_AVG
);
3600 /* Upclock if more than 85% busy over 10ms */
3601 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3602 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3604 /* Downclock if less than 60% busy over 32ms */
3605 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3606 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3608 I915_WRITE(GEN6_RP_CONTROL
,
3609 GEN6_RP_MEDIA_TURBO
|
3610 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3611 GEN6_RP_MEDIA_IS_GFX
|
3613 GEN6_RP_UP_BUSY_AVG
|
3614 GEN6_RP_DOWN_IDLE_AVG
);
3618 dev_priv
->rps
.power
= new_power
;
3619 dev_priv
->rps
.last_adj
= 0;
3622 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3626 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3627 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3628 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3630 if (val
== dev_priv
->rps
.cur_delay
)
3633 gen6_set_rps_thresholds(dev_priv
, val
);
3635 if (IS_HASWELL(dev
))
3636 I915_WRITE(GEN6_RPNSWREQ
,
3637 HSW_FREQUENCY(val
));
3639 I915_WRITE(GEN6_RPNSWREQ
,
3640 GEN6_FREQUENCY(val
) |
3642 GEN6_AGGRESSIVE_TURBO
);
3644 /* Make sure we continue to get interrupts
3645 * until we hit the minimum or maximum frequencies.
3647 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3648 gen6_rps_limits(dev_priv
, val
));
3650 POSTING_READ(GEN6_RPNSWREQ
);
3652 dev_priv
->rps
.cur_delay
= val
;
3654 trace_intel_gpu_freq_change(val
* 50);
3657 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3659 struct drm_device
*dev
= dev_priv
->dev
;
3661 mutex_lock(&dev_priv
->rps
.hw_lock
);
3662 if (dev_priv
->rps
.enabled
) {
3663 if (IS_VALLEYVIEW(dev
))
3664 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3666 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3667 dev_priv
->rps
.last_adj
= 0;
3669 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3672 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3674 struct drm_device
*dev
= dev_priv
->dev
;
3676 mutex_lock(&dev_priv
->rps
.hw_lock
);
3677 if (dev_priv
->rps
.enabled
) {
3678 if (IS_VALLEYVIEW(dev
))
3679 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_delay
);
3681 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_delay
);
3682 dev_priv
->rps
.last_adj
= 0;
3684 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3687 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3691 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3692 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3693 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3695 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3696 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_delay
),
3697 dev_priv
->rps
.cur_delay
,
3698 vlv_gpu_freq(dev_priv
, val
), val
);
3700 if (val
== dev_priv
->rps
.cur_delay
)
3703 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3705 dev_priv
->rps
.cur_delay
= val
;
3707 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
, val
));
3710 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3714 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3715 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) & ~GEN6_PM_RPS_EVENTS
);
3716 /* Complete PM interrupt masking here doesn't race with the rps work
3717 * item again unmasking PM interrupts because that is using a different
3718 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3719 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3721 spin_lock_irq(&dev_priv
->irq_lock
);
3722 dev_priv
->rps
.pm_iir
= 0;
3723 spin_unlock_irq(&dev_priv
->irq_lock
);
3725 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3728 static void gen6_disable_rps(struct drm_device
*dev
)
3730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3732 I915_WRITE(GEN6_RC_CONTROL
, 0);
3733 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3735 gen6_disable_rps_interrupts(dev
);
3738 static void valleyview_disable_rps(struct drm_device
*dev
)
3740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 I915_WRITE(GEN6_RC_CONTROL
, 0);
3744 gen6_disable_rps_interrupts(dev
);
3746 if (dev_priv
->vlv_pctx
) {
3747 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3748 dev_priv
->vlv_pctx
= NULL
;
3752 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3755 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3757 if (IS_HASWELL(dev
))
3758 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3760 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3761 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3762 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3763 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3766 int intel_enable_rc6(const struct drm_device
*dev
)
3768 /* No RC6 before Ironlake */
3769 if (INTEL_INFO(dev
)->gen
< 5)
3772 /* Respect the kernel parameter if it is set */
3773 if (i915_enable_rc6
>= 0)
3774 return i915_enable_rc6
;
3776 /* Disable RC6 on Ironlake */
3777 if (INTEL_INFO(dev
)->gen
== 5)
3780 if (IS_HASWELL(dev
))
3781 return INTEL_RC6_ENABLE
;
3783 /* snb/ivb have more than one rc6 state. */
3784 if (INTEL_INFO(dev
)->gen
== 6)
3785 return INTEL_RC6_ENABLE
;
3787 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3790 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3795 spin_lock_irq(&dev_priv
->irq_lock
);
3796 WARN_ON(dev_priv
->rps
.pm_iir
);
3797 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
3798 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3799 spin_unlock_irq(&dev_priv
->irq_lock
);
3801 /* only unmask PM interrupts we need. Mask all others. */
3802 enabled_intrs
= GEN6_PM_RPS_EVENTS
;
3804 /* IVB and SNB hard hangs on looping batchbuffer
3805 * if GEN6_PM_UP_EI_EXPIRED is masked.
3807 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
3808 enabled_intrs
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3810 I915_WRITE(GEN6_PMINTRMSK
, ~enabled_intrs
);
3813 static void gen8_enable_rps(struct drm_device
*dev
)
3815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3816 struct intel_ring_buffer
*ring
;
3817 uint32_t rc6_mask
= 0, rp_state_cap
;
3820 /* 1a: Software RC state - RC0 */
3821 I915_WRITE(GEN6_RC_STATE
, 0);
3823 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3824 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3825 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3827 /* 2a: Disable RC states. */
3828 I915_WRITE(GEN6_RC_CONTROL
, 0);
3830 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3832 /* 2b: Program RC6 thresholds.*/
3833 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3834 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3835 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3836 for_each_ring(ring
, dev_priv
, unused
)
3837 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3838 I915_WRITE(GEN6_RC_SLEEP
, 0);
3839 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3842 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3843 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3844 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
3845 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3846 GEN6_RC_CTL_EI_MODE(1) |
3849 /* 4 Program defaults and thresholds for RPS*/
3850 I915_WRITE(GEN6_RPNSWREQ
, HSW_FREQUENCY(10)); /* Request 500 MHz */
3851 I915_WRITE(GEN6_RC_VIDEO_FREQ
, HSW_FREQUENCY(12)); /* Request 600 MHz */
3852 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3853 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3855 /* Docs recommend 900MHz, and 300 MHz respectively */
3856 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3857 dev_priv
->rps
.max_delay
<< 24 |
3858 dev_priv
->rps
.min_delay
<< 16);
3860 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3861 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3862 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3863 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3865 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3868 I915_WRITE(GEN6_RP_CONTROL
,
3869 GEN6_RP_MEDIA_TURBO
|
3870 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3871 GEN6_RP_MEDIA_IS_GFX
|
3873 GEN6_RP_UP_BUSY_AVG
|
3874 GEN6_RP_DOWN_IDLE_AVG
);
3876 /* 6: Ring frequency + overclocking (our driver does this later */
3878 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3880 gen6_enable_rps_interrupts(dev
);
3882 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3885 static void gen6_enable_rps(struct drm_device
*dev
)
3887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3888 struct intel_ring_buffer
*ring
;
3891 u32 rc6vids
, pcu_mbox
, rc6_mask
= 0;
3896 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3898 /* Here begins a magic sequence of register writes to enable
3899 * auto-downclocking.
3901 * Perhaps there might be some value in exposing these to
3904 I915_WRITE(GEN6_RC_STATE
, 0);
3906 /* Clear the DBG now so we don't confuse earlier errors */
3907 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3908 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3909 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3912 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3914 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3915 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3917 /* In units of 50MHz */
3918 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
3919 dev_priv
->rps
.min_delay
= (rp_state_cap
>> 16) & 0xff;
3920 dev_priv
->rps
.rp1_delay
= (rp_state_cap
>> 8) & 0xff;
3921 dev_priv
->rps
.rp0_delay
= (rp_state_cap
>> 0) & 0xff;
3922 dev_priv
->rps
.rpe_delay
= dev_priv
->rps
.rp1_delay
;
3923 dev_priv
->rps
.cur_delay
= 0;
3925 /* disable the counters and set deterministic thresholds */
3926 I915_WRITE(GEN6_RC_CONTROL
, 0);
3928 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3929 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3930 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3931 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3932 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3934 for_each_ring(ring
, dev_priv
, i
)
3935 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3937 I915_WRITE(GEN6_RC_SLEEP
, 0);
3938 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3939 if (IS_IVYBRIDGE(dev
))
3940 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3942 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3943 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3944 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3946 /* Check if we are enabling RC6 */
3947 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3948 if (rc6_mode
& INTEL_RC6_ENABLE
)
3949 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3951 /* We don't use those on Haswell */
3952 if (!IS_HASWELL(dev
)) {
3953 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3954 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3956 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3957 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3960 intel_print_rc6_info(dev
, rc6_mask
);
3962 I915_WRITE(GEN6_RC_CONTROL
,
3964 GEN6_RC_CTL_EI_MODE(1) |
3965 GEN6_RC_CTL_HW_ENABLE
);
3967 /* Power down if completely idle for over 50ms */
3968 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3969 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3971 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3974 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3975 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3976 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3977 (dev_priv
->rps
.max_delay
& 0xff) * 50,
3978 (pcu_mbox
& 0xff) * 50);
3979 dev_priv
->rps
.hw_max
= pcu_mbox
& 0xff;
3982 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3985 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3986 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3988 gen6_enable_rps_interrupts(dev
);
3991 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3992 if (IS_GEN6(dev
) && ret
) {
3993 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3994 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3995 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3996 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3997 rc6vids
&= 0xffff00;
3998 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3999 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
4001 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4004 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4007 void gen6_update_ring_freq(struct drm_device
*dev
)
4009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4011 unsigned int gpu_freq
;
4012 unsigned int max_ia_freq
, min_ring_freq
;
4013 int scaling_factor
= 180;
4014 struct cpufreq_policy
*policy
;
4016 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4018 policy
= cpufreq_cpu_get(0);
4020 max_ia_freq
= policy
->cpuinfo
.max_freq
;
4021 cpufreq_cpu_put(policy
);
4024 * Default to measured freq if none found, PCU will ensure we
4027 max_ia_freq
= tsc_khz
;
4030 /* Convert from kHz to MHz */
4031 max_ia_freq
/= 1000;
4033 min_ring_freq
= I915_READ(DCLK
) & 0xf;
4034 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4035 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
4038 * For each potential GPU frequency, load a ring frequency we'd like
4039 * to use for memory access. We do this by specifying the IA frequency
4040 * the PCU should use as a reference to determine the ring frequency.
4042 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
4044 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
4045 unsigned int ia_freq
= 0, ring_freq
= 0;
4047 if (INTEL_INFO(dev
)->gen
>= 8) {
4048 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4049 ring_freq
= max(min_ring_freq
, gpu_freq
);
4050 } else if (IS_HASWELL(dev
)) {
4051 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4052 ring_freq
= max(min_ring_freq
, ring_freq
);
4053 /* leave ia_freq as the default, chosen by cpufreq */
4055 /* On older processors, there is no separate ring
4056 * clock domain, so in order to boost the bandwidth
4057 * of the ring, we need to upclock the CPU (ia_freq).
4059 * For GPU frequencies less than 750MHz,
4060 * just use the lowest ring freq.
4062 if (gpu_freq
< min_freq
)
4065 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4066 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4069 sandybridge_pcode_write(dev_priv
,
4070 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4071 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4072 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4077 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4081 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4083 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
4085 rp0
= min_t(u32
, rp0
, 0xea);
4090 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4094 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
4095 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
4096 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
4097 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
4102 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4104 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
4107 static void valleyview_setup_pctx(struct drm_device
*dev
)
4109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4110 struct drm_i915_gem_object
*pctx
;
4111 unsigned long pctx_paddr
;
4113 int pctx_size
= 24*1024;
4115 pcbr
= I915_READ(VLV_PCBR
);
4117 /* BIOS set it up already, grab the pre-alloc'd space */
4120 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4121 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4123 I915_GTT_OFFSET_NONE
,
4129 * From the Gunit register HAS:
4130 * The Gfx driver is expected to program this register and ensure
4131 * proper allocation within Gfx stolen memory. For example, this
4132 * register should be programmed such than the PCBR range does not
4133 * overlap with other ranges, such as the frame buffer, protected
4134 * memory, or any other relevant ranges.
4136 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4138 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4142 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4143 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4146 dev_priv
->vlv_pctx
= pctx
;
4149 static void valleyview_enable_rps(struct drm_device
*dev
)
4151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4152 struct intel_ring_buffer
*ring
;
4153 u32 gtfifodbg
, val
, rc6_mode
= 0;
4156 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4158 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4159 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4161 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4164 valleyview_setup_pctx(dev
);
4166 /* If VLV, Forcewake all wells, else re-direct to regular path */
4167 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4169 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4170 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4171 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4172 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4174 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4176 I915_WRITE(GEN6_RP_CONTROL
,
4177 GEN6_RP_MEDIA_TURBO
|
4178 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4179 GEN6_RP_MEDIA_IS_GFX
|
4181 GEN6_RP_UP_BUSY_AVG
|
4182 GEN6_RP_DOWN_IDLE_CONT
);
4184 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4185 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4186 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4188 for_each_ring(ring
, dev_priv
, i
)
4189 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4191 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4193 /* allows RC6 residency counter to work */
4194 I915_WRITE(VLV_COUNTER_CONTROL
,
4195 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4196 VLV_MEDIA_RC6_COUNT_EN
|
4197 VLV_RENDER_RC6_COUNT_EN
));
4198 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4199 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4201 intel_print_rc6_info(dev
, rc6_mode
);
4203 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4205 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4207 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4208 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4210 dev_priv
->rps
.cur_delay
= (val
>> 8) & 0xff;
4211 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4212 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_delay
),
4213 dev_priv
->rps
.cur_delay
);
4215 dev_priv
->rps
.max_delay
= valleyview_rps_max_freq(dev_priv
);
4216 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
;
4217 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4218 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_delay
),
4219 dev_priv
->rps
.max_delay
);
4221 dev_priv
->rps
.rpe_delay
= valleyview_rps_rpe_freq(dev_priv
);
4222 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4223 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rpe_delay
),
4224 dev_priv
->rps
.rpe_delay
);
4226 dev_priv
->rps
.min_delay
= valleyview_rps_min_freq(dev_priv
);
4227 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4228 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_delay
),
4229 dev_priv
->rps
.min_delay
);
4231 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4232 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rpe_delay
),
4233 dev_priv
->rps
.rpe_delay
);
4235 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.rpe_delay
);
4237 gen6_enable_rps_interrupts(dev
);
4239 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4242 void ironlake_teardown_rc6(struct drm_device
*dev
)
4244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4246 if (dev_priv
->ips
.renderctx
) {
4247 i915_gem_object_unpin(dev_priv
->ips
.renderctx
);
4248 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4249 dev_priv
->ips
.renderctx
= NULL
;
4252 if (dev_priv
->ips
.pwrctx
) {
4253 i915_gem_object_unpin(dev_priv
->ips
.pwrctx
);
4254 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4255 dev_priv
->ips
.pwrctx
= NULL
;
4259 static void ironlake_disable_rc6(struct drm_device
*dev
)
4261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4263 if (I915_READ(PWRCTXA
)) {
4264 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4265 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4266 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4269 I915_WRITE(PWRCTXA
, 0);
4270 POSTING_READ(PWRCTXA
);
4272 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4273 POSTING_READ(RSTDBYCTL
);
4277 static int ironlake_setup_rc6(struct drm_device
*dev
)
4279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4281 if (dev_priv
->ips
.renderctx
== NULL
)
4282 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4283 if (!dev_priv
->ips
.renderctx
)
4286 if (dev_priv
->ips
.pwrctx
== NULL
)
4287 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4288 if (!dev_priv
->ips
.pwrctx
) {
4289 ironlake_teardown_rc6(dev
);
4296 static void ironlake_enable_rc6(struct drm_device
*dev
)
4298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4299 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
4300 bool was_interruptible
;
4303 /* rc6 disabled by default due to repeated reports of hanging during
4306 if (!intel_enable_rc6(dev
))
4309 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4311 ret
= ironlake_setup_rc6(dev
);
4315 was_interruptible
= dev_priv
->mm
.interruptible
;
4316 dev_priv
->mm
.interruptible
= false;
4319 * GPU can automatically power down the render unit if given a page
4322 ret
= intel_ring_begin(ring
, 6);
4324 ironlake_teardown_rc6(dev
);
4325 dev_priv
->mm
.interruptible
= was_interruptible
;
4329 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4330 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4331 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4333 MI_SAVE_EXT_STATE_EN
|
4334 MI_RESTORE_EXT_STATE_EN
|
4335 MI_RESTORE_INHIBIT
);
4336 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4337 intel_ring_emit(ring
, MI_NOOP
);
4338 intel_ring_emit(ring
, MI_FLUSH
);
4339 intel_ring_advance(ring
);
4342 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4343 * does an implicit flush, combined with MI_FLUSH above, it should be
4344 * safe to assume that renderctx is valid
4346 ret
= intel_ring_idle(ring
);
4347 dev_priv
->mm
.interruptible
= was_interruptible
;
4349 DRM_ERROR("failed to enable ironlake power savings\n");
4350 ironlake_teardown_rc6(dev
);
4354 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4355 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4357 intel_print_rc6_info(dev
, INTEL_RC6_ENABLE
);
4360 static unsigned long intel_pxfreq(u32 vidfreq
)
4363 int div
= (vidfreq
& 0x3f0000) >> 16;
4364 int post
= (vidfreq
& 0x3000) >> 12;
4365 int pre
= (vidfreq
& 0x7);
4370 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4375 static const struct cparams
{
4381 { 1, 1333, 301, 28664 },
4382 { 1, 1066, 294, 24460 },
4383 { 1, 800, 294, 25192 },
4384 { 0, 1333, 276, 27605 },
4385 { 0, 1066, 276, 27605 },
4386 { 0, 800, 231, 23784 },
4389 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4391 u64 total_count
, diff
, ret
;
4392 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4393 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4396 assert_spin_locked(&mchdev_lock
);
4398 diff1
= now
- dev_priv
->ips
.last_time1
;
4400 /* Prevent division-by-zero if we are asking too fast.
4401 * Also, we don't get interesting results if we are polling
4402 * faster than once in 10ms, so just return the saved value
4406 return dev_priv
->ips
.chipset_power
;
4408 count1
= I915_READ(DMIEC
);
4409 count2
= I915_READ(DDREC
);
4410 count3
= I915_READ(CSIEC
);
4412 total_count
= count1
+ count2
+ count3
;
4414 /* FIXME: handle per-counter overflow */
4415 if (total_count
< dev_priv
->ips
.last_count1
) {
4416 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4417 diff
+= total_count
;
4419 diff
= total_count
- dev_priv
->ips
.last_count1
;
4422 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4423 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4424 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4431 diff
= div_u64(diff
, diff1
);
4432 ret
= ((m
* diff
) + c
);
4433 ret
= div_u64(ret
, 10);
4435 dev_priv
->ips
.last_count1
= total_count
;
4436 dev_priv
->ips
.last_time1
= now
;
4438 dev_priv
->ips
.chipset_power
= ret
;
4443 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4447 if (dev_priv
->info
->gen
!= 5)
4450 spin_lock_irq(&mchdev_lock
);
4452 val
= __i915_chipset_val(dev_priv
);
4454 spin_unlock_irq(&mchdev_lock
);
4459 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4461 unsigned long m
, x
, b
;
4464 tsfs
= I915_READ(TSFS
);
4466 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4467 x
= I915_READ8(TR1
);
4469 b
= tsfs
& TSFS_INTR_MASK
;
4471 return ((m
* x
) / 127) - b
;
4474 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4476 static const struct v_table
{
4477 u16 vd
; /* in .1 mil */
4478 u16 vm
; /* in .1 mil */
4609 if (dev_priv
->info
->is_mobile
)
4610 return v_table
[pxvid
].vm
;
4612 return v_table
[pxvid
].vd
;
4615 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4617 struct timespec now
, diff1
;
4619 unsigned long diffms
;
4622 assert_spin_locked(&mchdev_lock
);
4624 getrawmonotonic(&now
);
4625 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4627 /* Don't divide by 0 */
4628 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4632 count
= I915_READ(GFXEC
);
4634 if (count
< dev_priv
->ips
.last_count2
) {
4635 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4638 diff
= count
- dev_priv
->ips
.last_count2
;
4641 dev_priv
->ips
.last_count2
= count
;
4642 dev_priv
->ips
.last_time2
= now
;
4644 /* More magic constants... */
4646 diff
= div_u64(diff
, diffms
* 10);
4647 dev_priv
->ips
.gfx_power
= diff
;
4650 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4652 if (dev_priv
->info
->gen
!= 5)
4655 spin_lock_irq(&mchdev_lock
);
4657 __i915_update_gfx_val(dev_priv
);
4659 spin_unlock_irq(&mchdev_lock
);
4662 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4664 unsigned long t
, corr
, state1
, corr2
, state2
;
4667 assert_spin_locked(&mchdev_lock
);
4669 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
4670 pxvid
= (pxvid
>> 24) & 0x7f;
4671 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4675 t
= i915_mch_val(dev_priv
);
4677 /* Revel in the empirically derived constants */
4679 /* Correction factor in 1/100000 units */
4681 corr
= ((t
* 2349) + 135940);
4683 corr
= ((t
* 964) + 29317);
4685 corr
= ((t
* 301) + 1004);
4687 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4689 corr2
= (corr
* dev_priv
->ips
.corr
);
4691 state2
= (corr2
* state1
) / 10000;
4692 state2
/= 100; /* convert to mW */
4694 __i915_update_gfx_val(dev_priv
);
4696 return dev_priv
->ips
.gfx_power
+ state2
;
4699 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4703 if (dev_priv
->info
->gen
!= 5)
4706 spin_lock_irq(&mchdev_lock
);
4708 val
= __i915_gfx_val(dev_priv
);
4710 spin_unlock_irq(&mchdev_lock
);
4716 * i915_read_mch_val - return value for IPS use
4718 * Calculate and return a value for the IPS driver to use when deciding whether
4719 * we have thermal and power headroom to increase CPU or GPU power budget.
4721 unsigned long i915_read_mch_val(void)
4723 struct drm_i915_private
*dev_priv
;
4724 unsigned long chipset_val
, graphics_val
, ret
= 0;
4726 spin_lock_irq(&mchdev_lock
);
4729 dev_priv
= i915_mch_dev
;
4731 chipset_val
= __i915_chipset_val(dev_priv
);
4732 graphics_val
= __i915_gfx_val(dev_priv
);
4734 ret
= chipset_val
+ graphics_val
;
4737 spin_unlock_irq(&mchdev_lock
);
4741 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4744 * i915_gpu_raise - raise GPU frequency limit
4746 * Raise the limit; IPS indicates we have thermal headroom.
4748 bool i915_gpu_raise(void)
4750 struct drm_i915_private
*dev_priv
;
4753 spin_lock_irq(&mchdev_lock
);
4754 if (!i915_mch_dev
) {
4758 dev_priv
= i915_mch_dev
;
4760 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4761 dev_priv
->ips
.max_delay
--;
4764 spin_unlock_irq(&mchdev_lock
);
4768 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4771 * i915_gpu_lower - lower GPU frequency limit
4773 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4774 * frequency maximum.
4776 bool i915_gpu_lower(void)
4778 struct drm_i915_private
*dev_priv
;
4781 spin_lock_irq(&mchdev_lock
);
4782 if (!i915_mch_dev
) {
4786 dev_priv
= i915_mch_dev
;
4788 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4789 dev_priv
->ips
.max_delay
++;
4792 spin_unlock_irq(&mchdev_lock
);
4796 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4799 * i915_gpu_busy - indicate GPU business to IPS
4801 * Tell the IPS driver whether or not the GPU is busy.
4803 bool i915_gpu_busy(void)
4805 struct drm_i915_private
*dev_priv
;
4806 struct intel_ring_buffer
*ring
;
4810 spin_lock_irq(&mchdev_lock
);
4813 dev_priv
= i915_mch_dev
;
4815 for_each_ring(ring
, dev_priv
, i
)
4816 ret
|= !list_empty(&ring
->request_list
);
4819 spin_unlock_irq(&mchdev_lock
);
4823 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4826 * i915_gpu_turbo_disable - disable graphics turbo
4828 * Disable graphics turbo by resetting the max frequency and setting the
4829 * current frequency to the default.
4831 bool i915_gpu_turbo_disable(void)
4833 struct drm_i915_private
*dev_priv
;
4836 spin_lock_irq(&mchdev_lock
);
4837 if (!i915_mch_dev
) {
4841 dev_priv
= i915_mch_dev
;
4843 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4845 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4849 spin_unlock_irq(&mchdev_lock
);
4853 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4856 * Tells the intel_ips driver that the i915 driver is now loaded, if
4857 * IPS got loaded first.
4859 * This awkward dance is so that neither module has to depend on the
4860 * other in order for IPS to do the appropriate communication of
4861 * GPU turbo limits to i915.
4864 ips_ping_for_i915_load(void)
4868 link
= symbol_get(ips_link_to_i915_driver
);
4871 symbol_put(ips_link_to_i915_driver
);
4875 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4877 /* We only register the i915 ips part with intel-ips once everything is
4878 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4879 spin_lock_irq(&mchdev_lock
);
4880 i915_mch_dev
= dev_priv
;
4881 spin_unlock_irq(&mchdev_lock
);
4883 ips_ping_for_i915_load();
4886 void intel_gpu_ips_teardown(void)
4888 spin_lock_irq(&mchdev_lock
);
4889 i915_mch_dev
= NULL
;
4890 spin_unlock_irq(&mchdev_lock
);
4892 static void intel_init_emon(struct drm_device
*dev
)
4894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4899 /* Disable to program */
4903 /* Program energy weights for various events */
4904 I915_WRITE(SDEW
, 0x15040d00);
4905 I915_WRITE(CSIEW0
, 0x007f0000);
4906 I915_WRITE(CSIEW1
, 0x1e220004);
4907 I915_WRITE(CSIEW2
, 0x04000004);
4909 for (i
= 0; i
< 5; i
++)
4910 I915_WRITE(PEW
+ (i
* 4), 0);
4911 for (i
= 0; i
< 3; i
++)
4912 I915_WRITE(DEW
+ (i
* 4), 0);
4914 /* Program P-state weights to account for frequency power adjustment */
4915 for (i
= 0; i
< 16; i
++) {
4916 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4917 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4918 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4923 val
*= (freq
/ 1000);
4925 val
/= (127*127*900);
4927 DRM_ERROR("bad pxval: %ld\n", val
);
4930 /* Render standby states get 0 weight */
4934 for (i
= 0; i
< 4; i
++) {
4935 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4936 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4937 I915_WRITE(PXW
+ (i
* 4), val
);
4940 /* Adjust magic regs to magic values (more experimental results) */
4941 I915_WRITE(OGW0
, 0);
4942 I915_WRITE(OGW1
, 0);
4943 I915_WRITE(EG0
, 0x00007f00);
4944 I915_WRITE(EG1
, 0x0000000e);
4945 I915_WRITE(EG2
, 0x000e0000);
4946 I915_WRITE(EG3
, 0x68000300);
4947 I915_WRITE(EG4
, 0x42000000);
4948 I915_WRITE(EG5
, 0x00140031);
4952 for (i
= 0; i
< 8; i
++)
4953 I915_WRITE(PXWL
+ (i
* 4), 0);
4955 /* Enable PMON + select events */
4956 I915_WRITE(ECR
, 0x80000019);
4958 lcfuse
= I915_READ(LCFUSE02
);
4960 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4963 void intel_disable_gt_powersave(struct drm_device
*dev
)
4965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4967 /* Interrupts should be disabled already to avoid re-arming. */
4968 WARN_ON(dev
->irq_enabled
);
4970 if (IS_IRONLAKE_M(dev
)) {
4971 ironlake_disable_drps(dev
);
4972 ironlake_disable_rc6(dev
);
4973 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4974 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
4975 cancel_work_sync(&dev_priv
->rps
.work
);
4976 mutex_lock(&dev_priv
->rps
.hw_lock
);
4977 if (IS_VALLEYVIEW(dev
))
4978 valleyview_disable_rps(dev
);
4980 gen6_disable_rps(dev
);
4981 dev_priv
->rps
.enabled
= false;
4982 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4986 static void intel_gen6_powersave_work(struct work_struct
*work
)
4988 struct drm_i915_private
*dev_priv
=
4989 container_of(work
, struct drm_i915_private
,
4990 rps
.delayed_resume_work
.work
);
4991 struct drm_device
*dev
= dev_priv
->dev
;
4993 mutex_lock(&dev_priv
->rps
.hw_lock
);
4995 if (IS_VALLEYVIEW(dev
)) {
4996 valleyview_enable_rps(dev
);
4997 } else if (IS_BROADWELL(dev
)) {
4998 gen8_enable_rps(dev
);
4999 gen6_update_ring_freq(dev
);
5001 gen6_enable_rps(dev
);
5002 gen6_update_ring_freq(dev
);
5004 dev_priv
->rps
.enabled
= true;
5005 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5008 void intel_enable_gt_powersave(struct drm_device
*dev
)
5010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5012 if (IS_IRONLAKE_M(dev
)) {
5013 ironlake_enable_drps(dev
);
5014 ironlake_enable_rc6(dev
);
5015 intel_init_emon(dev
);
5016 } else if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
5018 * PCU communication is slow and this doesn't need to be
5019 * done at any specific time, so do this out of our fast path
5020 * to make resume and init faster.
5022 schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5023 round_jiffies_up_relative(HZ
));
5027 static void ibx_init_clock_gating(struct drm_device
*dev
)
5029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5032 * On Ibex Peak and Cougar Point, we need to disable clock
5033 * gating for the panel power sequencer or it will fail to
5034 * start up when no ports are active.
5036 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5039 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5044 for_each_pipe(pipe
) {
5045 I915_WRITE(DSPCNTR(pipe
),
5046 I915_READ(DSPCNTR(pipe
)) |
5047 DISPPLANE_TRICKLE_FEED_DISABLE
);
5048 intel_flush_primary_plane(dev_priv
, pipe
);
5052 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5055 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5059 * WaFbcDisableDpfcClockGating:ilk
5061 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5062 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5063 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5065 I915_WRITE(PCH_3DCGDIS0
,
5066 MARIUNIT_CLOCK_GATE_DISABLE
|
5067 SVSMUNIT_CLOCK_GATE_DISABLE
);
5068 I915_WRITE(PCH_3DCGDIS1
,
5069 VFMUNIT_CLOCK_GATE_DISABLE
);
5072 * According to the spec the following bits should be set in
5073 * order to enable memory self-refresh
5074 * The bit 22/21 of 0x42004
5075 * The bit 5 of 0x42020
5076 * The bit 15 of 0x45000
5078 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5079 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5080 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5081 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5082 I915_WRITE(DISP_ARB_CTL
,
5083 (I915_READ(DISP_ARB_CTL
) |
5085 I915_WRITE(WM3_LP_ILK
, 0);
5086 I915_WRITE(WM2_LP_ILK
, 0);
5087 I915_WRITE(WM1_LP_ILK
, 0);
5090 * Based on the document from hardware guys the following bits
5091 * should be set unconditionally in order to enable FBC.
5092 * The bit 22 of 0x42000
5093 * The bit 22 of 0x42004
5094 * The bit 7,8,9 of 0x42020.
5096 if (IS_IRONLAKE_M(dev
)) {
5097 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5098 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5099 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5101 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5102 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5106 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5108 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5109 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5110 ILK_ELPIN_409_SELECT
);
5111 I915_WRITE(_3D_CHICKEN2
,
5112 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5113 _3D_CHICKEN2_WM_READ_PIPELINED
);
5115 /* WaDisableRenderCachePipelinedFlush:ilk */
5116 I915_WRITE(CACHE_MODE_0
,
5117 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5119 g4x_disable_trickle_feed(dev
);
5121 ibx_init_clock_gating(dev
);
5124 static void cpt_init_clock_gating(struct drm_device
*dev
)
5126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5131 * On Ibex Peak and Cougar Point, we need to disable clock
5132 * gating for the panel power sequencer or it will fail to
5133 * start up when no ports are active.
5135 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5136 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5137 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5138 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5139 DPLS_EDP_PPS_FIX_DIS
);
5140 /* The below fixes the weird display corruption, a few pixels shifted
5141 * downward, on (only) LVDS of some HP laptops with IVY.
5143 for_each_pipe(pipe
) {
5144 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5145 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5146 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5147 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5148 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5149 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5150 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5151 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5152 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5154 /* WADP0ClockGatingDisable */
5155 for_each_pipe(pipe
) {
5156 I915_WRITE(TRANS_CHICKEN1(pipe
),
5157 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5161 static void gen6_check_mch_setup(struct drm_device
*dev
)
5163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5166 tmp
= I915_READ(MCH_SSKPD
);
5167 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
5168 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
5169 DRM_INFO("This can cause pipe underruns and display issues.\n");
5170 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5174 static void gen6_init_clock_gating(struct drm_device
*dev
)
5176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5177 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5179 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5181 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5182 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5183 ILK_ELPIN_409_SELECT
);
5185 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5186 I915_WRITE(_3D_CHICKEN
,
5187 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5189 /* WaSetupGtModeTdRowDispatch:snb */
5190 if (IS_SNB_GT1(dev
))
5191 I915_WRITE(GEN6_GT_MODE
,
5192 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5194 I915_WRITE(WM3_LP_ILK
, 0);
5195 I915_WRITE(WM2_LP_ILK
, 0);
5196 I915_WRITE(WM1_LP_ILK
, 0);
5198 I915_WRITE(CACHE_MODE_0
,
5199 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5201 I915_WRITE(GEN6_UCGCTL1
,
5202 I915_READ(GEN6_UCGCTL1
) |
5203 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5204 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5206 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5207 * gating disable must be set. Failure to set it results in
5208 * flickering pixels due to Z write ordering failures after
5209 * some amount of runtime in the Mesa "fire" demo, and Unigine
5210 * Sanctuary and Tropics, and apparently anything else with
5211 * alpha test or pixel discard.
5213 * According to the spec, bit 11 (RCCUNIT) must also be set,
5214 * but we didn't debug actual testcases to find it out.
5216 * Also apply WaDisableVDSUnitClockGating:snb and
5217 * WaDisableRCPBUnitClockGating:snb.
5219 I915_WRITE(GEN6_UCGCTL2
,
5220 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
5221 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5222 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5224 /* Bspec says we need to always set all mask bits. */
5225 I915_WRITE(_3D_CHICKEN3
, (0xFFFF << 16) |
5226 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
);
5229 * According to the spec the following bits should be
5230 * set in order to enable memory self-refresh and fbc:
5231 * The bit21 and bit22 of 0x42000
5232 * The bit21 and bit22 of 0x42004
5233 * The bit5 and bit7 of 0x42020
5234 * The bit14 of 0x70180
5235 * The bit14 of 0x71180
5237 * WaFbcAsynchFlipDisableFbcQueue:snb
5239 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5240 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5241 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5242 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5243 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5244 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5245 I915_WRITE(ILK_DSPCLK_GATE_D
,
5246 I915_READ(ILK_DSPCLK_GATE_D
) |
5247 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5248 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5250 g4x_disable_trickle_feed(dev
);
5252 /* The default value should be 0x200 according to docs, but the two
5253 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5254 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_DISABLE(0xffff));
5255 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI
));
5257 cpt_init_clock_gating(dev
);
5259 gen6_check_mch_setup(dev
);
5262 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5264 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5266 reg
&= ~GEN7_FF_SCHED_MASK
;
5267 reg
|= GEN7_FF_TS_SCHED_HW
;
5268 reg
|= GEN7_FF_VS_SCHED_HW
;
5269 reg
|= GEN7_FF_DS_SCHED_HW
;
5271 if (IS_HASWELL(dev_priv
->dev
))
5272 reg
&= ~GEN7_FF_VS_REF_CNT_FFME
;
5274 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5277 static void lpt_init_clock_gating(struct drm_device
*dev
)
5279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5282 * TODO: this bit should only be enabled when really needed, then
5283 * disabled when not needed anymore in order to save power.
5285 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5286 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5287 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5288 PCH_LP_PARTITION_LEVEL_DISABLE
);
5290 /* WADPOClockGatingDisable:hsw */
5291 I915_WRITE(_TRANSA_CHICKEN1
,
5292 I915_READ(_TRANSA_CHICKEN1
) |
5293 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5296 static void lpt_suspend_hw(struct drm_device
*dev
)
5298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5300 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5301 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5303 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5304 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5308 static void gen8_init_clock_gating(struct drm_device
*dev
)
5310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5313 I915_WRITE(WM3_LP_ILK
, 0);
5314 I915_WRITE(WM2_LP_ILK
, 0);
5315 I915_WRITE(WM1_LP_ILK
, 0);
5317 /* FIXME(BDW): Check all the w/a, some might only apply to
5318 * pre-production hw. */
5320 WARN(!i915_preliminary_hw_support
,
5321 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5322 I915_WRITE(HALF_SLICE_CHICKEN3
,
5323 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5324 I915_WRITE(HALF_SLICE_CHICKEN3
,
5325 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5326 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5328 I915_WRITE(_3D_CHICKEN3
,
5329 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5331 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5332 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5334 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5335 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5337 /* WaSwitchSolVfFArbitrationPriority:bdw */
5338 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5340 /* WaPsrDPAMaskVBlankInSRD:bdw */
5341 I915_WRITE(CHICKEN_PAR1_1
,
5342 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5344 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5346 I915_WRITE(CHICKEN_PIPESL_1(i
),
5347 I915_READ(CHICKEN_PIPESL_1(i
) |
5348 DPRS_MASK_VBLANK_SRD
));
5351 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5352 * workaround for for a possible hang in the unlikely event a TLB
5353 * invalidation occurs during a PSD flush.
5355 I915_WRITE(HDC_CHICKEN0
,
5356 I915_READ(HDC_CHICKEN0
) |
5357 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT
));
5359 /* WaVSRefCountFullforceMissDisable:bdw */
5360 /* WaDSRefCountFullforceMissDisable:bdw */
5361 I915_WRITE(GEN7_FF_THREAD_MODE
,
5362 I915_READ(GEN7_FF_THREAD_MODE
) &
5363 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5366 static void haswell_init_clock_gating(struct drm_device
*dev
)
5368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5370 I915_WRITE(WM3_LP_ILK
, 0);
5371 I915_WRITE(WM2_LP_ILK
, 0);
5372 I915_WRITE(WM1_LP_ILK
, 0);
5374 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5375 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5377 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5379 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5380 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5381 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5383 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5384 I915_WRITE(GEN7_L3CNTLREG1
,
5385 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5386 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5387 GEN7_WA_L3_CHICKEN_MODE
);
5389 /* L3 caching of data atomics doesn't work -- disable it. */
5390 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5391 I915_WRITE(HSW_ROW_CHICKEN3
,
5392 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5394 /* This is required by WaCatErrorRejectionIssue:hsw */
5395 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5396 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5397 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5399 /* WaVSRefCountFullforceMissDisable:hsw */
5400 gen7_setup_fixed_func_scheduler(dev_priv
);
5402 /* WaDisable4x2SubspanOptimization:hsw */
5403 I915_WRITE(CACHE_MODE_1
,
5404 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5406 /* WaSwitchSolVfFArbitrationPriority:hsw */
5407 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5409 /* WaRsPkgCStateDisplayPMReq:hsw */
5410 I915_WRITE(CHICKEN_PAR1_1
,
5411 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5413 lpt_init_clock_gating(dev
);
5416 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5421 I915_WRITE(WM3_LP_ILK
, 0);
5422 I915_WRITE(WM2_LP_ILK
, 0);
5423 I915_WRITE(WM1_LP_ILK
, 0);
5425 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5427 /* WaDisableEarlyCull:ivb */
5428 I915_WRITE(_3D_CHICKEN3
,
5429 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5431 /* WaDisableBackToBackFlipFix:ivb */
5432 I915_WRITE(IVB_CHICKEN3
,
5433 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5434 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5436 /* WaDisablePSDDualDispatchEnable:ivb */
5437 if (IS_IVB_GT1(dev
))
5438 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5439 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5441 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2
,
5442 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5444 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5445 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5446 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5448 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5449 I915_WRITE(GEN7_L3CNTLREG1
,
5450 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5451 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5452 GEN7_WA_L3_CHICKEN_MODE
);
5453 if (IS_IVB_GT1(dev
))
5454 I915_WRITE(GEN7_ROW_CHICKEN2
,
5455 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5457 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5458 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5461 /* WaForceL3Serialization:ivb */
5462 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5463 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5465 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5466 * gating disable must be set. Failure to set it results in
5467 * flickering pixels due to Z write ordering failures after
5468 * some amount of runtime in the Mesa "fire" demo, and Unigine
5469 * Sanctuary and Tropics, and apparently anything else with
5470 * alpha test or pixel discard.
5472 * According to the spec, bit 11 (RCCUNIT) must also be set,
5473 * but we didn't debug actual testcases to find it out.
5475 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5476 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5478 I915_WRITE(GEN6_UCGCTL2
,
5479 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
5480 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5482 /* This is required by WaCatErrorRejectionIssue:ivb */
5483 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5484 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5485 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5487 g4x_disable_trickle_feed(dev
);
5489 /* WaVSRefCountFullforceMissDisable:ivb */
5490 gen7_setup_fixed_func_scheduler(dev_priv
);
5492 /* WaDisable4x2SubspanOptimization:ivb */
5493 I915_WRITE(CACHE_MODE_1
,
5494 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5496 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5497 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5498 snpcr
|= GEN6_MBC_SNPCR_MED
;
5499 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5501 if (!HAS_PCH_NOP(dev
))
5502 cpt_init_clock_gating(dev
);
5504 gen6_check_mch_setup(dev
);
5507 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5512 mutex_lock(&dev_priv
->rps
.hw_lock
);
5513 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5514 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5515 switch ((val
>> 6) & 3) {
5517 dev_priv
->mem_freq
= 800;
5520 dev_priv
->mem_freq
= 1066;
5523 dev_priv
->mem_freq
= 1333;
5526 dev_priv
->mem_freq
= 1333;
5529 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5531 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5533 /* WaDisableEarlyCull:vlv */
5534 I915_WRITE(_3D_CHICKEN3
,
5535 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5537 /* WaDisableBackToBackFlipFix:vlv */
5538 I915_WRITE(IVB_CHICKEN3
,
5539 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5540 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5542 /* WaDisablePSDDualDispatchEnable:vlv */
5543 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5544 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5545 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5547 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5548 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5549 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5551 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5552 I915_WRITE(GEN7_L3CNTLREG1
, I915_READ(GEN7_L3CNTLREG1
) | GEN7_L3AGDIS
);
5553 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
5555 /* WaForceL3Serialization:vlv */
5556 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5557 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5559 /* WaDisableDopClockGating:vlv */
5560 I915_WRITE(GEN7_ROW_CHICKEN2
,
5561 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5563 /* This is required by WaCatErrorRejectionIssue:vlv */
5564 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5565 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5566 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5568 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5569 * gating disable must be set. Failure to set it results in
5570 * flickering pixels due to Z write ordering failures after
5571 * some amount of runtime in the Mesa "fire" demo, and Unigine
5572 * Sanctuary and Tropics, and apparently anything else with
5573 * alpha test or pixel discard.
5575 * According to the spec, bit 11 (RCCUNIT) must also be set,
5576 * but we didn't debug actual testcases to find it out.
5578 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5579 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5581 * Also apply WaDisableVDSUnitClockGating:vlv and
5582 * WaDisableRCPBUnitClockGating:vlv.
5584 I915_WRITE(GEN6_UCGCTL2
,
5585 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
5586 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
5587 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
5588 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5589 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5591 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5593 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5595 I915_WRITE(CACHE_MODE_1
,
5596 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5599 * WaDisableVLVClockGating_VBIIssue:vlv
5600 * Disable clock gating on th GCFG unit to prevent a delay
5601 * in the reporting of vblank events.
5603 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, 0xffffffff);
5605 /* Conservative clock gating settings for now */
5606 I915_WRITE(0x9400, 0xffffffff);
5607 I915_WRITE(0x9404, 0xffffffff);
5608 I915_WRITE(0x9408, 0xffffffff);
5609 I915_WRITE(0x940c, 0xffffffff);
5610 I915_WRITE(0x9410, 0xffffffff);
5611 I915_WRITE(0x9414, 0xffffffff);
5612 I915_WRITE(0x9418, 0xffffffff);
5615 static void g4x_init_clock_gating(struct drm_device
*dev
)
5617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5618 uint32_t dspclk_gate
;
5620 I915_WRITE(RENCLK_GATE_D1
, 0);
5621 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5622 GS_UNIT_CLOCK_GATE_DISABLE
|
5623 CL_UNIT_CLOCK_GATE_DISABLE
);
5624 I915_WRITE(RAMCLK_GATE_D
, 0);
5625 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5626 OVRUNIT_CLOCK_GATE_DISABLE
|
5627 OVCUNIT_CLOCK_GATE_DISABLE
;
5629 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5630 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5632 /* WaDisableRenderCachePipelinedFlush */
5633 I915_WRITE(CACHE_MODE_0
,
5634 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5636 g4x_disable_trickle_feed(dev
);
5639 static void crestline_init_clock_gating(struct drm_device
*dev
)
5641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5643 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5644 I915_WRITE(RENCLK_GATE_D2
, 0);
5645 I915_WRITE(DSPCLK_GATE_D
, 0);
5646 I915_WRITE(RAMCLK_GATE_D
, 0);
5647 I915_WRITE16(DEUC
, 0);
5648 I915_WRITE(MI_ARB_STATE
,
5649 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5652 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5656 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5657 I965_RCC_CLOCK_GATE_DISABLE
|
5658 I965_RCPB_CLOCK_GATE_DISABLE
|
5659 I965_ISC_CLOCK_GATE_DISABLE
|
5660 I965_FBC_CLOCK_GATE_DISABLE
);
5661 I915_WRITE(RENCLK_GATE_D2
, 0);
5662 I915_WRITE(MI_ARB_STATE
,
5663 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5666 static void gen3_init_clock_gating(struct drm_device
*dev
)
5668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5669 u32 dstate
= I915_READ(D_STATE
);
5671 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5672 DSTATE_DOT_CLOCK_GATING
;
5673 I915_WRITE(D_STATE
, dstate
);
5675 if (IS_PINEVIEW(dev
))
5676 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5678 /* IIR "flip pending" means done if this bit is set */
5679 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5682 static void i85x_init_clock_gating(struct drm_device
*dev
)
5684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5686 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5689 static void i830_init_clock_gating(struct drm_device
*dev
)
5691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5693 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5696 void intel_init_clock_gating(struct drm_device
*dev
)
5698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5700 dev_priv
->display
.init_clock_gating(dev
);
5703 void intel_suspend_hw(struct drm_device
*dev
)
5705 if (HAS_PCH_LPT(dev
))
5706 lpt_suspend_hw(dev
);
5709 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5711 i < (power_domains)->power_well_count && \
5712 ((power_well) = &(power_domains)->power_wells[i]); \
5714 if ((power_well)->domains & (domain_mask))
5716 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5717 for (i = (power_domains)->power_well_count - 1; \
5718 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5720 if ((power_well)->domains & (domain_mask))
5723 * We should only use the power well if we explicitly asked the hardware to
5724 * enable it, so check if it's enabled and also check if we've requested it to
5727 static bool hsw_power_well_enabled(struct drm_device
*dev
,
5728 struct i915_power_well
*power_well
)
5730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5732 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5733 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
5736 bool intel_display_power_enabled_sw(struct drm_device
*dev
,
5737 enum intel_display_power_domain domain
)
5739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5740 struct i915_power_domains
*power_domains
;
5742 power_domains
= &dev_priv
->power_domains
;
5744 return power_domains
->domain_use_count
[domain
];
5747 bool intel_display_power_enabled(struct drm_device
*dev
,
5748 enum intel_display_power_domain domain
)
5750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5751 struct i915_power_domains
*power_domains
;
5752 struct i915_power_well
*power_well
;
5756 power_domains
= &dev_priv
->power_domains
;
5760 mutex_lock(&power_domains
->lock
);
5761 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
5762 if (power_well
->always_on
)
5765 if (!power_well
->is_enabled(dev
, power_well
)) {
5770 mutex_unlock(&power_domains
->lock
);
5775 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
5777 struct drm_device
*dev
= dev_priv
->dev
;
5778 unsigned long irqflags
;
5781 * After we re-enable the power well, if we touch VGA register 0x3d5
5782 * we'll get unclaimed register interrupts. This stops after we write
5783 * anything to the VGA MSR register. The vgacon module uses this
5784 * register all the time, so if we unbind our driver and, as a
5785 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5786 * console_unlock(). So make here we touch the VGA MSR register, making
5787 * sure vgacon can keep working normally without triggering interrupts
5788 * and error messages.
5790 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5791 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
5792 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5794 if (IS_BROADWELL(dev
)) {
5795 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
5796 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B
),
5797 dev_priv
->de_irq_mask
[PIPE_B
]);
5798 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B
),
5799 ~dev_priv
->de_irq_mask
[PIPE_B
] |
5801 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C
),
5802 dev_priv
->de_irq_mask
[PIPE_C
]);
5803 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C
),
5804 ~dev_priv
->de_irq_mask
[PIPE_C
] |
5806 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C
));
5807 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
5811 static void hsw_power_well_post_disable(struct drm_i915_private
*dev_priv
)
5813 struct drm_device
*dev
= dev_priv
->dev
;
5815 unsigned long irqflags
;
5818 * After this, the registers on the pipes that are part of the power
5819 * well will become zero, so we have to adjust our counters according to
5822 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5824 spin_lock_irqsave(&dev
->vbl_lock
, irqflags
);
5827 dev
->vblank
[p
].last
= 0;
5828 spin_unlock_irqrestore(&dev
->vbl_lock
, irqflags
);
5831 static void hsw_set_power_well(struct drm_device
*dev
,
5832 struct i915_power_well
*power_well
, bool enable
)
5834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5835 bool is_enabled
, enable_requested
;
5838 WARN_ON(dev_priv
->pc8
.enabled
);
5840 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5841 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
5842 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
5845 if (!enable_requested
)
5846 I915_WRITE(HSW_PWR_WELL_DRIVER
,
5847 HSW_PWR_WELL_ENABLE_REQUEST
);
5850 DRM_DEBUG_KMS("Enabling power well\n");
5851 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5852 HSW_PWR_WELL_STATE_ENABLED
), 20))
5853 DRM_ERROR("Timeout enabling power well\n");
5856 hsw_power_well_post_enable(dev_priv
);
5858 if (enable_requested
) {
5859 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5860 POSTING_READ(HSW_PWR_WELL_DRIVER
);
5861 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5863 hsw_power_well_post_disable(dev_priv
);
5868 static void __intel_power_well_get(struct drm_device
*dev
,
5869 struct i915_power_well
*power_well
)
5871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5873 if (!power_well
->count
++ && power_well
->set
) {
5874 hsw_disable_package_c8(dev_priv
);
5875 power_well
->set(dev
, power_well
, true);
5879 static void __intel_power_well_put(struct drm_device
*dev
,
5880 struct i915_power_well
*power_well
)
5882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5884 WARN_ON(!power_well
->count
);
5886 if (!--power_well
->count
&& power_well
->set
&&
5887 i915_disable_power_well
) {
5888 power_well
->set(dev
, power_well
, false);
5889 hsw_enable_package_c8(dev_priv
);
5893 void intel_display_power_get(struct drm_device
*dev
,
5894 enum intel_display_power_domain domain
)
5896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5897 struct i915_power_domains
*power_domains
;
5898 struct i915_power_well
*power_well
;
5901 power_domains
= &dev_priv
->power_domains
;
5903 mutex_lock(&power_domains
->lock
);
5905 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
)
5906 __intel_power_well_get(dev
, power_well
);
5908 power_domains
->domain_use_count
[domain
]++;
5910 mutex_unlock(&power_domains
->lock
);
5913 void intel_display_power_put(struct drm_device
*dev
,
5914 enum intel_display_power_domain domain
)
5916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5917 struct i915_power_domains
*power_domains
;
5918 struct i915_power_well
*power_well
;
5921 power_domains
= &dev_priv
->power_domains
;
5923 mutex_lock(&power_domains
->lock
);
5925 WARN_ON(!power_domains
->domain_use_count
[domain
]);
5926 power_domains
->domain_use_count
[domain
]--;
5928 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
)
5929 __intel_power_well_put(dev
, power_well
);
5931 mutex_unlock(&power_domains
->lock
);
5934 static struct i915_power_domains
*hsw_pwr
;
5936 /* Display audio driver power well request */
5937 void i915_request_power_well(void)
5939 struct drm_i915_private
*dev_priv
;
5941 if (WARN_ON(!hsw_pwr
))
5944 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
5946 intel_display_power_get(dev_priv
->dev
, POWER_DOMAIN_AUDIO
);
5948 EXPORT_SYMBOL_GPL(i915_request_power_well
);
5950 /* Display audio driver power well release */
5951 void i915_release_power_well(void)
5953 struct drm_i915_private
*dev_priv
;
5955 if (WARN_ON(!hsw_pwr
))
5958 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
5960 intel_display_power_put(dev_priv
->dev
, POWER_DOMAIN_AUDIO
);
5962 EXPORT_SYMBOL_GPL(i915_release_power_well
);
5964 static struct i915_power_well i9xx_always_on_power_well
[] = {
5966 .name
= "always-on",
5968 .domains
= POWER_DOMAIN_MASK
,
5972 static struct i915_power_well hsw_power_wells
[] = {
5974 .name
= "always-on",
5976 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
5980 .domains
= POWER_DOMAIN_MASK
& ~HSW_ALWAYS_ON_POWER_DOMAINS
,
5981 .is_enabled
= hsw_power_well_enabled
,
5982 .set
= hsw_set_power_well
,
5986 static struct i915_power_well bdw_power_wells
[] = {
5988 .name
= "always-on",
5990 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
5994 .domains
= POWER_DOMAIN_MASK
& ~BDW_ALWAYS_ON_POWER_DOMAINS
,
5995 .is_enabled
= hsw_power_well_enabled
,
5996 .set
= hsw_set_power_well
,
6000 #define set_power_wells(power_domains, __power_wells) ({ \
6001 (power_domains)->power_wells = (__power_wells); \
6002 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6005 int intel_power_domains_init(struct drm_device
*dev
)
6007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6008 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6010 mutex_init(&power_domains
->lock
);
6013 * The enabling order will be from lower to higher indexed wells,
6014 * the disabling order is reversed.
6016 if (IS_HASWELL(dev
)) {
6017 set_power_wells(power_domains
, hsw_power_wells
);
6018 hsw_pwr
= power_domains
;
6019 } else if (IS_BROADWELL(dev
)) {
6020 set_power_wells(power_domains
, bdw_power_wells
);
6021 hsw_pwr
= power_domains
;
6023 set_power_wells(power_domains
, i9xx_always_on_power_well
);
6029 void intel_power_domains_remove(struct drm_device
*dev
)
6034 static void intel_power_domains_resume(struct drm_device
*dev
)
6036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6037 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6038 struct i915_power_well
*power_well
;
6041 mutex_lock(&power_domains
->lock
);
6042 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
6043 if (power_well
->set
)
6044 power_well
->set(dev
, power_well
, power_well
->count
> 0);
6046 mutex_unlock(&power_domains
->lock
);
6050 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6051 * when not needed anymore. We have 4 registers that can request the power well
6052 * to be enabled, and it will only be disabled if none of the registers is
6053 * requesting it to be enabled.
6055 void intel_power_domains_init_hw(struct drm_device
*dev
)
6057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6059 /* For now, we need the power well to be always enabled. */
6060 intel_display_set_init_power(dev
, true);
6061 intel_power_domains_resume(dev
);
6063 if (!(IS_HASWELL(dev
) || IS_BROADWELL(dev
)))
6066 /* We're taking over the BIOS, so clear any requests made by it since
6067 * the driver is in charge now. */
6068 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
6069 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
6072 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
6073 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
6075 hsw_disable_package_c8(dev_priv
);
6078 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
6080 hsw_enable_package_c8(dev_priv
);
6083 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
6085 struct drm_device
*dev
= dev_priv
->dev
;
6086 struct device
*device
= &dev
->pdev
->dev
;
6088 if (!HAS_RUNTIME_PM(dev
))
6091 pm_runtime_get_sync(device
);
6092 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
6095 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
6097 struct drm_device
*dev
= dev_priv
->dev
;
6098 struct device
*device
= &dev
->pdev
->dev
;
6100 if (!HAS_RUNTIME_PM(dev
))
6103 pm_runtime_mark_last_busy(device
);
6104 pm_runtime_put_autosuspend(device
);
6107 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
6109 struct drm_device
*dev
= dev_priv
->dev
;
6110 struct device
*device
= &dev
->pdev
->dev
;
6112 dev_priv
->pm
.suspended
= false;
6114 if (!HAS_RUNTIME_PM(dev
))
6117 pm_runtime_set_active(device
);
6119 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
6120 pm_runtime_mark_last_busy(device
);
6121 pm_runtime_use_autosuspend(device
);
6124 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
6126 struct drm_device
*dev
= dev_priv
->dev
;
6127 struct device
*device
= &dev
->pdev
->dev
;
6129 if (!HAS_RUNTIME_PM(dev
))
6132 /* Make sure we're not suspended first. */
6133 pm_runtime_get_sync(device
);
6134 pm_runtime_disable(device
);
6137 /* Set up chip specific power management-related functions */
6138 void intel_init_pm(struct drm_device
*dev
)
6140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6142 if (I915_HAS_FBC(dev
)) {
6143 if (INTEL_INFO(dev
)->gen
>= 7) {
6144 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6145 dev_priv
->display
.enable_fbc
= gen7_enable_fbc
;
6146 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6147 } else if (INTEL_INFO(dev
)->gen
>= 5) {
6148 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6149 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
6150 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6151 } else if (IS_GM45(dev
)) {
6152 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
6153 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
6154 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
6156 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
6157 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
6158 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
6160 /* This value was pulled out of someone's hat */
6161 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
6166 if (IS_PINEVIEW(dev
))
6167 i915_pineview_get_mem_freq(dev
);
6168 else if (IS_GEN5(dev
))
6169 i915_ironlake_get_mem_freq(dev
);
6171 /* For FIFO watermark updates */
6172 if (HAS_PCH_SPLIT(dev
)) {
6173 intel_setup_wm_latency(dev
);
6176 if (dev_priv
->wm
.pri_latency
[1] &&
6177 dev_priv
->wm
.spr_latency
[1] &&
6178 dev_priv
->wm
.cur_latency
[1])
6179 dev_priv
->display
.update_wm
= ironlake_update_wm
;
6181 DRM_DEBUG_KMS("Failed to get proper latency. "
6183 dev_priv
->display
.update_wm
= NULL
;
6185 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6186 } else if (IS_GEN6(dev
)) {
6187 if (dev_priv
->wm
.pri_latency
[0] &&
6188 dev_priv
->wm
.spr_latency
[0] &&
6189 dev_priv
->wm
.cur_latency
[0]) {
6190 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
6191 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
6193 DRM_DEBUG_KMS("Failed to read display plane latency. "
6195 dev_priv
->display
.update_wm
= NULL
;
6197 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6198 } else if (IS_IVYBRIDGE(dev
)) {
6199 if (dev_priv
->wm
.pri_latency
[0] &&
6200 dev_priv
->wm
.spr_latency
[0] &&
6201 dev_priv
->wm
.cur_latency
[0]) {
6202 dev_priv
->display
.update_wm
= ivybridge_update_wm
;
6203 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
6205 DRM_DEBUG_KMS("Failed to read display plane latency. "
6207 dev_priv
->display
.update_wm
= NULL
;
6209 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6210 } else if (IS_HASWELL(dev
)) {
6211 if (dev_priv
->wm
.pri_latency
[0] &&
6212 dev_priv
->wm
.spr_latency
[0] &&
6213 dev_priv
->wm
.cur_latency
[0]) {
6214 dev_priv
->display
.update_wm
= haswell_update_wm
;
6215 dev_priv
->display
.update_sprite_wm
=
6216 haswell_update_sprite_wm
;
6218 DRM_DEBUG_KMS("Failed to read display plane latency. "
6220 dev_priv
->display
.update_wm
= NULL
;
6222 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6223 } else if (INTEL_INFO(dev
)->gen
== 8) {
6224 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
6226 dev_priv
->display
.update_wm
= NULL
;
6227 } else if (IS_VALLEYVIEW(dev
)) {
6228 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6229 dev_priv
->display
.init_clock_gating
=
6230 valleyview_init_clock_gating
;
6231 } else if (IS_PINEVIEW(dev
)) {
6232 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6235 dev_priv
->mem_freq
)) {
6236 DRM_INFO("failed to find known CxSR latency "
6237 "(found ddr%s fsb freq %d, mem freq %d), "
6239 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6240 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6241 /* Disable CxSR and never update its watermark again */
6242 pineview_disable_cxsr(dev
);
6243 dev_priv
->display
.update_wm
= NULL
;
6245 dev_priv
->display
.update_wm
= pineview_update_wm
;
6246 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6247 } else if (IS_G4X(dev
)) {
6248 dev_priv
->display
.update_wm
= g4x_update_wm
;
6249 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6250 } else if (IS_GEN4(dev
)) {
6251 dev_priv
->display
.update_wm
= i965_update_wm
;
6252 if (IS_CRESTLINE(dev
))
6253 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6254 else if (IS_BROADWATER(dev
))
6255 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6256 } else if (IS_GEN3(dev
)) {
6257 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6258 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6259 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6260 } else if (IS_I865G(dev
)) {
6261 dev_priv
->display
.update_wm
= i830_update_wm
;
6262 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6263 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6264 } else if (IS_I85X(dev
)) {
6265 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6266 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
6267 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6269 dev_priv
->display
.update_wm
= i830_update_wm
;
6270 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6272 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6274 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6278 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
6280 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6282 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6283 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6287 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6288 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6290 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6292 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6296 *val
= I915_READ(GEN6_PCODE_DATA
);
6297 I915_WRITE(GEN6_PCODE_DATA
, 0);
6302 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
6304 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6306 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6307 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6311 I915_WRITE(GEN6_PCODE_DATA
, val
);
6312 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6314 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6316 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6320 I915_WRITE(GEN6_PCODE_DATA
, 0);
6325 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6330 switch (dev_priv
->mem_freq
) {
6344 return DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* (val
+ 6 - 0xbd), 4 * div
);
6347 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6352 switch (dev_priv
->mem_freq
) {
6366 return DIV_ROUND_CLOSEST(4 * mul
* val
, dev_priv
->mem_freq
) + 0xbd - 6;
6369 void intel_pm_init(struct drm_device
*dev
)
6371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6373 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6374 intel_gen6_powersave_work
);