2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
36 * RC6 is a special power stage which allows the GPU to enter an very
37 * low-voltage mode when idle, using down to 0V while at this stage. This
38 * stage is entered automatically when the GPU is idle when RC6 support is
39 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 * There are different RC6 modes available in Intel GPU, which differentiate
42 * among each other with the latency required to enter and leave RC6 and
43 * voltage consumed by the GPU in different states.
45 * The combination of the following flags define which states GPU is allowed
46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
47 * RC6pp is deepest RC6. Their support by hardware varies according to the
48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
49 * which brings the most power savings; deeper states save more power, but
50 * require higher latency to switch to and wake up.
52 #define INTEL_RC6_ENABLE (1<<0)
53 #define INTEL_RC6p_ENABLE (1<<1)
54 #define INTEL_RC6pp_ENABLE (1<<2)
56 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
57 * framebuffer contents in-memory, aiming at reducing the required bandwidth
58 * during in-memory transfers and, therefore, reduce the power packet.
60 * The benefits of FBC are mostly visible with solid backgrounds and
61 * variation-less patterns.
63 * FBC-related functionality can be enabled by the means of the
64 * i915.i915_enable_fbc parameter
67 static void i8xx_disable_fbc(struct drm_device
*dev
)
69 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
72 /* Disable compression */
73 fbc_ctl
= I915_READ(FBC_CONTROL
);
74 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
77 fbc_ctl
&= ~FBC_CTL_EN
;
78 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
80 /* Wait for compressing bit to clear */
81 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
82 DRM_DEBUG_KMS("FBC idle timed out\n");
86 DRM_DEBUG_KMS("disabled FBC\n");
89 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
91 struct drm_device
*dev
= crtc
->dev
;
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct drm_framebuffer
*fb
= crtc
->fb
;
94 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
95 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
96 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
99 u32 fbc_ctl
, fbc_ctl2
;
101 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
102 if (fb
->pitches
[0] < cfb_pitch
)
103 cfb_pitch
= fb
->pitches
[0];
105 /* FBC_CTL wants 64B units */
106 cfb_pitch
= (cfb_pitch
/ 64) - 1;
107 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
110 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
111 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
114 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
116 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
117 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
120 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
122 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
123 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
124 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
125 fbc_ctl
|= obj
->fence_reg
;
126 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
128 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
129 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
132 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
136 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
139 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
141 struct drm_device
*dev
= crtc
->dev
;
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 struct drm_framebuffer
*fb
= crtc
->fb
;
144 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
145 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
147 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
148 unsigned long stall_watermark
= 200;
151 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
152 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
153 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
155 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
156 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
157 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
158 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
161 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
163 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
166 static void g4x_disable_fbc(struct drm_device
*dev
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
171 /* Disable compression */
172 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
173 if (dpfc_ctl
& DPFC_CTL_EN
) {
174 dpfc_ctl
&= ~DPFC_CTL_EN
;
175 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
177 DRM_DEBUG_KMS("disabled FBC\n");
181 static bool g4x_fbc_enabled(struct drm_device
*dev
)
183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
185 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
188 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
193 /* Make sure blitter notifies FBC of writes */
194 gen6_gt_force_wake_get(dev_priv
);
195 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
196 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
197 GEN6_BLITTER_LOCK_SHIFT
;
198 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
199 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
200 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
201 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
202 GEN6_BLITTER_LOCK_SHIFT
);
203 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
204 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
205 gen6_gt_force_wake_put(dev_priv
);
208 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
210 struct drm_device
*dev
= crtc
->dev
;
211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
212 struct drm_framebuffer
*fb
= crtc
->fb
;
213 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
214 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
216 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
217 unsigned long stall_watermark
= 200;
220 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
221 dpfc_ctl
&= DPFC_RESERVED
;
222 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
223 /* Set persistent mode for front-buffer rendering, ala X. */
224 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
225 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
226 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
228 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
229 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
230 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
231 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
232 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
234 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
237 I915_WRITE(SNB_DPFC_CTL_SA
,
238 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
239 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
240 sandybridge_blit_fbc_update(dev
);
243 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
246 static void ironlake_disable_fbc(struct drm_device
*dev
)
248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
251 /* Disable compression */
252 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
253 if (dpfc_ctl
& DPFC_CTL_EN
) {
254 dpfc_ctl
&= ~DPFC_CTL_EN
;
255 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
257 DRM_DEBUG_KMS("disabled FBC\n");
261 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
265 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
268 static void gen7_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
270 struct drm_device
*dev
= crtc
->dev
;
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
272 struct drm_framebuffer
*fb
= crtc
->fb
;
273 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
274 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
277 I915_WRITE(IVB_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
));
279 I915_WRITE(ILK_DPFC_CONTROL
, DPFC_CTL_EN
| DPFC_CTL_LIMIT_1X
|
280 IVB_DPFC_CTL_FENCE_EN
|
281 intel_crtc
->plane
<< IVB_DPFC_CTL_PLANE_SHIFT
);
283 if (IS_IVYBRIDGE(dev
)) {
284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
285 I915_WRITE(ILK_DISPLAY_CHICKEN1
, ILK_FBCQ_DIS
);
287 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
288 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc
->pipe
),
289 HSW_BYPASS_FBC_QUEUE
);
292 I915_WRITE(SNB_DPFC_CTL_SA
,
293 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
294 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
296 sandybridge_blit_fbc_update(dev
);
298 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
301 bool intel_fbc_enabled(struct drm_device
*dev
)
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
305 if (!dev_priv
->display
.fbc_enabled
)
308 return dev_priv
->display
.fbc_enabled(dev
);
311 static void intel_fbc_work_fn(struct work_struct
*__work
)
313 struct intel_fbc_work
*work
=
314 container_of(to_delayed_work(__work
),
315 struct intel_fbc_work
, work
);
316 struct drm_device
*dev
= work
->crtc
->dev
;
317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
319 mutex_lock(&dev
->struct_mutex
);
320 if (work
== dev_priv
->fbc
.fbc_work
) {
321 /* Double check that we haven't switched fb without cancelling
324 if (work
->crtc
->fb
== work
->fb
) {
325 dev_priv
->display
.enable_fbc(work
->crtc
,
328 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
329 dev_priv
->fbc
.fb_id
= work
->crtc
->fb
->base
.id
;
330 dev_priv
->fbc
.y
= work
->crtc
->y
;
333 dev_priv
->fbc
.fbc_work
= NULL
;
335 mutex_unlock(&dev
->struct_mutex
);
340 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
342 if (dev_priv
->fbc
.fbc_work
== NULL
)
345 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
347 /* Synchronisation is provided by struct_mutex and checking of
348 * dev_priv->fbc.fbc_work, so we can perform the cancellation
349 * entirely asynchronously.
351 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
352 /* tasklet was killed before being run, clean up */
353 kfree(dev_priv
->fbc
.fbc_work
);
355 /* Mark the work as no longer wanted so that if it does
356 * wake-up (because the work was already running and waiting
357 * for our mutex), it will discover that is no longer
360 dev_priv
->fbc
.fbc_work
= NULL
;
363 static void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
365 struct intel_fbc_work
*work
;
366 struct drm_device
*dev
= crtc
->dev
;
367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
369 if (!dev_priv
->display
.enable_fbc
)
372 intel_cancel_fbc_work(dev_priv
);
374 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
376 DRM_ERROR("Failed to allocate FBC work structure\n");
377 dev_priv
->display
.enable_fbc(crtc
, interval
);
383 work
->interval
= interval
;
384 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
386 dev_priv
->fbc
.fbc_work
= work
;
388 /* Delay the actual enabling to let pageflipping cease and the
389 * display to settle before starting the compression. Note that
390 * this delay also serves a second purpose: it allows for a
391 * vblank to pass after disabling the FBC before we attempt
392 * to modify the control registers.
394 * A more complicated solution would involve tracking vblanks
395 * following the termination of the page-flipping sequence
396 * and indeed performing the enable as a co-routine and not
397 * waiting synchronously upon the vblank.
399 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
401 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
404 void intel_disable_fbc(struct drm_device
*dev
)
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
408 intel_cancel_fbc_work(dev_priv
);
410 if (!dev_priv
->display
.disable_fbc
)
413 dev_priv
->display
.disable_fbc(dev
);
414 dev_priv
->fbc
.plane
= -1;
417 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
418 enum no_fbc_reason reason
)
420 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
423 dev_priv
->fbc
.no_fbc_reason
= reason
;
428 * intel_update_fbc - enable/disable FBC as needed
429 * @dev: the drm_device
431 * Set up the framebuffer compression hardware at mode set time. We
432 * enable it if possible:
433 * - plane A only (on pre-965)
434 * - no pixel mulitply/line duplication
435 * - no alpha buffer discard
437 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
439 * We can't assume that any compression will take place (worst case),
440 * so the compressed buffer has to be the same size as the uncompressed
441 * one. It also must reside (along with the line length buffer) in
444 * We need to enable/disable FBC on a global basis.
446 void intel_update_fbc(struct drm_device
*dev
)
448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
449 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
450 struct intel_crtc
*intel_crtc
;
451 struct drm_framebuffer
*fb
;
452 struct intel_framebuffer
*intel_fb
;
453 struct drm_i915_gem_object
*obj
;
454 const struct drm_display_mode
*adjusted_mode
;
455 unsigned int max_width
, max_height
;
457 if (!I915_HAS_FBC(dev
)) {
458 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
462 if (!i915_powersave
) {
463 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
464 DRM_DEBUG_KMS("fbc disabled per module param\n");
469 * If FBC is already on, we just have to verify that we can
470 * keep it that way...
471 * Need to disable if:
472 * - more than one pipe is active
473 * - changing FBC params (stride, fence, mode)
474 * - new fb is too large to fit in compressed buffer
475 * - going to an unsupported config (interlace, pixel multiply, etc.)
477 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
478 if (intel_crtc_active(tmp_crtc
) &&
479 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
481 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
482 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
489 if (!crtc
|| crtc
->fb
== NULL
) {
490 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
491 DRM_DEBUG_KMS("no output, disabling\n");
495 intel_crtc
= to_intel_crtc(crtc
);
497 intel_fb
= to_intel_framebuffer(fb
);
499 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
501 if (i915_enable_fbc
< 0 &&
502 INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
)) {
503 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
504 DRM_DEBUG_KMS("disabled per chip default\n");
507 if (!i915_enable_fbc
) {
508 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
509 DRM_DEBUG_KMS("fbc disabled per module param\n");
512 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
513 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
514 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
515 DRM_DEBUG_KMS("mode incompatible with compression, "
520 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
527 if (intel_crtc
->config
.pipe_src_w
> max_width
||
528 intel_crtc
->config
.pipe_src_h
> max_height
) {
529 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
530 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
533 if ((IS_I915GM(dev
) || IS_I945GM(dev
) || IS_HASWELL(dev
)) &&
534 intel_crtc
->plane
!= 0) {
535 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
536 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
540 /* The use of a CPU fence is mandatory in order to detect writes
541 * by the CPU to the scanout and trigger updates to the FBC.
543 if (obj
->tiling_mode
!= I915_TILING_X
||
544 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
545 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
546 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
550 /* If the kernel debugger is active, always disable compression */
554 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
555 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
556 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
560 /* If the scanout has not changed, don't modify the FBC settings.
561 * Note that we make the fundamental assumption that the fb->obj
562 * cannot be unpinned (and have its GTT offset and fence revoked)
563 * without first being decoupled from the scanout and FBC disabled.
565 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
566 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
567 dev_priv
->fbc
.y
== crtc
->y
)
570 if (intel_fbc_enabled(dev
)) {
571 /* We update FBC along two paths, after changing fb/crtc
572 * configuration (modeswitching) and after page-flipping
573 * finishes. For the latter, we know that not only did
574 * we disable the FBC at the start of the page-flip
575 * sequence, but also more than one vblank has passed.
577 * For the former case of modeswitching, it is possible
578 * to switch between two FBC valid configurations
579 * instantaneously so we do need to disable the FBC
580 * before we can modify its control registers. We also
581 * have to wait for the next vblank for that to take
582 * effect. However, since we delay enabling FBC we can
583 * assume that a vblank has passed since disabling and
584 * that we can safely alter the registers in the deferred
587 * In the scenario that we go from a valid to invalid
588 * and then back to valid FBC configuration we have
589 * no strict enforcement that a vblank occurred since
590 * disabling the FBC. However, along all current pipe
591 * disabling paths we do need to wait for a vblank at
592 * some point. And we wait before enabling FBC anyway.
594 DRM_DEBUG_KMS("disabling active FBC for update\n");
595 intel_disable_fbc(dev
);
598 intel_enable_fbc(crtc
, 500);
599 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
603 /* Multiple disables should be harmless */
604 if (intel_fbc_enabled(dev
)) {
605 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
606 intel_disable_fbc(dev
);
608 i915_gem_stolen_cleanup_compression(dev
);
611 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
613 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
616 tmp
= I915_READ(CLKCFG
);
618 switch (tmp
& CLKCFG_FSB_MASK
) {
620 dev_priv
->fsb_freq
= 533; /* 133*4 */
623 dev_priv
->fsb_freq
= 800; /* 200*4 */
626 dev_priv
->fsb_freq
= 667; /* 167*4 */
629 dev_priv
->fsb_freq
= 400; /* 100*4 */
633 switch (tmp
& CLKCFG_MEM_MASK
) {
635 dev_priv
->mem_freq
= 533;
638 dev_priv
->mem_freq
= 667;
641 dev_priv
->mem_freq
= 800;
645 /* detect pineview DDR3 setting */
646 tmp
= I915_READ(CSHRDDR3CTL
);
647 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
650 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
655 ddrpll
= I915_READ16(DDRMPLL1
);
656 csipll
= I915_READ16(CSIPLL0
);
658 switch (ddrpll
& 0xff) {
660 dev_priv
->mem_freq
= 800;
663 dev_priv
->mem_freq
= 1066;
666 dev_priv
->mem_freq
= 1333;
669 dev_priv
->mem_freq
= 1600;
672 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
674 dev_priv
->mem_freq
= 0;
678 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
680 switch (csipll
& 0x3ff) {
682 dev_priv
->fsb_freq
= 3200;
685 dev_priv
->fsb_freq
= 3733;
688 dev_priv
->fsb_freq
= 4266;
691 dev_priv
->fsb_freq
= 4800;
694 dev_priv
->fsb_freq
= 5333;
697 dev_priv
->fsb_freq
= 5866;
700 dev_priv
->fsb_freq
= 6400;
703 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
705 dev_priv
->fsb_freq
= 0;
709 if (dev_priv
->fsb_freq
== 3200) {
710 dev_priv
->ips
.c_m
= 0;
711 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
712 dev_priv
->ips
.c_m
= 1;
714 dev_priv
->ips
.c_m
= 2;
718 static const struct cxsr_latency cxsr_latency_table
[] = {
719 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
720 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
721 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
722 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
723 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
725 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
726 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
727 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
728 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
729 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
731 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
732 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
733 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
734 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
735 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
737 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
738 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
739 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
740 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
741 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
743 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
744 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
745 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
746 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
747 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
749 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
750 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
751 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
752 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
753 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
756 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
761 const struct cxsr_latency
*latency
;
764 if (fsb
== 0 || mem
== 0)
767 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
768 latency
= &cxsr_latency_table
[i
];
769 if (is_desktop
== latency
->is_desktop
&&
770 is_ddr3
== latency
->is_ddr3
&&
771 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
775 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
780 static void pineview_disable_cxsr(struct drm_device
*dev
)
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 /* deactivate cxsr */
785 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
789 * Latency for FIFO fetches is dependent on several factors:
790 * - memory configuration (speed, channels)
792 * - current MCH state
793 * It can be fairly high in some situations, so here we assume a fairly
794 * pessimal value. It's a tradeoff between extra memory fetches (if we
795 * set this value too high, the FIFO will fetch frequently to stay full)
796 * and power consumption (set it too low to save power and we might see
797 * FIFO underruns and display "flicker").
799 * A value of 5us seems to be a good balance; safe for very low end
800 * platforms but not overly aggressive on lower latency configs.
802 static const int latency_ns
= 5000;
804 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
807 uint32_t dsparb
= I915_READ(DSPARB
);
810 size
= dsparb
& 0x7f;
812 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
814 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
815 plane
? "B" : "A", size
);
820 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
823 uint32_t dsparb
= I915_READ(DSPARB
);
826 size
= dsparb
& 0x1ff;
828 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
829 size
>>= 1; /* Convert to cachelines */
831 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
832 plane
? "B" : "A", size
);
837 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
840 uint32_t dsparb
= I915_READ(DSPARB
);
843 size
= dsparb
& 0x7f;
844 size
>>= 2; /* Convert to cachelines */
846 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
853 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
856 uint32_t dsparb
= I915_READ(DSPARB
);
859 size
= dsparb
& 0x7f;
860 size
>>= 1; /* Convert to cachelines */
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
863 plane
? "B" : "A", size
);
868 /* Pineview has different values for various configs */
869 static const struct intel_watermark_params pineview_display_wm
= {
870 PINEVIEW_DISPLAY_FIFO
,
874 PINEVIEW_FIFO_LINE_SIZE
876 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
877 PINEVIEW_DISPLAY_FIFO
,
879 PINEVIEW_DFT_HPLLOFF_WM
,
881 PINEVIEW_FIFO_LINE_SIZE
883 static const struct intel_watermark_params pineview_cursor_wm
= {
884 PINEVIEW_CURSOR_FIFO
,
885 PINEVIEW_CURSOR_MAX_WM
,
886 PINEVIEW_CURSOR_DFT_WM
,
887 PINEVIEW_CURSOR_GUARD_WM
,
888 PINEVIEW_FIFO_LINE_SIZE
,
890 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
891 PINEVIEW_CURSOR_FIFO
,
892 PINEVIEW_CURSOR_MAX_WM
,
893 PINEVIEW_CURSOR_DFT_WM
,
894 PINEVIEW_CURSOR_GUARD_WM
,
895 PINEVIEW_FIFO_LINE_SIZE
897 static const struct intel_watermark_params g4x_wm_info
= {
904 static const struct intel_watermark_params g4x_cursor_wm_info
= {
911 static const struct intel_watermark_params valleyview_wm_info
= {
912 VALLEYVIEW_FIFO_SIZE
,
918 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
920 VALLEYVIEW_CURSOR_MAX_WM
,
925 static const struct intel_watermark_params i965_cursor_wm_info
= {
932 static const struct intel_watermark_params i945_wm_info
= {
939 static const struct intel_watermark_params i915_wm_info
= {
946 static const struct intel_watermark_params i855_wm_info
= {
953 static const struct intel_watermark_params i830_wm_info
= {
961 static const struct intel_watermark_params ironlake_display_wm_info
= {
968 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
975 static const struct intel_watermark_params ironlake_display_srwm_info
= {
977 ILK_DISPLAY_MAX_SRWM
,
978 ILK_DISPLAY_DFT_SRWM
,
982 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
990 static const struct intel_watermark_params sandybridge_display_wm_info
= {
997 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
1004 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
1005 SNB_DISPLAY_SR_FIFO
,
1006 SNB_DISPLAY_MAX_SRWM
,
1007 SNB_DISPLAY_DFT_SRWM
,
1011 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
1013 SNB_CURSOR_MAX_SRWM
,
1014 SNB_CURSOR_DFT_SRWM
,
1021 * intel_calculate_wm - calculate watermark level
1022 * @clock_in_khz: pixel clock
1023 * @wm: chip FIFO params
1024 * @pixel_size: display pixel size
1025 * @latency_ns: memory latency for the platform
1027 * Calculate the watermark level (the level at which the display plane will
1028 * start fetching from memory again). Each chip has a different display
1029 * FIFO size and allocation, so the caller needs to figure that out and pass
1030 * in the correct intel_watermark_params structure.
1032 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1033 * on the pixel size. When it reaches the watermark level, it'll start
1034 * fetching FIFO line sized based chunks from memory until the FIFO fills
1035 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1036 * will occur, and a display engine hang could result.
1038 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1039 const struct intel_watermark_params
*wm
,
1042 unsigned long latency_ns
)
1044 long entries_required
, wm_size
;
1047 * Note: we need to make sure we don't overflow for various clock &
1049 * clocks go from a few thousand to several hundred thousand.
1050 * latency is usually a few thousand
1052 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1054 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1056 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1058 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1060 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1062 /* Don't promote wm_size to unsigned... */
1063 if (wm_size
> (long)wm
->max_wm
)
1064 wm_size
= wm
->max_wm
;
1066 wm_size
= wm
->default_wm
;
1070 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1072 struct drm_crtc
*crtc
, *enabled
= NULL
;
1074 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1075 if (intel_crtc_active(crtc
)) {
1085 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1087 struct drm_device
*dev
= unused_crtc
->dev
;
1088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1089 struct drm_crtc
*crtc
;
1090 const struct cxsr_latency
*latency
;
1094 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1095 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1097 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1098 pineview_disable_cxsr(dev
);
1102 crtc
= single_enabled_crtc(dev
);
1104 const struct drm_display_mode
*adjusted_mode
;
1105 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1108 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1109 clock
= adjusted_mode
->crtc_clock
;
1112 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1113 pineview_display_wm
.fifo_size
,
1114 pixel_size
, latency
->display_sr
);
1115 reg
= I915_READ(DSPFW1
);
1116 reg
&= ~DSPFW_SR_MASK
;
1117 reg
|= wm
<< DSPFW_SR_SHIFT
;
1118 I915_WRITE(DSPFW1
, reg
);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1122 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1123 pineview_display_wm
.fifo_size
,
1124 pixel_size
, latency
->cursor_sr
);
1125 reg
= I915_READ(DSPFW3
);
1126 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1127 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1128 I915_WRITE(DSPFW3
, reg
);
1130 /* Display HPLL off SR */
1131 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1132 pineview_display_hplloff_wm
.fifo_size
,
1133 pixel_size
, latency
->display_hpll_disable
);
1134 reg
= I915_READ(DSPFW3
);
1135 reg
&= ~DSPFW_HPLL_SR_MASK
;
1136 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1137 I915_WRITE(DSPFW3
, reg
);
1139 /* cursor HPLL off SR */
1140 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1141 pineview_display_hplloff_wm
.fifo_size
,
1142 pixel_size
, latency
->cursor_hpll_disable
);
1143 reg
= I915_READ(DSPFW3
);
1144 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1145 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1146 I915_WRITE(DSPFW3
, reg
);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1151 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1154 pineview_disable_cxsr(dev
);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1159 static bool g4x_compute_wm0(struct drm_device
*dev
,
1161 const struct intel_watermark_params
*display
,
1162 int display_latency_ns
,
1163 const struct intel_watermark_params
*cursor
,
1164 int cursor_latency_ns
,
1168 struct drm_crtc
*crtc
;
1169 const struct drm_display_mode
*adjusted_mode
;
1170 int htotal
, hdisplay
, clock
, pixel_size
;
1171 int line_time_us
, line_count
;
1172 int entries
, tlb_miss
;
1174 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1175 if (!intel_crtc_active(crtc
)) {
1176 *cursor_wm
= cursor
->guard_size
;
1177 *plane_wm
= display
->guard_size
;
1181 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1182 clock
= adjusted_mode
->crtc_clock
;
1183 htotal
= adjusted_mode
->htotal
;
1184 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1185 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1187 /* Use the small buffer method to calculate plane watermark */
1188 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1189 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1191 entries
+= tlb_miss
;
1192 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1193 *plane_wm
= entries
+ display
->guard_size
;
1194 if (*plane_wm
> (int)display
->max_wm
)
1195 *plane_wm
= display
->max_wm
;
1197 /* Use the large buffer method to calculate cursor watermark */
1198 line_time_us
= ((htotal
* 1000) / clock
);
1199 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1200 entries
= line_count
* 64 * pixel_size
;
1201 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1203 entries
+= tlb_miss
;
1204 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1205 *cursor_wm
= entries
+ cursor
->guard_size
;
1206 if (*cursor_wm
> (int)cursor
->max_wm
)
1207 *cursor_wm
= (int)cursor
->max_wm
;
1213 * Check the wm result.
1215 * If any calculated watermark values is larger than the maximum value that
1216 * can be programmed into the associated watermark register, that watermark
1219 static bool g4x_check_srwm(struct drm_device
*dev
,
1220 int display_wm
, int cursor_wm
,
1221 const struct intel_watermark_params
*display
,
1222 const struct intel_watermark_params
*cursor
)
1224 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1225 display_wm
, cursor_wm
);
1227 if (display_wm
> display
->max_wm
) {
1228 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1229 display_wm
, display
->max_wm
);
1233 if (cursor_wm
> cursor
->max_wm
) {
1234 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1235 cursor_wm
, cursor
->max_wm
);
1239 if (!(display_wm
|| cursor_wm
)) {
1240 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1247 static bool g4x_compute_srwm(struct drm_device
*dev
,
1250 const struct intel_watermark_params
*display
,
1251 const struct intel_watermark_params
*cursor
,
1252 int *display_wm
, int *cursor_wm
)
1254 struct drm_crtc
*crtc
;
1255 const struct drm_display_mode
*adjusted_mode
;
1256 int hdisplay
, htotal
, pixel_size
, clock
;
1257 unsigned long line_time_us
;
1258 int line_count
, line_size
;
1263 *display_wm
= *cursor_wm
= 0;
1267 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1268 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1269 clock
= adjusted_mode
->crtc_clock
;
1270 htotal
= adjusted_mode
->htotal
;
1271 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1272 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1274 line_time_us
= (htotal
* 1000) / clock
;
1275 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1276 line_size
= hdisplay
* pixel_size
;
1278 /* Use the minimum of the small and large buffer method for primary */
1279 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1280 large
= line_count
* line_size
;
1282 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1283 *display_wm
= entries
+ display
->guard_size
;
1285 /* calculate the self-refresh watermark for display cursor */
1286 entries
= line_count
* pixel_size
* 64;
1287 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1288 *cursor_wm
= entries
+ cursor
->guard_size
;
1290 return g4x_check_srwm(dev
,
1291 *display_wm
, *cursor_wm
,
1295 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1297 int *plane_prec_mult
,
1299 int *cursor_prec_mult
,
1302 struct drm_crtc
*crtc
;
1303 int clock
, pixel_size
;
1306 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1307 if (!intel_crtc_active(crtc
))
1310 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1311 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1313 entries
= (clock
/ 1000) * pixel_size
;
1314 *plane_prec_mult
= (entries
> 256) ?
1315 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1316 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1319 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1320 *cursor_prec_mult
= (entries
> 256) ?
1321 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1322 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1328 * Update drain latency registers of memory arbiter
1330 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1331 * to be programmed. Each plane has a drain latency multiplier and a drain
1335 static void vlv_update_drain_latency(struct drm_device
*dev
)
1337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1338 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1339 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1340 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1343 /* For plane A, Cursor A */
1344 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1345 &cursor_prec_mult
, &cursora_dl
)) {
1346 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1347 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1348 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1349 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1351 I915_WRITE(VLV_DDL1
, cursora_prec
|
1352 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1353 planea_prec
| planea_dl
);
1356 /* For plane B, Cursor B */
1357 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1358 &cursor_prec_mult
, &cursorb_dl
)) {
1359 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1360 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1361 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1362 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1364 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1365 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1366 planeb_prec
| planeb_dl
);
1370 #define single_plane_enabled(mask) is_power_of_2(mask)
1372 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1374 struct drm_device
*dev
= crtc
->dev
;
1375 static const int sr_latency_ns
= 12000;
1376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1377 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1378 int plane_sr
, cursor_sr
;
1379 int ignore_plane_sr
, ignore_cursor_sr
;
1380 unsigned int enabled
= 0;
1382 vlv_update_drain_latency(dev
);
1384 if (g4x_compute_wm0(dev
, PIPE_A
,
1385 &valleyview_wm_info
, latency_ns
,
1386 &valleyview_cursor_wm_info
, latency_ns
,
1387 &planea_wm
, &cursora_wm
))
1388 enabled
|= 1 << PIPE_A
;
1390 if (g4x_compute_wm0(dev
, PIPE_B
,
1391 &valleyview_wm_info
, latency_ns
,
1392 &valleyview_cursor_wm_info
, latency_ns
,
1393 &planeb_wm
, &cursorb_wm
))
1394 enabled
|= 1 << PIPE_B
;
1396 if (single_plane_enabled(enabled
) &&
1397 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1399 &valleyview_wm_info
,
1400 &valleyview_cursor_wm_info
,
1401 &plane_sr
, &ignore_cursor_sr
) &&
1402 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1404 &valleyview_wm_info
,
1405 &valleyview_cursor_wm_info
,
1406 &ignore_plane_sr
, &cursor_sr
)) {
1407 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1409 I915_WRITE(FW_BLC_SELF_VLV
,
1410 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1411 plane_sr
= cursor_sr
= 0;
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm
, cursora_wm
,
1416 planeb_wm
, cursorb_wm
,
1417 plane_sr
, cursor_sr
);
1420 (plane_sr
<< DSPFW_SR_SHIFT
) |
1421 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1422 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1425 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1426 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1428 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1429 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1432 static void g4x_update_wm(struct drm_crtc
*crtc
)
1434 struct drm_device
*dev
= crtc
->dev
;
1435 static const int sr_latency_ns
= 12000;
1436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1437 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1438 int plane_sr
, cursor_sr
;
1439 unsigned int enabled
= 0;
1441 if (g4x_compute_wm0(dev
, PIPE_A
,
1442 &g4x_wm_info
, latency_ns
,
1443 &g4x_cursor_wm_info
, latency_ns
,
1444 &planea_wm
, &cursora_wm
))
1445 enabled
|= 1 << PIPE_A
;
1447 if (g4x_compute_wm0(dev
, PIPE_B
,
1448 &g4x_wm_info
, latency_ns
,
1449 &g4x_cursor_wm_info
, latency_ns
,
1450 &planeb_wm
, &cursorb_wm
))
1451 enabled
|= 1 << PIPE_B
;
1453 if (single_plane_enabled(enabled
) &&
1454 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1457 &g4x_cursor_wm_info
,
1458 &plane_sr
, &cursor_sr
)) {
1459 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1461 I915_WRITE(FW_BLC_SELF
,
1462 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1463 plane_sr
= cursor_sr
= 0;
1466 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1467 planea_wm
, cursora_wm
,
1468 planeb_wm
, cursorb_wm
,
1469 plane_sr
, cursor_sr
);
1472 (plane_sr
<< DSPFW_SR_SHIFT
) |
1473 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1474 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1477 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1478 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1479 /* HPLL off in SR has some issues on G4x... disable it */
1481 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1482 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1485 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1487 struct drm_device
*dev
= unused_crtc
->dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 struct drm_crtc
*crtc
;
1493 /* Calc sr entries for one plane configs */
1494 crtc
= single_enabled_crtc(dev
);
1496 /* self-refresh has much higher latency */
1497 static const int sr_latency_ns
= 12000;
1498 const struct drm_display_mode
*adjusted_mode
=
1499 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1500 int clock
= adjusted_mode
->crtc_clock
;
1501 int htotal
= adjusted_mode
->htotal
;
1502 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1503 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1504 unsigned long line_time_us
;
1507 line_time_us
= ((htotal
* 1000) / clock
);
1509 /* Use ns/us then divide to preserve precision */
1510 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1511 pixel_size
* hdisplay
;
1512 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1513 srwm
= I965_FIFO_SIZE
- entries
;
1517 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1520 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1522 entries
= DIV_ROUND_UP(entries
,
1523 i965_cursor_wm_info
.cacheline_size
);
1524 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1525 (entries
+ i965_cursor_wm_info
.guard_size
);
1527 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1528 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1530 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1531 "cursor %d\n", srwm
, cursor_sr
);
1533 if (IS_CRESTLINE(dev
))
1534 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1536 /* Turn off self refresh if both pipes are enabled */
1537 if (IS_CRESTLINE(dev
))
1538 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1542 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1545 /* 965 has limitations... */
1546 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1547 (8 << 16) | (8 << 8) | (8 << 0));
1548 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1549 /* update cursor SR watermark */
1550 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1553 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1555 struct drm_device
*dev
= unused_crtc
->dev
;
1556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1557 const struct intel_watermark_params
*wm_info
;
1562 int planea_wm
, planeb_wm
;
1563 struct drm_crtc
*crtc
, *enabled
= NULL
;
1566 wm_info
= &i945_wm_info
;
1567 else if (!IS_GEN2(dev
))
1568 wm_info
= &i915_wm_info
;
1570 wm_info
= &i855_wm_info
;
1572 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1573 crtc
= intel_get_crtc_for_plane(dev
, 0);
1574 if (intel_crtc_active(crtc
)) {
1575 const struct drm_display_mode
*adjusted_mode
;
1576 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1580 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1581 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1582 wm_info
, fifo_size
, cpp
,
1586 planea_wm
= fifo_size
- wm_info
->guard_size
;
1588 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1589 crtc
= intel_get_crtc_for_plane(dev
, 1);
1590 if (intel_crtc_active(crtc
)) {
1591 const struct drm_display_mode
*adjusted_mode
;
1592 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1596 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1597 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1598 wm_info
, fifo_size
, cpp
,
1600 if (enabled
== NULL
)
1605 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1607 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1610 * Overlay gets an aggressive default since video jitter is bad.
1614 /* Play safe and disable self-refresh before adjusting watermarks. */
1615 if (IS_I945G(dev
) || IS_I945GM(dev
))
1616 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1617 else if (IS_I915GM(dev
))
1618 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1620 /* Calc sr entries for one plane configs */
1621 if (HAS_FW_BLC(dev
) && enabled
) {
1622 /* self-refresh has much higher latency */
1623 static const int sr_latency_ns
= 6000;
1624 const struct drm_display_mode
*adjusted_mode
=
1625 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1626 int clock
= adjusted_mode
->crtc_clock
;
1627 int htotal
= adjusted_mode
->htotal
;
1628 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1629 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1630 unsigned long line_time_us
;
1633 line_time_us
= (htotal
* 1000) / clock
;
1635 /* Use ns/us then divide to preserve precision */
1636 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1637 pixel_size
* hdisplay
;
1638 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1639 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1640 srwm
= wm_info
->fifo_size
- entries
;
1644 if (IS_I945G(dev
) || IS_I945GM(dev
))
1645 I915_WRITE(FW_BLC_SELF
,
1646 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1647 else if (IS_I915GM(dev
))
1648 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1651 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1652 planea_wm
, planeb_wm
, cwm
, srwm
);
1654 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1655 fwater_hi
= (cwm
& 0x1f);
1657 /* Set request length to 8 cachelines per fetch */
1658 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1659 fwater_hi
= fwater_hi
| (1 << 8);
1661 I915_WRITE(FW_BLC
, fwater_lo
);
1662 I915_WRITE(FW_BLC2
, fwater_hi
);
1664 if (HAS_FW_BLC(dev
)) {
1666 if (IS_I945G(dev
) || IS_I945GM(dev
))
1667 I915_WRITE(FW_BLC_SELF
,
1668 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1669 else if (IS_I915GM(dev
))
1670 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1671 DRM_DEBUG_KMS("memory self refresh enabled\n");
1673 DRM_DEBUG_KMS("memory self refresh disabled\n");
1677 static void i830_update_wm(struct drm_crtc
*unused_crtc
)
1679 struct drm_device
*dev
= unused_crtc
->dev
;
1680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1681 struct drm_crtc
*crtc
;
1682 const struct drm_display_mode
*adjusted_mode
;
1686 crtc
= single_enabled_crtc(dev
);
1690 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1691 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1693 dev_priv
->display
.get_fifo_size(dev
, 0),
1695 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1696 fwater_lo
|= (3<<8) | planea_wm
;
1698 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1700 I915_WRITE(FW_BLC
, fwater_lo
);
1704 * Check the wm result.
1706 * If any calculated watermark values is larger than the maximum value that
1707 * can be programmed into the associated watermark register, that watermark
1710 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1711 int fbc_wm
, int display_wm
, int cursor_wm
,
1712 const struct intel_watermark_params
*display
,
1713 const struct intel_watermark_params
*cursor
)
1715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1717 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1718 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1720 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1721 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1722 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1724 /* fbc has it's own way to disable FBC WM */
1725 I915_WRITE(DISP_ARB_CTL
,
1726 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1728 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1729 /* enable FBC WM (except on ILK, where it must remain off) */
1730 I915_WRITE(DISP_ARB_CTL
,
1731 I915_READ(DISP_ARB_CTL
) & ~DISP_FBC_WM_DIS
);
1734 if (display_wm
> display
->max_wm
) {
1735 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1736 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1740 if (cursor_wm
> cursor
->max_wm
) {
1741 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1742 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1746 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1747 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1755 * Compute watermark values of WM[1-3],
1757 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1759 const struct intel_watermark_params
*display
,
1760 const struct intel_watermark_params
*cursor
,
1761 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1763 struct drm_crtc
*crtc
;
1764 const struct drm_display_mode
*adjusted_mode
;
1765 unsigned long line_time_us
;
1766 int hdisplay
, htotal
, pixel_size
, clock
;
1767 int line_count
, line_size
;
1772 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1776 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1777 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1778 clock
= adjusted_mode
->crtc_clock
;
1779 htotal
= adjusted_mode
->htotal
;
1780 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1781 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1783 line_time_us
= (htotal
* 1000) / clock
;
1784 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1785 line_size
= hdisplay
* pixel_size
;
1787 /* Use the minimum of the small and large buffer method for primary */
1788 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1789 large
= line_count
* line_size
;
1791 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1792 *display_wm
= entries
+ display
->guard_size
;
1796 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1798 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1800 /* calculate the self-refresh watermark for display cursor */
1801 entries
= line_count
* pixel_size
* 64;
1802 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1803 *cursor_wm
= entries
+ cursor
->guard_size
;
1805 return ironlake_check_srwm(dev
, level
,
1806 *fbc_wm
, *display_wm
, *cursor_wm
,
1810 static void ironlake_update_wm(struct drm_crtc
*crtc
)
1812 struct drm_device
*dev
= crtc
->dev
;
1813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1814 int fbc_wm
, plane_wm
, cursor_wm
;
1815 unsigned int enabled
;
1818 if (g4x_compute_wm0(dev
, PIPE_A
,
1819 &ironlake_display_wm_info
,
1820 dev_priv
->wm
.pri_latency
[0] * 100,
1821 &ironlake_cursor_wm_info
,
1822 dev_priv
->wm
.cur_latency
[0] * 100,
1823 &plane_wm
, &cursor_wm
)) {
1824 I915_WRITE(WM0_PIPEA_ILK
,
1825 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1826 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1827 " plane %d, " "cursor: %d\n",
1828 plane_wm
, cursor_wm
);
1829 enabled
|= 1 << PIPE_A
;
1832 if (g4x_compute_wm0(dev
, PIPE_B
,
1833 &ironlake_display_wm_info
,
1834 dev_priv
->wm
.pri_latency
[0] * 100,
1835 &ironlake_cursor_wm_info
,
1836 dev_priv
->wm
.cur_latency
[0] * 100,
1837 &plane_wm
, &cursor_wm
)) {
1838 I915_WRITE(WM0_PIPEB_ILK
,
1839 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1840 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1841 " plane %d, cursor: %d\n",
1842 plane_wm
, cursor_wm
);
1843 enabled
|= 1 << PIPE_B
;
1847 * Calculate and update the self-refresh watermark only when one
1848 * display plane is used.
1850 I915_WRITE(WM3_LP_ILK
, 0);
1851 I915_WRITE(WM2_LP_ILK
, 0);
1852 I915_WRITE(WM1_LP_ILK
, 0);
1854 if (!single_plane_enabled(enabled
))
1856 enabled
= ffs(enabled
) - 1;
1859 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1860 dev_priv
->wm
.pri_latency
[1] * 500,
1861 &ironlake_display_srwm_info
,
1862 &ironlake_cursor_srwm_info
,
1863 &fbc_wm
, &plane_wm
, &cursor_wm
))
1866 I915_WRITE(WM1_LP_ILK
,
1868 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
1869 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1870 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1874 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1875 dev_priv
->wm
.pri_latency
[2] * 500,
1876 &ironlake_display_srwm_info
,
1877 &ironlake_cursor_srwm_info
,
1878 &fbc_wm
, &plane_wm
, &cursor_wm
))
1881 I915_WRITE(WM2_LP_ILK
,
1883 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
1884 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1885 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1889 * WM3 is unsupported on ILK, probably because we don't have latency
1890 * data for that power state
1894 static void sandybridge_update_wm(struct drm_crtc
*crtc
)
1896 struct drm_device
*dev
= crtc
->dev
;
1897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1898 int latency
= dev_priv
->wm
.pri_latency
[0] * 100; /* In unit 0.1us */
1900 int fbc_wm
, plane_wm
, cursor_wm
;
1901 unsigned int enabled
;
1904 if (g4x_compute_wm0(dev
, PIPE_A
,
1905 &sandybridge_display_wm_info
, latency
,
1906 &sandybridge_cursor_wm_info
, latency
,
1907 &plane_wm
, &cursor_wm
)) {
1908 val
= I915_READ(WM0_PIPEA_ILK
);
1909 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1910 I915_WRITE(WM0_PIPEA_ILK
, val
|
1911 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1912 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1913 " plane %d, " "cursor: %d\n",
1914 plane_wm
, cursor_wm
);
1915 enabled
|= 1 << PIPE_A
;
1918 if (g4x_compute_wm0(dev
, PIPE_B
,
1919 &sandybridge_display_wm_info
, latency
,
1920 &sandybridge_cursor_wm_info
, latency
,
1921 &plane_wm
, &cursor_wm
)) {
1922 val
= I915_READ(WM0_PIPEB_ILK
);
1923 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1924 I915_WRITE(WM0_PIPEB_ILK
, val
|
1925 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1926 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1927 " plane %d, cursor: %d\n",
1928 plane_wm
, cursor_wm
);
1929 enabled
|= 1 << PIPE_B
;
1933 * Calculate and update the self-refresh watermark only when one
1934 * display plane is used.
1936 * SNB support 3 levels of watermark.
1938 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1939 * and disabled in the descending order
1942 I915_WRITE(WM3_LP_ILK
, 0);
1943 I915_WRITE(WM2_LP_ILK
, 0);
1944 I915_WRITE(WM1_LP_ILK
, 0);
1946 if (!single_plane_enabled(enabled
) ||
1947 dev_priv
->sprite_scaling_enabled
)
1949 enabled
= ffs(enabled
) - 1;
1952 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1953 dev_priv
->wm
.pri_latency
[1] * 500,
1954 &sandybridge_display_srwm_info
,
1955 &sandybridge_cursor_srwm_info
,
1956 &fbc_wm
, &plane_wm
, &cursor_wm
))
1959 I915_WRITE(WM1_LP_ILK
,
1961 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
1962 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1963 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1967 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1968 dev_priv
->wm
.pri_latency
[2] * 500,
1969 &sandybridge_display_srwm_info
,
1970 &sandybridge_cursor_srwm_info
,
1971 &fbc_wm
, &plane_wm
, &cursor_wm
))
1974 I915_WRITE(WM2_LP_ILK
,
1976 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
1977 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1978 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1982 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1983 dev_priv
->wm
.pri_latency
[3] * 500,
1984 &sandybridge_display_srwm_info
,
1985 &sandybridge_cursor_srwm_info
,
1986 &fbc_wm
, &plane_wm
, &cursor_wm
))
1989 I915_WRITE(WM3_LP_ILK
,
1991 (dev_priv
->wm
.pri_latency
[3] << WM1_LP_LATENCY_SHIFT
) |
1992 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1993 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1997 static void ivybridge_update_wm(struct drm_crtc
*crtc
)
1999 struct drm_device
*dev
= crtc
->dev
;
2000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 int latency
= dev_priv
->wm
.pri_latency
[0] * 100; /* In unit 0.1us */
2003 int fbc_wm
, plane_wm
, cursor_wm
;
2004 int ignore_fbc_wm
, ignore_plane_wm
, ignore_cursor_wm
;
2005 unsigned int enabled
;
2008 if (g4x_compute_wm0(dev
, PIPE_A
,
2009 &sandybridge_display_wm_info
, latency
,
2010 &sandybridge_cursor_wm_info
, latency
,
2011 &plane_wm
, &cursor_wm
)) {
2012 val
= I915_READ(WM0_PIPEA_ILK
);
2013 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2014 I915_WRITE(WM0_PIPEA_ILK
, val
|
2015 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2016 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2017 " plane %d, " "cursor: %d\n",
2018 plane_wm
, cursor_wm
);
2019 enabled
|= 1 << PIPE_A
;
2022 if (g4x_compute_wm0(dev
, PIPE_B
,
2023 &sandybridge_display_wm_info
, latency
,
2024 &sandybridge_cursor_wm_info
, latency
,
2025 &plane_wm
, &cursor_wm
)) {
2026 val
= I915_READ(WM0_PIPEB_ILK
);
2027 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2028 I915_WRITE(WM0_PIPEB_ILK
, val
|
2029 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2030 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2031 " plane %d, cursor: %d\n",
2032 plane_wm
, cursor_wm
);
2033 enabled
|= 1 << PIPE_B
;
2036 if (g4x_compute_wm0(dev
, PIPE_C
,
2037 &sandybridge_display_wm_info
, latency
,
2038 &sandybridge_cursor_wm_info
, latency
,
2039 &plane_wm
, &cursor_wm
)) {
2040 val
= I915_READ(WM0_PIPEC_IVB
);
2041 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2042 I915_WRITE(WM0_PIPEC_IVB
, val
|
2043 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2044 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2045 " plane %d, cursor: %d\n",
2046 plane_wm
, cursor_wm
);
2047 enabled
|= 1 << PIPE_C
;
2051 * Calculate and update the self-refresh watermark only when one
2052 * display plane is used.
2054 * SNB support 3 levels of watermark.
2056 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2057 * and disabled in the descending order
2060 I915_WRITE(WM3_LP_ILK
, 0);
2061 I915_WRITE(WM2_LP_ILK
, 0);
2062 I915_WRITE(WM1_LP_ILK
, 0);
2064 if (!single_plane_enabled(enabled
) ||
2065 dev_priv
->sprite_scaling_enabled
)
2067 enabled
= ffs(enabled
) - 1;
2070 if (!ironlake_compute_srwm(dev
, 1, enabled
,
2071 dev_priv
->wm
.pri_latency
[1] * 500,
2072 &sandybridge_display_srwm_info
,
2073 &sandybridge_cursor_srwm_info
,
2074 &fbc_wm
, &plane_wm
, &cursor_wm
))
2077 I915_WRITE(WM1_LP_ILK
,
2079 (dev_priv
->wm
.pri_latency
[1] << WM1_LP_LATENCY_SHIFT
) |
2080 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2081 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2085 if (!ironlake_compute_srwm(dev
, 2, enabled
,
2086 dev_priv
->wm
.pri_latency
[2] * 500,
2087 &sandybridge_display_srwm_info
,
2088 &sandybridge_cursor_srwm_info
,
2089 &fbc_wm
, &plane_wm
, &cursor_wm
))
2092 I915_WRITE(WM2_LP_ILK
,
2094 (dev_priv
->wm
.pri_latency
[2] << WM1_LP_LATENCY_SHIFT
) |
2095 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2096 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2099 /* WM3, note we have to correct the cursor latency */
2100 if (!ironlake_compute_srwm(dev
, 3, enabled
,
2101 dev_priv
->wm
.pri_latency
[3] * 500,
2102 &sandybridge_display_srwm_info
,
2103 &sandybridge_cursor_srwm_info
,
2104 &fbc_wm
, &plane_wm
, &ignore_cursor_wm
) ||
2105 !ironlake_compute_srwm(dev
, 3, enabled
,
2106 dev_priv
->wm
.cur_latency
[3] * 500,
2107 &sandybridge_display_srwm_info
,
2108 &sandybridge_cursor_srwm_info
,
2109 &ignore_fbc_wm
, &ignore_plane_wm
, &cursor_wm
))
2112 I915_WRITE(WM3_LP_ILK
,
2114 (dev_priv
->wm
.pri_latency
[3] << WM1_LP_LATENCY_SHIFT
) |
2115 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2116 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2120 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
2121 struct drm_crtc
*crtc
)
2123 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2124 uint32_t pixel_rate
;
2126 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
2128 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2129 * adjust the pixel_rate here. */
2131 if (intel_crtc
->config
.pch_pfit
.enabled
) {
2132 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
2133 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
2135 pipe_w
= intel_crtc
->config
.pipe_src_w
;
2136 pipe_h
= intel_crtc
->config
.pipe_src_h
;
2137 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
2138 pfit_h
= pfit_size
& 0xFFFF;
2139 if (pipe_w
< pfit_w
)
2141 if (pipe_h
< pfit_h
)
2144 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
2151 /* latency must be in 0.1us units. */
2152 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2157 if (WARN(latency
== 0, "Latency value missing\n"))
2160 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
2161 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
2166 /* latency must be in 0.1us units. */
2167 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2168 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2173 if (WARN(latency
== 0, "Latency value missing\n"))
2176 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
2177 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
2178 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2182 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2183 uint8_t bytes_per_pixel
)
2185 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
2188 struct hsw_pipe_wm_parameters
{
2190 uint32_t pipe_htotal
;
2191 uint32_t pixel_rate
;
2192 struct intel_plane_wm_parameters pri
;
2193 struct intel_plane_wm_parameters spr
;
2194 struct intel_plane_wm_parameters cur
;
2197 struct hsw_wm_maximums
{
2204 /* used in computing the new watermarks state */
2205 struct intel_wm_config
{
2206 unsigned int num_pipes_active
;
2207 bool sprites_enabled
;
2208 bool sprites_scaled
;
2212 * For both WM_PIPE and WM_LP.
2213 * mem_value must be in 0.1us units.
2215 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters
*params
,
2219 uint32_t method1
, method2
;
2221 if (!params
->active
|| !params
->pri
.enabled
)
2224 method1
= ilk_wm_method1(params
->pixel_rate
,
2225 params
->pri
.bytes_per_pixel
,
2231 method2
= ilk_wm_method2(params
->pixel_rate
,
2232 params
->pipe_htotal
,
2233 params
->pri
.horiz_pixels
,
2234 params
->pri
.bytes_per_pixel
,
2237 return min(method1
, method2
);
2241 * For both WM_PIPE and WM_LP.
2242 * mem_value must be in 0.1us units.
2244 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters
*params
,
2247 uint32_t method1
, method2
;
2249 if (!params
->active
|| !params
->spr
.enabled
)
2252 method1
= ilk_wm_method1(params
->pixel_rate
,
2253 params
->spr
.bytes_per_pixel
,
2255 method2
= ilk_wm_method2(params
->pixel_rate
,
2256 params
->pipe_htotal
,
2257 params
->spr
.horiz_pixels
,
2258 params
->spr
.bytes_per_pixel
,
2260 return min(method1
, method2
);
2264 * For both WM_PIPE and WM_LP.
2265 * mem_value must be in 0.1us units.
2267 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters
*params
,
2270 if (!params
->active
|| !params
->cur
.enabled
)
2273 return ilk_wm_method2(params
->pixel_rate
,
2274 params
->pipe_htotal
,
2275 params
->cur
.horiz_pixels
,
2276 params
->cur
.bytes_per_pixel
,
2280 /* Only for WM_LP. */
2281 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters
*params
,
2284 if (!params
->active
|| !params
->pri
.enabled
)
2287 return ilk_wm_fbc(pri_val
,
2288 params
->pri
.horiz_pixels
,
2289 params
->pri
.bytes_per_pixel
);
2292 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
2294 if (INTEL_INFO(dev
)->gen
>= 8)
2296 else if (INTEL_INFO(dev
)->gen
>= 7)
2302 /* Calculate the maximum primary/sprite plane watermark */
2303 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2305 const struct intel_wm_config
*config
,
2306 enum intel_ddb_partitioning ddb_partitioning
,
2309 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
2312 /* if sprites aren't enabled, sprites get nothing */
2313 if (is_sprite
&& !config
->sprites_enabled
)
2316 /* HSW allows LP1+ watermarks even with multiple pipes */
2317 if (level
== 0 || config
->num_pipes_active
> 1) {
2318 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
2321 * For some reason the non self refresh
2322 * FIFO size is only half of the self
2323 * refresh FIFO size on ILK/SNB.
2325 if (INTEL_INFO(dev
)->gen
<= 6)
2329 if (config
->sprites_enabled
) {
2330 /* level 0 is always calculated with 1:1 split */
2331 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2340 /* clamp to max that the registers can hold */
2341 if (INTEL_INFO(dev
)->gen
>= 8)
2342 max
= level
== 0 ? 255 : 2047;
2343 else if (INTEL_INFO(dev
)->gen
>= 7)
2344 /* IVB/HSW primary/sprite plane watermarks */
2345 max
= level
== 0 ? 127 : 1023;
2346 else if (!is_sprite
)
2347 /* ILK/SNB primary plane watermarks */
2348 max
= level
== 0 ? 127 : 511;
2350 /* ILK/SNB sprite plane watermarks */
2351 max
= level
== 0 ? 63 : 255;
2353 return min(fifo_size
, max
);
2356 /* Calculate the maximum cursor plane watermark */
2357 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2359 const struct intel_wm_config
*config
)
2361 /* HSW LP1+ watermarks w/ multiple pipes */
2362 if (level
> 0 && config
->num_pipes_active
> 1)
2365 /* otherwise just report max that registers can hold */
2366 if (INTEL_INFO(dev
)->gen
>= 7)
2367 return level
== 0 ? 63 : 255;
2369 return level
== 0 ? 31 : 63;
2372 /* Calculate the maximum FBC watermark */
2373 static unsigned int ilk_fbc_wm_max(struct drm_device
*dev
)
2375 /* max that registers can hold */
2376 if (INTEL_INFO(dev
)->gen
>= 8)
2382 static void ilk_compute_wm_maximums(struct drm_device
*dev
,
2384 const struct intel_wm_config
*config
,
2385 enum intel_ddb_partitioning ddb_partitioning
,
2386 struct hsw_wm_maximums
*max
)
2388 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2389 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2390 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2391 max
->fbc
= ilk_fbc_wm_max(dev
);
2394 static bool ilk_validate_wm_level(int level
,
2395 const struct hsw_wm_maximums
*max
,
2396 struct intel_wm_level
*result
)
2400 /* already determined to be invalid? */
2401 if (!result
->enable
)
2404 result
->enable
= result
->pri_val
<= max
->pri
&&
2405 result
->spr_val
<= max
->spr
&&
2406 result
->cur_val
<= max
->cur
;
2408 ret
= result
->enable
;
2411 * HACK until we can pre-compute everything,
2412 * and thus fail gracefully if LP0 watermarks
2415 if (level
== 0 && !result
->enable
) {
2416 if (result
->pri_val
> max
->pri
)
2417 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2418 level
, result
->pri_val
, max
->pri
);
2419 if (result
->spr_val
> max
->spr
)
2420 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2421 level
, result
->spr_val
, max
->spr
);
2422 if (result
->cur_val
> max
->cur
)
2423 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2424 level
, result
->cur_val
, max
->cur
);
2426 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2427 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2428 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2429 result
->enable
= true;
2435 static void ilk_compute_wm_level(struct drm_i915_private
*dev_priv
,
2437 const struct hsw_pipe_wm_parameters
*p
,
2438 struct intel_wm_level
*result
)
2440 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2441 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2442 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2444 /* WM1+ latency values stored in 0.5us units */
2451 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2452 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2453 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2454 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2455 result
->enable
= true;
2459 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2463 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2464 u32 linetime
, ips_linetime
;
2466 if (!intel_crtc_active(crtc
))
2469 /* The WM are computed with base on how long it takes to fill a single
2470 * row at the given clock rate, multiplied by 8.
2472 linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8, mode
->clock
);
2473 ips_linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8,
2474 intel_ddi_get_cdclk_freq(dev_priv
));
2476 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2477 PIPE_WM_LINETIME_TIME(linetime
);
2480 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2484 if (IS_HASWELL(dev
)) {
2485 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2487 wm
[0] = (sskpd
>> 56) & 0xFF;
2489 wm
[0] = sskpd
& 0xF;
2490 wm
[1] = (sskpd
>> 4) & 0xFF;
2491 wm
[2] = (sskpd
>> 12) & 0xFF;
2492 wm
[3] = (sskpd
>> 20) & 0x1FF;
2493 wm
[4] = (sskpd
>> 32) & 0x1FF;
2494 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2495 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2497 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2498 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2499 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2500 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2501 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2502 uint32_t mltr
= I915_READ(MLTR_ILK
);
2504 /* ILK primary LP0 latency is 700 ns */
2506 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2507 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2511 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2513 /* ILK sprite LP0 latency is 1300 ns */
2514 if (INTEL_INFO(dev
)->gen
== 5)
2518 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2520 /* ILK cursor LP0 latency is 1300 ns */
2521 if (INTEL_INFO(dev
)->gen
== 5)
2524 /* WaDoubleCursorLP3Latency:ivb */
2525 if (IS_IVYBRIDGE(dev
))
2529 static int ilk_wm_max_level(const struct drm_device
*dev
)
2531 /* how many WM levels are we expecting */
2532 if (IS_HASWELL(dev
))
2534 else if (INTEL_INFO(dev
)->gen
>= 6)
2540 static void intel_print_wm_latency(struct drm_device
*dev
,
2542 const uint16_t wm
[5])
2544 int level
, max_level
= ilk_wm_max_level(dev
);
2546 for (level
= 0; level
<= max_level
; level
++) {
2547 unsigned int latency
= wm
[level
];
2550 DRM_ERROR("%s WM%d latency not provided\n",
2555 /* WM1+ latency values in 0.5us units */
2559 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2560 name
, level
, wm
[level
],
2561 latency
/ 10, latency
% 10);
2565 static void intel_setup_wm_latency(struct drm_device
*dev
)
2567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2571 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2572 sizeof(dev_priv
->wm
.pri_latency
));
2573 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2574 sizeof(dev_priv
->wm
.pri_latency
));
2576 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2577 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2579 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2580 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2581 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2584 static void hsw_compute_wm_parameters(struct drm_crtc
*crtc
,
2585 struct hsw_pipe_wm_parameters
*p
,
2586 struct intel_wm_config
*config
)
2588 struct drm_device
*dev
= crtc
->dev
;
2589 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2590 enum pipe pipe
= intel_crtc
->pipe
;
2591 struct drm_plane
*plane
;
2593 p
->active
= intel_crtc_active(crtc
);
2595 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.htotal
;
2596 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2597 p
->pri
.bytes_per_pixel
= crtc
->fb
->bits_per_pixel
/ 8;
2598 p
->cur
.bytes_per_pixel
= 4;
2599 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2600 p
->cur
.horiz_pixels
= 64;
2601 /* TODO: for now, assume primary and cursor planes are always enabled. */
2602 p
->pri
.enabled
= true;
2603 p
->cur
.enabled
= true;
2606 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
2607 config
->num_pipes_active
+= intel_crtc_active(crtc
);
2609 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2610 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2612 if (intel_plane
->pipe
== pipe
)
2613 p
->spr
= intel_plane
->wm
;
2615 config
->sprites_enabled
|= intel_plane
->wm
.enabled
;
2616 config
->sprites_scaled
|= intel_plane
->wm
.scaled
;
2620 /* Compute new watermarks for the pipe */
2621 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2622 const struct hsw_pipe_wm_parameters
*params
,
2623 struct intel_pipe_wm
*pipe_wm
)
2625 struct drm_device
*dev
= crtc
->dev
;
2626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2627 int level
, max_level
= ilk_wm_max_level(dev
);
2628 /* LP0 watermark maximums depend on this pipe alone */
2629 struct intel_wm_config config
= {
2630 .num_pipes_active
= 1,
2631 .sprites_enabled
= params
->spr
.enabled
,
2632 .sprites_scaled
= params
->spr
.scaled
,
2634 struct hsw_wm_maximums max
;
2636 /* LP0 watermarks always use 1/2 DDB partitioning */
2637 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2639 for (level
= 0; level
<= max_level
; level
++)
2640 ilk_compute_wm_level(dev_priv
, level
, params
,
2641 &pipe_wm
->wm
[level
]);
2643 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2645 /* At least LP0 must be valid */
2646 return ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]);
2650 * Merge the watermarks from all active pipes for a specific level.
2652 static void ilk_merge_wm_level(struct drm_device
*dev
,
2654 struct intel_wm_level
*ret_wm
)
2656 const struct intel_crtc
*intel_crtc
;
2658 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2659 const struct intel_wm_level
*wm
=
2660 &intel_crtc
->wm
.active
.wm
[level
];
2665 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2666 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2667 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2668 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2671 ret_wm
->enable
= true;
2675 * Merge all low power watermarks for all active pipes.
2677 static void ilk_wm_merge(struct drm_device
*dev
,
2678 const struct hsw_wm_maximums
*max
,
2679 struct intel_pipe_wm
*merged
)
2681 int level
, max_level
= ilk_wm_max_level(dev
);
2683 merged
->fbc_wm_enabled
= true;
2685 /* merge each WM1+ level */
2686 for (level
= 1; level
<= max_level
; level
++) {
2687 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2689 ilk_merge_wm_level(dev
, level
, wm
);
2691 if (!ilk_validate_wm_level(level
, max
, wm
))
2695 * The spec says it is preferred to disable
2696 * FBC WMs instead of disabling a WM level.
2698 if (wm
->fbc_val
> max
->fbc
) {
2699 merged
->fbc_wm_enabled
= false;
2705 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2707 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2708 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2711 static void hsw_compute_wm_results(struct drm_device
*dev
,
2712 const struct intel_pipe_wm
*merged
,
2713 enum intel_ddb_partitioning partitioning
,
2714 struct hsw_wm_values
*results
)
2716 struct intel_crtc
*intel_crtc
;
2719 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2720 results
->partitioning
= partitioning
;
2722 /* LP1+ register values */
2723 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2724 const struct intel_wm_level
*r
;
2726 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2728 r
= &merged
->wm
[level
];
2732 results
->wm_lp
[wm_lp
- 1] = WM3_LP_EN
|
2733 ((level
* 2) << WM1_LP_LATENCY_SHIFT
) |
2734 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2737 if (INTEL_INFO(dev
)->gen
>= 8)
2738 results
->wm_lp
[wm_lp
- 1] |=
2739 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2741 results
->wm_lp
[wm_lp
- 1] |=
2742 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2744 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2747 /* LP0 register values */
2748 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2749 enum pipe pipe
= intel_crtc
->pipe
;
2750 const struct intel_wm_level
*r
=
2751 &intel_crtc
->wm
.active
.wm
[0];
2753 if (WARN_ON(!r
->enable
))
2756 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2758 results
->wm_pipe
[pipe
] =
2759 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2760 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2765 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2766 * case both are at the same level. Prefer r1 in case they're the same. */
2767 static struct intel_pipe_wm
*hsw_find_best_result(struct drm_device
*dev
,
2768 struct intel_pipe_wm
*r1
,
2769 struct intel_pipe_wm
*r2
)
2771 int level
, max_level
= ilk_wm_max_level(dev
);
2772 int level1
= 0, level2
= 0;
2774 for (level
= 1; level
<= max_level
; level
++) {
2775 if (r1
->wm
[level
].enable
)
2777 if (r2
->wm
[level
].enable
)
2781 if (level1
== level2
) {
2782 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2786 } else if (level1
> level2
) {
2793 /* dirty bits used to track which watermarks need changes */
2794 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2795 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2796 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2797 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2798 #define WM_DIRTY_FBC (1 << 24)
2799 #define WM_DIRTY_DDB (1 << 25)
2801 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2802 const struct hsw_wm_values
*old
,
2803 const struct hsw_wm_values
*new)
2805 unsigned int dirty
= 0;
2809 for_each_pipe(pipe
) {
2810 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2811 dirty
|= WM_DIRTY_LINETIME(pipe
);
2812 /* Must disable LP1+ watermarks too */
2813 dirty
|= WM_DIRTY_LP_ALL
;
2816 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2817 dirty
|= WM_DIRTY_PIPE(pipe
);
2818 /* Must disable LP1+ watermarks too */
2819 dirty
|= WM_DIRTY_LP_ALL
;
2823 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2824 dirty
|= WM_DIRTY_FBC
;
2825 /* Must disable LP1+ watermarks too */
2826 dirty
|= WM_DIRTY_LP_ALL
;
2829 if (old
->partitioning
!= new->partitioning
) {
2830 dirty
|= WM_DIRTY_DDB
;
2831 /* Must disable LP1+ watermarks too */
2832 dirty
|= WM_DIRTY_LP_ALL
;
2835 /* LP1+ watermarks already deemed dirty, no need to continue */
2836 if (dirty
& WM_DIRTY_LP_ALL
)
2839 /* Find the lowest numbered LP1+ watermark in need of an update... */
2840 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2841 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2842 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2846 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2847 for (; wm_lp
<= 3; wm_lp
++)
2848 dirty
|= WM_DIRTY_LP(wm_lp
);
2854 * The spec says we shouldn't write when we don't need, because every write
2855 * causes WMs to be re-evaluated, expending some power.
2857 static void hsw_write_wm_values(struct drm_i915_private
*dev_priv
,
2858 struct hsw_wm_values
*results
)
2860 struct hsw_wm_values
*previous
= &dev_priv
->wm
.hw
;
2864 dirty
= ilk_compute_wm_dirty(dev_priv
->dev
, previous
, results
);
2868 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != 0)
2869 I915_WRITE(WM3_LP_ILK
, 0);
2870 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != 0)
2871 I915_WRITE(WM2_LP_ILK
, 0);
2872 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != 0)
2873 I915_WRITE(WM1_LP_ILK
, 0);
2875 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2876 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2877 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2878 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2879 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2880 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2882 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2883 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2884 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2885 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2886 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2887 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2889 if (dirty
& WM_DIRTY_DDB
) {
2890 val
= I915_READ(WM_MISC
);
2891 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2892 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2894 val
|= WM_MISC_DATA_PARTITION_5_6
;
2895 I915_WRITE(WM_MISC
, val
);
2898 if (dirty
& WM_DIRTY_FBC
) {
2899 val
= I915_READ(DISP_ARB_CTL
);
2900 if (results
->enable_fbc_wm
)
2901 val
&= ~DISP_FBC_WM_DIS
;
2903 val
|= DISP_FBC_WM_DIS
;
2904 I915_WRITE(DISP_ARB_CTL
, val
);
2907 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2908 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2909 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2910 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2911 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2912 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2914 if (dirty
& WM_DIRTY_LP(1) && results
->wm_lp
[0] != 0)
2915 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2916 if (dirty
& WM_DIRTY_LP(2) && results
->wm_lp
[1] != 0)
2917 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2918 if (dirty
& WM_DIRTY_LP(3) && results
->wm_lp
[2] != 0)
2919 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2921 dev_priv
->wm
.hw
= *results
;
2924 static void haswell_update_wm(struct drm_crtc
*crtc
)
2926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2927 struct drm_device
*dev
= crtc
->dev
;
2928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2929 struct hsw_wm_maximums max
;
2930 struct hsw_pipe_wm_parameters params
= {};
2931 struct hsw_wm_values results
= {};
2932 enum intel_ddb_partitioning partitioning
;
2933 struct intel_pipe_wm pipe_wm
= {};
2934 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2935 struct intel_wm_config config
= {};
2937 hsw_compute_wm_parameters(crtc
, ¶ms
, &config
);
2939 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2941 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2944 intel_crtc
->wm
.active
= pipe_wm
;
2946 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2947 ilk_wm_merge(dev
, &max
, &lp_wm_1_2
);
2949 /* 5/6 split only in single pipe config on IVB+ */
2950 if (INTEL_INFO(dev
)->gen
>= 7 &&
2951 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2952 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2953 ilk_wm_merge(dev
, &max
, &lp_wm_5_6
);
2955 best_lp_wm
= hsw_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2957 best_lp_wm
= &lp_wm_1_2
;
2960 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2961 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2963 hsw_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2965 hsw_write_wm_values(dev_priv
, &results
);
2968 static void haswell_update_sprite_wm(struct drm_plane
*plane
,
2969 struct drm_crtc
*crtc
,
2970 uint32_t sprite_width
, int pixel_size
,
2971 bool enabled
, bool scaled
)
2973 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2975 intel_plane
->wm
.enabled
= enabled
;
2976 intel_plane
->wm
.scaled
= scaled
;
2977 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2978 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2980 haswell_update_wm(crtc
);
2984 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
2985 uint32_t sprite_width
, int pixel_size
,
2986 const struct intel_watermark_params
*display
,
2987 int display_latency_ns
, int *sprite_wm
)
2989 struct drm_crtc
*crtc
;
2991 int entries
, tlb_miss
;
2993 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2994 if (!intel_crtc_active(crtc
)) {
2995 *sprite_wm
= display
->guard_size
;
2999 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3001 /* Use the small buffer method to calculate the sprite watermark */
3002 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
3003 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
3006 entries
+= tlb_miss
;
3007 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
3008 *sprite_wm
= entries
+ display
->guard_size
;
3009 if (*sprite_wm
> (int)display
->max_wm
)
3010 *sprite_wm
= display
->max_wm
;
3016 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
3017 uint32_t sprite_width
, int pixel_size
,
3018 const struct intel_watermark_params
*display
,
3019 int latency_ns
, int *sprite_wm
)
3021 struct drm_crtc
*crtc
;
3022 unsigned long line_time_us
;
3024 int line_count
, line_size
;
3033 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3034 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3040 line_time_us
= (sprite_width
* 1000) / clock
;
3041 if (!line_time_us
) {
3046 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
3047 line_size
= sprite_width
* pixel_size
;
3049 /* Use the minimum of the small and large buffer method for primary */
3050 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
3051 large
= line_count
* line_size
;
3053 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
3054 *sprite_wm
= entries
+ display
->guard_size
;
3056 return *sprite_wm
> 0x3ff ? false : true;
3059 static void sandybridge_update_sprite_wm(struct drm_plane
*plane
,
3060 struct drm_crtc
*crtc
,
3061 uint32_t sprite_width
, int pixel_size
,
3062 bool enabled
, bool scaled
)
3064 struct drm_device
*dev
= plane
->dev
;
3065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3066 int pipe
= to_intel_plane(plane
)->pipe
;
3067 int latency
= dev_priv
->wm
.spr_latency
[0] * 100; /* In unit 0.1us */
3077 reg
= WM0_PIPEA_ILK
;
3080 reg
= WM0_PIPEB_ILK
;
3083 reg
= WM0_PIPEC_IVB
;
3086 return; /* bad pipe */
3089 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
3090 &sandybridge_display_wm_info
,
3091 latency
, &sprite_wm
);
3093 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3098 val
= I915_READ(reg
);
3099 val
&= ~WM0_PIPE_SPRITE_MASK
;
3100 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
3101 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe
), sprite_wm
);
3104 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3106 &sandybridge_display_srwm_info
,
3107 dev_priv
->wm
.spr_latency
[1] * 500,
3110 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3114 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
3116 /* Only IVB has two more LP watermarks for sprite */
3117 if (!IS_IVYBRIDGE(dev
))
3120 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3122 &sandybridge_display_srwm_info
,
3123 dev_priv
->wm
.spr_latency
[2] * 500,
3126 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3130 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
3132 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
3134 &sandybridge_display_srwm_info
,
3135 dev_priv
->wm
.spr_latency
[3] * 500,
3138 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3142 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
3145 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3147 struct drm_device
*dev
= crtc
->dev
;
3148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3149 struct hsw_wm_values
*hw
= &dev_priv
->wm
.hw
;
3150 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3151 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
3152 enum pipe pipe
= intel_crtc
->pipe
;
3153 static const unsigned int wm0_pipe_reg
[] = {
3154 [PIPE_A
] = WM0_PIPEA_ILK
,
3155 [PIPE_B
] = WM0_PIPEB_ILK
,
3156 [PIPE_C
] = WM0_PIPEC_IVB
,
3159 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3160 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3162 if (intel_crtc_active(crtc
)) {
3163 u32 tmp
= hw
->wm_pipe
[pipe
];
3166 * For active pipes LP0 watermark is marked as
3167 * enabled, and LP1+ watermaks as disabled since
3168 * we can't really reverse compute them in case
3169 * multiple pipes are active.
3171 active
->wm
[0].enable
= true;
3172 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3173 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3174 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3175 active
->linetime
= hw
->wm_linetime
[pipe
];
3177 int level
, max_level
= ilk_wm_max_level(dev
);
3180 * For inactive pipes, all watermark levels
3181 * should be marked as enabled but zeroed,
3182 * which is what we'd compute them to.
3184 for (level
= 0; level
<= max_level
; level
++)
3185 active
->wm
[level
].enable
= true;
3189 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3192 struct hsw_wm_values
*hw
= &dev_priv
->wm
.hw
;
3193 struct drm_crtc
*crtc
;
3195 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3196 ilk_pipe_wm_get_hw_state(crtc
);
3198 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3199 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3200 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3202 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3203 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3204 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3206 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3207 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3210 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3214 * intel_update_watermarks - update FIFO watermark values based on current modes
3216 * Calculate watermark values for the various WM regs based on current mode
3217 * and plane configuration.
3219 * There are several cases to deal with here:
3220 * - normal (i.e. non-self-refresh)
3221 * - self-refresh (SR) mode
3222 * - lines are large relative to FIFO size (buffer can hold up to 2)
3223 * - lines are small relative to FIFO size (buffer can hold more than 2
3224 * lines), so need to account for TLB latency
3226 * The normal calculation is:
3227 * watermark = dotclock * bytes per pixel * latency
3228 * where latency is platform & configuration dependent (we assume pessimal
3231 * The SR calculation is:
3232 * watermark = (trunc(latency/line time)+1) * surface width *
3235 * line time = htotal / dotclock
3236 * surface width = hdisplay for normal plane and 64 for cursor
3237 * and latency is assumed to be high, as above.
3239 * The final value programmed to the register should always be rounded up,
3240 * and include an extra 2 entries to account for clock crossings.
3242 * We don't use the sprite, so we can ignore that. And on Crestline we have
3243 * to set the non-SR watermarks to 8.
3245 void intel_update_watermarks(struct drm_crtc
*crtc
)
3247 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3249 if (dev_priv
->display
.update_wm
)
3250 dev_priv
->display
.update_wm(crtc
);
3253 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
3254 struct drm_crtc
*crtc
,
3255 uint32_t sprite_width
, int pixel_size
,
3256 bool enabled
, bool scaled
)
3258 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
3260 if (dev_priv
->display
.update_sprite_wm
)
3261 dev_priv
->display
.update_sprite_wm(plane
, crtc
, sprite_width
,
3262 pixel_size
, enabled
, scaled
);
3265 static struct drm_i915_gem_object
*
3266 intel_alloc_context_page(struct drm_device
*dev
)
3268 struct drm_i915_gem_object
*ctx
;
3271 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3273 ctx
= i915_gem_alloc_object(dev
, 4096);
3275 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3279 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, true, false);
3281 DRM_ERROR("failed to pin power context: %d\n", ret
);
3285 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
3287 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
3294 i915_gem_object_unpin(ctx
);
3296 drm_gem_object_unreference(&ctx
->base
);
3301 * Lock protecting IPS related data structures
3303 DEFINE_SPINLOCK(mchdev_lock
);
3305 /* Global for IPS driver to get at the current i915 device. Protected by
3307 static struct drm_i915_private
*i915_mch_dev
;
3309 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3314 assert_spin_locked(&mchdev_lock
);
3316 rgvswctl
= I915_READ16(MEMSWCTL
);
3317 if (rgvswctl
& MEMCTL_CMD_STS
) {
3318 DRM_DEBUG("gpu busy, RCS change rejected\n");
3319 return false; /* still busy with another command */
3322 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3323 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3324 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3325 POSTING_READ16(MEMSWCTL
);
3327 rgvswctl
|= MEMCTL_CMD_STS
;
3328 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3333 static void ironlake_enable_drps(struct drm_device
*dev
)
3335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3336 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3337 u8 fmax
, fmin
, fstart
, vstart
;
3339 spin_lock_irq(&mchdev_lock
);
3341 /* Enable temp reporting */
3342 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3343 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3345 /* 100ms RC evaluation intervals */
3346 I915_WRITE(RCUPEI
, 100000);
3347 I915_WRITE(RCDNEI
, 100000);
3349 /* Set max/min thresholds to 90ms and 80ms respectively */
3350 I915_WRITE(RCBMAXAVG
, 90000);
3351 I915_WRITE(RCBMINAVG
, 80000);
3353 I915_WRITE(MEMIHYST
, 1);
3355 /* Set up min, max, and cur for interrupt handling */
3356 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3357 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3358 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3359 MEMMODE_FSTART_SHIFT
;
3361 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3364 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3365 dev_priv
->ips
.fstart
= fstart
;
3367 dev_priv
->ips
.max_delay
= fstart
;
3368 dev_priv
->ips
.min_delay
= fmin
;
3369 dev_priv
->ips
.cur_delay
= fstart
;
3371 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3372 fmax
, fmin
, fstart
);
3374 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3377 * Interrupts will be enabled in ironlake_irq_postinstall
3380 I915_WRITE(VIDSTART
, vstart
);
3381 POSTING_READ(VIDSTART
);
3383 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3384 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3386 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3387 DRM_ERROR("stuck trying to change perf mode\n");
3390 ironlake_set_drps(dev
, fstart
);
3392 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3394 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3395 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3396 getrawmonotonic(&dev_priv
->ips
.last_time2
);
3398 spin_unlock_irq(&mchdev_lock
);
3401 static void ironlake_disable_drps(struct drm_device
*dev
)
3403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3406 spin_lock_irq(&mchdev_lock
);
3408 rgvswctl
= I915_READ16(MEMSWCTL
);
3410 /* Ack interrupts, disable EFC interrupt */
3411 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3412 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3413 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3414 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3415 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3417 /* Go back to the starting frequency */
3418 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3420 rgvswctl
|= MEMCTL_CMD_STS
;
3421 I915_WRITE(MEMSWCTL
, rgvswctl
);
3424 spin_unlock_irq(&mchdev_lock
);
3427 /* There's a funny hw issue where the hw returns all 0 when reading from
3428 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3429 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3430 * all limits and the gpu stuck at whatever frequency it is at atm).
3432 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8
*val
)
3438 if (*val
>= dev_priv
->rps
.max_delay
)
3439 *val
= dev_priv
->rps
.max_delay
;
3440 limits
|= dev_priv
->rps
.max_delay
<< 24;
3442 /* Only set the down limit when we've reached the lowest level to avoid
3443 * getting more interrupts, otherwise leave this clear. This prevents a
3444 * race in the hw when coming out of rc6: There's a tiny window where
3445 * the hw runs at the minimal clock before selecting the desired
3446 * frequency, if the down threshold expires in that window we will not
3447 * receive a down interrupt. */
3448 if (*val
<= dev_priv
->rps
.min_delay
) {
3449 *val
= dev_priv
->rps
.min_delay
;
3450 limits
|= dev_priv
->rps
.min_delay
<< 16;
3456 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3460 new_power
= dev_priv
->rps
.power
;
3461 switch (dev_priv
->rps
.power
) {
3463 if (val
> dev_priv
->rps
.rpe_delay
+ 1 && val
> dev_priv
->rps
.cur_delay
)
3464 new_power
= BETWEEN
;
3468 if (val
<= dev_priv
->rps
.rpe_delay
&& val
< dev_priv
->rps
.cur_delay
)
3469 new_power
= LOW_POWER
;
3470 else if (val
>= dev_priv
->rps
.rp0_delay
&& val
> dev_priv
->rps
.cur_delay
)
3471 new_power
= HIGH_POWER
;
3475 if (val
< (dev_priv
->rps
.rp1_delay
+ dev_priv
->rps
.rp0_delay
) >> 1 && val
< dev_priv
->rps
.cur_delay
)
3476 new_power
= BETWEEN
;
3479 /* Max/min bins are special */
3480 if (val
== dev_priv
->rps
.min_delay
)
3481 new_power
= LOW_POWER
;
3482 if (val
== dev_priv
->rps
.max_delay
)
3483 new_power
= HIGH_POWER
;
3484 if (new_power
== dev_priv
->rps
.power
)
3487 /* Note the units here are not exactly 1us, but 1280ns. */
3488 switch (new_power
) {
3490 /* Upclock if more than 95% busy over 16ms */
3491 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3492 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3494 /* Downclock if less than 85% busy over 32ms */
3495 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3496 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3498 I915_WRITE(GEN6_RP_CONTROL
,
3499 GEN6_RP_MEDIA_TURBO
|
3500 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3501 GEN6_RP_MEDIA_IS_GFX
|
3503 GEN6_RP_UP_BUSY_AVG
|
3504 GEN6_RP_DOWN_IDLE_AVG
);
3508 /* Upclock if more than 90% busy over 13ms */
3509 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3510 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3512 /* Downclock if less than 75% busy over 32ms */
3513 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3514 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3516 I915_WRITE(GEN6_RP_CONTROL
,
3517 GEN6_RP_MEDIA_TURBO
|
3518 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3519 GEN6_RP_MEDIA_IS_GFX
|
3521 GEN6_RP_UP_BUSY_AVG
|
3522 GEN6_RP_DOWN_IDLE_AVG
);
3526 /* Upclock if more than 85% busy over 10ms */
3527 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3528 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3530 /* Downclock if less than 60% busy over 32ms */
3531 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3532 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3534 I915_WRITE(GEN6_RP_CONTROL
,
3535 GEN6_RP_MEDIA_TURBO
|
3536 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3537 GEN6_RP_MEDIA_IS_GFX
|
3539 GEN6_RP_UP_BUSY_AVG
|
3540 GEN6_RP_DOWN_IDLE_AVG
);
3544 dev_priv
->rps
.power
= new_power
;
3545 dev_priv
->rps
.last_adj
= 0;
3548 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3551 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
3553 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3554 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3555 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3557 if (val
== dev_priv
->rps
.cur_delay
)
3560 gen6_set_rps_thresholds(dev_priv
, val
);
3562 if (IS_HASWELL(dev
))
3563 I915_WRITE(GEN6_RPNSWREQ
,
3564 HSW_FREQUENCY(val
));
3566 I915_WRITE(GEN6_RPNSWREQ
,
3567 GEN6_FREQUENCY(val
) |
3569 GEN6_AGGRESSIVE_TURBO
);
3571 /* Make sure we continue to get interrupts
3572 * until we hit the minimum or maximum frequencies.
3574 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
3576 POSTING_READ(GEN6_RPNSWREQ
);
3578 dev_priv
->rps
.cur_delay
= val
;
3580 trace_intel_gpu_freq_change(val
* 50);
3583 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3585 mutex_lock(&dev_priv
->rps
.hw_lock
);
3586 if (dev_priv
->rps
.enabled
) {
3587 if (dev_priv
->info
->is_valleyview
)
3588 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3590 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3591 dev_priv
->rps
.last_adj
= 0;
3593 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3596 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3598 mutex_lock(&dev_priv
->rps
.hw_lock
);
3599 if (dev_priv
->rps
.enabled
) {
3600 if (dev_priv
->info
->is_valleyview
)
3601 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_delay
);
3603 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_delay
);
3604 dev_priv
->rps
.last_adj
= 0;
3606 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3610 * Wait until the previous freq change has completed,
3611 * or the timeout elapsed, and then update our notion
3612 * of the current GPU frequency.
3614 static void vlv_update_rps_cur_delay(struct drm_i915_private
*dev_priv
)
3618 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3620 if (wait_for(((pval
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
)) & GENFREQSTATUS
) == 0, 10))
3621 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3625 if (pval
!= dev_priv
->rps
.cur_delay
)
3626 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3627 vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.cur_delay
),
3628 dev_priv
->rps
.cur_delay
,
3629 vlv_gpu_freq(dev_priv
->mem_freq
, pval
), pval
);
3631 dev_priv
->rps
.cur_delay
= pval
;
3634 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3638 gen6_rps_limits(dev_priv
, &val
);
3640 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3641 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3642 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3644 vlv_update_rps_cur_delay(dev_priv
);
3646 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3647 vlv_gpu_freq(dev_priv
->mem_freq
,
3648 dev_priv
->rps
.cur_delay
),
3649 dev_priv
->rps
.cur_delay
,
3650 vlv_gpu_freq(dev_priv
->mem_freq
, val
), val
);
3652 if (val
== dev_priv
->rps
.cur_delay
)
3655 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3657 dev_priv
->rps
.cur_delay
= val
;
3659 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
->mem_freq
, val
));
3662 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3666 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3667 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) & ~GEN6_PM_RPS_EVENTS
);
3668 /* Complete PM interrupt masking here doesn't race with the rps work
3669 * item again unmasking PM interrupts because that is using a different
3670 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3671 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3673 spin_lock_irq(&dev_priv
->irq_lock
);
3674 dev_priv
->rps
.pm_iir
= 0;
3675 spin_unlock_irq(&dev_priv
->irq_lock
);
3677 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3680 static void gen6_disable_rps(struct drm_device
*dev
)
3682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3684 I915_WRITE(GEN6_RC_CONTROL
, 0);
3685 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3687 gen6_disable_rps_interrupts(dev
);
3690 static void valleyview_disable_rps(struct drm_device
*dev
)
3692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3694 I915_WRITE(GEN6_RC_CONTROL
, 0);
3696 gen6_disable_rps_interrupts(dev
);
3698 if (dev_priv
->vlv_pctx
) {
3699 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3700 dev_priv
->vlv_pctx
= NULL
;
3704 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3707 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3709 if (IS_HASWELL(dev
))
3710 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3712 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3713 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3714 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3715 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3718 int intel_enable_rc6(const struct drm_device
*dev
)
3720 /* No RC6 before Ironlake */
3721 if (INTEL_INFO(dev
)->gen
< 5)
3724 /* Respect the kernel parameter if it is set */
3725 if (i915_enable_rc6
>= 0)
3726 return i915_enable_rc6
;
3728 /* Disable RC6 on Ironlake */
3729 if (INTEL_INFO(dev
)->gen
== 5)
3732 if (IS_HASWELL(dev
))
3733 return INTEL_RC6_ENABLE
;
3735 /* snb/ivb have more than one rc6 state. */
3736 if (INTEL_INFO(dev
)->gen
== 6)
3737 return INTEL_RC6_ENABLE
;
3739 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3742 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3747 spin_lock_irq(&dev_priv
->irq_lock
);
3748 WARN_ON(dev_priv
->rps
.pm_iir
);
3749 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
3750 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3751 spin_unlock_irq(&dev_priv
->irq_lock
);
3753 /* only unmask PM interrupts we need. Mask all others. */
3754 enabled_intrs
= GEN6_PM_RPS_EVENTS
;
3756 /* IVB and SNB hard hangs on looping batchbuffer
3757 * if GEN6_PM_UP_EI_EXPIRED is masked.
3759 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
3760 enabled_intrs
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3762 I915_WRITE(GEN6_PMINTRMSK
, ~enabled_intrs
);
3765 static void gen8_enable_rps(struct drm_device
*dev
)
3767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3768 struct intel_ring_buffer
*ring
;
3769 uint32_t rc6_mask
= 0, rp_state_cap
;
3772 /* 1a: Software RC state - RC0 */
3773 I915_WRITE(GEN6_RC_STATE
, 0);
3775 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3776 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3777 gen6_gt_force_wake_get(dev_priv
);
3779 /* 2a: Disable RC states. */
3780 I915_WRITE(GEN6_RC_CONTROL
, 0);
3782 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3784 /* 2b: Program RC6 thresholds.*/
3785 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3786 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3787 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3788 for_each_ring(ring
, dev_priv
, unused
)
3789 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3790 I915_WRITE(GEN6_RC_SLEEP
, 0);
3791 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3794 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3795 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3796 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
3797 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3798 GEN6_RC_CTL_EI_MODE(1) |
3801 /* 4 Program defaults and thresholds for RPS*/
3802 I915_WRITE(GEN6_RPNSWREQ
, HSW_FREQUENCY(10)); /* Request 500 MHz */
3803 I915_WRITE(GEN6_RC_VIDEO_FREQ
, HSW_FREQUENCY(12)); /* Request 600 MHz */
3804 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3805 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3807 /* Docs recommend 900MHz, and 300 MHz respectively */
3808 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3809 dev_priv
->rps
.max_delay
<< 24 |
3810 dev_priv
->rps
.min_delay
<< 16);
3812 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3813 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3814 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3815 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3817 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3820 I915_WRITE(GEN6_RP_CONTROL
,
3821 GEN6_RP_MEDIA_TURBO
|
3822 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3823 GEN6_RP_MEDIA_IS_GFX
|
3825 GEN6_RP_UP_BUSY_AVG
|
3826 GEN6_RP_DOWN_IDLE_AVG
);
3828 /* 6: Ring frequency + overclocking (our driver does this later */
3830 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3832 gen6_enable_rps_interrupts(dev
);
3834 gen6_gt_force_wake_put(dev_priv
);
3837 static void gen6_enable_rps(struct drm_device
*dev
)
3839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3840 struct intel_ring_buffer
*ring
;
3843 u32 rc6vids
, pcu_mbox
, rc6_mask
= 0;
3848 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3850 /* Here begins a magic sequence of register writes to enable
3851 * auto-downclocking.
3853 * Perhaps there might be some value in exposing these to
3856 I915_WRITE(GEN6_RC_STATE
, 0);
3858 /* Clear the DBG now so we don't confuse earlier errors */
3859 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3860 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3861 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3864 gen6_gt_force_wake_get(dev_priv
);
3866 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3867 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3869 /* In units of 50MHz */
3870 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
3871 dev_priv
->rps
.min_delay
= (rp_state_cap
>> 16) & 0xff;
3872 dev_priv
->rps
.rp1_delay
= (rp_state_cap
>> 8) & 0xff;
3873 dev_priv
->rps
.rp0_delay
= (rp_state_cap
>> 0) & 0xff;
3874 dev_priv
->rps
.rpe_delay
= dev_priv
->rps
.rp1_delay
;
3875 dev_priv
->rps
.cur_delay
= 0;
3877 /* disable the counters and set deterministic thresholds */
3878 I915_WRITE(GEN6_RC_CONTROL
, 0);
3880 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3881 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3882 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3883 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3884 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3886 for_each_ring(ring
, dev_priv
, i
)
3887 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3889 I915_WRITE(GEN6_RC_SLEEP
, 0);
3890 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3891 if (INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
))
3892 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3894 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3895 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3896 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3898 /* Check if we are enabling RC6 */
3899 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3900 if (rc6_mode
& INTEL_RC6_ENABLE
)
3901 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3903 /* We don't use those on Haswell */
3904 if (!IS_HASWELL(dev
)) {
3905 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3906 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3908 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3909 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3912 intel_print_rc6_info(dev
, rc6_mask
);
3914 I915_WRITE(GEN6_RC_CONTROL
,
3916 GEN6_RC_CTL_EI_MODE(1) |
3917 GEN6_RC_CTL_HW_ENABLE
);
3919 /* Power down if completely idle for over 50ms */
3920 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3921 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3923 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3926 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3927 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3928 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3929 (dev_priv
->rps
.max_delay
& 0xff) * 50,
3930 (pcu_mbox
& 0xff) * 50);
3931 dev_priv
->rps
.hw_max
= pcu_mbox
& 0xff;
3934 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3937 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3938 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_delay
);
3940 gen6_enable_rps_interrupts(dev
);
3943 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3944 if (IS_GEN6(dev
) && ret
) {
3945 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3946 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3947 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3948 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3949 rc6vids
&= 0xffff00;
3950 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3951 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3953 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3956 gen6_gt_force_wake_put(dev_priv
);
3959 void gen6_update_ring_freq(struct drm_device
*dev
)
3961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3963 unsigned int gpu_freq
;
3964 unsigned int max_ia_freq
, min_ring_freq
;
3965 int scaling_factor
= 180;
3966 struct cpufreq_policy
*policy
;
3968 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3970 policy
= cpufreq_cpu_get(0);
3972 max_ia_freq
= policy
->cpuinfo
.max_freq
;
3973 cpufreq_cpu_put(policy
);
3976 * Default to measured freq if none found, PCU will ensure we
3979 max_ia_freq
= tsc_khz
;
3982 /* Convert from kHz to MHz */
3983 max_ia_freq
/= 1000;
3985 min_ring_freq
= I915_READ(DCLK
) & 0xf;
3986 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3987 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
3990 * For each potential GPU frequency, load a ring frequency we'd like
3991 * to use for memory access. We do this by specifying the IA frequency
3992 * the PCU should use as a reference to determine the ring frequency.
3994 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
3996 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
3997 unsigned int ia_freq
= 0, ring_freq
= 0;
3999 if (INTEL_INFO(dev
)->gen
>= 8) {
4000 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4001 ring_freq
= max(min_ring_freq
, gpu_freq
);
4002 } else if (IS_HASWELL(dev
)) {
4003 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4004 ring_freq
= max(min_ring_freq
, ring_freq
);
4005 /* leave ia_freq as the default, chosen by cpufreq */
4007 /* On older processors, there is no separate ring
4008 * clock domain, so in order to boost the bandwidth
4009 * of the ring, we need to upclock the CPU (ia_freq).
4011 * For GPU frequencies less than 750MHz,
4012 * just use the lowest ring freq.
4014 if (gpu_freq
< min_freq
)
4017 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4018 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4021 sandybridge_pcode_write(dev_priv
,
4022 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4023 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4024 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4029 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4033 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4035 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
4037 rp0
= min_t(u32
, rp0
, 0xea);
4042 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4046 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
4047 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
4048 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
4049 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
4054 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4056 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
4059 static void valleyview_setup_pctx(struct drm_device
*dev
)
4061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4062 struct drm_i915_gem_object
*pctx
;
4063 unsigned long pctx_paddr
;
4065 int pctx_size
= 24*1024;
4067 pcbr
= I915_READ(VLV_PCBR
);
4069 /* BIOS set it up already, grab the pre-alloc'd space */
4072 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4073 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4075 I915_GTT_OFFSET_NONE
,
4081 * From the Gunit register HAS:
4082 * The Gfx driver is expected to program this register and ensure
4083 * proper allocation within Gfx stolen memory. For example, this
4084 * register should be programmed such than the PCBR range does not
4085 * overlap with other ranges, such as the frame buffer, protected
4086 * memory, or any other relevant ranges.
4088 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4090 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4094 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4095 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4098 dev_priv
->vlv_pctx
= pctx
;
4101 static void valleyview_enable_rps(struct drm_device
*dev
)
4103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4104 struct intel_ring_buffer
*ring
;
4105 u32 gtfifodbg
, val
, rc6_mode
= 0;
4108 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4110 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4111 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4113 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4116 valleyview_setup_pctx(dev
);
4118 gen6_gt_force_wake_get(dev_priv
);
4120 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4121 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4122 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4123 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4125 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4127 I915_WRITE(GEN6_RP_CONTROL
,
4128 GEN6_RP_MEDIA_TURBO
|
4129 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4130 GEN6_RP_MEDIA_IS_GFX
|
4132 GEN6_RP_UP_BUSY_AVG
|
4133 GEN6_RP_DOWN_IDLE_CONT
);
4135 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4136 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4137 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4139 for_each_ring(ring
, dev_priv
, i
)
4140 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4142 I915_WRITE(GEN6_RC6_THRESHOLD
, 0xc350);
4144 /* allows RC6 residency counter to work */
4145 I915_WRITE(VLV_COUNTER_CONTROL
,
4146 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4147 VLV_MEDIA_RC6_COUNT_EN
|
4148 VLV_RENDER_RC6_COUNT_EN
));
4149 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4150 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
4152 intel_print_rc6_info(dev
, rc6_mode
);
4154 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4156 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4157 switch ((val
>> 6) & 3) {
4160 dev_priv
->mem_freq
= 800;
4163 dev_priv
->mem_freq
= 1066;
4166 dev_priv
->mem_freq
= 1333;
4169 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
4171 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4172 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4174 dev_priv
->rps
.cur_delay
= (val
>> 8) & 0xff;
4175 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4176 vlv_gpu_freq(dev_priv
->mem_freq
,
4177 dev_priv
->rps
.cur_delay
),
4178 dev_priv
->rps
.cur_delay
);
4180 dev_priv
->rps
.max_delay
= valleyview_rps_max_freq(dev_priv
);
4181 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
;
4182 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4183 vlv_gpu_freq(dev_priv
->mem_freq
,
4184 dev_priv
->rps
.max_delay
),
4185 dev_priv
->rps
.max_delay
);
4187 dev_priv
->rps
.rpe_delay
= valleyview_rps_rpe_freq(dev_priv
);
4188 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4189 vlv_gpu_freq(dev_priv
->mem_freq
,
4190 dev_priv
->rps
.rpe_delay
),
4191 dev_priv
->rps
.rpe_delay
);
4193 dev_priv
->rps
.min_delay
= valleyview_rps_min_freq(dev_priv
);
4194 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4195 vlv_gpu_freq(dev_priv
->mem_freq
,
4196 dev_priv
->rps
.min_delay
),
4197 dev_priv
->rps
.min_delay
);
4199 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4200 vlv_gpu_freq(dev_priv
->mem_freq
,
4201 dev_priv
->rps
.rpe_delay
),
4202 dev_priv
->rps
.rpe_delay
);
4204 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.rpe_delay
);
4206 gen6_enable_rps_interrupts(dev
);
4208 gen6_gt_force_wake_put(dev_priv
);
4211 void ironlake_teardown_rc6(struct drm_device
*dev
)
4213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4215 if (dev_priv
->ips
.renderctx
) {
4216 i915_gem_object_unpin(dev_priv
->ips
.renderctx
);
4217 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4218 dev_priv
->ips
.renderctx
= NULL
;
4221 if (dev_priv
->ips
.pwrctx
) {
4222 i915_gem_object_unpin(dev_priv
->ips
.pwrctx
);
4223 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4224 dev_priv
->ips
.pwrctx
= NULL
;
4228 static void ironlake_disable_rc6(struct drm_device
*dev
)
4230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4232 if (I915_READ(PWRCTXA
)) {
4233 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4234 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4235 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4238 I915_WRITE(PWRCTXA
, 0);
4239 POSTING_READ(PWRCTXA
);
4241 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4242 POSTING_READ(RSTDBYCTL
);
4246 static int ironlake_setup_rc6(struct drm_device
*dev
)
4248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4250 if (dev_priv
->ips
.renderctx
== NULL
)
4251 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4252 if (!dev_priv
->ips
.renderctx
)
4255 if (dev_priv
->ips
.pwrctx
== NULL
)
4256 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4257 if (!dev_priv
->ips
.pwrctx
) {
4258 ironlake_teardown_rc6(dev
);
4265 static void ironlake_enable_rc6(struct drm_device
*dev
)
4267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4268 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
4269 bool was_interruptible
;
4272 /* rc6 disabled by default due to repeated reports of hanging during
4275 if (!intel_enable_rc6(dev
))
4278 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4280 ret
= ironlake_setup_rc6(dev
);
4284 was_interruptible
= dev_priv
->mm
.interruptible
;
4285 dev_priv
->mm
.interruptible
= false;
4288 * GPU can automatically power down the render unit if given a page
4291 ret
= intel_ring_begin(ring
, 6);
4293 ironlake_teardown_rc6(dev
);
4294 dev_priv
->mm
.interruptible
= was_interruptible
;
4298 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4299 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4300 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4302 MI_SAVE_EXT_STATE_EN
|
4303 MI_RESTORE_EXT_STATE_EN
|
4304 MI_RESTORE_INHIBIT
);
4305 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4306 intel_ring_emit(ring
, MI_NOOP
);
4307 intel_ring_emit(ring
, MI_FLUSH
);
4308 intel_ring_advance(ring
);
4311 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4312 * does an implicit flush, combined with MI_FLUSH above, it should be
4313 * safe to assume that renderctx is valid
4315 ret
= intel_ring_idle(ring
);
4316 dev_priv
->mm
.interruptible
= was_interruptible
;
4318 DRM_ERROR("failed to enable ironlake power savings\n");
4319 ironlake_teardown_rc6(dev
);
4323 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4324 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4326 intel_print_rc6_info(dev
, INTEL_RC6_ENABLE
);
4329 static unsigned long intel_pxfreq(u32 vidfreq
)
4332 int div
= (vidfreq
& 0x3f0000) >> 16;
4333 int post
= (vidfreq
& 0x3000) >> 12;
4334 int pre
= (vidfreq
& 0x7);
4339 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4344 static const struct cparams
{
4350 { 1, 1333, 301, 28664 },
4351 { 1, 1066, 294, 24460 },
4352 { 1, 800, 294, 25192 },
4353 { 0, 1333, 276, 27605 },
4354 { 0, 1066, 276, 27605 },
4355 { 0, 800, 231, 23784 },
4358 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4360 u64 total_count
, diff
, ret
;
4361 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4362 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4365 assert_spin_locked(&mchdev_lock
);
4367 diff1
= now
- dev_priv
->ips
.last_time1
;
4369 /* Prevent division-by-zero if we are asking too fast.
4370 * Also, we don't get interesting results if we are polling
4371 * faster than once in 10ms, so just return the saved value
4375 return dev_priv
->ips
.chipset_power
;
4377 count1
= I915_READ(DMIEC
);
4378 count2
= I915_READ(DDREC
);
4379 count3
= I915_READ(CSIEC
);
4381 total_count
= count1
+ count2
+ count3
;
4383 /* FIXME: handle per-counter overflow */
4384 if (total_count
< dev_priv
->ips
.last_count1
) {
4385 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4386 diff
+= total_count
;
4388 diff
= total_count
- dev_priv
->ips
.last_count1
;
4391 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4392 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4393 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4400 diff
= div_u64(diff
, diff1
);
4401 ret
= ((m
* diff
) + c
);
4402 ret
= div_u64(ret
, 10);
4404 dev_priv
->ips
.last_count1
= total_count
;
4405 dev_priv
->ips
.last_time1
= now
;
4407 dev_priv
->ips
.chipset_power
= ret
;
4412 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4416 if (dev_priv
->info
->gen
!= 5)
4419 spin_lock_irq(&mchdev_lock
);
4421 val
= __i915_chipset_val(dev_priv
);
4423 spin_unlock_irq(&mchdev_lock
);
4428 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4430 unsigned long m
, x
, b
;
4433 tsfs
= I915_READ(TSFS
);
4435 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4436 x
= I915_READ8(TR1
);
4438 b
= tsfs
& TSFS_INTR_MASK
;
4440 return ((m
* x
) / 127) - b
;
4443 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4445 static const struct v_table
{
4446 u16 vd
; /* in .1 mil */
4447 u16 vm
; /* in .1 mil */
4578 if (dev_priv
->info
->is_mobile
)
4579 return v_table
[pxvid
].vm
;
4581 return v_table
[pxvid
].vd
;
4584 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4586 struct timespec now
, diff1
;
4588 unsigned long diffms
;
4591 assert_spin_locked(&mchdev_lock
);
4593 getrawmonotonic(&now
);
4594 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4596 /* Don't divide by 0 */
4597 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4601 count
= I915_READ(GFXEC
);
4603 if (count
< dev_priv
->ips
.last_count2
) {
4604 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4607 diff
= count
- dev_priv
->ips
.last_count2
;
4610 dev_priv
->ips
.last_count2
= count
;
4611 dev_priv
->ips
.last_time2
= now
;
4613 /* More magic constants... */
4615 diff
= div_u64(diff
, diffms
* 10);
4616 dev_priv
->ips
.gfx_power
= diff
;
4619 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4621 if (dev_priv
->info
->gen
!= 5)
4624 spin_lock_irq(&mchdev_lock
);
4626 __i915_update_gfx_val(dev_priv
);
4628 spin_unlock_irq(&mchdev_lock
);
4631 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4633 unsigned long t
, corr
, state1
, corr2
, state2
;
4636 assert_spin_locked(&mchdev_lock
);
4638 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
4639 pxvid
= (pxvid
>> 24) & 0x7f;
4640 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4644 t
= i915_mch_val(dev_priv
);
4646 /* Revel in the empirically derived constants */
4648 /* Correction factor in 1/100000 units */
4650 corr
= ((t
* 2349) + 135940);
4652 corr
= ((t
* 964) + 29317);
4654 corr
= ((t
* 301) + 1004);
4656 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4658 corr2
= (corr
* dev_priv
->ips
.corr
);
4660 state2
= (corr2
* state1
) / 10000;
4661 state2
/= 100; /* convert to mW */
4663 __i915_update_gfx_val(dev_priv
);
4665 return dev_priv
->ips
.gfx_power
+ state2
;
4668 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4672 if (dev_priv
->info
->gen
!= 5)
4675 spin_lock_irq(&mchdev_lock
);
4677 val
= __i915_gfx_val(dev_priv
);
4679 spin_unlock_irq(&mchdev_lock
);
4685 * i915_read_mch_val - return value for IPS use
4687 * Calculate and return a value for the IPS driver to use when deciding whether
4688 * we have thermal and power headroom to increase CPU or GPU power budget.
4690 unsigned long i915_read_mch_val(void)
4692 struct drm_i915_private
*dev_priv
;
4693 unsigned long chipset_val
, graphics_val
, ret
= 0;
4695 spin_lock_irq(&mchdev_lock
);
4698 dev_priv
= i915_mch_dev
;
4700 chipset_val
= __i915_chipset_val(dev_priv
);
4701 graphics_val
= __i915_gfx_val(dev_priv
);
4703 ret
= chipset_val
+ graphics_val
;
4706 spin_unlock_irq(&mchdev_lock
);
4710 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4713 * i915_gpu_raise - raise GPU frequency limit
4715 * Raise the limit; IPS indicates we have thermal headroom.
4717 bool i915_gpu_raise(void)
4719 struct drm_i915_private
*dev_priv
;
4722 spin_lock_irq(&mchdev_lock
);
4723 if (!i915_mch_dev
) {
4727 dev_priv
= i915_mch_dev
;
4729 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4730 dev_priv
->ips
.max_delay
--;
4733 spin_unlock_irq(&mchdev_lock
);
4737 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4740 * i915_gpu_lower - lower GPU frequency limit
4742 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4743 * frequency maximum.
4745 bool i915_gpu_lower(void)
4747 struct drm_i915_private
*dev_priv
;
4750 spin_lock_irq(&mchdev_lock
);
4751 if (!i915_mch_dev
) {
4755 dev_priv
= i915_mch_dev
;
4757 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4758 dev_priv
->ips
.max_delay
++;
4761 spin_unlock_irq(&mchdev_lock
);
4765 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4768 * i915_gpu_busy - indicate GPU business to IPS
4770 * Tell the IPS driver whether or not the GPU is busy.
4772 bool i915_gpu_busy(void)
4774 struct drm_i915_private
*dev_priv
;
4775 struct intel_ring_buffer
*ring
;
4779 spin_lock_irq(&mchdev_lock
);
4782 dev_priv
= i915_mch_dev
;
4784 for_each_ring(ring
, dev_priv
, i
)
4785 ret
|= !list_empty(&ring
->request_list
);
4788 spin_unlock_irq(&mchdev_lock
);
4792 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4795 * i915_gpu_turbo_disable - disable graphics turbo
4797 * Disable graphics turbo by resetting the max frequency and setting the
4798 * current frequency to the default.
4800 bool i915_gpu_turbo_disable(void)
4802 struct drm_i915_private
*dev_priv
;
4805 spin_lock_irq(&mchdev_lock
);
4806 if (!i915_mch_dev
) {
4810 dev_priv
= i915_mch_dev
;
4812 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4814 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4818 spin_unlock_irq(&mchdev_lock
);
4822 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4825 * Tells the intel_ips driver that the i915 driver is now loaded, if
4826 * IPS got loaded first.
4828 * This awkward dance is so that neither module has to depend on the
4829 * other in order for IPS to do the appropriate communication of
4830 * GPU turbo limits to i915.
4833 ips_ping_for_i915_load(void)
4837 link
= symbol_get(ips_link_to_i915_driver
);
4840 symbol_put(ips_link_to_i915_driver
);
4844 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4846 /* We only register the i915 ips part with intel-ips once everything is
4847 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4848 spin_lock_irq(&mchdev_lock
);
4849 i915_mch_dev
= dev_priv
;
4850 spin_unlock_irq(&mchdev_lock
);
4852 ips_ping_for_i915_load();
4855 void intel_gpu_ips_teardown(void)
4857 spin_lock_irq(&mchdev_lock
);
4858 i915_mch_dev
= NULL
;
4859 spin_unlock_irq(&mchdev_lock
);
4861 static void intel_init_emon(struct drm_device
*dev
)
4863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4868 /* Disable to program */
4872 /* Program energy weights for various events */
4873 I915_WRITE(SDEW
, 0x15040d00);
4874 I915_WRITE(CSIEW0
, 0x007f0000);
4875 I915_WRITE(CSIEW1
, 0x1e220004);
4876 I915_WRITE(CSIEW2
, 0x04000004);
4878 for (i
= 0; i
< 5; i
++)
4879 I915_WRITE(PEW
+ (i
* 4), 0);
4880 for (i
= 0; i
< 3; i
++)
4881 I915_WRITE(DEW
+ (i
* 4), 0);
4883 /* Program P-state weights to account for frequency power adjustment */
4884 for (i
= 0; i
< 16; i
++) {
4885 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4886 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4887 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4892 val
*= (freq
/ 1000);
4894 val
/= (127*127*900);
4896 DRM_ERROR("bad pxval: %ld\n", val
);
4899 /* Render standby states get 0 weight */
4903 for (i
= 0; i
< 4; i
++) {
4904 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4905 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4906 I915_WRITE(PXW
+ (i
* 4), val
);
4909 /* Adjust magic regs to magic values (more experimental results) */
4910 I915_WRITE(OGW0
, 0);
4911 I915_WRITE(OGW1
, 0);
4912 I915_WRITE(EG0
, 0x00007f00);
4913 I915_WRITE(EG1
, 0x0000000e);
4914 I915_WRITE(EG2
, 0x000e0000);
4915 I915_WRITE(EG3
, 0x68000300);
4916 I915_WRITE(EG4
, 0x42000000);
4917 I915_WRITE(EG5
, 0x00140031);
4921 for (i
= 0; i
< 8; i
++)
4922 I915_WRITE(PXWL
+ (i
* 4), 0);
4924 /* Enable PMON + select events */
4925 I915_WRITE(ECR
, 0x80000019);
4927 lcfuse
= I915_READ(LCFUSE02
);
4929 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4932 void intel_disable_gt_powersave(struct drm_device
*dev
)
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4936 /* Interrupts should be disabled already to avoid re-arming. */
4937 WARN_ON(dev
->irq_enabled
);
4939 if (IS_IRONLAKE_M(dev
)) {
4940 ironlake_disable_drps(dev
);
4941 ironlake_disable_rc6(dev
);
4942 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4943 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
4944 cancel_work_sync(&dev_priv
->rps
.work
);
4945 mutex_lock(&dev_priv
->rps
.hw_lock
);
4946 if (IS_VALLEYVIEW(dev
))
4947 valleyview_disable_rps(dev
);
4949 gen6_disable_rps(dev
);
4950 dev_priv
->rps
.enabled
= false;
4951 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4955 static void intel_gen6_powersave_work(struct work_struct
*work
)
4957 struct drm_i915_private
*dev_priv
=
4958 container_of(work
, struct drm_i915_private
,
4959 rps
.delayed_resume_work
.work
);
4960 struct drm_device
*dev
= dev_priv
->dev
;
4962 mutex_lock(&dev_priv
->rps
.hw_lock
);
4964 if (IS_VALLEYVIEW(dev
)) {
4965 valleyview_enable_rps(dev
);
4966 } else if (IS_BROADWELL(dev
)) {
4967 gen8_enable_rps(dev
);
4968 gen6_update_ring_freq(dev
);
4970 gen6_enable_rps(dev
);
4971 gen6_update_ring_freq(dev
);
4973 dev_priv
->rps
.enabled
= true;
4974 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4977 void intel_enable_gt_powersave(struct drm_device
*dev
)
4979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4981 if (IS_IRONLAKE_M(dev
)) {
4982 ironlake_enable_drps(dev
);
4983 ironlake_enable_rc6(dev
);
4984 intel_init_emon(dev
);
4985 } else if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
4987 * PCU communication is slow and this doesn't need to be
4988 * done at any specific time, so do this out of our fast path
4989 * to make resume and init faster.
4991 schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
4992 round_jiffies_up_relative(HZ
));
4996 static void ibx_init_clock_gating(struct drm_device
*dev
)
4998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5001 * On Ibex Peak and Cougar Point, we need to disable clock
5002 * gating for the panel power sequencer or it will fail to
5003 * start up when no ports are active.
5005 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5008 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5013 for_each_pipe(pipe
) {
5014 I915_WRITE(DSPCNTR(pipe
),
5015 I915_READ(DSPCNTR(pipe
)) |
5016 DISPPLANE_TRICKLE_FEED_DISABLE
);
5017 intel_flush_primary_plane(dev_priv
, pipe
);
5021 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5024 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5028 * WaFbcDisableDpfcClockGating:ilk
5030 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5031 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5032 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5034 I915_WRITE(PCH_3DCGDIS0
,
5035 MARIUNIT_CLOCK_GATE_DISABLE
|
5036 SVSMUNIT_CLOCK_GATE_DISABLE
);
5037 I915_WRITE(PCH_3DCGDIS1
,
5038 VFMUNIT_CLOCK_GATE_DISABLE
);
5041 * According to the spec the following bits should be set in
5042 * order to enable memory self-refresh
5043 * The bit 22/21 of 0x42004
5044 * The bit 5 of 0x42020
5045 * The bit 15 of 0x45000
5047 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5048 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5049 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5050 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5051 I915_WRITE(DISP_ARB_CTL
,
5052 (I915_READ(DISP_ARB_CTL
) |
5054 I915_WRITE(WM3_LP_ILK
, 0);
5055 I915_WRITE(WM2_LP_ILK
, 0);
5056 I915_WRITE(WM1_LP_ILK
, 0);
5059 * Based on the document from hardware guys the following bits
5060 * should be set unconditionally in order to enable FBC.
5061 * The bit 22 of 0x42000
5062 * The bit 22 of 0x42004
5063 * The bit 7,8,9 of 0x42020.
5065 if (IS_IRONLAKE_M(dev
)) {
5066 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5067 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5068 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5070 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5071 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5075 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5077 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5078 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5079 ILK_ELPIN_409_SELECT
);
5080 I915_WRITE(_3D_CHICKEN2
,
5081 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5082 _3D_CHICKEN2_WM_READ_PIPELINED
);
5084 /* WaDisableRenderCachePipelinedFlush:ilk */
5085 I915_WRITE(CACHE_MODE_0
,
5086 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5088 g4x_disable_trickle_feed(dev
);
5090 ibx_init_clock_gating(dev
);
5093 static void cpt_init_clock_gating(struct drm_device
*dev
)
5095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5100 * On Ibex Peak and Cougar Point, we need to disable clock
5101 * gating for the panel power sequencer or it will fail to
5102 * start up when no ports are active.
5104 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5105 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5106 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5107 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5108 DPLS_EDP_PPS_FIX_DIS
);
5109 /* The below fixes the weird display corruption, a few pixels shifted
5110 * downward, on (only) LVDS of some HP laptops with IVY.
5112 for_each_pipe(pipe
) {
5113 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5114 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5115 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5116 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5117 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5118 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5119 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5120 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5121 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5123 /* WADP0ClockGatingDisable */
5124 for_each_pipe(pipe
) {
5125 I915_WRITE(TRANS_CHICKEN1(pipe
),
5126 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5130 static void gen6_check_mch_setup(struct drm_device
*dev
)
5132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5135 tmp
= I915_READ(MCH_SSKPD
);
5136 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
5137 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
5138 DRM_INFO("This can cause pipe underruns and display issues.\n");
5139 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5143 static void gen6_init_clock_gating(struct drm_device
*dev
)
5145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5146 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5148 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5150 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5151 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5152 ILK_ELPIN_409_SELECT
);
5154 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5155 I915_WRITE(_3D_CHICKEN
,
5156 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5158 /* WaSetupGtModeTdRowDispatch:snb */
5159 if (IS_SNB_GT1(dev
))
5160 I915_WRITE(GEN6_GT_MODE
,
5161 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5163 I915_WRITE(WM3_LP_ILK
, 0);
5164 I915_WRITE(WM2_LP_ILK
, 0);
5165 I915_WRITE(WM1_LP_ILK
, 0);
5167 I915_WRITE(CACHE_MODE_0
,
5168 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5170 I915_WRITE(GEN6_UCGCTL1
,
5171 I915_READ(GEN6_UCGCTL1
) |
5172 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5173 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5175 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5176 * gating disable must be set. Failure to set it results in
5177 * flickering pixels due to Z write ordering failures after
5178 * some amount of runtime in the Mesa "fire" demo, and Unigine
5179 * Sanctuary and Tropics, and apparently anything else with
5180 * alpha test or pixel discard.
5182 * According to the spec, bit 11 (RCCUNIT) must also be set,
5183 * but we didn't debug actual testcases to find it out.
5185 * Also apply WaDisableVDSUnitClockGating:snb and
5186 * WaDisableRCPBUnitClockGating:snb.
5188 I915_WRITE(GEN6_UCGCTL2
,
5189 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
5190 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5191 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5193 /* Bspec says we need to always set all mask bits. */
5194 I915_WRITE(_3D_CHICKEN3
, (0xFFFF << 16) |
5195 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
);
5198 * According to the spec the following bits should be
5199 * set in order to enable memory self-refresh and fbc:
5200 * The bit21 and bit22 of 0x42000
5201 * The bit21 and bit22 of 0x42004
5202 * The bit5 and bit7 of 0x42020
5203 * The bit14 of 0x70180
5204 * The bit14 of 0x71180
5206 * WaFbcAsynchFlipDisableFbcQueue:snb
5208 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5209 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5210 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5211 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5212 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5213 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5214 I915_WRITE(ILK_DSPCLK_GATE_D
,
5215 I915_READ(ILK_DSPCLK_GATE_D
) |
5216 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5217 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5219 g4x_disable_trickle_feed(dev
);
5221 /* The default value should be 0x200 according to docs, but the two
5222 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5223 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_DISABLE(0xffff));
5224 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI
));
5226 cpt_init_clock_gating(dev
);
5228 gen6_check_mch_setup(dev
);
5231 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5233 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5235 reg
&= ~GEN7_FF_SCHED_MASK
;
5236 reg
|= GEN7_FF_TS_SCHED_HW
;
5237 reg
|= GEN7_FF_VS_SCHED_HW
;
5238 reg
|= GEN7_FF_DS_SCHED_HW
;
5240 if (IS_HASWELL(dev_priv
->dev
))
5241 reg
&= ~GEN7_FF_VS_REF_CNT_FFME
;
5243 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5246 static void lpt_init_clock_gating(struct drm_device
*dev
)
5248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5251 * TODO: this bit should only be enabled when really needed, then
5252 * disabled when not needed anymore in order to save power.
5254 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5255 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5256 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5257 PCH_LP_PARTITION_LEVEL_DISABLE
);
5259 /* WADPOClockGatingDisable:hsw */
5260 I915_WRITE(_TRANSA_CHICKEN1
,
5261 I915_READ(_TRANSA_CHICKEN1
) |
5262 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5265 static void lpt_suspend_hw(struct drm_device
*dev
)
5267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5269 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5270 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5272 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5273 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5277 static void gen8_init_clock_gating(struct drm_device
*dev
)
5279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5282 I915_WRITE(WM3_LP_ILK
, 0);
5283 I915_WRITE(WM2_LP_ILK
, 0);
5284 I915_WRITE(WM1_LP_ILK
, 0);
5286 /* FIXME(BDW): Check all the w/a, some might only apply to
5287 * pre-production hw. */
5289 WARN(!i915_preliminary_hw_support
,
5290 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5291 I915_WRITE(HALF_SLICE_CHICKEN3
,
5292 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5293 I915_WRITE(HALF_SLICE_CHICKEN3
,
5294 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5295 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5297 I915_WRITE(_3D_CHICKEN3
,
5298 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5300 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5301 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5303 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5304 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5306 /* WaSwitchSolVfFArbitrationPriority */
5307 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5309 /* WaPsrDPAMaskVBlankInSRD */
5310 I915_WRITE(CHICKEN_PAR1_1
,
5311 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5313 /* WaPsrDPRSUnmaskVBlankInSRD */
5315 I915_WRITE(CHICKEN_PIPESL_1(i
),
5316 I915_READ(CHICKEN_PIPESL_1(i
) |
5317 DPRS_MASK_VBLANK_SRD
));
5321 static void haswell_init_clock_gating(struct drm_device
*dev
)
5323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5325 I915_WRITE(WM3_LP_ILK
, 0);
5326 I915_WRITE(WM2_LP_ILK
, 0);
5327 I915_WRITE(WM1_LP_ILK
, 0);
5329 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5330 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5332 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5334 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5335 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5336 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5338 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5339 I915_WRITE(GEN7_L3CNTLREG1
,
5340 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5341 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5342 GEN7_WA_L3_CHICKEN_MODE
);
5344 /* L3 caching of data atomics doesn't work -- disable it. */
5345 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5346 I915_WRITE(HSW_ROW_CHICKEN3
,
5347 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5349 /* This is required by WaCatErrorRejectionIssue:hsw */
5350 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5351 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5352 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5354 /* WaVSRefCountFullforceMissDisable:hsw */
5355 gen7_setup_fixed_func_scheduler(dev_priv
);
5357 /* WaDisable4x2SubspanOptimization:hsw */
5358 I915_WRITE(CACHE_MODE_1
,
5359 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5361 /* WaSwitchSolVfFArbitrationPriority:hsw */
5362 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5364 /* WaRsPkgCStateDisplayPMReq:hsw */
5365 I915_WRITE(CHICKEN_PAR1_1
,
5366 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5368 lpt_init_clock_gating(dev
);
5371 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5376 I915_WRITE(WM3_LP_ILK
, 0);
5377 I915_WRITE(WM2_LP_ILK
, 0);
5378 I915_WRITE(WM1_LP_ILK
, 0);
5380 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5382 /* WaDisableEarlyCull:ivb */
5383 I915_WRITE(_3D_CHICKEN3
,
5384 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5386 /* WaDisableBackToBackFlipFix:ivb */
5387 I915_WRITE(IVB_CHICKEN3
,
5388 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5389 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5391 /* WaDisablePSDDualDispatchEnable:ivb */
5392 if (IS_IVB_GT1(dev
))
5393 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5394 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5396 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2
,
5397 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5399 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5400 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5401 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5403 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5404 I915_WRITE(GEN7_L3CNTLREG1
,
5405 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5406 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5407 GEN7_WA_L3_CHICKEN_MODE
);
5408 if (IS_IVB_GT1(dev
))
5409 I915_WRITE(GEN7_ROW_CHICKEN2
,
5410 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5412 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5413 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5416 /* WaForceL3Serialization:ivb */
5417 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5418 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5420 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5421 * gating disable must be set. Failure to set it results in
5422 * flickering pixels due to Z write ordering failures after
5423 * some amount of runtime in the Mesa "fire" demo, and Unigine
5424 * Sanctuary and Tropics, and apparently anything else with
5425 * alpha test or pixel discard.
5427 * According to the spec, bit 11 (RCCUNIT) must also be set,
5428 * but we didn't debug actual testcases to find it out.
5430 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5431 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5433 I915_WRITE(GEN6_UCGCTL2
,
5434 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
5435 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5437 /* This is required by WaCatErrorRejectionIssue:ivb */
5438 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5439 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5440 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5442 g4x_disable_trickle_feed(dev
);
5444 /* WaVSRefCountFullforceMissDisable:ivb */
5445 gen7_setup_fixed_func_scheduler(dev_priv
);
5447 /* WaDisable4x2SubspanOptimization:ivb */
5448 I915_WRITE(CACHE_MODE_1
,
5449 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5451 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5452 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5453 snpcr
|= GEN6_MBC_SNPCR_MED
;
5454 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5456 if (!HAS_PCH_NOP(dev
))
5457 cpt_init_clock_gating(dev
);
5459 gen6_check_mch_setup(dev
);
5462 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5466 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5468 /* WaDisableEarlyCull:vlv */
5469 I915_WRITE(_3D_CHICKEN3
,
5470 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5472 /* WaDisableBackToBackFlipFix:vlv */
5473 I915_WRITE(IVB_CHICKEN3
,
5474 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5475 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5477 /* WaDisablePSDDualDispatchEnable:vlv */
5478 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5479 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5480 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5482 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5483 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5484 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5486 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5487 I915_WRITE(GEN7_L3CNTLREG1
, I915_READ(GEN7_L3CNTLREG1
) | GEN7_L3AGDIS
);
5488 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
5490 /* WaForceL3Serialization:vlv */
5491 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5492 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5494 /* WaDisableDopClockGating:vlv */
5495 I915_WRITE(GEN7_ROW_CHICKEN2
,
5496 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5498 /* This is required by WaCatErrorRejectionIssue:vlv */
5499 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5500 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5501 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5503 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5504 * gating disable must be set. Failure to set it results in
5505 * flickering pixels due to Z write ordering failures after
5506 * some amount of runtime in the Mesa "fire" demo, and Unigine
5507 * Sanctuary and Tropics, and apparently anything else with
5508 * alpha test or pixel discard.
5510 * According to the spec, bit 11 (RCCUNIT) must also be set,
5511 * but we didn't debug actual testcases to find it out.
5513 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5514 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5516 * Also apply WaDisableVDSUnitClockGating:vlv and
5517 * WaDisableRCPBUnitClockGating:vlv.
5519 I915_WRITE(GEN6_UCGCTL2
,
5520 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
5521 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
5522 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
5523 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5524 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5526 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5528 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5530 I915_WRITE(CACHE_MODE_1
,
5531 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5534 * WaDisableVLVClockGating_VBIIssue:vlv
5535 * Disable clock gating on th GCFG unit to prevent a delay
5536 * in the reporting of vblank events.
5538 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, 0xffffffff);
5540 /* Conservative clock gating settings for now */
5541 I915_WRITE(0x9400, 0xffffffff);
5542 I915_WRITE(0x9404, 0xffffffff);
5543 I915_WRITE(0x9408, 0xffffffff);
5544 I915_WRITE(0x940c, 0xffffffff);
5545 I915_WRITE(0x9410, 0xffffffff);
5546 I915_WRITE(0x9414, 0xffffffff);
5547 I915_WRITE(0x9418, 0xffffffff);
5550 static void g4x_init_clock_gating(struct drm_device
*dev
)
5552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5553 uint32_t dspclk_gate
;
5555 I915_WRITE(RENCLK_GATE_D1
, 0);
5556 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5557 GS_UNIT_CLOCK_GATE_DISABLE
|
5558 CL_UNIT_CLOCK_GATE_DISABLE
);
5559 I915_WRITE(RAMCLK_GATE_D
, 0);
5560 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5561 OVRUNIT_CLOCK_GATE_DISABLE
|
5562 OVCUNIT_CLOCK_GATE_DISABLE
;
5564 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5565 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5567 /* WaDisableRenderCachePipelinedFlush */
5568 I915_WRITE(CACHE_MODE_0
,
5569 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5571 g4x_disable_trickle_feed(dev
);
5574 static void crestline_init_clock_gating(struct drm_device
*dev
)
5576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5578 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5579 I915_WRITE(RENCLK_GATE_D2
, 0);
5580 I915_WRITE(DSPCLK_GATE_D
, 0);
5581 I915_WRITE(RAMCLK_GATE_D
, 0);
5582 I915_WRITE16(DEUC
, 0);
5583 I915_WRITE(MI_ARB_STATE
,
5584 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5587 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5591 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5592 I965_RCC_CLOCK_GATE_DISABLE
|
5593 I965_RCPB_CLOCK_GATE_DISABLE
|
5594 I965_ISC_CLOCK_GATE_DISABLE
|
5595 I965_FBC_CLOCK_GATE_DISABLE
);
5596 I915_WRITE(RENCLK_GATE_D2
, 0);
5597 I915_WRITE(MI_ARB_STATE
,
5598 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5601 static void gen3_init_clock_gating(struct drm_device
*dev
)
5603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5604 u32 dstate
= I915_READ(D_STATE
);
5606 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5607 DSTATE_DOT_CLOCK_GATING
;
5608 I915_WRITE(D_STATE
, dstate
);
5610 if (IS_PINEVIEW(dev
))
5611 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5613 /* IIR "flip pending" means done if this bit is set */
5614 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5617 static void i85x_init_clock_gating(struct drm_device
*dev
)
5619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5621 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5624 static void i830_init_clock_gating(struct drm_device
*dev
)
5626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5628 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5631 void intel_init_clock_gating(struct drm_device
*dev
)
5633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5635 dev_priv
->display
.init_clock_gating(dev
);
5638 void intel_suspend_hw(struct drm_device
*dev
)
5640 if (HAS_PCH_LPT(dev
))
5641 lpt_suspend_hw(dev
);
5644 static bool is_always_on_power_domain(struct drm_device
*dev
,
5645 enum intel_display_power_domain domain
)
5647 unsigned long always_on_domains
;
5649 BUG_ON(BIT(domain
) & ~POWER_DOMAIN_MASK
);
5651 if (IS_BROADWELL(dev
)) {
5652 always_on_domains
= BDW_ALWAYS_ON_POWER_DOMAINS
;
5653 } else if (IS_HASWELL(dev
)) {
5654 always_on_domains
= HSW_ALWAYS_ON_POWER_DOMAINS
;
5660 return BIT(domain
) & always_on_domains
;
5664 * We should only use the power well if we explicitly asked the hardware to
5665 * enable it, so check if it's enabled and also check if we've requested it to
5668 bool intel_display_power_enabled(struct drm_device
*dev
,
5669 enum intel_display_power_domain domain
)
5671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5673 if (!HAS_POWER_WELL(dev
))
5676 if (is_always_on_power_domain(dev
, domain
))
5679 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5680 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
5683 static void __intel_set_power_well(struct drm_device
*dev
, bool enable
)
5685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5686 bool is_enabled
, enable_requested
;
5689 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5690 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
5691 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
5694 if (!enable_requested
)
5695 I915_WRITE(HSW_PWR_WELL_DRIVER
,
5696 HSW_PWR_WELL_ENABLE_REQUEST
);
5699 DRM_DEBUG_KMS("Enabling power well\n");
5700 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5701 HSW_PWR_WELL_STATE_ENABLED
), 20))
5702 DRM_ERROR("Timeout enabling power well\n");
5705 if (enable_requested
) {
5706 unsigned long irqflags
;
5709 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5710 POSTING_READ(HSW_PWR_WELL_DRIVER
);
5711 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5714 * After this, the registers on the pipes that are part
5715 * of the power well will become zero, so we have to
5716 * adjust our counters according to that.
5718 * FIXME: Should we do this in general in
5719 * drm_vblank_post_modeset?
5721 spin_lock_irqsave(&dev
->vbl_lock
, irqflags
);
5724 dev
->vblank
[p
].last
= 0;
5725 spin_unlock_irqrestore(&dev
->vbl_lock
, irqflags
);
5730 static void __intel_power_well_get(struct drm_device
*dev
,
5731 struct i915_power_well
*power_well
)
5733 if (!power_well
->count
++)
5734 __intel_set_power_well(dev
, true);
5737 static void __intel_power_well_put(struct drm_device
*dev
,
5738 struct i915_power_well
*power_well
)
5740 WARN_ON(!power_well
->count
);
5741 if (!--power_well
->count
&& i915_disable_power_well
)
5742 __intel_set_power_well(dev
, false);
5745 void intel_display_power_get(struct drm_device
*dev
,
5746 enum intel_display_power_domain domain
)
5748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5749 struct i915_power_domains
*power_domains
;
5751 if (!HAS_POWER_WELL(dev
))
5754 if (is_always_on_power_domain(dev
, domain
))
5757 power_domains
= &dev_priv
->power_domains
;
5759 mutex_lock(&power_domains
->lock
);
5760 __intel_power_well_get(dev
, &power_domains
->power_wells
[0]);
5761 mutex_unlock(&power_domains
->lock
);
5764 void intel_display_power_put(struct drm_device
*dev
,
5765 enum intel_display_power_domain domain
)
5767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5768 struct i915_power_domains
*power_domains
;
5770 if (!HAS_POWER_WELL(dev
))
5773 if (is_always_on_power_domain(dev
, domain
))
5776 power_domains
= &dev_priv
->power_domains
;
5778 mutex_lock(&power_domains
->lock
);
5779 __intel_power_well_put(dev
, &power_domains
->power_wells
[0]);
5780 mutex_unlock(&power_domains
->lock
);
5783 static struct i915_power_domains
*hsw_pwr
;
5785 /* Display audio driver power well request */
5786 void i915_request_power_well(void)
5788 struct drm_i915_private
*dev_priv
;
5790 if (WARN_ON(!hsw_pwr
))
5793 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
5796 mutex_lock(&hsw_pwr
->lock
);
5797 __intel_power_well_get(dev_priv
->dev
, &hsw_pwr
->power_wells
[0]);
5798 mutex_unlock(&hsw_pwr
->lock
);
5800 EXPORT_SYMBOL_GPL(i915_request_power_well
);
5802 /* Display audio driver power well release */
5803 void i915_release_power_well(void)
5805 struct drm_i915_private
*dev_priv
;
5807 if (WARN_ON(!hsw_pwr
))
5810 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
5813 mutex_lock(&hsw_pwr
->lock
);
5814 __intel_power_well_put(dev_priv
->dev
, &hsw_pwr
->power_wells
[0]);
5815 mutex_unlock(&hsw_pwr
->lock
);
5817 EXPORT_SYMBOL_GPL(i915_release_power_well
);
5819 int intel_power_domains_init(struct drm_device
*dev
)
5821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5822 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
5823 struct i915_power_well
*power_well
;
5825 mutex_init(&power_domains
->lock
);
5826 hsw_pwr
= power_domains
;
5828 power_well
= &power_domains
->power_wells
[0];
5829 power_well
->count
= 0;
5834 void intel_power_domains_remove(struct drm_device
*dev
)
5839 static void intel_power_domains_resume(struct drm_device
*dev
)
5841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5842 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
5843 struct i915_power_well
*power_well
;
5845 if (!HAS_POWER_WELL(dev
))
5848 mutex_lock(&power_domains
->lock
);
5850 power_well
= &power_domains
->power_wells
[0];
5851 __intel_set_power_well(dev
, power_well
->count
> 0);
5853 mutex_unlock(&power_domains
->lock
);
5857 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5858 * when not needed anymore. We have 4 registers that can request the power well
5859 * to be enabled, and it will only be disabled if none of the registers is
5860 * requesting it to be enabled.
5862 void intel_power_domains_init_hw(struct drm_device
*dev
)
5864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5866 if (!HAS_POWER_WELL(dev
))
5869 /* For now, we need the power well to be always enabled. */
5870 intel_display_set_init_power(dev
, true);
5871 intel_power_domains_resume(dev
);
5873 /* We're taking over the BIOS, so clear any requests made by it since
5874 * the driver is in charge now. */
5875 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
5876 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
5879 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5880 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
5882 hsw_disable_package_c8(dev_priv
);
5885 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
5887 hsw_enable_package_c8(dev_priv
);
5890 /* Set up chip specific power management-related functions */
5891 void intel_init_pm(struct drm_device
*dev
)
5893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5895 if (I915_HAS_FBC(dev
)) {
5896 if (HAS_PCH_SPLIT(dev
)) {
5897 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5898 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
5899 dev_priv
->display
.enable_fbc
=
5902 dev_priv
->display
.enable_fbc
=
5903 ironlake_enable_fbc
;
5904 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5905 } else if (IS_GM45(dev
)) {
5906 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5907 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5908 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5909 } else if (IS_CRESTLINE(dev
)) {
5910 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5911 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5912 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5914 /* 855GM needs testing */
5918 if (IS_PINEVIEW(dev
))
5919 i915_pineview_get_mem_freq(dev
);
5920 else if (IS_GEN5(dev
))
5921 i915_ironlake_get_mem_freq(dev
);
5923 /* For FIFO watermark updates */
5924 if (HAS_PCH_SPLIT(dev
)) {
5925 intel_setup_wm_latency(dev
);
5928 if (dev_priv
->wm
.pri_latency
[1] &&
5929 dev_priv
->wm
.spr_latency
[1] &&
5930 dev_priv
->wm
.cur_latency
[1])
5931 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5933 DRM_DEBUG_KMS("Failed to get proper latency. "
5935 dev_priv
->display
.update_wm
= NULL
;
5937 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
5938 } else if (IS_GEN6(dev
)) {
5939 if (dev_priv
->wm
.pri_latency
[0] &&
5940 dev_priv
->wm
.spr_latency
[0] &&
5941 dev_priv
->wm
.cur_latency
[0]) {
5942 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
5943 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5945 DRM_DEBUG_KMS("Failed to read display plane latency. "
5947 dev_priv
->display
.update_wm
= NULL
;
5949 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
5950 } else if (IS_IVYBRIDGE(dev
)) {
5951 if (dev_priv
->wm
.pri_latency
[0] &&
5952 dev_priv
->wm
.spr_latency
[0] &&
5953 dev_priv
->wm
.cur_latency
[0]) {
5954 dev_priv
->display
.update_wm
= ivybridge_update_wm
;
5955 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5957 DRM_DEBUG_KMS("Failed to read display plane latency. "
5959 dev_priv
->display
.update_wm
= NULL
;
5961 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
5962 } else if (IS_HASWELL(dev
)) {
5963 if (dev_priv
->wm
.pri_latency
[0] &&
5964 dev_priv
->wm
.spr_latency
[0] &&
5965 dev_priv
->wm
.cur_latency
[0]) {
5966 dev_priv
->display
.update_wm
= haswell_update_wm
;
5967 dev_priv
->display
.update_sprite_wm
=
5968 haswell_update_sprite_wm
;
5970 DRM_DEBUG_KMS("Failed to read display plane latency. "
5972 dev_priv
->display
.update_wm
= NULL
;
5974 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
5975 } else if (INTEL_INFO(dev
)->gen
== 8) {
5976 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
5978 dev_priv
->display
.update_wm
= NULL
;
5979 } else if (IS_VALLEYVIEW(dev
)) {
5980 dev_priv
->display
.update_wm
= valleyview_update_wm
;
5981 dev_priv
->display
.init_clock_gating
=
5982 valleyview_init_clock_gating
;
5983 } else if (IS_PINEVIEW(dev
)) {
5984 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5987 dev_priv
->mem_freq
)) {
5988 DRM_INFO("failed to find known CxSR latency "
5989 "(found ddr%s fsb freq %d, mem freq %d), "
5991 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
5992 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5993 /* Disable CxSR and never update its watermark again */
5994 pineview_disable_cxsr(dev
);
5995 dev_priv
->display
.update_wm
= NULL
;
5997 dev_priv
->display
.update_wm
= pineview_update_wm
;
5998 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
5999 } else if (IS_G4X(dev
)) {
6000 dev_priv
->display
.update_wm
= g4x_update_wm
;
6001 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6002 } else if (IS_GEN4(dev
)) {
6003 dev_priv
->display
.update_wm
= i965_update_wm
;
6004 if (IS_CRESTLINE(dev
))
6005 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6006 else if (IS_BROADWATER(dev
))
6007 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6008 } else if (IS_GEN3(dev
)) {
6009 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6010 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6011 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6012 } else if (IS_I865G(dev
)) {
6013 dev_priv
->display
.update_wm
= i830_update_wm
;
6014 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6015 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6016 } else if (IS_I85X(dev
)) {
6017 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6018 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
6019 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6021 dev_priv
->display
.update_wm
= i830_update_wm
;
6022 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6024 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6026 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6030 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
6032 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6034 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6035 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6039 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6040 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6042 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6044 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6048 *val
= I915_READ(GEN6_PCODE_DATA
);
6049 I915_WRITE(GEN6_PCODE_DATA
, 0);
6054 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
6056 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6058 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6059 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6063 I915_WRITE(GEN6_PCODE_DATA
, val
);
6064 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6066 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6068 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6072 I915_WRITE(GEN6_PCODE_DATA
, 0);
6077 int vlv_gpu_freq(int ddr_freq
, int val
)
6098 return ((val
- 0xbd) * mult
) + base
;
6101 int vlv_freq_opcode(int ddr_freq
, int val
)
6132 void intel_pm_init(struct drm_device
*dev
)
6134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6136 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6137 intel_gen6_powersave_work
);