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drm/i915: Drop WaApplyL3ControlAndL3ChickenMode:hsw
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int i;
101 u32 fbc_ctl;
102
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
126
127 /* enable it... */
128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
139 }
140
141 static bool i8xx_fbc_enabled(struct drm_device *dev)
142 {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146 }
147
148 static void g4x_enable_fbc(struct drm_crtc *crtc)
149 {
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_framebuffer *fb = crtc->fb;
153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
156 u32 dpfc_ctl;
157
158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
164
165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
169
170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
171 }
172
173 static void g4x_disable_fbc(struct drm_device *dev)
174 {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186 }
187
188 static bool g4x_fbc_enabled(struct drm_device *dev)
189 {
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193 }
194
195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
196 {
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
205
206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
216
217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
218 }
219
220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
221 {
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 struct drm_framebuffer *fb = crtc->fb;
225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
228 u32 dpfc_ctl;
229
230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
238
239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
252 }
253
254 static void ironlake_disable_fbc(struct drm_device *dev)
255 {
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267 }
268
269 static bool ironlake_fbc_enabled(struct drm_device *dev)
270 {
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274 }
275
276 static void gen7_enable_fbc(struct drm_crtc *crtc)
277 {
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct drm_framebuffer *fb = crtc->fb;
281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
284 u32 dpfc_ctl;
285
286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
294
295 if (IS_IVYBRIDGE(dev)) {
296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
297 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
298 } else {
299 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
300 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
301 HSW_BYPASS_FBC_QUEUE);
302 }
303
304 I915_WRITE(SNB_DPFC_CTL_SA,
305 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
306 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
307
308 sandybridge_blit_fbc_update(dev);
309
310 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
311 }
312
313 bool intel_fbc_enabled(struct drm_device *dev)
314 {
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 if (!dev_priv->display.fbc_enabled)
318 return false;
319
320 return dev_priv->display.fbc_enabled(dev);
321 }
322
323 static void intel_fbc_work_fn(struct work_struct *__work)
324 {
325 struct intel_fbc_work *work =
326 container_of(to_delayed_work(__work),
327 struct intel_fbc_work, work);
328 struct drm_device *dev = work->crtc->dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330
331 mutex_lock(&dev->struct_mutex);
332 if (work == dev_priv->fbc.fbc_work) {
333 /* Double check that we haven't switched fb without cancelling
334 * the prior work.
335 */
336 if (work->crtc->fb == work->fb) {
337 dev_priv->display.enable_fbc(work->crtc);
338
339 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
340 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
341 dev_priv->fbc.y = work->crtc->y;
342 }
343
344 dev_priv->fbc.fbc_work = NULL;
345 }
346 mutex_unlock(&dev->struct_mutex);
347
348 kfree(work);
349 }
350
351 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
352 {
353 if (dev_priv->fbc.fbc_work == NULL)
354 return;
355
356 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
357
358 /* Synchronisation is provided by struct_mutex and checking of
359 * dev_priv->fbc.fbc_work, so we can perform the cancellation
360 * entirely asynchronously.
361 */
362 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
363 /* tasklet was killed before being run, clean up */
364 kfree(dev_priv->fbc.fbc_work);
365
366 /* Mark the work as no longer wanted so that if it does
367 * wake-up (because the work was already running and waiting
368 * for our mutex), it will discover that is no longer
369 * necessary to run.
370 */
371 dev_priv->fbc.fbc_work = NULL;
372 }
373
374 static void intel_enable_fbc(struct drm_crtc *crtc)
375 {
376 struct intel_fbc_work *work;
377 struct drm_device *dev = crtc->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379
380 if (!dev_priv->display.enable_fbc)
381 return;
382
383 intel_cancel_fbc_work(dev_priv);
384
385 work = kzalloc(sizeof(*work), GFP_KERNEL);
386 if (work == NULL) {
387 DRM_ERROR("Failed to allocate FBC work structure\n");
388 dev_priv->display.enable_fbc(crtc);
389 return;
390 }
391
392 work->crtc = crtc;
393 work->fb = crtc->fb;
394 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
395
396 dev_priv->fbc.fbc_work = work;
397
398 /* Delay the actual enabling to let pageflipping cease and the
399 * display to settle before starting the compression. Note that
400 * this delay also serves a second purpose: it allows for a
401 * vblank to pass after disabling the FBC before we attempt
402 * to modify the control registers.
403 *
404 * A more complicated solution would involve tracking vblanks
405 * following the termination of the page-flipping sequence
406 * and indeed performing the enable as a co-routine and not
407 * waiting synchronously upon the vblank.
408 *
409 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
410 */
411 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
412 }
413
414 void intel_disable_fbc(struct drm_device *dev)
415 {
416 struct drm_i915_private *dev_priv = dev->dev_private;
417
418 intel_cancel_fbc_work(dev_priv);
419
420 if (!dev_priv->display.disable_fbc)
421 return;
422
423 dev_priv->display.disable_fbc(dev);
424 dev_priv->fbc.plane = -1;
425 }
426
427 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
428 enum no_fbc_reason reason)
429 {
430 if (dev_priv->fbc.no_fbc_reason == reason)
431 return false;
432
433 dev_priv->fbc.no_fbc_reason = reason;
434 return true;
435 }
436
437 /**
438 * intel_update_fbc - enable/disable FBC as needed
439 * @dev: the drm_device
440 *
441 * Set up the framebuffer compression hardware at mode set time. We
442 * enable it if possible:
443 * - plane A only (on pre-965)
444 * - no pixel mulitply/line duplication
445 * - no alpha buffer discard
446 * - no dual wide
447 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
448 *
449 * We can't assume that any compression will take place (worst case),
450 * so the compressed buffer has to be the same size as the uncompressed
451 * one. It also must reside (along with the line length buffer) in
452 * stolen memory.
453 *
454 * We need to enable/disable FBC on a global basis.
455 */
456 void intel_update_fbc(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459 struct drm_crtc *crtc = NULL, *tmp_crtc;
460 struct intel_crtc *intel_crtc;
461 struct drm_framebuffer *fb;
462 struct intel_framebuffer *intel_fb;
463 struct drm_i915_gem_object *obj;
464 const struct drm_display_mode *adjusted_mode;
465 unsigned int max_width, max_height;
466
467 if (!HAS_FBC(dev)) {
468 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
469 return;
470 }
471
472 if (!i915.powersave) {
473 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
474 DRM_DEBUG_KMS("fbc disabled per module param\n");
475 return;
476 }
477
478 /*
479 * If FBC is already on, we just have to verify that we can
480 * keep it that way...
481 * Need to disable if:
482 * - more than one pipe is active
483 * - changing FBC params (stride, fence, mode)
484 * - new fb is too large to fit in compressed buffer
485 * - going to an unsupported config (interlace, pixel multiply, etc.)
486 */
487 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
488 if (intel_crtc_active(tmp_crtc) &&
489 to_intel_crtc(tmp_crtc)->primary_enabled) {
490 if (crtc) {
491 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
492 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
493 goto out_disable;
494 }
495 crtc = tmp_crtc;
496 }
497 }
498
499 if (!crtc || crtc->fb == NULL) {
500 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
501 DRM_DEBUG_KMS("no output, disabling\n");
502 goto out_disable;
503 }
504
505 intel_crtc = to_intel_crtc(crtc);
506 fb = crtc->fb;
507 intel_fb = to_intel_framebuffer(fb);
508 obj = intel_fb->obj;
509 adjusted_mode = &intel_crtc->config.adjusted_mode;
510
511 if (i915.enable_fbc < 0 &&
512 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
513 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
514 DRM_DEBUG_KMS("disabled per chip default\n");
515 goto out_disable;
516 }
517 if (!i915.enable_fbc) {
518 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
519 DRM_DEBUG_KMS("fbc disabled per module param\n");
520 goto out_disable;
521 }
522 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
523 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
524 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
525 DRM_DEBUG_KMS("mode incompatible with compression, "
526 "disabling\n");
527 goto out_disable;
528 }
529
530 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
531 max_width = 4096;
532 max_height = 2048;
533 } else {
534 max_width = 2048;
535 max_height = 1536;
536 }
537 if (intel_crtc->config.pipe_src_w > max_width ||
538 intel_crtc->config.pipe_src_h > max_height) {
539 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
540 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
541 goto out_disable;
542 }
543 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
544 intel_crtc->plane != PLANE_A) {
545 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
546 DRM_DEBUG_KMS("plane not A, disabling compression\n");
547 goto out_disable;
548 }
549
550 /* The use of a CPU fence is mandatory in order to detect writes
551 * by the CPU to the scanout and trigger updates to the FBC.
552 */
553 if (obj->tiling_mode != I915_TILING_X ||
554 obj->fence_reg == I915_FENCE_REG_NONE) {
555 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
556 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
557 goto out_disable;
558 }
559
560 /* If the kernel debugger is active, always disable compression */
561 if (in_dbg_master())
562 goto out_disable;
563
564 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
565 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
566 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
567 goto out_disable;
568 }
569
570 /* If the scanout has not changed, don't modify the FBC settings.
571 * Note that we make the fundamental assumption that the fb->obj
572 * cannot be unpinned (and have its GTT offset and fence revoked)
573 * without first being decoupled from the scanout and FBC disabled.
574 */
575 if (dev_priv->fbc.plane == intel_crtc->plane &&
576 dev_priv->fbc.fb_id == fb->base.id &&
577 dev_priv->fbc.y == crtc->y)
578 return;
579
580 if (intel_fbc_enabled(dev)) {
581 /* We update FBC along two paths, after changing fb/crtc
582 * configuration (modeswitching) and after page-flipping
583 * finishes. For the latter, we know that not only did
584 * we disable the FBC at the start of the page-flip
585 * sequence, but also more than one vblank has passed.
586 *
587 * For the former case of modeswitching, it is possible
588 * to switch between two FBC valid configurations
589 * instantaneously so we do need to disable the FBC
590 * before we can modify its control registers. We also
591 * have to wait for the next vblank for that to take
592 * effect. However, since we delay enabling FBC we can
593 * assume that a vblank has passed since disabling and
594 * that we can safely alter the registers in the deferred
595 * callback.
596 *
597 * In the scenario that we go from a valid to invalid
598 * and then back to valid FBC configuration we have
599 * no strict enforcement that a vblank occurred since
600 * disabling the FBC. However, along all current pipe
601 * disabling paths we do need to wait for a vblank at
602 * some point. And we wait before enabling FBC anyway.
603 */
604 DRM_DEBUG_KMS("disabling active FBC for update\n");
605 intel_disable_fbc(dev);
606 }
607
608 intel_enable_fbc(crtc);
609 dev_priv->fbc.no_fbc_reason = FBC_OK;
610 return;
611
612 out_disable:
613 /* Multiple disables should be harmless */
614 if (intel_fbc_enabled(dev)) {
615 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
616 intel_disable_fbc(dev);
617 }
618 i915_gem_stolen_cleanup_compression(dev);
619 }
620
621 static void i915_pineview_get_mem_freq(struct drm_device *dev)
622 {
623 drm_i915_private_t *dev_priv = dev->dev_private;
624 u32 tmp;
625
626 tmp = I915_READ(CLKCFG);
627
628 switch (tmp & CLKCFG_FSB_MASK) {
629 case CLKCFG_FSB_533:
630 dev_priv->fsb_freq = 533; /* 133*4 */
631 break;
632 case CLKCFG_FSB_800:
633 dev_priv->fsb_freq = 800; /* 200*4 */
634 break;
635 case CLKCFG_FSB_667:
636 dev_priv->fsb_freq = 667; /* 167*4 */
637 break;
638 case CLKCFG_FSB_400:
639 dev_priv->fsb_freq = 400; /* 100*4 */
640 break;
641 }
642
643 switch (tmp & CLKCFG_MEM_MASK) {
644 case CLKCFG_MEM_533:
645 dev_priv->mem_freq = 533;
646 break;
647 case CLKCFG_MEM_667:
648 dev_priv->mem_freq = 667;
649 break;
650 case CLKCFG_MEM_800:
651 dev_priv->mem_freq = 800;
652 break;
653 }
654
655 /* detect pineview DDR3 setting */
656 tmp = I915_READ(CSHRDDR3CTL);
657 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
658 }
659
660 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
661 {
662 drm_i915_private_t *dev_priv = dev->dev_private;
663 u16 ddrpll, csipll;
664
665 ddrpll = I915_READ16(DDRMPLL1);
666 csipll = I915_READ16(CSIPLL0);
667
668 switch (ddrpll & 0xff) {
669 case 0xc:
670 dev_priv->mem_freq = 800;
671 break;
672 case 0x10:
673 dev_priv->mem_freq = 1066;
674 break;
675 case 0x14:
676 dev_priv->mem_freq = 1333;
677 break;
678 case 0x18:
679 dev_priv->mem_freq = 1600;
680 break;
681 default:
682 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
683 ddrpll & 0xff);
684 dev_priv->mem_freq = 0;
685 break;
686 }
687
688 dev_priv->ips.r_t = dev_priv->mem_freq;
689
690 switch (csipll & 0x3ff) {
691 case 0x00c:
692 dev_priv->fsb_freq = 3200;
693 break;
694 case 0x00e:
695 dev_priv->fsb_freq = 3733;
696 break;
697 case 0x010:
698 dev_priv->fsb_freq = 4266;
699 break;
700 case 0x012:
701 dev_priv->fsb_freq = 4800;
702 break;
703 case 0x014:
704 dev_priv->fsb_freq = 5333;
705 break;
706 case 0x016:
707 dev_priv->fsb_freq = 5866;
708 break;
709 case 0x018:
710 dev_priv->fsb_freq = 6400;
711 break;
712 default:
713 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
714 csipll & 0x3ff);
715 dev_priv->fsb_freq = 0;
716 break;
717 }
718
719 if (dev_priv->fsb_freq == 3200) {
720 dev_priv->ips.c_m = 0;
721 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
722 dev_priv->ips.c_m = 1;
723 } else {
724 dev_priv->ips.c_m = 2;
725 }
726 }
727
728 static const struct cxsr_latency cxsr_latency_table[] = {
729 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
730 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
731 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
732 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
733 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
734
735 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
736 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
737 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
738 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
739 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
740
741 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
742 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
743 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
744 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
745 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
746
747 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
748 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
749 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
750 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
751 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
752
753 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
754 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
755 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
756 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
757 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
758
759 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
760 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
761 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
762 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
763 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
764 };
765
766 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
767 int is_ddr3,
768 int fsb,
769 int mem)
770 {
771 const struct cxsr_latency *latency;
772 int i;
773
774 if (fsb == 0 || mem == 0)
775 return NULL;
776
777 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
778 latency = &cxsr_latency_table[i];
779 if (is_desktop == latency->is_desktop &&
780 is_ddr3 == latency->is_ddr3 &&
781 fsb == latency->fsb_freq && mem == latency->mem_freq)
782 return latency;
783 }
784
785 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
786
787 return NULL;
788 }
789
790 static void pineview_disable_cxsr(struct drm_device *dev)
791 {
792 struct drm_i915_private *dev_priv = dev->dev_private;
793
794 /* deactivate cxsr */
795 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
796 }
797
798 /*
799 * Latency for FIFO fetches is dependent on several factors:
800 * - memory configuration (speed, channels)
801 * - chipset
802 * - current MCH state
803 * It can be fairly high in some situations, so here we assume a fairly
804 * pessimal value. It's a tradeoff between extra memory fetches (if we
805 * set this value too high, the FIFO will fetch frequently to stay full)
806 * and power consumption (set it too low to save power and we might see
807 * FIFO underruns and display "flicker").
808 *
809 * A value of 5us seems to be a good balance; safe for very low end
810 * platforms but not overly aggressive on lower latency configs.
811 */
812 static const int latency_ns = 5000;
813
814 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
815 {
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 uint32_t dsparb = I915_READ(DSPARB);
818 int size;
819
820 size = dsparb & 0x7f;
821 if (plane)
822 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
823
824 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
825 plane ? "B" : "A", size);
826
827 return size;
828 }
829
830 static int i830_get_fifo_size(struct drm_device *dev, int plane)
831 {
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 uint32_t dsparb = I915_READ(DSPARB);
834 int size;
835
836 size = dsparb & 0x1ff;
837 if (plane)
838 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
839 size >>= 1; /* Convert to cachelines */
840
841 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
842 plane ? "B" : "A", size);
843
844 return size;
845 }
846
847 static int i845_get_fifo_size(struct drm_device *dev, int plane)
848 {
849 struct drm_i915_private *dev_priv = dev->dev_private;
850 uint32_t dsparb = I915_READ(DSPARB);
851 int size;
852
853 size = dsparb & 0x7f;
854 size >>= 2; /* Convert to cachelines */
855
856 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
857 plane ? "B" : "A",
858 size);
859
860 return size;
861 }
862
863 /* Pineview has different values for various configs */
864 static const struct intel_watermark_params pineview_display_wm = {
865 PINEVIEW_DISPLAY_FIFO,
866 PINEVIEW_MAX_WM,
867 PINEVIEW_DFT_WM,
868 PINEVIEW_GUARD_WM,
869 PINEVIEW_FIFO_LINE_SIZE
870 };
871 static const struct intel_watermark_params pineview_display_hplloff_wm = {
872 PINEVIEW_DISPLAY_FIFO,
873 PINEVIEW_MAX_WM,
874 PINEVIEW_DFT_HPLLOFF_WM,
875 PINEVIEW_GUARD_WM,
876 PINEVIEW_FIFO_LINE_SIZE
877 };
878 static const struct intel_watermark_params pineview_cursor_wm = {
879 PINEVIEW_CURSOR_FIFO,
880 PINEVIEW_CURSOR_MAX_WM,
881 PINEVIEW_CURSOR_DFT_WM,
882 PINEVIEW_CURSOR_GUARD_WM,
883 PINEVIEW_FIFO_LINE_SIZE,
884 };
885 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
886 PINEVIEW_CURSOR_FIFO,
887 PINEVIEW_CURSOR_MAX_WM,
888 PINEVIEW_CURSOR_DFT_WM,
889 PINEVIEW_CURSOR_GUARD_WM,
890 PINEVIEW_FIFO_LINE_SIZE
891 };
892 static const struct intel_watermark_params g4x_wm_info = {
893 G4X_FIFO_SIZE,
894 G4X_MAX_WM,
895 G4X_MAX_WM,
896 2,
897 G4X_FIFO_LINE_SIZE,
898 };
899 static const struct intel_watermark_params g4x_cursor_wm_info = {
900 I965_CURSOR_FIFO,
901 I965_CURSOR_MAX_WM,
902 I965_CURSOR_DFT_WM,
903 2,
904 G4X_FIFO_LINE_SIZE,
905 };
906 static const struct intel_watermark_params valleyview_wm_info = {
907 VALLEYVIEW_FIFO_SIZE,
908 VALLEYVIEW_MAX_WM,
909 VALLEYVIEW_MAX_WM,
910 2,
911 G4X_FIFO_LINE_SIZE,
912 };
913 static const struct intel_watermark_params valleyview_cursor_wm_info = {
914 I965_CURSOR_FIFO,
915 VALLEYVIEW_CURSOR_MAX_WM,
916 I965_CURSOR_DFT_WM,
917 2,
918 G4X_FIFO_LINE_SIZE,
919 };
920 static const struct intel_watermark_params i965_cursor_wm_info = {
921 I965_CURSOR_FIFO,
922 I965_CURSOR_MAX_WM,
923 I965_CURSOR_DFT_WM,
924 2,
925 I915_FIFO_LINE_SIZE,
926 };
927 static const struct intel_watermark_params i945_wm_info = {
928 I945_FIFO_SIZE,
929 I915_MAX_WM,
930 1,
931 2,
932 I915_FIFO_LINE_SIZE
933 };
934 static const struct intel_watermark_params i915_wm_info = {
935 I915_FIFO_SIZE,
936 I915_MAX_WM,
937 1,
938 2,
939 I915_FIFO_LINE_SIZE
940 };
941 static const struct intel_watermark_params i830_wm_info = {
942 I855GM_FIFO_SIZE,
943 I915_MAX_WM,
944 1,
945 2,
946 I830_FIFO_LINE_SIZE
947 };
948 static const struct intel_watermark_params i845_wm_info = {
949 I830_FIFO_SIZE,
950 I915_MAX_WM,
951 1,
952 2,
953 I830_FIFO_LINE_SIZE
954 };
955
956 /**
957 * intel_calculate_wm - calculate watermark level
958 * @clock_in_khz: pixel clock
959 * @wm: chip FIFO params
960 * @pixel_size: display pixel size
961 * @latency_ns: memory latency for the platform
962 *
963 * Calculate the watermark level (the level at which the display plane will
964 * start fetching from memory again). Each chip has a different display
965 * FIFO size and allocation, so the caller needs to figure that out and pass
966 * in the correct intel_watermark_params structure.
967 *
968 * As the pixel clock runs, the FIFO will be drained at a rate that depends
969 * on the pixel size. When it reaches the watermark level, it'll start
970 * fetching FIFO line sized based chunks from memory until the FIFO fills
971 * past the watermark point. If the FIFO drains completely, a FIFO underrun
972 * will occur, and a display engine hang could result.
973 */
974 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
975 const struct intel_watermark_params *wm,
976 int fifo_size,
977 int pixel_size,
978 unsigned long latency_ns)
979 {
980 long entries_required, wm_size;
981
982 /*
983 * Note: we need to make sure we don't overflow for various clock &
984 * latency values.
985 * clocks go from a few thousand to several hundred thousand.
986 * latency is usually a few thousand
987 */
988 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
989 1000;
990 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
991
992 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
993
994 wm_size = fifo_size - (entries_required + wm->guard_size);
995
996 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
997
998 /* Don't promote wm_size to unsigned... */
999 if (wm_size > (long)wm->max_wm)
1000 wm_size = wm->max_wm;
1001 if (wm_size <= 0)
1002 wm_size = wm->default_wm;
1003 return wm_size;
1004 }
1005
1006 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1007 {
1008 struct drm_crtc *crtc, *enabled = NULL;
1009
1010 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1011 if (intel_crtc_active(crtc)) {
1012 if (enabled)
1013 return NULL;
1014 enabled = crtc;
1015 }
1016 }
1017
1018 return enabled;
1019 }
1020
1021 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1022 {
1023 struct drm_device *dev = unused_crtc->dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 struct drm_crtc *crtc;
1026 const struct cxsr_latency *latency;
1027 u32 reg;
1028 unsigned long wm;
1029
1030 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1031 dev_priv->fsb_freq, dev_priv->mem_freq);
1032 if (!latency) {
1033 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1034 pineview_disable_cxsr(dev);
1035 return;
1036 }
1037
1038 crtc = single_enabled_crtc(dev);
1039 if (crtc) {
1040 const struct drm_display_mode *adjusted_mode;
1041 int pixel_size = crtc->fb->bits_per_pixel / 8;
1042 int clock;
1043
1044 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1045 clock = adjusted_mode->crtc_clock;
1046
1047 /* Display SR */
1048 wm = intel_calculate_wm(clock, &pineview_display_wm,
1049 pineview_display_wm.fifo_size,
1050 pixel_size, latency->display_sr);
1051 reg = I915_READ(DSPFW1);
1052 reg &= ~DSPFW_SR_MASK;
1053 reg |= wm << DSPFW_SR_SHIFT;
1054 I915_WRITE(DSPFW1, reg);
1055 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1056
1057 /* cursor SR */
1058 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1059 pineview_display_wm.fifo_size,
1060 pixel_size, latency->cursor_sr);
1061 reg = I915_READ(DSPFW3);
1062 reg &= ~DSPFW_CURSOR_SR_MASK;
1063 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1064 I915_WRITE(DSPFW3, reg);
1065
1066 /* Display HPLL off SR */
1067 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1068 pineview_display_hplloff_wm.fifo_size,
1069 pixel_size, latency->display_hpll_disable);
1070 reg = I915_READ(DSPFW3);
1071 reg &= ~DSPFW_HPLL_SR_MASK;
1072 reg |= wm & DSPFW_HPLL_SR_MASK;
1073 I915_WRITE(DSPFW3, reg);
1074
1075 /* cursor HPLL off SR */
1076 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1077 pineview_display_hplloff_wm.fifo_size,
1078 pixel_size, latency->cursor_hpll_disable);
1079 reg = I915_READ(DSPFW3);
1080 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1081 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1082 I915_WRITE(DSPFW3, reg);
1083 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1084
1085 /* activate cxsr */
1086 I915_WRITE(DSPFW3,
1087 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1088 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1089 } else {
1090 pineview_disable_cxsr(dev);
1091 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1092 }
1093 }
1094
1095 static bool g4x_compute_wm0(struct drm_device *dev,
1096 int plane,
1097 const struct intel_watermark_params *display,
1098 int display_latency_ns,
1099 const struct intel_watermark_params *cursor,
1100 int cursor_latency_ns,
1101 int *plane_wm,
1102 int *cursor_wm)
1103 {
1104 struct drm_crtc *crtc;
1105 const struct drm_display_mode *adjusted_mode;
1106 int htotal, hdisplay, clock, pixel_size;
1107 int line_time_us, line_count;
1108 int entries, tlb_miss;
1109
1110 crtc = intel_get_crtc_for_plane(dev, plane);
1111 if (!intel_crtc_active(crtc)) {
1112 *cursor_wm = cursor->guard_size;
1113 *plane_wm = display->guard_size;
1114 return false;
1115 }
1116
1117 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1118 clock = adjusted_mode->crtc_clock;
1119 htotal = adjusted_mode->crtc_htotal;
1120 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1121 pixel_size = crtc->fb->bits_per_pixel / 8;
1122
1123 /* Use the small buffer method to calculate plane watermark */
1124 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1125 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1126 if (tlb_miss > 0)
1127 entries += tlb_miss;
1128 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1129 *plane_wm = entries + display->guard_size;
1130 if (*plane_wm > (int)display->max_wm)
1131 *plane_wm = display->max_wm;
1132
1133 /* Use the large buffer method to calculate cursor watermark */
1134 line_time_us = ((htotal * 1000) / clock);
1135 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1136 entries = line_count * 64 * pixel_size;
1137 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1138 if (tlb_miss > 0)
1139 entries += tlb_miss;
1140 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1141 *cursor_wm = entries + cursor->guard_size;
1142 if (*cursor_wm > (int)cursor->max_wm)
1143 *cursor_wm = (int)cursor->max_wm;
1144
1145 return true;
1146 }
1147
1148 /*
1149 * Check the wm result.
1150 *
1151 * If any calculated watermark values is larger than the maximum value that
1152 * can be programmed into the associated watermark register, that watermark
1153 * must be disabled.
1154 */
1155 static bool g4x_check_srwm(struct drm_device *dev,
1156 int display_wm, int cursor_wm,
1157 const struct intel_watermark_params *display,
1158 const struct intel_watermark_params *cursor)
1159 {
1160 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1161 display_wm, cursor_wm);
1162
1163 if (display_wm > display->max_wm) {
1164 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1165 display_wm, display->max_wm);
1166 return false;
1167 }
1168
1169 if (cursor_wm > cursor->max_wm) {
1170 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1171 cursor_wm, cursor->max_wm);
1172 return false;
1173 }
1174
1175 if (!(display_wm || cursor_wm)) {
1176 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1177 return false;
1178 }
1179
1180 return true;
1181 }
1182
1183 static bool g4x_compute_srwm(struct drm_device *dev,
1184 int plane,
1185 int latency_ns,
1186 const struct intel_watermark_params *display,
1187 const struct intel_watermark_params *cursor,
1188 int *display_wm, int *cursor_wm)
1189 {
1190 struct drm_crtc *crtc;
1191 const struct drm_display_mode *adjusted_mode;
1192 int hdisplay, htotal, pixel_size, clock;
1193 unsigned long line_time_us;
1194 int line_count, line_size;
1195 int small, large;
1196 int entries;
1197
1198 if (!latency_ns) {
1199 *display_wm = *cursor_wm = 0;
1200 return false;
1201 }
1202
1203 crtc = intel_get_crtc_for_plane(dev, plane);
1204 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1205 clock = adjusted_mode->crtc_clock;
1206 htotal = adjusted_mode->crtc_htotal;
1207 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1208 pixel_size = crtc->fb->bits_per_pixel / 8;
1209
1210 line_time_us = (htotal * 1000) / clock;
1211 line_count = (latency_ns / line_time_us + 1000) / 1000;
1212 line_size = hdisplay * pixel_size;
1213
1214 /* Use the minimum of the small and large buffer method for primary */
1215 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1216 large = line_count * line_size;
1217
1218 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1219 *display_wm = entries + display->guard_size;
1220
1221 /* calculate the self-refresh watermark for display cursor */
1222 entries = line_count * pixel_size * 64;
1223 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1224 *cursor_wm = entries + cursor->guard_size;
1225
1226 return g4x_check_srwm(dev,
1227 *display_wm, *cursor_wm,
1228 display, cursor);
1229 }
1230
1231 static bool vlv_compute_drain_latency(struct drm_device *dev,
1232 int plane,
1233 int *plane_prec_mult,
1234 int *plane_dl,
1235 int *cursor_prec_mult,
1236 int *cursor_dl)
1237 {
1238 struct drm_crtc *crtc;
1239 int clock, pixel_size;
1240 int entries;
1241
1242 crtc = intel_get_crtc_for_plane(dev, plane);
1243 if (!intel_crtc_active(crtc))
1244 return false;
1245
1246 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1247 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1248
1249 entries = (clock / 1000) * pixel_size;
1250 *plane_prec_mult = (entries > 256) ?
1251 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1252 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1253 pixel_size);
1254
1255 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1256 *cursor_prec_mult = (entries > 256) ?
1257 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1258 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1259
1260 return true;
1261 }
1262
1263 /*
1264 * Update drain latency registers of memory arbiter
1265 *
1266 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1267 * to be programmed. Each plane has a drain latency multiplier and a drain
1268 * latency value.
1269 */
1270
1271 static void vlv_update_drain_latency(struct drm_device *dev)
1272 {
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1275 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1276 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1277 either 16 or 32 */
1278
1279 /* For plane A, Cursor A */
1280 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1281 &cursor_prec_mult, &cursora_dl)) {
1282 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1283 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1284 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1285 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1286
1287 I915_WRITE(VLV_DDL1, cursora_prec |
1288 (cursora_dl << DDL_CURSORA_SHIFT) |
1289 planea_prec | planea_dl);
1290 }
1291
1292 /* For plane B, Cursor B */
1293 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1294 &cursor_prec_mult, &cursorb_dl)) {
1295 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1296 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1297 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1298 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1299
1300 I915_WRITE(VLV_DDL2, cursorb_prec |
1301 (cursorb_dl << DDL_CURSORB_SHIFT) |
1302 planeb_prec | planeb_dl);
1303 }
1304 }
1305
1306 #define single_plane_enabled(mask) is_power_of_2(mask)
1307
1308 static void valleyview_update_wm(struct drm_crtc *crtc)
1309 {
1310 struct drm_device *dev = crtc->dev;
1311 static const int sr_latency_ns = 12000;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1314 int plane_sr, cursor_sr;
1315 int ignore_plane_sr, ignore_cursor_sr;
1316 unsigned int enabled = 0;
1317
1318 vlv_update_drain_latency(dev);
1319
1320 if (g4x_compute_wm0(dev, PIPE_A,
1321 &valleyview_wm_info, latency_ns,
1322 &valleyview_cursor_wm_info, latency_ns,
1323 &planea_wm, &cursora_wm))
1324 enabled |= 1 << PIPE_A;
1325
1326 if (g4x_compute_wm0(dev, PIPE_B,
1327 &valleyview_wm_info, latency_ns,
1328 &valleyview_cursor_wm_info, latency_ns,
1329 &planeb_wm, &cursorb_wm))
1330 enabled |= 1 << PIPE_B;
1331
1332 if (single_plane_enabled(enabled) &&
1333 g4x_compute_srwm(dev, ffs(enabled) - 1,
1334 sr_latency_ns,
1335 &valleyview_wm_info,
1336 &valleyview_cursor_wm_info,
1337 &plane_sr, &ignore_cursor_sr) &&
1338 g4x_compute_srwm(dev, ffs(enabled) - 1,
1339 2*sr_latency_ns,
1340 &valleyview_wm_info,
1341 &valleyview_cursor_wm_info,
1342 &ignore_plane_sr, &cursor_sr)) {
1343 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1344 } else {
1345 I915_WRITE(FW_BLC_SELF_VLV,
1346 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1347 plane_sr = cursor_sr = 0;
1348 }
1349
1350 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1351 planea_wm, cursora_wm,
1352 planeb_wm, cursorb_wm,
1353 plane_sr, cursor_sr);
1354
1355 I915_WRITE(DSPFW1,
1356 (plane_sr << DSPFW_SR_SHIFT) |
1357 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1358 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1359 planea_wm);
1360 I915_WRITE(DSPFW2,
1361 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1362 (cursora_wm << DSPFW_CURSORA_SHIFT));
1363 I915_WRITE(DSPFW3,
1364 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1365 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1366 }
1367
1368 static void g4x_update_wm(struct drm_crtc *crtc)
1369 {
1370 struct drm_device *dev = crtc->dev;
1371 static const int sr_latency_ns = 12000;
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1374 int plane_sr, cursor_sr;
1375 unsigned int enabled = 0;
1376
1377 if (g4x_compute_wm0(dev, PIPE_A,
1378 &g4x_wm_info, latency_ns,
1379 &g4x_cursor_wm_info, latency_ns,
1380 &planea_wm, &cursora_wm))
1381 enabled |= 1 << PIPE_A;
1382
1383 if (g4x_compute_wm0(dev, PIPE_B,
1384 &g4x_wm_info, latency_ns,
1385 &g4x_cursor_wm_info, latency_ns,
1386 &planeb_wm, &cursorb_wm))
1387 enabled |= 1 << PIPE_B;
1388
1389 if (single_plane_enabled(enabled) &&
1390 g4x_compute_srwm(dev, ffs(enabled) - 1,
1391 sr_latency_ns,
1392 &g4x_wm_info,
1393 &g4x_cursor_wm_info,
1394 &plane_sr, &cursor_sr)) {
1395 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1396 } else {
1397 I915_WRITE(FW_BLC_SELF,
1398 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1399 plane_sr = cursor_sr = 0;
1400 }
1401
1402 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403 planea_wm, cursora_wm,
1404 planeb_wm, cursorb_wm,
1405 plane_sr, cursor_sr);
1406
1407 I915_WRITE(DSPFW1,
1408 (plane_sr << DSPFW_SR_SHIFT) |
1409 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1410 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1411 planea_wm);
1412 I915_WRITE(DSPFW2,
1413 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1414 (cursora_wm << DSPFW_CURSORA_SHIFT));
1415 /* HPLL off in SR has some issues on G4x... disable it */
1416 I915_WRITE(DSPFW3,
1417 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1418 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1419 }
1420
1421 static void i965_update_wm(struct drm_crtc *unused_crtc)
1422 {
1423 struct drm_device *dev = unused_crtc->dev;
1424 struct drm_i915_private *dev_priv = dev->dev_private;
1425 struct drm_crtc *crtc;
1426 int srwm = 1;
1427 int cursor_sr = 16;
1428
1429 /* Calc sr entries for one plane configs */
1430 crtc = single_enabled_crtc(dev);
1431 if (crtc) {
1432 /* self-refresh has much higher latency */
1433 static const int sr_latency_ns = 12000;
1434 const struct drm_display_mode *adjusted_mode =
1435 &to_intel_crtc(crtc)->config.adjusted_mode;
1436 int clock = adjusted_mode->crtc_clock;
1437 int htotal = adjusted_mode->crtc_htotal;
1438 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1439 int pixel_size = crtc->fb->bits_per_pixel / 8;
1440 unsigned long line_time_us;
1441 int entries;
1442
1443 line_time_us = ((htotal * 1000) / clock);
1444
1445 /* Use ns/us then divide to preserve precision */
1446 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1447 pixel_size * hdisplay;
1448 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1449 srwm = I965_FIFO_SIZE - entries;
1450 if (srwm < 0)
1451 srwm = 1;
1452 srwm &= 0x1ff;
1453 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1454 entries, srwm);
1455
1456 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1457 pixel_size * 64;
1458 entries = DIV_ROUND_UP(entries,
1459 i965_cursor_wm_info.cacheline_size);
1460 cursor_sr = i965_cursor_wm_info.fifo_size -
1461 (entries + i965_cursor_wm_info.guard_size);
1462
1463 if (cursor_sr > i965_cursor_wm_info.max_wm)
1464 cursor_sr = i965_cursor_wm_info.max_wm;
1465
1466 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1467 "cursor %d\n", srwm, cursor_sr);
1468
1469 if (IS_CRESTLINE(dev))
1470 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1471 } else {
1472 /* Turn off self refresh if both pipes are enabled */
1473 if (IS_CRESTLINE(dev))
1474 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1475 & ~FW_BLC_SELF_EN);
1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
1482 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1483 (8 << 16) | (8 << 8) | (8 << 0));
1484 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1485 /* update cursor SR watermark */
1486 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1487 }
1488
1489 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1490 {
1491 struct drm_device *dev = unused_crtc->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 const struct intel_watermark_params *wm_info;
1494 uint32_t fwater_lo;
1495 uint32_t fwater_hi;
1496 int cwm, srwm = 1;
1497 int fifo_size;
1498 int planea_wm, planeb_wm;
1499 struct drm_crtc *crtc, *enabled = NULL;
1500
1501 if (IS_I945GM(dev))
1502 wm_info = &i945_wm_info;
1503 else if (!IS_GEN2(dev))
1504 wm_info = &i915_wm_info;
1505 else
1506 wm_info = &i830_wm_info;
1507
1508 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1509 crtc = intel_get_crtc_for_plane(dev, 0);
1510 if (intel_crtc_active(crtc)) {
1511 const struct drm_display_mode *adjusted_mode;
1512 int cpp = crtc->fb->bits_per_pixel / 8;
1513 if (IS_GEN2(dev))
1514 cpp = 4;
1515
1516 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1517 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1518 wm_info, fifo_size, cpp,
1519 latency_ns);
1520 enabled = crtc;
1521 } else
1522 planea_wm = fifo_size - wm_info->guard_size;
1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
1526 if (intel_crtc_active(crtc)) {
1527 const struct drm_display_mode *adjusted_mode;
1528 int cpp = crtc->fb->bits_per_pixel / 8;
1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
1532 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534 wm_info, fifo_size, cpp,
1535 latency_ns);
1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
1540 } else
1541 planeb_wm = fifo_size - wm_info->guard_size;
1542
1543 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1544
1545 /*
1546 * Overlay gets an aggressive default since video jitter is bad.
1547 */
1548 cwm = 2;
1549
1550 /* Play safe and disable self-refresh before adjusting watermarks. */
1551 if (IS_I945G(dev) || IS_I945GM(dev))
1552 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1553 else if (IS_I915GM(dev))
1554 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1555
1556 /* Calc sr entries for one plane configs */
1557 if (HAS_FW_BLC(dev) && enabled) {
1558 /* self-refresh has much higher latency */
1559 static const int sr_latency_ns = 6000;
1560 const struct drm_display_mode *adjusted_mode =
1561 &to_intel_crtc(enabled)->config.adjusted_mode;
1562 int clock = adjusted_mode->crtc_clock;
1563 int htotal = adjusted_mode->crtc_htotal;
1564 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1565 int pixel_size = enabled->fb->bits_per_pixel / 8;
1566 unsigned long line_time_us;
1567 int entries;
1568
1569 line_time_us = (htotal * 1000) / clock;
1570
1571 /* Use ns/us then divide to preserve precision */
1572 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1573 pixel_size * hdisplay;
1574 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1575 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1576 srwm = wm_info->fifo_size - entries;
1577 if (srwm < 0)
1578 srwm = 1;
1579
1580 if (IS_I945G(dev) || IS_I945GM(dev))
1581 I915_WRITE(FW_BLC_SELF,
1582 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1583 else if (IS_I915GM(dev))
1584 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1585 }
1586
1587 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1588 planea_wm, planeb_wm, cwm, srwm);
1589
1590 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1591 fwater_hi = (cwm & 0x1f);
1592
1593 /* Set request length to 8 cachelines per fetch */
1594 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1595 fwater_hi = fwater_hi | (1 << 8);
1596
1597 I915_WRITE(FW_BLC, fwater_lo);
1598 I915_WRITE(FW_BLC2, fwater_hi);
1599
1600 if (HAS_FW_BLC(dev)) {
1601 if (enabled) {
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1605 else if (IS_I915GM(dev))
1606 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1607 DRM_DEBUG_KMS("memory self refresh enabled\n");
1608 } else
1609 DRM_DEBUG_KMS("memory self refresh disabled\n");
1610 }
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615 struct drm_device *dev = unused_crtc->dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
1618 const struct drm_display_mode *adjusted_mode;
1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
1626 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628 &i845_wm_info,
1629 dev_priv->display.get_fifo_size(dev, 0),
1630 4, latency_ns);
1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1640 struct drm_crtc *crtc)
1641 {
1642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1643 uint32_t pixel_rate;
1644
1645 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1646
1647 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1648 * adjust the pixel_rate here. */
1649
1650 if (intel_crtc->config.pch_pfit.enabled) {
1651 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1652 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1653
1654 pipe_w = intel_crtc->config.pipe_src_w;
1655 pipe_h = intel_crtc->config.pipe_src_h;
1656 pfit_w = (pfit_size >> 16) & 0xFFFF;
1657 pfit_h = pfit_size & 0xFFFF;
1658 if (pipe_w < pfit_w)
1659 pipe_w = pfit_w;
1660 if (pipe_h < pfit_h)
1661 pipe_h = pfit_h;
1662
1663 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1664 pfit_w * pfit_h);
1665 }
1666
1667 return pixel_rate;
1668 }
1669
1670 /* latency must be in 0.1us units. */
1671 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1672 uint32_t latency)
1673 {
1674 uint64_t ret;
1675
1676 if (WARN(latency == 0, "Latency value missing\n"))
1677 return UINT_MAX;
1678
1679 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1680 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1681
1682 return ret;
1683 }
1684
1685 /* latency must be in 0.1us units. */
1686 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1687 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1688 uint32_t latency)
1689 {
1690 uint32_t ret;
1691
1692 if (WARN(latency == 0, "Latency value missing\n"))
1693 return UINT_MAX;
1694
1695 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1696 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1697 ret = DIV_ROUND_UP(ret, 64) + 2;
1698 return ret;
1699 }
1700
1701 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1702 uint8_t bytes_per_pixel)
1703 {
1704 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1705 }
1706
1707 struct ilk_pipe_wm_parameters {
1708 bool active;
1709 uint32_t pipe_htotal;
1710 uint32_t pixel_rate;
1711 struct intel_plane_wm_parameters pri;
1712 struct intel_plane_wm_parameters spr;
1713 struct intel_plane_wm_parameters cur;
1714 };
1715
1716 struct ilk_wm_maximums {
1717 uint16_t pri;
1718 uint16_t spr;
1719 uint16_t cur;
1720 uint16_t fbc;
1721 };
1722
1723 /* used in computing the new watermarks state */
1724 struct intel_wm_config {
1725 unsigned int num_pipes_active;
1726 bool sprites_enabled;
1727 bool sprites_scaled;
1728 };
1729
1730 /*
1731 * For both WM_PIPE and WM_LP.
1732 * mem_value must be in 0.1us units.
1733 */
1734 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1735 uint32_t mem_value,
1736 bool is_lp)
1737 {
1738 uint32_t method1, method2;
1739
1740 if (!params->active || !params->pri.enabled)
1741 return 0;
1742
1743 method1 = ilk_wm_method1(params->pixel_rate,
1744 params->pri.bytes_per_pixel,
1745 mem_value);
1746
1747 if (!is_lp)
1748 return method1;
1749
1750 method2 = ilk_wm_method2(params->pixel_rate,
1751 params->pipe_htotal,
1752 params->pri.horiz_pixels,
1753 params->pri.bytes_per_pixel,
1754 mem_value);
1755
1756 return min(method1, method2);
1757 }
1758
1759 /*
1760 * For both WM_PIPE and WM_LP.
1761 * mem_value must be in 0.1us units.
1762 */
1763 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1764 uint32_t mem_value)
1765 {
1766 uint32_t method1, method2;
1767
1768 if (!params->active || !params->spr.enabled)
1769 return 0;
1770
1771 method1 = ilk_wm_method1(params->pixel_rate,
1772 params->spr.bytes_per_pixel,
1773 mem_value);
1774 method2 = ilk_wm_method2(params->pixel_rate,
1775 params->pipe_htotal,
1776 params->spr.horiz_pixels,
1777 params->spr.bytes_per_pixel,
1778 mem_value);
1779 return min(method1, method2);
1780 }
1781
1782 /*
1783 * For both WM_PIPE and WM_LP.
1784 * mem_value must be in 0.1us units.
1785 */
1786 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1787 uint32_t mem_value)
1788 {
1789 if (!params->active || !params->cur.enabled)
1790 return 0;
1791
1792 return ilk_wm_method2(params->pixel_rate,
1793 params->pipe_htotal,
1794 params->cur.horiz_pixels,
1795 params->cur.bytes_per_pixel,
1796 mem_value);
1797 }
1798
1799 /* Only for WM_LP. */
1800 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1801 uint32_t pri_val)
1802 {
1803 if (!params->active || !params->pri.enabled)
1804 return 0;
1805
1806 return ilk_wm_fbc(pri_val,
1807 params->pri.horiz_pixels,
1808 params->pri.bytes_per_pixel);
1809 }
1810
1811 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1812 {
1813 if (INTEL_INFO(dev)->gen >= 8)
1814 return 3072;
1815 else if (INTEL_INFO(dev)->gen >= 7)
1816 return 768;
1817 else
1818 return 512;
1819 }
1820
1821 /* Calculate the maximum primary/sprite plane watermark */
1822 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1823 int level,
1824 const struct intel_wm_config *config,
1825 enum intel_ddb_partitioning ddb_partitioning,
1826 bool is_sprite)
1827 {
1828 unsigned int fifo_size = ilk_display_fifo_size(dev);
1829 unsigned int max;
1830
1831 /* if sprites aren't enabled, sprites get nothing */
1832 if (is_sprite && !config->sprites_enabled)
1833 return 0;
1834
1835 /* HSW allows LP1+ watermarks even with multiple pipes */
1836 if (level == 0 || config->num_pipes_active > 1) {
1837 fifo_size /= INTEL_INFO(dev)->num_pipes;
1838
1839 /*
1840 * For some reason the non self refresh
1841 * FIFO size is only half of the self
1842 * refresh FIFO size on ILK/SNB.
1843 */
1844 if (INTEL_INFO(dev)->gen <= 6)
1845 fifo_size /= 2;
1846 }
1847
1848 if (config->sprites_enabled) {
1849 /* level 0 is always calculated with 1:1 split */
1850 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1851 if (is_sprite)
1852 fifo_size *= 5;
1853 fifo_size /= 6;
1854 } else {
1855 fifo_size /= 2;
1856 }
1857 }
1858
1859 /* clamp to max that the registers can hold */
1860 if (INTEL_INFO(dev)->gen >= 8)
1861 max = level == 0 ? 255 : 2047;
1862 else if (INTEL_INFO(dev)->gen >= 7)
1863 /* IVB/HSW primary/sprite plane watermarks */
1864 max = level == 0 ? 127 : 1023;
1865 else if (!is_sprite)
1866 /* ILK/SNB primary plane watermarks */
1867 max = level == 0 ? 127 : 511;
1868 else
1869 /* ILK/SNB sprite plane watermarks */
1870 max = level == 0 ? 63 : 255;
1871
1872 return min(fifo_size, max);
1873 }
1874
1875 /* Calculate the maximum cursor plane watermark */
1876 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1877 int level,
1878 const struct intel_wm_config *config)
1879 {
1880 /* HSW LP1+ watermarks w/ multiple pipes */
1881 if (level > 0 && config->num_pipes_active > 1)
1882 return 64;
1883
1884 /* otherwise just report max that registers can hold */
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889 }
1890
1891 /* Calculate the maximum FBC watermark */
1892 static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
1893 {
1894 /* max that registers can hold */
1895 if (INTEL_INFO(dev)->gen >= 8)
1896 return 31;
1897 else
1898 return 15;
1899 }
1900
1901 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1902 int level,
1903 const struct intel_wm_config *config,
1904 enum intel_ddb_partitioning ddb_partitioning,
1905 struct ilk_wm_maximums *max)
1906 {
1907 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1908 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1909 max->cur = ilk_cursor_wm_max(dev, level, config);
1910 max->fbc = ilk_fbc_wm_max(dev);
1911 }
1912
1913 static bool ilk_validate_wm_level(int level,
1914 const struct ilk_wm_maximums *max,
1915 struct intel_wm_level *result)
1916 {
1917 bool ret;
1918
1919 /* already determined to be invalid? */
1920 if (!result->enable)
1921 return false;
1922
1923 result->enable = result->pri_val <= max->pri &&
1924 result->spr_val <= max->spr &&
1925 result->cur_val <= max->cur;
1926
1927 ret = result->enable;
1928
1929 /*
1930 * HACK until we can pre-compute everything,
1931 * and thus fail gracefully if LP0 watermarks
1932 * are exceeded...
1933 */
1934 if (level == 0 && !result->enable) {
1935 if (result->pri_val > max->pri)
1936 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1937 level, result->pri_val, max->pri);
1938 if (result->spr_val > max->spr)
1939 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1940 level, result->spr_val, max->spr);
1941 if (result->cur_val > max->cur)
1942 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1943 level, result->cur_val, max->cur);
1944
1945 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1946 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1947 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1948 result->enable = true;
1949 }
1950
1951 return ret;
1952 }
1953
1954 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1955 int level,
1956 const struct ilk_pipe_wm_parameters *p,
1957 struct intel_wm_level *result)
1958 {
1959 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1960 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1961 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1962
1963 /* WM1+ latency values stored in 0.5us units */
1964 if (level > 0) {
1965 pri_latency *= 5;
1966 spr_latency *= 5;
1967 cur_latency *= 5;
1968 }
1969
1970 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1971 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1972 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1973 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1974 result->enable = true;
1975 }
1976
1977 static uint32_t
1978 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1979 {
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1982 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1983 u32 linetime, ips_linetime;
1984
1985 if (!intel_crtc_active(crtc))
1986 return 0;
1987
1988 /* The WM are computed with base on how long it takes to fill a single
1989 * row at the given clock rate, multiplied by 8.
1990 * */
1991 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1992 mode->crtc_clock);
1993 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1994 intel_ddi_get_cdclk_freq(dev_priv));
1995
1996 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1997 PIPE_WM_LINETIME_TIME(linetime);
1998 }
1999
2000 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2001 {
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003
2004 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2005 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2006
2007 wm[0] = (sskpd >> 56) & 0xFF;
2008 if (wm[0] == 0)
2009 wm[0] = sskpd & 0xF;
2010 wm[1] = (sskpd >> 4) & 0xFF;
2011 wm[2] = (sskpd >> 12) & 0xFF;
2012 wm[3] = (sskpd >> 20) & 0x1FF;
2013 wm[4] = (sskpd >> 32) & 0x1FF;
2014 } else if (INTEL_INFO(dev)->gen >= 6) {
2015 uint32_t sskpd = I915_READ(MCH_SSKPD);
2016
2017 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2018 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2019 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2020 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2021 } else if (INTEL_INFO(dev)->gen >= 5) {
2022 uint32_t mltr = I915_READ(MLTR_ILK);
2023
2024 /* ILK primary LP0 latency is 700 ns */
2025 wm[0] = 7;
2026 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2027 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2028 }
2029 }
2030
2031 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032 {
2033 /* ILK sprite LP0 latency is 1300 ns */
2034 if (INTEL_INFO(dev)->gen == 5)
2035 wm[0] = 13;
2036 }
2037
2038 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2039 {
2040 /* ILK cursor LP0 latency is 1300 ns */
2041 if (INTEL_INFO(dev)->gen == 5)
2042 wm[0] = 13;
2043
2044 /* WaDoubleCursorLP3Latency:ivb */
2045 if (IS_IVYBRIDGE(dev))
2046 wm[3] *= 2;
2047 }
2048
2049 static int ilk_wm_max_level(const struct drm_device *dev)
2050 {
2051 /* how many WM levels are we expecting */
2052 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2053 return 4;
2054 else if (INTEL_INFO(dev)->gen >= 6)
2055 return 3;
2056 else
2057 return 2;
2058 }
2059
2060 static void intel_print_wm_latency(struct drm_device *dev,
2061 const char *name,
2062 const uint16_t wm[5])
2063 {
2064 int level, max_level = ilk_wm_max_level(dev);
2065
2066 for (level = 0; level <= max_level; level++) {
2067 unsigned int latency = wm[level];
2068
2069 if (latency == 0) {
2070 DRM_ERROR("%s WM%d latency not provided\n",
2071 name, level);
2072 continue;
2073 }
2074
2075 /* WM1+ latency values in 0.5us units */
2076 if (level > 0)
2077 latency *= 5;
2078
2079 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2080 name, level, wm[level],
2081 latency / 10, latency % 10);
2082 }
2083 }
2084
2085 static void intel_setup_wm_latency(struct drm_device *dev)
2086 {
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088
2089 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2090
2091 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2092 sizeof(dev_priv->wm.pri_latency));
2093 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2094 sizeof(dev_priv->wm.pri_latency));
2095
2096 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2097 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2098
2099 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2100 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2101 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2102 }
2103
2104 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2105 struct ilk_pipe_wm_parameters *p,
2106 struct intel_wm_config *config)
2107 {
2108 struct drm_device *dev = crtc->dev;
2109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2110 enum pipe pipe = intel_crtc->pipe;
2111 struct drm_plane *plane;
2112
2113 p->active = intel_crtc_active(crtc);
2114 if (p->active) {
2115 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2116 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2117 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2118 p->cur.bytes_per_pixel = 4;
2119 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2120 p->cur.horiz_pixels = 64;
2121 /* TODO: for now, assume primary and cursor planes are always enabled. */
2122 p->pri.enabled = true;
2123 p->cur.enabled = true;
2124 }
2125
2126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2127 config->num_pipes_active += intel_crtc_active(crtc);
2128
2129 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2130 struct intel_plane *intel_plane = to_intel_plane(plane);
2131
2132 if (intel_plane->pipe == pipe)
2133 p->spr = intel_plane->wm;
2134
2135 config->sprites_enabled |= intel_plane->wm.enabled;
2136 config->sprites_scaled |= intel_plane->wm.scaled;
2137 }
2138 }
2139
2140 /* Compute new watermarks for the pipe */
2141 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2142 const struct ilk_pipe_wm_parameters *params,
2143 struct intel_pipe_wm *pipe_wm)
2144 {
2145 struct drm_device *dev = crtc->dev;
2146 const struct drm_i915_private *dev_priv = dev->dev_private;
2147 int level, max_level = ilk_wm_max_level(dev);
2148 /* LP0 watermark maximums depend on this pipe alone */
2149 struct intel_wm_config config = {
2150 .num_pipes_active = 1,
2151 .sprites_enabled = params->spr.enabled,
2152 .sprites_scaled = params->spr.scaled,
2153 };
2154 struct ilk_wm_maximums max;
2155
2156 /* LP0 watermarks always use 1/2 DDB partitioning */
2157 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2158
2159 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2160 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2161 max_level = 1;
2162
2163 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2164 if (params->spr.scaled)
2165 max_level = 0;
2166
2167 for (level = 0; level <= max_level; level++)
2168 ilk_compute_wm_level(dev_priv, level, params,
2169 &pipe_wm->wm[level]);
2170
2171 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2172 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2173
2174 /* At least LP0 must be valid */
2175 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2176 }
2177
2178 /*
2179 * Merge the watermarks from all active pipes for a specific level.
2180 */
2181 static void ilk_merge_wm_level(struct drm_device *dev,
2182 int level,
2183 struct intel_wm_level *ret_wm)
2184 {
2185 const struct intel_crtc *intel_crtc;
2186
2187 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2188 const struct intel_wm_level *wm =
2189 &intel_crtc->wm.active.wm[level];
2190
2191 if (!wm->enable)
2192 return;
2193
2194 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2195 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2196 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2197 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2198 }
2199
2200 ret_wm->enable = true;
2201 }
2202
2203 /*
2204 * Merge all low power watermarks for all active pipes.
2205 */
2206 static void ilk_wm_merge(struct drm_device *dev,
2207 const struct intel_wm_config *config,
2208 const struct ilk_wm_maximums *max,
2209 struct intel_pipe_wm *merged)
2210 {
2211 int level, max_level = ilk_wm_max_level(dev);
2212
2213 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2214 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2215 config->num_pipes_active > 1)
2216 return;
2217
2218 /* ILK: FBC WM must be disabled always */
2219 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2220
2221 /* merge each WM1+ level */
2222 for (level = 1; level <= max_level; level++) {
2223 struct intel_wm_level *wm = &merged->wm[level];
2224
2225 ilk_merge_wm_level(dev, level, wm);
2226
2227 if (!ilk_validate_wm_level(level, max, wm))
2228 break;
2229
2230 /*
2231 * The spec says it is preferred to disable
2232 * FBC WMs instead of disabling a WM level.
2233 */
2234 if (wm->fbc_val > max->fbc) {
2235 merged->fbc_wm_enabled = false;
2236 wm->fbc_val = 0;
2237 }
2238 }
2239
2240 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2241 /*
2242 * FIXME this is racy. FBC might get enabled later.
2243 * What we should check here is whether FBC can be
2244 * enabled sometime later.
2245 */
2246 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2247 for (level = 2; level <= max_level; level++) {
2248 struct intel_wm_level *wm = &merged->wm[level];
2249
2250 wm->enable = false;
2251 }
2252 }
2253 }
2254
2255 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2256 {
2257 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2258 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2259 }
2260
2261 /* The value we need to program into the WM_LPx latency field */
2262 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2263 {
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265
2266 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2267 return 2 * level;
2268 else
2269 return dev_priv->wm.pri_latency[level];
2270 }
2271
2272 static void ilk_compute_wm_results(struct drm_device *dev,
2273 const struct intel_pipe_wm *merged,
2274 enum intel_ddb_partitioning partitioning,
2275 struct ilk_wm_values *results)
2276 {
2277 struct intel_crtc *intel_crtc;
2278 int level, wm_lp;
2279
2280 results->enable_fbc_wm = merged->fbc_wm_enabled;
2281 results->partitioning = partitioning;
2282
2283 /* LP1+ register values */
2284 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2285 const struct intel_wm_level *r;
2286
2287 level = ilk_wm_lp_to_level(wm_lp, merged);
2288
2289 r = &merged->wm[level];
2290 if (!r->enable)
2291 break;
2292
2293 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2294 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2295 (r->pri_val << WM1_LP_SR_SHIFT) |
2296 r->cur_val;
2297
2298 if (INTEL_INFO(dev)->gen >= 8)
2299 results->wm_lp[wm_lp - 1] |=
2300 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2301 else
2302 results->wm_lp[wm_lp - 1] |=
2303 r->fbc_val << WM1_LP_FBC_SHIFT;
2304
2305 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2306 WARN_ON(wm_lp != 1);
2307 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2308 } else
2309 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2310 }
2311
2312 /* LP0 register values */
2313 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2314 enum pipe pipe = intel_crtc->pipe;
2315 const struct intel_wm_level *r =
2316 &intel_crtc->wm.active.wm[0];
2317
2318 if (WARN_ON(!r->enable))
2319 continue;
2320
2321 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2322
2323 results->wm_pipe[pipe] =
2324 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2325 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2326 r->cur_val;
2327 }
2328 }
2329
2330 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2331 * case both are at the same level. Prefer r1 in case they're the same. */
2332 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2333 struct intel_pipe_wm *r1,
2334 struct intel_pipe_wm *r2)
2335 {
2336 int level, max_level = ilk_wm_max_level(dev);
2337 int level1 = 0, level2 = 0;
2338
2339 for (level = 1; level <= max_level; level++) {
2340 if (r1->wm[level].enable)
2341 level1 = level;
2342 if (r2->wm[level].enable)
2343 level2 = level;
2344 }
2345
2346 if (level1 == level2) {
2347 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2348 return r2;
2349 else
2350 return r1;
2351 } else if (level1 > level2) {
2352 return r1;
2353 } else {
2354 return r2;
2355 }
2356 }
2357
2358 /* dirty bits used to track which watermarks need changes */
2359 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2360 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2361 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2362 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2363 #define WM_DIRTY_FBC (1 << 24)
2364 #define WM_DIRTY_DDB (1 << 25)
2365
2366 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2367 const struct ilk_wm_values *old,
2368 const struct ilk_wm_values *new)
2369 {
2370 unsigned int dirty = 0;
2371 enum pipe pipe;
2372 int wm_lp;
2373
2374 for_each_pipe(pipe) {
2375 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2376 dirty |= WM_DIRTY_LINETIME(pipe);
2377 /* Must disable LP1+ watermarks too */
2378 dirty |= WM_DIRTY_LP_ALL;
2379 }
2380
2381 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2382 dirty |= WM_DIRTY_PIPE(pipe);
2383 /* Must disable LP1+ watermarks too */
2384 dirty |= WM_DIRTY_LP_ALL;
2385 }
2386 }
2387
2388 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2389 dirty |= WM_DIRTY_FBC;
2390 /* Must disable LP1+ watermarks too */
2391 dirty |= WM_DIRTY_LP_ALL;
2392 }
2393
2394 if (old->partitioning != new->partitioning) {
2395 dirty |= WM_DIRTY_DDB;
2396 /* Must disable LP1+ watermarks too */
2397 dirty |= WM_DIRTY_LP_ALL;
2398 }
2399
2400 /* LP1+ watermarks already deemed dirty, no need to continue */
2401 if (dirty & WM_DIRTY_LP_ALL)
2402 return dirty;
2403
2404 /* Find the lowest numbered LP1+ watermark in need of an update... */
2405 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2406 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2407 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2408 break;
2409 }
2410
2411 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2412 for (; wm_lp <= 3; wm_lp++)
2413 dirty |= WM_DIRTY_LP(wm_lp);
2414
2415 return dirty;
2416 }
2417
2418 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2419 unsigned int dirty)
2420 {
2421 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2422 bool changed = false;
2423
2424 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2425 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2426 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2427 changed = true;
2428 }
2429 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2430 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2431 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2432 changed = true;
2433 }
2434 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2435 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2436 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2437 changed = true;
2438 }
2439
2440 /*
2441 * Don't touch WM1S_LP_EN here.
2442 * Doing so could cause underruns.
2443 */
2444
2445 return changed;
2446 }
2447
2448 /*
2449 * The spec says we shouldn't write when we don't need, because every write
2450 * causes WMs to be re-evaluated, expending some power.
2451 */
2452 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2453 struct ilk_wm_values *results)
2454 {
2455 struct drm_device *dev = dev_priv->dev;
2456 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2457 unsigned int dirty;
2458 uint32_t val;
2459
2460 dirty = ilk_compute_wm_dirty(dev, previous, results);
2461 if (!dirty)
2462 return;
2463
2464 _ilk_disable_lp_wm(dev_priv, dirty);
2465
2466 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2467 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2468 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2469 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2470 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2471 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2472
2473 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2474 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2475 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2476 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2477 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2478 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2479
2480 if (dirty & WM_DIRTY_DDB) {
2481 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2482 val = I915_READ(WM_MISC);
2483 if (results->partitioning == INTEL_DDB_PART_1_2)
2484 val &= ~WM_MISC_DATA_PARTITION_5_6;
2485 else
2486 val |= WM_MISC_DATA_PARTITION_5_6;
2487 I915_WRITE(WM_MISC, val);
2488 } else {
2489 val = I915_READ(DISP_ARB_CTL2);
2490 if (results->partitioning == INTEL_DDB_PART_1_2)
2491 val &= ~DISP_DATA_PARTITION_5_6;
2492 else
2493 val |= DISP_DATA_PARTITION_5_6;
2494 I915_WRITE(DISP_ARB_CTL2, val);
2495 }
2496 }
2497
2498 if (dirty & WM_DIRTY_FBC) {
2499 val = I915_READ(DISP_ARB_CTL);
2500 if (results->enable_fbc_wm)
2501 val &= ~DISP_FBC_WM_DIS;
2502 else
2503 val |= DISP_FBC_WM_DIS;
2504 I915_WRITE(DISP_ARB_CTL, val);
2505 }
2506
2507 if (dirty & WM_DIRTY_LP(1) &&
2508 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2509 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2510
2511 if (INTEL_INFO(dev)->gen >= 7) {
2512 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2513 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2514 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2515 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2516 }
2517
2518 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2519 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2520 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2521 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2522 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2523 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2524
2525 dev_priv->wm.hw = *results;
2526 }
2527
2528 static bool ilk_disable_lp_wm(struct drm_device *dev)
2529 {
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531
2532 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2533 }
2534
2535 static void ilk_update_wm(struct drm_crtc *crtc)
2536 {
2537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2538 struct drm_device *dev = crtc->dev;
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct ilk_wm_maximums max;
2541 struct ilk_pipe_wm_parameters params = {};
2542 struct ilk_wm_values results = {};
2543 enum intel_ddb_partitioning partitioning;
2544 struct intel_pipe_wm pipe_wm = {};
2545 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2546 struct intel_wm_config config = {};
2547
2548 ilk_compute_wm_parameters(crtc, &params, &config);
2549
2550 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2551
2552 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2553 return;
2554
2555 intel_crtc->wm.active = pipe_wm;
2556
2557 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2558 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2559
2560 /* 5/6 split only in single pipe config on IVB+ */
2561 if (INTEL_INFO(dev)->gen >= 7 &&
2562 config.num_pipes_active == 1 && config.sprites_enabled) {
2563 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2564 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2565
2566 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2567 } else {
2568 best_lp_wm = &lp_wm_1_2;
2569 }
2570
2571 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2572 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2573
2574 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2575
2576 ilk_write_wm_values(dev_priv, &results);
2577 }
2578
2579 static void ilk_update_sprite_wm(struct drm_plane *plane,
2580 struct drm_crtc *crtc,
2581 uint32_t sprite_width, int pixel_size,
2582 bool enabled, bool scaled)
2583 {
2584 struct drm_device *dev = plane->dev;
2585 struct intel_plane *intel_plane = to_intel_plane(plane);
2586
2587 intel_plane->wm.enabled = enabled;
2588 intel_plane->wm.scaled = scaled;
2589 intel_plane->wm.horiz_pixels = sprite_width;
2590 intel_plane->wm.bytes_per_pixel = pixel_size;
2591
2592 /*
2593 * IVB workaround: must disable low power watermarks for at least
2594 * one frame before enabling scaling. LP watermarks can be re-enabled
2595 * when scaling is disabled.
2596 *
2597 * WaCxSRDisabledForSpriteScaling:ivb
2598 */
2599 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2600 intel_wait_for_vblank(dev, intel_plane->pipe);
2601
2602 ilk_update_wm(crtc);
2603 }
2604
2605 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2606 {
2607 struct drm_device *dev = crtc->dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2611 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2612 enum pipe pipe = intel_crtc->pipe;
2613 static const unsigned int wm0_pipe_reg[] = {
2614 [PIPE_A] = WM0_PIPEA_ILK,
2615 [PIPE_B] = WM0_PIPEB_ILK,
2616 [PIPE_C] = WM0_PIPEC_IVB,
2617 };
2618
2619 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2620 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2621 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2622
2623 if (intel_crtc_active(crtc)) {
2624 u32 tmp = hw->wm_pipe[pipe];
2625
2626 /*
2627 * For active pipes LP0 watermark is marked as
2628 * enabled, and LP1+ watermaks as disabled since
2629 * we can't really reverse compute them in case
2630 * multiple pipes are active.
2631 */
2632 active->wm[0].enable = true;
2633 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2634 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2635 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2636 active->linetime = hw->wm_linetime[pipe];
2637 } else {
2638 int level, max_level = ilk_wm_max_level(dev);
2639
2640 /*
2641 * For inactive pipes, all watermark levels
2642 * should be marked as enabled but zeroed,
2643 * which is what we'd compute them to.
2644 */
2645 for (level = 0; level <= max_level; level++)
2646 active->wm[level].enable = true;
2647 }
2648 }
2649
2650 void ilk_wm_get_hw_state(struct drm_device *dev)
2651 {
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2654 struct drm_crtc *crtc;
2655
2656 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2657 ilk_pipe_wm_get_hw_state(crtc);
2658
2659 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2660 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2661 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2662
2663 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2664 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2665 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2666
2667 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2668 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2669 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2670 else if (IS_IVYBRIDGE(dev))
2671 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2672 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2673
2674 hw->enable_fbc_wm =
2675 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2676 }
2677
2678 /**
2679 * intel_update_watermarks - update FIFO watermark values based on current modes
2680 *
2681 * Calculate watermark values for the various WM regs based on current mode
2682 * and plane configuration.
2683 *
2684 * There are several cases to deal with here:
2685 * - normal (i.e. non-self-refresh)
2686 * - self-refresh (SR) mode
2687 * - lines are large relative to FIFO size (buffer can hold up to 2)
2688 * - lines are small relative to FIFO size (buffer can hold more than 2
2689 * lines), so need to account for TLB latency
2690 *
2691 * The normal calculation is:
2692 * watermark = dotclock * bytes per pixel * latency
2693 * where latency is platform & configuration dependent (we assume pessimal
2694 * values here).
2695 *
2696 * The SR calculation is:
2697 * watermark = (trunc(latency/line time)+1) * surface width *
2698 * bytes per pixel
2699 * where
2700 * line time = htotal / dotclock
2701 * surface width = hdisplay for normal plane and 64 for cursor
2702 * and latency is assumed to be high, as above.
2703 *
2704 * The final value programmed to the register should always be rounded up,
2705 * and include an extra 2 entries to account for clock crossings.
2706 *
2707 * We don't use the sprite, so we can ignore that. And on Crestline we have
2708 * to set the non-SR watermarks to 8.
2709 */
2710 void intel_update_watermarks(struct drm_crtc *crtc)
2711 {
2712 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2713
2714 if (dev_priv->display.update_wm)
2715 dev_priv->display.update_wm(crtc);
2716 }
2717
2718 void intel_update_sprite_watermarks(struct drm_plane *plane,
2719 struct drm_crtc *crtc,
2720 uint32_t sprite_width, int pixel_size,
2721 bool enabled, bool scaled)
2722 {
2723 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2724
2725 if (dev_priv->display.update_sprite_wm)
2726 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2727 pixel_size, enabled, scaled);
2728 }
2729
2730 static struct drm_i915_gem_object *
2731 intel_alloc_context_page(struct drm_device *dev)
2732 {
2733 struct drm_i915_gem_object *ctx;
2734 int ret;
2735
2736 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2737
2738 ctx = i915_gem_alloc_object(dev, 4096);
2739 if (!ctx) {
2740 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2741 return NULL;
2742 }
2743
2744 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2745 if (ret) {
2746 DRM_ERROR("failed to pin power context: %d\n", ret);
2747 goto err_unref;
2748 }
2749
2750 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2751 if (ret) {
2752 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2753 goto err_unpin;
2754 }
2755
2756 return ctx;
2757
2758 err_unpin:
2759 i915_gem_object_ggtt_unpin(ctx);
2760 err_unref:
2761 drm_gem_object_unreference(&ctx->base);
2762 return NULL;
2763 }
2764
2765 /**
2766 * Lock protecting IPS related data structures
2767 */
2768 DEFINE_SPINLOCK(mchdev_lock);
2769
2770 /* Global for IPS driver to get at the current i915 device. Protected by
2771 * mchdev_lock. */
2772 static struct drm_i915_private *i915_mch_dev;
2773
2774 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2775 {
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 u16 rgvswctl;
2778
2779 assert_spin_locked(&mchdev_lock);
2780
2781 rgvswctl = I915_READ16(MEMSWCTL);
2782 if (rgvswctl & MEMCTL_CMD_STS) {
2783 DRM_DEBUG("gpu busy, RCS change rejected\n");
2784 return false; /* still busy with another command */
2785 }
2786
2787 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2788 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2789 I915_WRITE16(MEMSWCTL, rgvswctl);
2790 POSTING_READ16(MEMSWCTL);
2791
2792 rgvswctl |= MEMCTL_CMD_STS;
2793 I915_WRITE16(MEMSWCTL, rgvswctl);
2794
2795 return true;
2796 }
2797
2798 static void ironlake_enable_drps(struct drm_device *dev)
2799 {
2800 struct drm_i915_private *dev_priv = dev->dev_private;
2801 u32 rgvmodectl = I915_READ(MEMMODECTL);
2802 u8 fmax, fmin, fstart, vstart;
2803
2804 spin_lock_irq(&mchdev_lock);
2805
2806 /* Enable temp reporting */
2807 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2808 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2809
2810 /* 100ms RC evaluation intervals */
2811 I915_WRITE(RCUPEI, 100000);
2812 I915_WRITE(RCDNEI, 100000);
2813
2814 /* Set max/min thresholds to 90ms and 80ms respectively */
2815 I915_WRITE(RCBMAXAVG, 90000);
2816 I915_WRITE(RCBMINAVG, 80000);
2817
2818 I915_WRITE(MEMIHYST, 1);
2819
2820 /* Set up min, max, and cur for interrupt handling */
2821 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2822 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2823 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2824 MEMMODE_FSTART_SHIFT;
2825
2826 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2827 PXVFREQ_PX_SHIFT;
2828
2829 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2830 dev_priv->ips.fstart = fstart;
2831
2832 dev_priv->ips.max_delay = fstart;
2833 dev_priv->ips.min_delay = fmin;
2834 dev_priv->ips.cur_delay = fstart;
2835
2836 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2837 fmax, fmin, fstart);
2838
2839 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2840
2841 /*
2842 * Interrupts will be enabled in ironlake_irq_postinstall
2843 */
2844
2845 I915_WRITE(VIDSTART, vstart);
2846 POSTING_READ(VIDSTART);
2847
2848 rgvmodectl |= MEMMODE_SWMODE_EN;
2849 I915_WRITE(MEMMODECTL, rgvmodectl);
2850
2851 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2852 DRM_ERROR("stuck trying to change perf mode\n");
2853 mdelay(1);
2854
2855 ironlake_set_drps(dev, fstart);
2856
2857 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2858 I915_READ(0x112e0);
2859 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2860 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2861 getrawmonotonic(&dev_priv->ips.last_time2);
2862
2863 spin_unlock_irq(&mchdev_lock);
2864 }
2865
2866 static void ironlake_disable_drps(struct drm_device *dev)
2867 {
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 u16 rgvswctl;
2870
2871 spin_lock_irq(&mchdev_lock);
2872
2873 rgvswctl = I915_READ16(MEMSWCTL);
2874
2875 /* Ack interrupts, disable EFC interrupt */
2876 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2877 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2878 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2879 I915_WRITE(DEIIR, DE_PCU_EVENT);
2880 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2881
2882 /* Go back to the starting frequency */
2883 ironlake_set_drps(dev, dev_priv->ips.fstart);
2884 mdelay(1);
2885 rgvswctl |= MEMCTL_CMD_STS;
2886 I915_WRITE(MEMSWCTL, rgvswctl);
2887 mdelay(1);
2888
2889 spin_unlock_irq(&mchdev_lock);
2890 }
2891
2892 /* There's a funny hw issue where the hw returns all 0 when reading from
2893 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2894 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2895 * all limits and the gpu stuck at whatever frequency it is at atm).
2896 */
2897 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2898 {
2899 u32 limits;
2900
2901 /* Only set the down limit when we've reached the lowest level to avoid
2902 * getting more interrupts, otherwise leave this clear. This prevents a
2903 * race in the hw when coming out of rc6: There's a tiny window where
2904 * the hw runs at the minimal clock before selecting the desired
2905 * frequency, if the down threshold expires in that window we will not
2906 * receive a down interrupt. */
2907 limits = dev_priv->rps.max_delay << 24;
2908 if (val <= dev_priv->rps.min_delay)
2909 limits |= dev_priv->rps.min_delay << 16;
2910
2911 return limits;
2912 }
2913
2914 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2915 {
2916 int new_power;
2917
2918 new_power = dev_priv->rps.power;
2919 switch (dev_priv->rps.power) {
2920 case LOW_POWER:
2921 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2922 new_power = BETWEEN;
2923 break;
2924
2925 case BETWEEN:
2926 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2927 new_power = LOW_POWER;
2928 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2929 new_power = HIGH_POWER;
2930 break;
2931
2932 case HIGH_POWER:
2933 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2934 new_power = BETWEEN;
2935 break;
2936 }
2937 /* Max/min bins are special */
2938 if (val == dev_priv->rps.min_delay)
2939 new_power = LOW_POWER;
2940 if (val == dev_priv->rps.max_delay)
2941 new_power = HIGH_POWER;
2942 if (new_power == dev_priv->rps.power)
2943 return;
2944
2945 /* Note the units here are not exactly 1us, but 1280ns. */
2946 switch (new_power) {
2947 case LOW_POWER:
2948 /* Upclock if more than 95% busy over 16ms */
2949 I915_WRITE(GEN6_RP_UP_EI, 12500);
2950 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2951
2952 /* Downclock if less than 85% busy over 32ms */
2953 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2954 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2955
2956 I915_WRITE(GEN6_RP_CONTROL,
2957 GEN6_RP_MEDIA_TURBO |
2958 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2959 GEN6_RP_MEDIA_IS_GFX |
2960 GEN6_RP_ENABLE |
2961 GEN6_RP_UP_BUSY_AVG |
2962 GEN6_RP_DOWN_IDLE_AVG);
2963 break;
2964
2965 case BETWEEN:
2966 /* Upclock if more than 90% busy over 13ms */
2967 I915_WRITE(GEN6_RP_UP_EI, 10250);
2968 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2969
2970 /* Downclock if less than 75% busy over 32ms */
2971 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2972 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2973
2974 I915_WRITE(GEN6_RP_CONTROL,
2975 GEN6_RP_MEDIA_TURBO |
2976 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2977 GEN6_RP_MEDIA_IS_GFX |
2978 GEN6_RP_ENABLE |
2979 GEN6_RP_UP_BUSY_AVG |
2980 GEN6_RP_DOWN_IDLE_AVG);
2981 break;
2982
2983 case HIGH_POWER:
2984 /* Upclock if more than 85% busy over 10ms */
2985 I915_WRITE(GEN6_RP_UP_EI, 8000);
2986 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2987
2988 /* Downclock if less than 60% busy over 32ms */
2989 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2990 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2991
2992 I915_WRITE(GEN6_RP_CONTROL,
2993 GEN6_RP_MEDIA_TURBO |
2994 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2995 GEN6_RP_MEDIA_IS_GFX |
2996 GEN6_RP_ENABLE |
2997 GEN6_RP_UP_BUSY_AVG |
2998 GEN6_RP_DOWN_IDLE_AVG);
2999 break;
3000 }
3001
3002 dev_priv->rps.power = new_power;
3003 dev_priv->rps.last_adj = 0;
3004 }
3005
3006 void gen6_set_rps(struct drm_device *dev, u8 val)
3007 {
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009
3010 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3011 WARN_ON(val > dev_priv->rps.max_delay);
3012 WARN_ON(val < dev_priv->rps.min_delay);
3013
3014 if (val == dev_priv->rps.cur_delay)
3015 return;
3016
3017 gen6_set_rps_thresholds(dev_priv, val);
3018
3019 if (IS_HASWELL(dev))
3020 I915_WRITE(GEN6_RPNSWREQ,
3021 HSW_FREQUENCY(val));
3022 else
3023 I915_WRITE(GEN6_RPNSWREQ,
3024 GEN6_FREQUENCY(val) |
3025 GEN6_OFFSET(0) |
3026 GEN6_AGGRESSIVE_TURBO);
3027
3028 /* Make sure we continue to get interrupts
3029 * until we hit the minimum or maximum frequencies.
3030 */
3031 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3032 gen6_rps_limits(dev_priv, val));
3033
3034 POSTING_READ(GEN6_RPNSWREQ);
3035
3036 dev_priv->rps.cur_delay = val;
3037
3038 trace_intel_gpu_freq_change(val * 50);
3039 }
3040
3041 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3042 {
3043 struct drm_device *dev = dev_priv->dev;
3044
3045 mutex_lock(&dev_priv->rps.hw_lock);
3046 if (dev_priv->rps.enabled) {
3047 if (IS_VALLEYVIEW(dev))
3048 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3049 else
3050 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3051 dev_priv->rps.last_adj = 0;
3052 }
3053 mutex_unlock(&dev_priv->rps.hw_lock);
3054 }
3055
3056 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3057 {
3058 struct drm_device *dev = dev_priv->dev;
3059
3060 mutex_lock(&dev_priv->rps.hw_lock);
3061 if (dev_priv->rps.enabled) {
3062 if (IS_VALLEYVIEW(dev))
3063 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3064 else
3065 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3066 dev_priv->rps.last_adj = 0;
3067 }
3068 mutex_unlock(&dev_priv->rps.hw_lock);
3069 }
3070
3071 void valleyview_set_rps(struct drm_device *dev, u8 val)
3072 {
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074
3075 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3076 WARN_ON(val > dev_priv->rps.max_delay);
3077 WARN_ON(val < dev_priv->rps.min_delay);
3078
3079 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3080 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3081 dev_priv->rps.cur_delay,
3082 vlv_gpu_freq(dev_priv, val), val);
3083
3084 if (val == dev_priv->rps.cur_delay)
3085 return;
3086
3087 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3088
3089 dev_priv->rps.cur_delay = val;
3090
3091 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3092 }
3093
3094 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3095 {
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097
3098 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3099 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3100 /* Complete PM interrupt masking here doesn't race with the rps work
3101 * item again unmasking PM interrupts because that is using a different
3102 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3103 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3104
3105 spin_lock_irq(&dev_priv->irq_lock);
3106 dev_priv->rps.pm_iir = 0;
3107 spin_unlock_irq(&dev_priv->irq_lock);
3108
3109 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3110 }
3111
3112 static void gen6_disable_rps(struct drm_device *dev)
3113 {
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115
3116 I915_WRITE(GEN6_RC_CONTROL, 0);
3117 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3118
3119 gen6_disable_rps_interrupts(dev);
3120 }
3121
3122 static void valleyview_disable_rps(struct drm_device *dev)
3123 {
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125
3126 I915_WRITE(GEN6_RC_CONTROL, 0);
3127
3128 gen6_disable_rps_interrupts(dev);
3129
3130 if (dev_priv->vlv_pctx) {
3131 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3132 dev_priv->vlv_pctx = NULL;
3133 }
3134 }
3135
3136 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3137 {
3138 if (IS_GEN6(dev))
3139 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3140
3141 if (IS_HASWELL(dev))
3142 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3143
3144 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3145 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3146 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3147 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3148 }
3149
3150 int intel_enable_rc6(const struct drm_device *dev)
3151 {
3152 /* No RC6 before Ironlake */
3153 if (INTEL_INFO(dev)->gen < 5)
3154 return 0;
3155
3156 /* Respect the kernel parameter if it is set */
3157 if (i915.enable_rc6 >= 0)
3158 return i915.enable_rc6;
3159
3160 /* Disable RC6 on Ironlake */
3161 if (INTEL_INFO(dev)->gen == 5)
3162 return 0;
3163
3164 if (IS_HASWELL(dev))
3165 return INTEL_RC6_ENABLE;
3166
3167 /* snb/ivb have more than one rc6 state. */
3168 if (INTEL_INFO(dev)->gen == 6)
3169 return INTEL_RC6_ENABLE;
3170
3171 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3172 }
3173
3174 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3175 {
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 u32 enabled_intrs;
3178
3179 spin_lock_irq(&dev_priv->irq_lock);
3180 WARN_ON(dev_priv->rps.pm_iir);
3181 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3182 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3183 spin_unlock_irq(&dev_priv->irq_lock);
3184
3185 /* only unmask PM interrupts we need. Mask all others. */
3186 enabled_intrs = GEN6_PM_RPS_EVENTS;
3187
3188 /* IVB and SNB hard hangs on looping batchbuffer
3189 * if GEN6_PM_UP_EI_EXPIRED is masked.
3190 */
3191 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3192 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3193
3194 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3195 }
3196
3197 static void gen8_enable_rps(struct drm_device *dev)
3198 {
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_ring_buffer *ring;
3201 uint32_t rc6_mask = 0, rp_state_cap;
3202 int unused;
3203
3204 /* 1a: Software RC state - RC0 */
3205 I915_WRITE(GEN6_RC_STATE, 0);
3206
3207 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3208 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3209 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3210
3211 /* 2a: Disable RC states. */
3212 I915_WRITE(GEN6_RC_CONTROL, 0);
3213
3214 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3215
3216 /* 2b: Program RC6 thresholds.*/
3217 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3218 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3219 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3220 for_each_ring(ring, dev_priv, unused)
3221 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3222 I915_WRITE(GEN6_RC_SLEEP, 0);
3223 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3224
3225 /* 3: Enable RC6 */
3226 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3227 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3228 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3229 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3230 GEN6_RC_CTL_EI_MODE(1) |
3231 rc6_mask);
3232
3233 /* 4 Program defaults and thresholds for RPS*/
3234 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3235 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3236 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3237 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3238
3239 /* Docs recommend 900MHz, and 300 MHz respectively */
3240 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3241 dev_priv->rps.max_delay << 24 |
3242 dev_priv->rps.min_delay << 16);
3243
3244 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3245 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3246 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3247 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3248
3249 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3250
3251 /* 5: Enable RPS */
3252 I915_WRITE(GEN6_RP_CONTROL,
3253 GEN6_RP_MEDIA_TURBO |
3254 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3255 GEN6_RP_MEDIA_IS_GFX |
3256 GEN6_RP_ENABLE |
3257 GEN6_RP_UP_BUSY_AVG |
3258 GEN6_RP_DOWN_IDLE_AVG);
3259
3260 /* 6: Ring frequency + overclocking (our driver does this later */
3261
3262 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3263
3264 gen6_enable_rps_interrupts(dev);
3265
3266 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3267 }
3268
3269 static void gen6_enable_rps(struct drm_device *dev)
3270 {
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct intel_ring_buffer *ring;
3273 u32 rp_state_cap;
3274 u32 gt_perf_status;
3275 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3276 u32 gtfifodbg;
3277 int rc6_mode;
3278 int i, ret;
3279
3280 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3281
3282 /* Here begins a magic sequence of register writes to enable
3283 * auto-downclocking.
3284 *
3285 * Perhaps there might be some value in exposing these to
3286 * userspace...
3287 */
3288 I915_WRITE(GEN6_RC_STATE, 0);
3289
3290 /* Clear the DBG now so we don't confuse earlier errors */
3291 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3292 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3293 I915_WRITE(GTFIFODBG, gtfifodbg);
3294 }
3295
3296 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3297
3298 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3299 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3300
3301 /* In units of 50MHz */
3302 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3303 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3304 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3305 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3306 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3307 dev_priv->rps.cur_delay = 0;
3308
3309 /* disable the counters and set deterministic thresholds */
3310 I915_WRITE(GEN6_RC_CONTROL, 0);
3311
3312 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3313 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3314 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3315 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3316 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3317
3318 for_each_ring(ring, dev_priv, i)
3319 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3320
3321 I915_WRITE(GEN6_RC_SLEEP, 0);
3322 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3323 if (IS_IVYBRIDGE(dev))
3324 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3325 else
3326 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3327 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3328 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3329
3330 /* Check if we are enabling RC6 */
3331 rc6_mode = intel_enable_rc6(dev_priv->dev);
3332 if (rc6_mode & INTEL_RC6_ENABLE)
3333 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3334
3335 /* We don't use those on Haswell */
3336 if (!IS_HASWELL(dev)) {
3337 if (rc6_mode & INTEL_RC6p_ENABLE)
3338 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3339
3340 if (rc6_mode & INTEL_RC6pp_ENABLE)
3341 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3342 }
3343
3344 intel_print_rc6_info(dev, rc6_mask);
3345
3346 I915_WRITE(GEN6_RC_CONTROL,
3347 rc6_mask |
3348 GEN6_RC_CTL_EI_MODE(1) |
3349 GEN6_RC_CTL_HW_ENABLE);
3350
3351 /* Power down if completely idle for over 50ms */
3352 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3353 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3354
3355 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3356 if (!ret) {
3357 pcu_mbox = 0;
3358 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3359 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3360 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3361 (dev_priv->rps.max_delay & 0xff) * 50,
3362 (pcu_mbox & 0xff) * 50);
3363 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3364 }
3365 } else {
3366 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3367 }
3368
3369 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3370 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3371
3372 gen6_enable_rps_interrupts(dev);
3373
3374 rc6vids = 0;
3375 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3376 if (IS_GEN6(dev) && ret) {
3377 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3378 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3379 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3380 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3381 rc6vids &= 0xffff00;
3382 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3383 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3384 if (ret)
3385 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3386 }
3387
3388 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3389 }
3390
3391 void gen6_update_ring_freq(struct drm_device *dev)
3392 {
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394 int min_freq = 15;
3395 unsigned int gpu_freq;
3396 unsigned int max_ia_freq, min_ring_freq;
3397 int scaling_factor = 180;
3398 struct cpufreq_policy *policy;
3399
3400 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3401
3402 policy = cpufreq_cpu_get(0);
3403 if (policy) {
3404 max_ia_freq = policy->cpuinfo.max_freq;
3405 cpufreq_cpu_put(policy);
3406 } else {
3407 /*
3408 * Default to measured freq if none found, PCU will ensure we
3409 * don't go over
3410 */
3411 max_ia_freq = tsc_khz;
3412 }
3413
3414 /* Convert from kHz to MHz */
3415 max_ia_freq /= 1000;
3416
3417 min_ring_freq = I915_READ(DCLK) & 0xf;
3418 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3419 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3420
3421 /*
3422 * For each potential GPU frequency, load a ring frequency we'd like
3423 * to use for memory access. We do this by specifying the IA frequency
3424 * the PCU should use as a reference to determine the ring frequency.
3425 */
3426 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3427 gpu_freq--) {
3428 int diff = dev_priv->rps.max_delay - gpu_freq;
3429 unsigned int ia_freq = 0, ring_freq = 0;
3430
3431 if (INTEL_INFO(dev)->gen >= 8) {
3432 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3433 ring_freq = max(min_ring_freq, gpu_freq);
3434 } else if (IS_HASWELL(dev)) {
3435 ring_freq = mult_frac(gpu_freq, 5, 4);
3436 ring_freq = max(min_ring_freq, ring_freq);
3437 /* leave ia_freq as the default, chosen by cpufreq */
3438 } else {
3439 /* On older processors, there is no separate ring
3440 * clock domain, so in order to boost the bandwidth
3441 * of the ring, we need to upclock the CPU (ia_freq).
3442 *
3443 * For GPU frequencies less than 750MHz,
3444 * just use the lowest ring freq.
3445 */
3446 if (gpu_freq < min_freq)
3447 ia_freq = 800;
3448 else
3449 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3450 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3451 }
3452
3453 sandybridge_pcode_write(dev_priv,
3454 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3455 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3456 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3457 gpu_freq);
3458 }
3459 }
3460
3461 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3462 {
3463 u32 val, rp0;
3464
3465 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3466
3467 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3468 /* Clamp to max */
3469 rp0 = min_t(u32, rp0, 0xea);
3470
3471 return rp0;
3472 }
3473
3474 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3475 {
3476 u32 val, rpe;
3477
3478 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3479 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3480 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3481 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3482
3483 return rpe;
3484 }
3485
3486 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3487 {
3488 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3489 }
3490
3491 static void valleyview_setup_pctx(struct drm_device *dev)
3492 {
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct drm_i915_gem_object *pctx;
3495 unsigned long pctx_paddr;
3496 u32 pcbr;
3497 int pctx_size = 24*1024;
3498
3499 pcbr = I915_READ(VLV_PCBR);
3500 if (pcbr) {
3501 /* BIOS set it up already, grab the pre-alloc'd space */
3502 int pcbr_offset;
3503
3504 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3505 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3506 pcbr_offset,
3507 I915_GTT_OFFSET_NONE,
3508 pctx_size);
3509 goto out;
3510 }
3511
3512 /*
3513 * From the Gunit register HAS:
3514 * The Gfx driver is expected to program this register and ensure
3515 * proper allocation within Gfx stolen memory. For example, this
3516 * register should be programmed such than the PCBR range does not
3517 * overlap with other ranges, such as the frame buffer, protected
3518 * memory, or any other relevant ranges.
3519 */
3520 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3521 if (!pctx) {
3522 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3523 return;
3524 }
3525
3526 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3527 I915_WRITE(VLV_PCBR, pctx_paddr);
3528
3529 out:
3530 dev_priv->vlv_pctx = pctx;
3531 }
3532
3533 static void valleyview_enable_rps(struct drm_device *dev)
3534 {
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 struct intel_ring_buffer *ring;
3537 u32 gtfifodbg, val, rc6_mode = 0;
3538 int i;
3539
3540 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3541
3542 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3543 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3544 gtfifodbg);
3545 I915_WRITE(GTFIFODBG, gtfifodbg);
3546 }
3547
3548 valleyview_setup_pctx(dev);
3549
3550 /* If VLV, Forcewake all wells, else re-direct to regular path */
3551 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3552
3553 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3554 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3555 I915_WRITE(GEN6_RP_UP_EI, 66000);
3556 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3557
3558 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3559
3560 I915_WRITE(GEN6_RP_CONTROL,
3561 GEN6_RP_MEDIA_TURBO |
3562 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3563 GEN6_RP_MEDIA_IS_GFX |
3564 GEN6_RP_ENABLE |
3565 GEN6_RP_UP_BUSY_AVG |
3566 GEN6_RP_DOWN_IDLE_CONT);
3567
3568 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3569 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3570 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3571
3572 for_each_ring(ring, dev_priv, i)
3573 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3574
3575 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3576
3577 /* allows RC6 residency counter to work */
3578 I915_WRITE(VLV_COUNTER_CONTROL,
3579 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3580 VLV_MEDIA_RC6_COUNT_EN |
3581 VLV_RENDER_RC6_COUNT_EN));
3582 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3583 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3584
3585 intel_print_rc6_info(dev, rc6_mode);
3586
3587 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3588
3589 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3590
3591 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3592 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3593
3594 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3595 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3596 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3597 dev_priv->rps.cur_delay);
3598
3599 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3600 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3601 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3602 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
3603 dev_priv->rps.max_delay);
3604
3605 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3606 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3607 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3608 dev_priv->rps.rpe_delay);
3609
3610 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3611 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3612 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
3613 dev_priv->rps.min_delay);
3614
3615 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3616 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3617 dev_priv->rps.rpe_delay);
3618
3619 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3620
3621 gen6_enable_rps_interrupts(dev);
3622
3623 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3624 }
3625
3626 void ironlake_teardown_rc6(struct drm_device *dev)
3627 {
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629
3630 if (dev_priv->ips.renderctx) {
3631 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3632 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3633 dev_priv->ips.renderctx = NULL;
3634 }
3635
3636 if (dev_priv->ips.pwrctx) {
3637 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3638 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3639 dev_priv->ips.pwrctx = NULL;
3640 }
3641 }
3642
3643 static void ironlake_disable_rc6(struct drm_device *dev)
3644 {
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646
3647 if (I915_READ(PWRCTXA)) {
3648 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3649 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3650 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3651 50);
3652
3653 I915_WRITE(PWRCTXA, 0);
3654 POSTING_READ(PWRCTXA);
3655
3656 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3657 POSTING_READ(RSTDBYCTL);
3658 }
3659 }
3660
3661 static int ironlake_setup_rc6(struct drm_device *dev)
3662 {
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664
3665 if (dev_priv->ips.renderctx == NULL)
3666 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3667 if (!dev_priv->ips.renderctx)
3668 return -ENOMEM;
3669
3670 if (dev_priv->ips.pwrctx == NULL)
3671 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3672 if (!dev_priv->ips.pwrctx) {
3673 ironlake_teardown_rc6(dev);
3674 return -ENOMEM;
3675 }
3676
3677 return 0;
3678 }
3679
3680 static void ironlake_enable_rc6(struct drm_device *dev)
3681 {
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3684 bool was_interruptible;
3685 int ret;
3686
3687 /* rc6 disabled by default due to repeated reports of hanging during
3688 * boot and resume.
3689 */
3690 if (!intel_enable_rc6(dev))
3691 return;
3692
3693 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3694
3695 ret = ironlake_setup_rc6(dev);
3696 if (ret)
3697 return;
3698
3699 was_interruptible = dev_priv->mm.interruptible;
3700 dev_priv->mm.interruptible = false;
3701
3702 /*
3703 * GPU can automatically power down the render unit if given a page
3704 * to save state.
3705 */
3706 ret = intel_ring_begin(ring, 6);
3707 if (ret) {
3708 ironlake_teardown_rc6(dev);
3709 dev_priv->mm.interruptible = was_interruptible;
3710 return;
3711 }
3712
3713 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3714 intel_ring_emit(ring, MI_SET_CONTEXT);
3715 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3716 MI_MM_SPACE_GTT |
3717 MI_SAVE_EXT_STATE_EN |
3718 MI_RESTORE_EXT_STATE_EN |
3719 MI_RESTORE_INHIBIT);
3720 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3721 intel_ring_emit(ring, MI_NOOP);
3722 intel_ring_emit(ring, MI_FLUSH);
3723 intel_ring_advance(ring);
3724
3725 /*
3726 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3727 * does an implicit flush, combined with MI_FLUSH above, it should be
3728 * safe to assume that renderctx is valid
3729 */
3730 ret = intel_ring_idle(ring);
3731 dev_priv->mm.interruptible = was_interruptible;
3732 if (ret) {
3733 DRM_ERROR("failed to enable ironlake power savings\n");
3734 ironlake_teardown_rc6(dev);
3735 return;
3736 }
3737
3738 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3739 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3740
3741 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3742 }
3743
3744 static unsigned long intel_pxfreq(u32 vidfreq)
3745 {
3746 unsigned long freq;
3747 int div = (vidfreq & 0x3f0000) >> 16;
3748 int post = (vidfreq & 0x3000) >> 12;
3749 int pre = (vidfreq & 0x7);
3750
3751 if (!pre)
3752 return 0;
3753
3754 freq = ((div * 133333) / ((1<<post) * pre));
3755
3756 return freq;
3757 }
3758
3759 static const struct cparams {
3760 u16 i;
3761 u16 t;
3762 u16 m;
3763 u16 c;
3764 } cparams[] = {
3765 { 1, 1333, 301, 28664 },
3766 { 1, 1066, 294, 24460 },
3767 { 1, 800, 294, 25192 },
3768 { 0, 1333, 276, 27605 },
3769 { 0, 1066, 276, 27605 },
3770 { 0, 800, 231, 23784 },
3771 };
3772
3773 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3774 {
3775 u64 total_count, diff, ret;
3776 u32 count1, count2, count3, m = 0, c = 0;
3777 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3778 int i;
3779
3780 assert_spin_locked(&mchdev_lock);
3781
3782 diff1 = now - dev_priv->ips.last_time1;
3783
3784 /* Prevent division-by-zero if we are asking too fast.
3785 * Also, we don't get interesting results if we are polling
3786 * faster than once in 10ms, so just return the saved value
3787 * in such cases.
3788 */
3789 if (diff1 <= 10)
3790 return dev_priv->ips.chipset_power;
3791
3792 count1 = I915_READ(DMIEC);
3793 count2 = I915_READ(DDREC);
3794 count3 = I915_READ(CSIEC);
3795
3796 total_count = count1 + count2 + count3;
3797
3798 /* FIXME: handle per-counter overflow */
3799 if (total_count < dev_priv->ips.last_count1) {
3800 diff = ~0UL - dev_priv->ips.last_count1;
3801 diff += total_count;
3802 } else {
3803 diff = total_count - dev_priv->ips.last_count1;
3804 }
3805
3806 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3807 if (cparams[i].i == dev_priv->ips.c_m &&
3808 cparams[i].t == dev_priv->ips.r_t) {
3809 m = cparams[i].m;
3810 c = cparams[i].c;
3811 break;
3812 }
3813 }
3814
3815 diff = div_u64(diff, diff1);
3816 ret = ((m * diff) + c);
3817 ret = div_u64(ret, 10);
3818
3819 dev_priv->ips.last_count1 = total_count;
3820 dev_priv->ips.last_time1 = now;
3821
3822 dev_priv->ips.chipset_power = ret;
3823
3824 return ret;
3825 }
3826
3827 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3828 {
3829 unsigned long val;
3830
3831 if (dev_priv->info->gen != 5)
3832 return 0;
3833
3834 spin_lock_irq(&mchdev_lock);
3835
3836 val = __i915_chipset_val(dev_priv);
3837
3838 spin_unlock_irq(&mchdev_lock);
3839
3840 return val;
3841 }
3842
3843 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3844 {
3845 unsigned long m, x, b;
3846 u32 tsfs;
3847
3848 tsfs = I915_READ(TSFS);
3849
3850 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3851 x = I915_READ8(TR1);
3852
3853 b = tsfs & TSFS_INTR_MASK;
3854
3855 return ((m * x) / 127) - b;
3856 }
3857
3858 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3859 {
3860 static const struct v_table {
3861 u16 vd; /* in .1 mil */
3862 u16 vm; /* in .1 mil */
3863 } v_table[] = {
3864 { 0, 0, },
3865 { 375, 0, },
3866 { 500, 0, },
3867 { 625, 0, },
3868 { 750, 0, },
3869 { 875, 0, },
3870 { 1000, 0, },
3871 { 1125, 0, },
3872 { 4125, 3000, },
3873 { 4125, 3000, },
3874 { 4125, 3000, },
3875 { 4125, 3000, },
3876 { 4125, 3000, },
3877 { 4125, 3000, },
3878 { 4125, 3000, },
3879 { 4125, 3000, },
3880 { 4125, 3000, },
3881 { 4125, 3000, },
3882 { 4125, 3000, },
3883 { 4125, 3000, },
3884 { 4125, 3000, },
3885 { 4125, 3000, },
3886 { 4125, 3000, },
3887 { 4125, 3000, },
3888 { 4125, 3000, },
3889 { 4125, 3000, },
3890 { 4125, 3000, },
3891 { 4125, 3000, },
3892 { 4125, 3000, },
3893 { 4125, 3000, },
3894 { 4125, 3000, },
3895 { 4125, 3000, },
3896 { 4250, 3125, },
3897 { 4375, 3250, },
3898 { 4500, 3375, },
3899 { 4625, 3500, },
3900 { 4750, 3625, },
3901 { 4875, 3750, },
3902 { 5000, 3875, },
3903 { 5125, 4000, },
3904 { 5250, 4125, },
3905 { 5375, 4250, },
3906 { 5500, 4375, },
3907 { 5625, 4500, },
3908 { 5750, 4625, },
3909 { 5875, 4750, },
3910 { 6000, 4875, },
3911 { 6125, 5000, },
3912 { 6250, 5125, },
3913 { 6375, 5250, },
3914 { 6500, 5375, },
3915 { 6625, 5500, },
3916 { 6750, 5625, },
3917 { 6875, 5750, },
3918 { 7000, 5875, },
3919 { 7125, 6000, },
3920 { 7250, 6125, },
3921 { 7375, 6250, },
3922 { 7500, 6375, },
3923 { 7625, 6500, },
3924 { 7750, 6625, },
3925 { 7875, 6750, },
3926 { 8000, 6875, },
3927 { 8125, 7000, },
3928 { 8250, 7125, },
3929 { 8375, 7250, },
3930 { 8500, 7375, },
3931 { 8625, 7500, },
3932 { 8750, 7625, },
3933 { 8875, 7750, },
3934 { 9000, 7875, },
3935 { 9125, 8000, },
3936 { 9250, 8125, },
3937 { 9375, 8250, },
3938 { 9500, 8375, },
3939 { 9625, 8500, },
3940 { 9750, 8625, },
3941 { 9875, 8750, },
3942 { 10000, 8875, },
3943 { 10125, 9000, },
3944 { 10250, 9125, },
3945 { 10375, 9250, },
3946 { 10500, 9375, },
3947 { 10625, 9500, },
3948 { 10750, 9625, },
3949 { 10875, 9750, },
3950 { 11000, 9875, },
3951 { 11125, 10000, },
3952 { 11250, 10125, },
3953 { 11375, 10250, },
3954 { 11500, 10375, },
3955 { 11625, 10500, },
3956 { 11750, 10625, },
3957 { 11875, 10750, },
3958 { 12000, 10875, },
3959 { 12125, 11000, },
3960 { 12250, 11125, },
3961 { 12375, 11250, },
3962 { 12500, 11375, },
3963 { 12625, 11500, },
3964 { 12750, 11625, },
3965 { 12875, 11750, },
3966 { 13000, 11875, },
3967 { 13125, 12000, },
3968 { 13250, 12125, },
3969 { 13375, 12250, },
3970 { 13500, 12375, },
3971 { 13625, 12500, },
3972 { 13750, 12625, },
3973 { 13875, 12750, },
3974 { 14000, 12875, },
3975 { 14125, 13000, },
3976 { 14250, 13125, },
3977 { 14375, 13250, },
3978 { 14500, 13375, },
3979 { 14625, 13500, },
3980 { 14750, 13625, },
3981 { 14875, 13750, },
3982 { 15000, 13875, },
3983 { 15125, 14000, },
3984 { 15250, 14125, },
3985 { 15375, 14250, },
3986 { 15500, 14375, },
3987 { 15625, 14500, },
3988 { 15750, 14625, },
3989 { 15875, 14750, },
3990 { 16000, 14875, },
3991 { 16125, 15000, },
3992 };
3993 if (dev_priv->info->is_mobile)
3994 return v_table[pxvid].vm;
3995 else
3996 return v_table[pxvid].vd;
3997 }
3998
3999 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4000 {
4001 struct timespec now, diff1;
4002 u64 diff;
4003 unsigned long diffms;
4004 u32 count;
4005
4006 assert_spin_locked(&mchdev_lock);
4007
4008 getrawmonotonic(&now);
4009 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4010
4011 /* Don't divide by 0 */
4012 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4013 if (!diffms)
4014 return;
4015
4016 count = I915_READ(GFXEC);
4017
4018 if (count < dev_priv->ips.last_count2) {
4019 diff = ~0UL - dev_priv->ips.last_count2;
4020 diff += count;
4021 } else {
4022 diff = count - dev_priv->ips.last_count2;
4023 }
4024
4025 dev_priv->ips.last_count2 = count;
4026 dev_priv->ips.last_time2 = now;
4027
4028 /* More magic constants... */
4029 diff = diff * 1181;
4030 diff = div_u64(diff, diffms * 10);
4031 dev_priv->ips.gfx_power = diff;
4032 }
4033
4034 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4035 {
4036 if (dev_priv->info->gen != 5)
4037 return;
4038
4039 spin_lock_irq(&mchdev_lock);
4040
4041 __i915_update_gfx_val(dev_priv);
4042
4043 spin_unlock_irq(&mchdev_lock);
4044 }
4045
4046 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4047 {
4048 unsigned long t, corr, state1, corr2, state2;
4049 u32 pxvid, ext_v;
4050
4051 assert_spin_locked(&mchdev_lock);
4052
4053 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4054 pxvid = (pxvid >> 24) & 0x7f;
4055 ext_v = pvid_to_extvid(dev_priv, pxvid);
4056
4057 state1 = ext_v;
4058
4059 t = i915_mch_val(dev_priv);
4060
4061 /* Revel in the empirically derived constants */
4062
4063 /* Correction factor in 1/100000 units */
4064 if (t > 80)
4065 corr = ((t * 2349) + 135940);
4066 else if (t >= 50)
4067 corr = ((t * 964) + 29317);
4068 else /* < 50 */
4069 corr = ((t * 301) + 1004);
4070
4071 corr = corr * ((150142 * state1) / 10000 - 78642);
4072 corr /= 100000;
4073 corr2 = (corr * dev_priv->ips.corr);
4074
4075 state2 = (corr2 * state1) / 10000;
4076 state2 /= 100; /* convert to mW */
4077
4078 __i915_update_gfx_val(dev_priv);
4079
4080 return dev_priv->ips.gfx_power + state2;
4081 }
4082
4083 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4084 {
4085 unsigned long val;
4086
4087 if (dev_priv->info->gen != 5)
4088 return 0;
4089
4090 spin_lock_irq(&mchdev_lock);
4091
4092 val = __i915_gfx_val(dev_priv);
4093
4094 spin_unlock_irq(&mchdev_lock);
4095
4096 return val;
4097 }
4098
4099 /**
4100 * i915_read_mch_val - return value for IPS use
4101 *
4102 * Calculate and return a value for the IPS driver to use when deciding whether
4103 * we have thermal and power headroom to increase CPU or GPU power budget.
4104 */
4105 unsigned long i915_read_mch_val(void)
4106 {
4107 struct drm_i915_private *dev_priv;
4108 unsigned long chipset_val, graphics_val, ret = 0;
4109
4110 spin_lock_irq(&mchdev_lock);
4111 if (!i915_mch_dev)
4112 goto out_unlock;
4113 dev_priv = i915_mch_dev;
4114
4115 chipset_val = __i915_chipset_val(dev_priv);
4116 graphics_val = __i915_gfx_val(dev_priv);
4117
4118 ret = chipset_val + graphics_val;
4119
4120 out_unlock:
4121 spin_unlock_irq(&mchdev_lock);
4122
4123 return ret;
4124 }
4125 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4126
4127 /**
4128 * i915_gpu_raise - raise GPU frequency limit
4129 *
4130 * Raise the limit; IPS indicates we have thermal headroom.
4131 */
4132 bool i915_gpu_raise(void)
4133 {
4134 struct drm_i915_private *dev_priv;
4135 bool ret = true;
4136
4137 spin_lock_irq(&mchdev_lock);
4138 if (!i915_mch_dev) {
4139 ret = false;
4140 goto out_unlock;
4141 }
4142 dev_priv = i915_mch_dev;
4143
4144 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4145 dev_priv->ips.max_delay--;
4146
4147 out_unlock:
4148 spin_unlock_irq(&mchdev_lock);
4149
4150 return ret;
4151 }
4152 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4153
4154 /**
4155 * i915_gpu_lower - lower GPU frequency limit
4156 *
4157 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4158 * frequency maximum.
4159 */
4160 bool i915_gpu_lower(void)
4161 {
4162 struct drm_i915_private *dev_priv;
4163 bool ret = true;
4164
4165 spin_lock_irq(&mchdev_lock);
4166 if (!i915_mch_dev) {
4167 ret = false;
4168 goto out_unlock;
4169 }
4170 dev_priv = i915_mch_dev;
4171
4172 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4173 dev_priv->ips.max_delay++;
4174
4175 out_unlock:
4176 spin_unlock_irq(&mchdev_lock);
4177
4178 return ret;
4179 }
4180 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4181
4182 /**
4183 * i915_gpu_busy - indicate GPU business to IPS
4184 *
4185 * Tell the IPS driver whether or not the GPU is busy.
4186 */
4187 bool i915_gpu_busy(void)
4188 {
4189 struct drm_i915_private *dev_priv;
4190 struct intel_ring_buffer *ring;
4191 bool ret = false;
4192 int i;
4193
4194 spin_lock_irq(&mchdev_lock);
4195 if (!i915_mch_dev)
4196 goto out_unlock;
4197 dev_priv = i915_mch_dev;
4198
4199 for_each_ring(ring, dev_priv, i)
4200 ret |= !list_empty(&ring->request_list);
4201
4202 out_unlock:
4203 spin_unlock_irq(&mchdev_lock);
4204
4205 return ret;
4206 }
4207 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4208
4209 /**
4210 * i915_gpu_turbo_disable - disable graphics turbo
4211 *
4212 * Disable graphics turbo by resetting the max frequency and setting the
4213 * current frequency to the default.
4214 */
4215 bool i915_gpu_turbo_disable(void)
4216 {
4217 struct drm_i915_private *dev_priv;
4218 bool ret = true;
4219
4220 spin_lock_irq(&mchdev_lock);
4221 if (!i915_mch_dev) {
4222 ret = false;
4223 goto out_unlock;
4224 }
4225 dev_priv = i915_mch_dev;
4226
4227 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4228
4229 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4230 ret = false;
4231
4232 out_unlock:
4233 spin_unlock_irq(&mchdev_lock);
4234
4235 return ret;
4236 }
4237 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4238
4239 /**
4240 * Tells the intel_ips driver that the i915 driver is now loaded, if
4241 * IPS got loaded first.
4242 *
4243 * This awkward dance is so that neither module has to depend on the
4244 * other in order for IPS to do the appropriate communication of
4245 * GPU turbo limits to i915.
4246 */
4247 static void
4248 ips_ping_for_i915_load(void)
4249 {
4250 void (*link)(void);
4251
4252 link = symbol_get(ips_link_to_i915_driver);
4253 if (link) {
4254 link();
4255 symbol_put(ips_link_to_i915_driver);
4256 }
4257 }
4258
4259 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4260 {
4261 /* We only register the i915 ips part with intel-ips once everything is
4262 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4263 spin_lock_irq(&mchdev_lock);
4264 i915_mch_dev = dev_priv;
4265 spin_unlock_irq(&mchdev_lock);
4266
4267 ips_ping_for_i915_load();
4268 }
4269
4270 void intel_gpu_ips_teardown(void)
4271 {
4272 spin_lock_irq(&mchdev_lock);
4273 i915_mch_dev = NULL;
4274 spin_unlock_irq(&mchdev_lock);
4275 }
4276 static void intel_init_emon(struct drm_device *dev)
4277 {
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279 u32 lcfuse;
4280 u8 pxw[16];
4281 int i;
4282
4283 /* Disable to program */
4284 I915_WRITE(ECR, 0);
4285 POSTING_READ(ECR);
4286
4287 /* Program energy weights for various events */
4288 I915_WRITE(SDEW, 0x15040d00);
4289 I915_WRITE(CSIEW0, 0x007f0000);
4290 I915_WRITE(CSIEW1, 0x1e220004);
4291 I915_WRITE(CSIEW2, 0x04000004);
4292
4293 for (i = 0; i < 5; i++)
4294 I915_WRITE(PEW + (i * 4), 0);
4295 for (i = 0; i < 3; i++)
4296 I915_WRITE(DEW + (i * 4), 0);
4297
4298 /* Program P-state weights to account for frequency power adjustment */
4299 for (i = 0; i < 16; i++) {
4300 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4301 unsigned long freq = intel_pxfreq(pxvidfreq);
4302 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4303 PXVFREQ_PX_SHIFT;
4304 unsigned long val;
4305
4306 val = vid * vid;
4307 val *= (freq / 1000);
4308 val *= 255;
4309 val /= (127*127*900);
4310 if (val > 0xff)
4311 DRM_ERROR("bad pxval: %ld\n", val);
4312 pxw[i] = val;
4313 }
4314 /* Render standby states get 0 weight */
4315 pxw[14] = 0;
4316 pxw[15] = 0;
4317
4318 for (i = 0; i < 4; i++) {
4319 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4320 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4321 I915_WRITE(PXW + (i * 4), val);
4322 }
4323
4324 /* Adjust magic regs to magic values (more experimental results) */
4325 I915_WRITE(OGW0, 0);
4326 I915_WRITE(OGW1, 0);
4327 I915_WRITE(EG0, 0x00007f00);
4328 I915_WRITE(EG1, 0x0000000e);
4329 I915_WRITE(EG2, 0x000e0000);
4330 I915_WRITE(EG3, 0x68000300);
4331 I915_WRITE(EG4, 0x42000000);
4332 I915_WRITE(EG5, 0x00140031);
4333 I915_WRITE(EG6, 0);
4334 I915_WRITE(EG7, 0);
4335
4336 for (i = 0; i < 8; i++)
4337 I915_WRITE(PXWL + (i * 4), 0);
4338
4339 /* Enable PMON + select events */
4340 I915_WRITE(ECR, 0x80000019);
4341
4342 lcfuse = I915_READ(LCFUSE02);
4343
4344 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4345 }
4346
4347 void intel_disable_gt_powersave(struct drm_device *dev)
4348 {
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350
4351 /* Interrupts should be disabled already to avoid re-arming. */
4352 WARN_ON(dev->irq_enabled);
4353
4354 if (IS_IRONLAKE_M(dev)) {
4355 ironlake_disable_drps(dev);
4356 ironlake_disable_rc6(dev);
4357 } else if (INTEL_INFO(dev)->gen >= 6) {
4358 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4359 cancel_work_sync(&dev_priv->rps.work);
4360 mutex_lock(&dev_priv->rps.hw_lock);
4361 if (IS_VALLEYVIEW(dev))
4362 valleyview_disable_rps(dev);
4363 else
4364 gen6_disable_rps(dev);
4365 dev_priv->rps.enabled = false;
4366 mutex_unlock(&dev_priv->rps.hw_lock);
4367 }
4368 }
4369
4370 static void intel_gen6_powersave_work(struct work_struct *work)
4371 {
4372 struct drm_i915_private *dev_priv =
4373 container_of(work, struct drm_i915_private,
4374 rps.delayed_resume_work.work);
4375 struct drm_device *dev = dev_priv->dev;
4376
4377 mutex_lock(&dev_priv->rps.hw_lock);
4378
4379 if (IS_VALLEYVIEW(dev)) {
4380 valleyview_enable_rps(dev);
4381 } else if (IS_BROADWELL(dev)) {
4382 gen8_enable_rps(dev);
4383 gen6_update_ring_freq(dev);
4384 } else {
4385 gen6_enable_rps(dev);
4386 gen6_update_ring_freq(dev);
4387 }
4388 dev_priv->rps.enabled = true;
4389 mutex_unlock(&dev_priv->rps.hw_lock);
4390 }
4391
4392 void intel_enable_gt_powersave(struct drm_device *dev)
4393 {
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395
4396 if (IS_IRONLAKE_M(dev)) {
4397 ironlake_enable_drps(dev);
4398 ironlake_enable_rc6(dev);
4399 intel_init_emon(dev);
4400 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4401 /*
4402 * PCU communication is slow and this doesn't need to be
4403 * done at any specific time, so do this out of our fast path
4404 * to make resume and init faster.
4405 */
4406 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4407 round_jiffies_up_relative(HZ));
4408 }
4409 }
4410
4411 static void ibx_init_clock_gating(struct drm_device *dev)
4412 {
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414
4415 /*
4416 * On Ibex Peak and Cougar Point, we need to disable clock
4417 * gating for the panel power sequencer or it will fail to
4418 * start up when no ports are active.
4419 */
4420 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4421 }
4422
4423 static void g4x_disable_trickle_feed(struct drm_device *dev)
4424 {
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426 int pipe;
4427
4428 for_each_pipe(pipe) {
4429 I915_WRITE(DSPCNTR(pipe),
4430 I915_READ(DSPCNTR(pipe)) |
4431 DISPPLANE_TRICKLE_FEED_DISABLE);
4432 intel_flush_primary_plane(dev_priv, pipe);
4433 }
4434 }
4435
4436 static void ilk_init_lp_watermarks(struct drm_device *dev)
4437 {
4438 struct drm_i915_private *dev_priv = dev->dev_private;
4439
4440 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4441 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4442 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4443
4444 /*
4445 * Don't touch WM1S_LP_EN here.
4446 * Doing so could cause underruns.
4447 */
4448 }
4449
4450 static void ironlake_init_clock_gating(struct drm_device *dev)
4451 {
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4454
4455 /*
4456 * Required for FBC
4457 * WaFbcDisableDpfcClockGating:ilk
4458 */
4459 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4460 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4461 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4462
4463 I915_WRITE(PCH_3DCGDIS0,
4464 MARIUNIT_CLOCK_GATE_DISABLE |
4465 SVSMUNIT_CLOCK_GATE_DISABLE);
4466 I915_WRITE(PCH_3DCGDIS1,
4467 VFMUNIT_CLOCK_GATE_DISABLE);
4468
4469 /*
4470 * According to the spec the following bits should be set in
4471 * order to enable memory self-refresh
4472 * The bit 22/21 of 0x42004
4473 * The bit 5 of 0x42020
4474 * The bit 15 of 0x45000
4475 */
4476 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4477 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4478 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4479 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4480 I915_WRITE(DISP_ARB_CTL,
4481 (I915_READ(DISP_ARB_CTL) |
4482 DISP_FBC_WM_DIS));
4483
4484 ilk_init_lp_watermarks(dev);
4485
4486 /*
4487 * Based on the document from hardware guys the following bits
4488 * should be set unconditionally in order to enable FBC.
4489 * The bit 22 of 0x42000
4490 * The bit 22 of 0x42004
4491 * The bit 7,8,9 of 0x42020.
4492 */
4493 if (IS_IRONLAKE_M(dev)) {
4494 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4495 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4496 I915_READ(ILK_DISPLAY_CHICKEN1) |
4497 ILK_FBCQ_DIS);
4498 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4499 I915_READ(ILK_DISPLAY_CHICKEN2) |
4500 ILK_DPARB_GATE);
4501 }
4502
4503 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4504
4505 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4506 I915_READ(ILK_DISPLAY_CHICKEN2) |
4507 ILK_ELPIN_409_SELECT);
4508 I915_WRITE(_3D_CHICKEN2,
4509 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4510 _3D_CHICKEN2_WM_READ_PIPELINED);
4511
4512 /* WaDisableRenderCachePipelinedFlush:ilk */
4513 I915_WRITE(CACHE_MODE_0,
4514 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4515
4516 g4x_disable_trickle_feed(dev);
4517
4518 ibx_init_clock_gating(dev);
4519 }
4520
4521 static void cpt_init_clock_gating(struct drm_device *dev)
4522 {
4523 struct drm_i915_private *dev_priv = dev->dev_private;
4524 int pipe;
4525 uint32_t val;
4526
4527 /*
4528 * On Ibex Peak and Cougar Point, we need to disable clock
4529 * gating for the panel power sequencer or it will fail to
4530 * start up when no ports are active.
4531 */
4532 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4533 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4534 PCH_CPUNIT_CLOCK_GATE_DISABLE);
4535 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4536 DPLS_EDP_PPS_FIX_DIS);
4537 /* The below fixes the weird display corruption, a few pixels shifted
4538 * downward, on (only) LVDS of some HP laptops with IVY.
4539 */
4540 for_each_pipe(pipe) {
4541 val = I915_READ(TRANS_CHICKEN2(pipe));
4542 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4543 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4544 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4545 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4546 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4547 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4548 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4549 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4550 }
4551 /* WADP0ClockGatingDisable */
4552 for_each_pipe(pipe) {
4553 I915_WRITE(TRANS_CHICKEN1(pipe),
4554 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4555 }
4556 }
4557
4558 static void gen6_check_mch_setup(struct drm_device *dev)
4559 {
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 uint32_t tmp;
4562
4563 tmp = I915_READ(MCH_SSKPD);
4564 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4565 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4566 DRM_INFO("This can cause pipe underruns and display issues.\n");
4567 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4568 }
4569 }
4570
4571 static void gen6_init_clock_gating(struct drm_device *dev)
4572 {
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4575
4576 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4577
4578 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4579 I915_READ(ILK_DISPLAY_CHICKEN2) |
4580 ILK_ELPIN_409_SELECT);
4581
4582 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4583 I915_WRITE(_3D_CHICKEN,
4584 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4585
4586 /* WaSetupGtModeTdRowDispatch:snb */
4587 if (IS_SNB_GT1(dev))
4588 I915_WRITE(GEN6_GT_MODE,
4589 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4590
4591 ilk_init_lp_watermarks(dev);
4592
4593 I915_WRITE(CACHE_MODE_0,
4594 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4595
4596 I915_WRITE(GEN6_UCGCTL1,
4597 I915_READ(GEN6_UCGCTL1) |
4598 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4599 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4600
4601 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4602 * gating disable must be set. Failure to set it results in
4603 * flickering pixels due to Z write ordering failures after
4604 * some amount of runtime in the Mesa "fire" demo, and Unigine
4605 * Sanctuary and Tropics, and apparently anything else with
4606 * alpha test or pixel discard.
4607 *
4608 * According to the spec, bit 11 (RCCUNIT) must also be set,
4609 * but we didn't debug actual testcases to find it out.
4610 *
4611 * WaDisableRCCUnitClockGating:snb
4612 * WaDisableRCPBUnitClockGating:snb
4613 */
4614 I915_WRITE(GEN6_UCGCTL2,
4615 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4616 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4617
4618 /* Bspec says we need to always set all mask bits. */
4619 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4620 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4621
4622 /*
4623 * According to the spec the following bits should be
4624 * set in order to enable memory self-refresh and fbc:
4625 * The bit21 and bit22 of 0x42000
4626 * The bit21 and bit22 of 0x42004
4627 * The bit5 and bit7 of 0x42020
4628 * The bit14 of 0x70180
4629 * The bit14 of 0x71180
4630 *
4631 * WaFbcAsynchFlipDisableFbcQueue:snb
4632 */
4633 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4634 I915_READ(ILK_DISPLAY_CHICKEN1) |
4635 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4636 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4637 I915_READ(ILK_DISPLAY_CHICKEN2) |
4638 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4639 I915_WRITE(ILK_DSPCLK_GATE_D,
4640 I915_READ(ILK_DSPCLK_GATE_D) |
4641 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4642 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4643
4644 g4x_disable_trickle_feed(dev);
4645
4646 /* The default value should be 0x200 according to docs, but the two
4647 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4648 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4649 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4650
4651 cpt_init_clock_gating(dev);
4652
4653 gen6_check_mch_setup(dev);
4654 }
4655
4656 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4657 {
4658 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4659
4660 reg &= ~GEN7_FF_SCHED_MASK;
4661 reg |= GEN7_FF_TS_SCHED_HW;
4662 reg |= GEN7_FF_VS_SCHED_HW;
4663 reg |= GEN7_FF_DS_SCHED_HW;
4664
4665 if (IS_HASWELL(dev_priv->dev))
4666 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4667
4668 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4669 }
4670
4671 static void lpt_init_clock_gating(struct drm_device *dev)
4672 {
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674
4675 /*
4676 * TODO: this bit should only be enabled when really needed, then
4677 * disabled when not needed anymore in order to save power.
4678 */
4679 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4680 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4681 I915_READ(SOUTH_DSPCLK_GATE_D) |
4682 PCH_LP_PARTITION_LEVEL_DISABLE);
4683
4684 /* WADPOClockGatingDisable:hsw */
4685 I915_WRITE(_TRANSA_CHICKEN1,
4686 I915_READ(_TRANSA_CHICKEN1) |
4687 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4688 }
4689
4690 static void lpt_suspend_hw(struct drm_device *dev)
4691 {
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693
4694 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4695 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4696
4697 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4698 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4699 }
4700 }
4701
4702 static void gen8_init_clock_gating(struct drm_device *dev)
4703 {
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 enum pipe i;
4706
4707 I915_WRITE(WM3_LP_ILK, 0);
4708 I915_WRITE(WM2_LP_ILK, 0);
4709 I915_WRITE(WM1_LP_ILK, 0);
4710
4711 /* FIXME(BDW): Check all the w/a, some might only apply to
4712 * pre-production hw. */
4713
4714 /*
4715 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4716 * pre-production hardware
4717 */
4718 I915_WRITE(HALF_SLICE_CHICKEN3,
4719 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4720 I915_WRITE(HALF_SLICE_CHICKEN3,
4721 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4722 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4723
4724 I915_WRITE(_3D_CHICKEN3,
4725 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4726
4727 I915_WRITE(COMMON_SLICE_CHICKEN2,
4728 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4729
4730 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4731 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4732
4733 /* WaSwitchSolVfFArbitrationPriority:bdw */
4734 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4735
4736 /* WaPsrDPAMaskVBlankInSRD:bdw */
4737 I915_WRITE(CHICKEN_PAR1_1,
4738 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4739
4740 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4741 for_each_pipe(i) {
4742 I915_WRITE(CHICKEN_PIPESL_1(i),
4743 I915_READ(CHICKEN_PIPESL_1(i) |
4744 DPRS_MASK_VBLANK_SRD));
4745 }
4746
4747 /* Use Force Non-Coherent whenever executing a 3D context. This is a
4748 * workaround for for a possible hang in the unlikely event a TLB
4749 * invalidation occurs during a PSD flush.
4750 */
4751 I915_WRITE(HDC_CHICKEN0,
4752 I915_READ(HDC_CHICKEN0) |
4753 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4754
4755 /* WaVSRefCountFullforceMissDisable:bdw */
4756 /* WaDSRefCountFullforceMissDisable:bdw */
4757 I915_WRITE(GEN7_FF_THREAD_MODE,
4758 I915_READ(GEN7_FF_THREAD_MODE) &
4759 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4760 }
4761
4762 static void haswell_init_clock_gating(struct drm_device *dev)
4763 {
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765
4766 ilk_init_lp_watermarks(dev);
4767
4768 /* L3 caching of data atomics doesn't work -- disable it. */
4769 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4770 I915_WRITE(HSW_ROW_CHICKEN3,
4771 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4772
4773 /* This is required by WaCatErrorRejectionIssue:hsw */
4774 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4775 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4776 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4777
4778 /* WaVSRefCountFullforceMissDisable:hsw */
4779 gen7_setup_fixed_func_scheduler(dev_priv);
4780
4781 /* WaDisable4x2SubspanOptimization:hsw */
4782 I915_WRITE(CACHE_MODE_1,
4783 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4784
4785 /* WaSwitchSolVfFArbitrationPriority:hsw */
4786 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4787
4788 /* WaRsPkgCStateDisplayPMReq:hsw */
4789 I915_WRITE(CHICKEN_PAR1_1,
4790 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4791
4792 lpt_init_clock_gating(dev);
4793 }
4794
4795 static void ivybridge_init_clock_gating(struct drm_device *dev)
4796 {
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 uint32_t snpcr;
4799
4800 ilk_init_lp_watermarks(dev);
4801
4802 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4803
4804 /* WaDisableEarlyCull:ivb */
4805 I915_WRITE(_3D_CHICKEN3,
4806 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4807
4808 /* WaDisableBackToBackFlipFix:ivb */
4809 I915_WRITE(IVB_CHICKEN3,
4810 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4811 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4812
4813 /* WaDisablePSDDualDispatchEnable:ivb */
4814 if (IS_IVB_GT1(dev))
4815 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4816 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4817 else
4818 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4819 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4820
4821 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4822 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4823 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4824
4825 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4826 I915_WRITE(GEN7_L3CNTLREG1,
4827 GEN7_WA_FOR_GEN7_L3_CONTROL);
4828 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4829 GEN7_WA_L3_CHICKEN_MODE);
4830 if (IS_IVB_GT1(dev))
4831 I915_WRITE(GEN7_ROW_CHICKEN2,
4832 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4833 else
4834 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4835 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4836
4837
4838 /* WaForceL3Serialization:ivb */
4839 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4840 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4841
4842 /*
4843 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4844 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4845 */
4846 I915_WRITE(GEN6_UCGCTL2,
4847 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4848
4849 /* This is required by WaCatErrorRejectionIssue:ivb */
4850 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4851 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4852 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4853
4854 g4x_disable_trickle_feed(dev);
4855
4856 /* WaVSRefCountFullforceMissDisable:ivb */
4857 gen7_setup_fixed_func_scheduler(dev_priv);
4858
4859 /* WaDisable4x2SubspanOptimization:ivb */
4860 I915_WRITE(CACHE_MODE_1,
4861 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4862
4863 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4864 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4865 snpcr |= GEN6_MBC_SNPCR_MED;
4866 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4867
4868 if (!HAS_PCH_NOP(dev))
4869 cpt_init_clock_gating(dev);
4870
4871 gen6_check_mch_setup(dev);
4872 }
4873
4874 static void valleyview_init_clock_gating(struct drm_device *dev)
4875 {
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 u32 val;
4878
4879 mutex_lock(&dev_priv->rps.hw_lock);
4880 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4881 mutex_unlock(&dev_priv->rps.hw_lock);
4882 switch ((val >> 6) & 3) {
4883 case 0:
4884 dev_priv->mem_freq = 800;
4885 break;
4886 case 1:
4887 dev_priv->mem_freq = 1066;
4888 break;
4889 case 2:
4890 dev_priv->mem_freq = 1333;
4891 break;
4892 case 3:
4893 dev_priv->mem_freq = 1333;
4894 break;
4895 }
4896 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4897
4898 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4899
4900 /* WaDisableEarlyCull:vlv */
4901 I915_WRITE(_3D_CHICKEN3,
4902 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4903
4904 /* WaDisableBackToBackFlipFix:vlv */
4905 I915_WRITE(IVB_CHICKEN3,
4906 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4907 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4908
4909 /* WaPsdDispatchEnable:vlv */
4910 /* WaDisablePSDDualDispatchEnable:vlv */
4911 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4912 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4913 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4914
4915 /* WaDisableL3CacheAging:vlv */
4916 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4917
4918 /* WaForceL3Serialization:vlv */
4919 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4920 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4921
4922 /* WaDisableDopClockGating:vlv */
4923 I915_WRITE(GEN7_ROW_CHICKEN2,
4924 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4925
4926 /* This is required by WaCatErrorRejectionIssue:vlv */
4927 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4928 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4929 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4930
4931 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4932 * gating disable must be set. Failure to set it results in
4933 * flickering pixels due to Z write ordering failures after
4934 * some amount of runtime in the Mesa "fire" demo, and Unigine
4935 * Sanctuary and Tropics, and apparently anything else with
4936 * alpha test or pixel discard.
4937 *
4938 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4939 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4940 *
4941 * Also apply WaDisableVDSUnitClockGating:vlv and
4942 * WaDisableRCPBUnitClockGating:vlv.
4943 */
4944 I915_WRITE(GEN6_UCGCTL2,
4945 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4946 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4947 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4948 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
4949
4950 /* WaDisableL3Bank2xClockGate:vlv */
4951 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4952
4953 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4954
4955 I915_WRITE(CACHE_MODE_1,
4956 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4957
4958 /*
4959 * WaIncreaseL3CreditsForVLVB0:vlv
4960 * This is the hardware default actually.
4961 */
4962 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
4963
4964 /*
4965 * WaDisableVLVClockGating_VBIIssue:vlv
4966 * Disable clock gating on th GCFG unit to prevent a delay
4967 * in the reporting of vblank events.
4968 */
4969 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4970
4971 /* Conservative clock gating settings for now */
4972 I915_WRITE(0x9400, 0xffffffff);
4973 I915_WRITE(0x9404, 0xffffffff);
4974 I915_WRITE(0x9408, 0xffffffff);
4975 I915_WRITE(0x940c, 0xffffffff);
4976 I915_WRITE(0x9410, 0xffffffff);
4977 I915_WRITE(0x9414, 0xffffffff);
4978 I915_WRITE(0x9418, 0xffffffff);
4979 }
4980
4981 static void g4x_init_clock_gating(struct drm_device *dev)
4982 {
4983 struct drm_i915_private *dev_priv = dev->dev_private;
4984 uint32_t dspclk_gate;
4985
4986 I915_WRITE(RENCLK_GATE_D1, 0);
4987 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4988 GS_UNIT_CLOCK_GATE_DISABLE |
4989 CL_UNIT_CLOCK_GATE_DISABLE);
4990 I915_WRITE(RAMCLK_GATE_D, 0);
4991 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4992 OVRUNIT_CLOCK_GATE_DISABLE |
4993 OVCUNIT_CLOCK_GATE_DISABLE;
4994 if (IS_GM45(dev))
4995 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4996 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4997
4998 /* WaDisableRenderCachePipelinedFlush */
4999 I915_WRITE(CACHE_MODE_0,
5000 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5001
5002 g4x_disable_trickle_feed(dev);
5003 }
5004
5005 static void crestline_init_clock_gating(struct drm_device *dev)
5006 {
5007 struct drm_i915_private *dev_priv = dev->dev_private;
5008
5009 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5010 I915_WRITE(RENCLK_GATE_D2, 0);
5011 I915_WRITE(DSPCLK_GATE_D, 0);
5012 I915_WRITE(RAMCLK_GATE_D, 0);
5013 I915_WRITE16(DEUC, 0);
5014 I915_WRITE(MI_ARB_STATE,
5015 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5016 }
5017
5018 static void broadwater_init_clock_gating(struct drm_device *dev)
5019 {
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021
5022 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5023 I965_RCC_CLOCK_GATE_DISABLE |
5024 I965_RCPB_CLOCK_GATE_DISABLE |
5025 I965_ISC_CLOCK_GATE_DISABLE |
5026 I965_FBC_CLOCK_GATE_DISABLE);
5027 I915_WRITE(RENCLK_GATE_D2, 0);
5028 I915_WRITE(MI_ARB_STATE,
5029 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5030 }
5031
5032 static void gen3_init_clock_gating(struct drm_device *dev)
5033 {
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035 u32 dstate = I915_READ(D_STATE);
5036
5037 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5038 DSTATE_DOT_CLOCK_GATING;
5039 I915_WRITE(D_STATE, dstate);
5040
5041 if (IS_PINEVIEW(dev))
5042 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5043
5044 /* IIR "flip pending" means done if this bit is set */
5045 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5046 }
5047
5048 static void i85x_init_clock_gating(struct drm_device *dev)
5049 {
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051
5052 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5053 }
5054
5055 static void i830_init_clock_gating(struct drm_device *dev)
5056 {
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058
5059 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5060 }
5061
5062 void intel_init_clock_gating(struct drm_device *dev)
5063 {
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065
5066 dev_priv->display.init_clock_gating(dev);
5067 }
5068
5069 void intel_suspend_hw(struct drm_device *dev)
5070 {
5071 if (HAS_PCH_LPT(dev))
5072 lpt_suspend_hw(dev);
5073 }
5074
5075 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5076 for (i = 0; \
5077 i < (power_domains)->power_well_count && \
5078 ((power_well) = &(power_domains)->power_wells[i]); \
5079 i++) \
5080 if ((power_well)->domains & (domain_mask))
5081
5082 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5083 for (i = (power_domains)->power_well_count - 1; \
5084 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5085 i--) \
5086 if ((power_well)->domains & (domain_mask))
5087
5088 /**
5089 * We should only use the power well if we explicitly asked the hardware to
5090 * enable it, so check if it's enabled and also check if we've requested it to
5091 * be enabled.
5092 */
5093 static bool hsw_power_well_enabled(struct drm_device *dev,
5094 struct i915_power_well *power_well)
5095 {
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097
5098 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5099 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5100 }
5101
5102 bool intel_display_power_enabled_sw(struct drm_device *dev,
5103 enum intel_display_power_domain domain)
5104 {
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106 struct i915_power_domains *power_domains;
5107
5108 power_domains = &dev_priv->power_domains;
5109
5110 return power_domains->domain_use_count[domain];
5111 }
5112
5113 bool intel_display_power_enabled(struct drm_device *dev,
5114 enum intel_display_power_domain domain)
5115 {
5116 struct drm_i915_private *dev_priv = dev->dev_private;
5117 struct i915_power_domains *power_domains;
5118 struct i915_power_well *power_well;
5119 bool is_enabled;
5120 int i;
5121
5122 power_domains = &dev_priv->power_domains;
5123
5124 is_enabled = true;
5125
5126 mutex_lock(&power_domains->lock);
5127 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5128 if (power_well->always_on)
5129 continue;
5130
5131 if (!power_well->is_enabled(dev, power_well)) {
5132 is_enabled = false;
5133 break;
5134 }
5135 }
5136 mutex_unlock(&power_domains->lock);
5137
5138 return is_enabled;
5139 }
5140
5141 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5142 {
5143 struct drm_device *dev = dev_priv->dev;
5144 unsigned long irqflags;
5145
5146 /*
5147 * After we re-enable the power well, if we touch VGA register 0x3d5
5148 * we'll get unclaimed register interrupts. This stops after we write
5149 * anything to the VGA MSR register. The vgacon module uses this
5150 * register all the time, so if we unbind our driver and, as a
5151 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5152 * console_unlock(). So make here we touch the VGA MSR register, making
5153 * sure vgacon can keep working normally without triggering interrupts
5154 * and error messages.
5155 */
5156 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5157 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5158 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5159
5160 if (IS_BROADWELL(dev)) {
5161 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5162 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5163 dev_priv->de_irq_mask[PIPE_B]);
5164 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5165 ~dev_priv->de_irq_mask[PIPE_B] |
5166 GEN8_PIPE_VBLANK);
5167 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5168 dev_priv->de_irq_mask[PIPE_C]);
5169 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5170 ~dev_priv->de_irq_mask[PIPE_C] |
5171 GEN8_PIPE_VBLANK);
5172 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5173 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5174 }
5175 }
5176
5177 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5178 {
5179 struct drm_device *dev = dev_priv->dev;
5180 enum pipe p;
5181 unsigned long irqflags;
5182
5183 /*
5184 * After this, the registers on the pipes that are part of the power
5185 * well will become zero, so we have to adjust our counters according to
5186 * that.
5187 *
5188 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5189 */
5190 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5191 for_each_pipe(p)
5192 if (p != PIPE_A)
5193 dev->vblank[p].last = 0;
5194 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5195 }
5196
5197 static void hsw_set_power_well(struct drm_device *dev,
5198 struct i915_power_well *power_well, bool enable)
5199 {
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 bool is_enabled, enable_requested;
5202 uint32_t tmp;
5203
5204 WARN_ON(dev_priv->pc8.enabled);
5205
5206 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5207 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5208 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5209
5210 if (enable) {
5211 if (!enable_requested)
5212 I915_WRITE(HSW_PWR_WELL_DRIVER,
5213 HSW_PWR_WELL_ENABLE_REQUEST);
5214
5215 if (!is_enabled) {
5216 DRM_DEBUG_KMS("Enabling power well\n");
5217 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5218 HSW_PWR_WELL_STATE_ENABLED), 20))
5219 DRM_ERROR("Timeout enabling power well\n");
5220 }
5221
5222 hsw_power_well_post_enable(dev_priv);
5223 } else {
5224 if (enable_requested) {
5225 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5226 POSTING_READ(HSW_PWR_WELL_DRIVER);
5227 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5228
5229 hsw_power_well_post_disable(dev_priv);
5230 }
5231 }
5232 }
5233
5234 static void __intel_power_well_get(struct drm_device *dev,
5235 struct i915_power_well *power_well)
5236 {
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238
5239 if (!power_well->count++ && power_well->set) {
5240 hsw_disable_package_c8(dev_priv);
5241 power_well->set(dev, power_well, true);
5242 }
5243 }
5244
5245 static void __intel_power_well_put(struct drm_device *dev,
5246 struct i915_power_well *power_well)
5247 {
5248 struct drm_i915_private *dev_priv = dev->dev_private;
5249
5250 WARN_ON(!power_well->count);
5251
5252 if (!--power_well->count && power_well->set &&
5253 i915.disable_power_well) {
5254 power_well->set(dev, power_well, false);
5255 hsw_enable_package_c8(dev_priv);
5256 }
5257 }
5258
5259 void intel_display_power_get(struct drm_device *dev,
5260 enum intel_display_power_domain domain)
5261 {
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 struct i915_power_domains *power_domains;
5264 struct i915_power_well *power_well;
5265 int i;
5266
5267 power_domains = &dev_priv->power_domains;
5268
5269 mutex_lock(&power_domains->lock);
5270
5271 for_each_power_well(i, power_well, BIT(domain), power_domains)
5272 __intel_power_well_get(dev, power_well);
5273
5274 power_domains->domain_use_count[domain]++;
5275
5276 mutex_unlock(&power_domains->lock);
5277 }
5278
5279 void intel_display_power_put(struct drm_device *dev,
5280 enum intel_display_power_domain domain)
5281 {
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 struct i915_power_domains *power_domains;
5284 struct i915_power_well *power_well;
5285 int i;
5286
5287 power_domains = &dev_priv->power_domains;
5288
5289 mutex_lock(&power_domains->lock);
5290
5291 WARN_ON(!power_domains->domain_use_count[domain]);
5292 power_domains->domain_use_count[domain]--;
5293
5294 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5295 __intel_power_well_put(dev, power_well);
5296
5297 mutex_unlock(&power_domains->lock);
5298 }
5299
5300 static struct i915_power_domains *hsw_pwr;
5301
5302 /* Display audio driver power well request */
5303 void i915_request_power_well(void)
5304 {
5305 struct drm_i915_private *dev_priv;
5306
5307 if (WARN_ON(!hsw_pwr))
5308 return;
5309
5310 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5311 power_domains);
5312 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5313 }
5314 EXPORT_SYMBOL_GPL(i915_request_power_well);
5315
5316 /* Display audio driver power well release */
5317 void i915_release_power_well(void)
5318 {
5319 struct drm_i915_private *dev_priv;
5320
5321 if (WARN_ON(!hsw_pwr))
5322 return;
5323
5324 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5325 power_domains);
5326 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5327 }
5328 EXPORT_SYMBOL_GPL(i915_release_power_well);
5329
5330 static struct i915_power_well i9xx_always_on_power_well[] = {
5331 {
5332 .name = "always-on",
5333 .always_on = 1,
5334 .domains = POWER_DOMAIN_MASK,
5335 },
5336 };
5337
5338 static struct i915_power_well hsw_power_wells[] = {
5339 {
5340 .name = "always-on",
5341 .always_on = 1,
5342 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5343 },
5344 {
5345 .name = "display",
5346 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5347 .is_enabled = hsw_power_well_enabled,
5348 .set = hsw_set_power_well,
5349 },
5350 };
5351
5352 static struct i915_power_well bdw_power_wells[] = {
5353 {
5354 .name = "always-on",
5355 .always_on = 1,
5356 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5357 },
5358 {
5359 .name = "display",
5360 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5361 .is_enabled = hsw_power_well_enabled,
5362 .set = hsw_set_power_well,
5363 },
5364 };
5365
5366 #define set_power_wells(power_domains, __power_wells) ({ \
5367 (power_domains)->power_wells = (__power_wells); \
5368 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5369 })
5370
5371 int intel_power_domains_init(struct drm_device *dev)
5372 {
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5375
5376 mutex_init(&power_domains->lock);
5377
5378 /*
5379 * The enabling order will be from lower to higher indexed wells,
5380 * the disabling order is reversed.
5381 */
5382 if (IS_HASWELL(dev)) {
5383 set_power_wells(power_domains, hsw_power_wells);
5384 hsw_pwr = power_domains;
5385 } else if (IS_BROADWELL(dev)) {
5386 set_power_wells(power_domains, bdw_power_wells);
5387 hsw_pwr = power_domains;
5388 } else {
5389 set_power_wells(power_domains, i9xx_always_on_power_well);
5390 }
5391
5392 return 0;
5393 }
5394
5395 void intel_power_domains_remove(struct drm_device *dev)
5396 {
5397 hsw_pwr = NULL;
5398 }
5399
5400 static void intel_power_domains_resume(struct drm_device *dev)
5401 {
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5404 struct i915_power_well *power_well;
5405 int i;
5406
5407 mutex_lock(&power_domains->lock);
5408 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5409 if (power_well->set)
5410 power_well->set(dev, power_well, power_well->count > 0);
5411 }
5412 mutex_unlock(&power_domains->lock);
5413 }
5414
5415 /*
5416 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5417 * when not needed anymore. We have 4 registers that can request the power well
5418 * to be enabled, and it will only be disabled if none of the registers is
5419 * requesting it to be enabled.
5420 */
5421 void intel_power_domains_init_hw(struct drm_device *dev)
5422 {
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5424
5425 /* For now, we need the power well to be always enabled. */
5426 intel_display_set_init_power(dev, true);
5427 intel_power_domains_resume(dev);
5428
5429 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5430 return;
5431
5432 /* We're taking over the BIOS, so clear any requests made by it since
5433 * the driver is in charge now. */
5434 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5435 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5436 }
5437
5438 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5439 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5440 {
5441 hsw_disable_package_c8(dev_priv);
5442 }
5443
5444 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5445 {
5446 hsw_enable_package_c8(dev_priv);
5447 }
5448
5449 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5450 {
5451 struct drm_device *dev = dev_priv->dev;
5452 struct device *device = &dev->pdev->dev;
5453
5454 if (!HAS_RUNTIME_PM(dev))
5455 return;
5456
5457 pm_runtime_get_sync(device);
5458 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5459 }
5460
5461 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5462 {
5463 struct drm_device *dev = dev_priv->dev;
5464 struct device *device = &dev->pdev->dev;
5465
5466 if (!HAS_RUNTIME_PM(dev))
5467 return;
5468
5469 pm_runtime_mark_last_busy(device);
5470 pm_runtime_put_autosuspend(device);
5471 }
5472
5473 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5474 {
5475 struct drm_device *dev = dev_priv->dev;
5476 struct device *device = &dev->pdev->dev;
5477
5478 dev_priv->pm.suspended = false;
5479
5480 if (!HAS_RUNTIME_PM(dev))
5481 return;
5482
5483 pm_runtime_set_active(device);
5484
5485 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5486 pm_runtime_mark_last_busy(device);
5487 pm_runtime_use_autosuspend(device);
5488 }
5489
5490 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5491 {
5492 struct drm_device *dev = dev_priv->dev;
5493 struct device *device = &dev->pdev->dev;
5494
5495 if (!HAS_RUNTIME_PM(dev))
5496 return;
5497
5498 /* Make sure we're not suspended first. */
5499 pm_runtime_get_sync(device);
5500 pm_runtime_disable(device);
5501 }
5502
5503 /* Set up chip specific power management-related functions */
5504 void intel_init_pm(struct drm_device *dev)
5505 {
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507
5508 if (HAS_FBC(dev)) {
5509 if (INTEL_INFO(dev)->gen >= 7) {
5510 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5511 dev_priv->display.enable_fbc = gen7_enable_fbc;
5512 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5513 } else if (INTEL_INFO(dev)->gen >= 5) {
5514 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5515 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5516 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5517 } else if (IS_GM45(dev)) {
5518 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5519 dev_priv->display.enable_fbc = g4x_enable_fbc;
5520 dev_priv->display.disable_fbc = g4x_disable_fbc;
5521 } else {
5522 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5523 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5524 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5525
5526 /* This value was pulled out of someone's hat */
5527 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
5528 }
5529 }
5530
5531 /* For cxsr */
5532 if (IS_PINEVIEW(dev))
5533 i915_pineview_get_mem_freq(dev);
5534 else if (IS_GEN5(dev))
5535 i915_ironlake_get_mem_freq(dev);
5536
5537 /* For FIFO watermark updates */
5538 if (HAS_PCH_SPLIT(dev)) {
5539 intel_setup_wm_latency(dev);
5540
5541 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5542 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5543 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
5544 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
5545 dev_priv->display.update_wm = ilk_update_wm;
5546 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
5547 } else {
5548 DRM_DEBUG_KMS("Failed to read display plane latency. "
5549 "Disable CxSR\n");
5550 }
5551
5552 if (IS_GEN5(dev))
5553 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5554 else if (IS_GEN6(dev))
5555 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5556 else if (IS_IVYBRIDGE(dev))
5557 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5558 else if (IS_HASWELL(dev))
5559 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5560 else if (INTEL_INFO(dev)->gen == 8)
5561 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
5562 } else if (IS_VALLEYVIEW(dev)) {
5563 dev_priv->display.update_wm = valleyview_update_wm;
5564 dev_priv->display.init_clock_gating =
5565 valleyview_init_clock_gating;
5566 } else if (IS_PINEVIEW(dev)) {
5567 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5568 dev_priv->is_ddr3,
5569 dev_priv->fsb_freq,
5570 dev_priv->mem_freq)) {
5571 DRM_INFO("failed to find known CxSR latency "
5572 "(found ddr%s fsb freq %d, mem freq %d), "
5573 "disabling CxSR\n",
5574 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5575 dev_priv->fsb_freq, dev_priv->mem_freq);
5576 /* Disable CxSR and never update its watermark again */
5577 pineview_disable_cxsr(dev);
5578 dev_priv->display.update_wm = NULL;
5579 } else
5580 dev_priv->display.update_wm = pineview_update_wm;
5581 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5582 } else if (IS_G4X(dev)) {
5583 dev_priv->display.update_wm = g4x_update_wm;
5584 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5585 } else if (IS_GEN4(dev)) {
5586 dev_priv->display.update_wm = i965_update_wm;
5587 if (IS_CRESTLINE(dev))
5588 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5589 else if (IS_BROADWATER(dev))
5590 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5591 } else if (IS_GEN3(dev)) {
5592 dev_priv->display.update_wm = i9xx_update_wm;
5593 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5594 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5595 } else if (IS_GEN2(dev)) {
5596 if (INTEL_INFO(dev)->num_pipes == 1) {
5597 dev_priv->display.update_wm = i845_update_wm;
5598 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5599 } else {
5600 dev_priv->display.update_wm = i9xx_update_wm;
5601 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5602 }
5603
5604 if (IS_I85X(dev) || IS_I865G(dev))
5605 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5606 else
5607 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5608 } else {
5609 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
5610 }
5611 }
5612
5613 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5614 {
5615 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5616
5617 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5618 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5619 return -EAGAIN;
5620 }
5621
5622 I915_WRITE(GEN6_PCODE_DATA, *val);
5623 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5624
5625 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5626 500)) {
5627 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5628 return -ETIMEDOUT;
5629 }
5630
5631 *val = I915_READ(GEN6_PCODE_DATA);
5632 I915_WRITE(GEN6_PCODE_DATA, 0);
5633
5634 return 0;
5635 }
5636
5637 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5638 {
5639 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5640
5641 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5642 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5643 return -EAGAIN;
5644 }
5645
5646 I915_WRITE(GEN6_PCODE_DATA, val);
5647 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5648
5649 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5650 500)) {
5651 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5652 return -ETIMEDOUT;
5653 }
5654
5655 I915_WRITE(GEN6_PCODE_DATA, 0);
5656
5657 return 0;
5658 }
5659
5660 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
5661 {
5662 int div;
5663
5664 /* 4 x czclk */
5665 switch (dev_priv->mem_freq) {
5666 case 800:
5667 div = 10;
5668 break;
5669 case 1066:
5670 div = 12;
5671 break;
5672 case 1333:
5673 div = 16;
5674 break;
5675 default:
5676 return -1;
5677 }
5678
5679 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
5680 }
5681
5682 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
5683 {
5684 int mul;
5685
5686 /* 4 x czclk */
5687 switch (dev_priv->mem_freq) {
5688 case 800:
5689 mul = 10;
5690 break;
5691 case 1066:
5692 mul = 12;
5693 break;
5694 case 1333:
5695 mul = 16;
5696 break;
5697 default:
5698 return -1;
5699 }
5700
5701 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
5702 }
5703
5704 void intel_pm_setup(struct drm_device *dev)
5705 {
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707
5708 mutex_init(&dev_priv->rps.hw_lock);
5709
5710 mutex_init(&dev_priv->pc8.lock);
5711 dev_priv->pc8.requirements_met = false;
5712 dev_priv->pc8.gpu_idle = false;
5713 dev_priv->pc8.irqs_disabled = false;
5714 dev_priv->pc8.enabled = false;
5715 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
5716 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
5717 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5718 intel_gen6_powersave_work);
5719 }
Linux kernel - Deliverables
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