2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Panel Self Refresh (PSR/SRD)
27 * Since Haswell Display controller supports Panel Self-Refresh on display
28 * panels witch have a remote frame buffer (RFB) implemented according to PSR
29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
30 * when system is idle but display is on as it eliminates display refresh
31 * request to DDR memory completely as long as the frame buffer for that
32 * display is unchanged.
34 * Panel Self Refresh must be supported by both Hardware (source) and
37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
38 * to power down the link and memory controller. For DSI panels the same idea
39 * is called "manual mode".
41 * The implementation uses the hardware-based PSR support which automatically
42 * enters/exits self-refresh mode. The hardware takes care of sending the
43 * required DP aux message and could even retrain the link (that part isn't
44 * enabled yet though). The hardware also keeps track of any frontbuffer
45 * changes to know when to exit self-refresh mode again. Unfortunately that
46 * part doesn't work too well, hence why the i915 PSR support uses the
47 * software frontbuffer tracking to make sure it doesn't miss a screen
48 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
49 * get called by the frontbuffer tracking code. Note that because of locking
50 * issues the self-refresh re-enable code is done from a work queue, which
51 * must be correctly synchronized/cancelled when shutting down the pipe."
56 #include "intel_drv.h"
59 static bool is_edp_psr(struct intel_dp
*intel_dp
)
61 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
64 static bool vlv_is_psr_active_on_pipe(struct drm_device
*dev
, int pipe
)
66 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
69 val
= I915_READ(VLV_PSRSTAT(pipe
)) &
70 VLV_EDP_PSR_CURR_STATE_MASK
;
71 return (val
== VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
72 (val
== VLV_EDP_PSR_ACTIVE_SF_UPDATE
);
75 static void intel_psr_write_vsc(struct intel_dp
*intel_dp
,
76 const struct edp_vsc_psr
*vsc_psr
)
78 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
79 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
80 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
81 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
82 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
83 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
84 uint32_t *data
= (uint32_t *) vsc_psr
;
87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
88 the video DIP being updated before program video DIP data buffer
89 registers for DIP being updated. */
90 I915_WRITE(ctl_reg
, 0);
91 POSTING_READ(ctl_reg
);
93 for (i
= 0; i
< sizeof(*vsc_psr
); i
+= 4) {
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
,
98 for (; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4)
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
,
102 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
103 POSTING_READ(ctl_reg
);
106 static void vlv_psr_setup_vsc(struct intel_dp
*intel_dp
)
108 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
109 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
112 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
115 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
116 val
= I915_READ(VLV_VSCSDP(pipe
));
117 val
&= ~VLV_EDP_PSR_SDP_FREQ_MASK
;
118 val
|= VLV_EDP_PSR_SDP_FREQ_EVFRAME
;
119 I915_WRITE(VLV_VSCSDP(pipe
), val
);
122 static void skl_psr_setup_su_vsc(struct intel_dp
*intel_dp
)
124 struct edp_vsc_psr psr_vsc
;
126 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
127 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
128 psr_vsc
.sdp_header
.HB0
= 0;
129 psr_vsc
.sdp_header
.HB1
= 0x7;
130 psr_vsc
.sdp_header
.HB2
= 0x3;
131 psr_vsc
.sdp_header
.HB3
= 0xb;
132 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
135 static void hsw_psr_setup_vsc(struct intel_dp
*intel_dp
)
137 struct edp_vsc_psr psr_vsc
;
139 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
140 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
141 psr_vsc
.sdp_header
.HB0
= 0;
142 psr_vsc
.sdp_header
.HB1
= 0x7;
143 psr_vsc
.sdp_header
.HB2
= 0x2;
144 psr_vsc
.sdp_header
.HB3
= 0x8;
145 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
148 static void vlv_psr_enable_sink(struct intel_dp
*intel_dp
)
150 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
151 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
154 static i915_reg_t
psr_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
157 if (INTEL_INFO(dev_priv
)->gen
>= 9)
158 return DP_AUX_CH_CTL(port
);
160 return EDP_PSR_AUX_CTL
;
163 static i915_reg_t
psr_aux_data_reg(struct drm_i915_private
*dev_priv
,
164 enum port port
, int index
)
166 if (INTEL_INFO(dev_priv
)->gen
>= 9)
167 return DP_AUX_CH_DATA(port
, index
);
169 return EDP_PSR_AUX_DATA(index
);
172 static void hsw_psr_enable_sink(struct intel_dp
*intel_dp
)
174 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
175 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
177 uint32_t aux_clock_divider
;
178 i915_reg_t aux_ctl_reg
;
180 static const uint8_t aux_msg
[] = {
181 [0] = DP_AUX_NATIVE_WRITE
<< 4,
182 [1] = DP_SET_POWER
>> 8,
183 [2] = DP_SET_POWER
& 0xff,
185 [4] = DP_SET_POWER_D0
,
187 enum port port
= dig_port
->port
;
190 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
192 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
194 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
195 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
197 /* Enable AUX frame sync at sink */
198 if (dev_priv
->psr
.aux_frame_sync
)
199 drm_dp_dpcd_writeb(&intel_dp
->aux
,
200 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF
,
201 DP_AUX_FRAME_SYNC_ENABLE
);
203 aux_ctl_reg
= psr_aux_ctl_reg(dev_priv
, port
);
205 /* Setup AUX registers */
206 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
207 I915_WRITE(psr_aux_data_reg(dev_priv
, port
, i
>> 2),
208 intel_dp_pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
210 if (INTEL_INFO(dev
)->gen
>= 9) {
213 val
= I915_READ(aux_ctl_reg
);
214 val
&= ~DP_AUX_CH_CTL_TIME_OUT_MASK
;
215 val
|= DP_AUX_CH_CTL_TIME_OUT_1600us
;
216 val
&= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
;
217 val
|= (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
218 /* Use hardcoded data values for PSR, frame sync and GTC */
219 val
&= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL
;
220 val
&= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL
;
221 val
&= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL
;
222 I915_WRITE(aux_ctl_reg
, val
);
224 I915_WRITE(aux_ctl_reg
,
225 DP_AUX_CH_CTL_TIME_OUT_400us
|
226 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
227 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
228 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
231 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
, DP_PSR_ENABLE
);
234 static void vlv_psr_enable_source(struct intel_dp
*intel_dp
)
236 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
237 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
240 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
242 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
243 I915_WRITE(VLV_PSRCTL(pipe
),
244 VLV_EDP_PSR_MODE_SW_TIMER
|
245 VLV_EDP_PSR_SRC_TRANSMITTER_STATE
|
249 static void vlv_psr_activate(struct intel_dp
*intel_dp
)
251 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
252 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
254 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
255 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
257 /* Let's do the transition from PSR_state 1 to PSR_state 2
258 * that is PSR transition to active - static frame transmission.
259 * Then Hardware is responsible for the transition to PSR_state 3
260 * that is PSR active - no Remote Frame Buffer (RFB) update.
262 I915_WRITE(VLV_PSRCTL(pipe
), I915_READ(VLV_PSRCTL(pipe
)) |
263 VLV_EDP_PSR_ACTIVE_ENTRY
);
266 static void hsw_psr_enable_source(struct intel_dp
*intel_dp
)
268 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
269 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
272 uint32_t max_sleep_time
= 0x1f;
273 /* Lately it was identified that depending on panel idle frame count
274 * calculated at HW can be off by 1. So let's use what came
276 * There are also other cases where panel demands at least 4
277 * but VBT is not being set. To cover these 2 cases lets use
278 * at least 5 when VBT isn't set to be on the safest side.
280 uint32_t idle_frames
= dev_priv
->vbt
.psr
.idle_frames
?
281 dev_priv
->vbt
.psr
.idle_frames
+ 1 : 5;
283 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
285 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
286 /* It doesn't mean we shouldn't send TPS patters, so let's
287 send the minimal TP1 possible and skip TP2. */
288 val
|= EDP_PSR_TP1_TIME_100us
;
289 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
290 val
|= EDP_PSR_SKIP_AUX_EXIT
;
291 /* Sink should be able to train with the 5 or 6 idle patterns */
295 I915_WRITE(EDP_PSR_CTL
, val
|
296 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
297 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
298 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
301 if (dev_priv
->psr
.psr2_support
)
302 I915_WRITE(EDP_PSR2_CTL
, EDP_PSR2_ENABLE
|
303 EDP_SU_TRACK_ENABLE
| EDP_PSR2_TP2_TIME_100
);
306 static bool intel_psr_match_conditions(struct intel_dp
*intel_dp
)
308 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
309 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
311 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
314 lockdep_assert_held(&dev_priv
->psr
.lock
);
315 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
316 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
318 dev_priv
->psr
.source_ok
= false;
320 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
321 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
325 if (!i915
.enable_psr
) {
326 DRM_DEBUG_KMS("PSR disable by flag\n");
330 if (IS_HASWELL(dev
) &&
331 I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
->cpu_transcoder
)) &
333 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
337 if (IS_HASWELL(dev
) &&
338 intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
339 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
343 if (!IS_VALLEYVIEW(dev
) && ((dev_priv
->vbt
.psr
.full_link
) ||
344 (dig_port
->port
!= PORT_A
))) {
345 DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
349 dev_priv
->psr
.source_ok
= true;
353 static void intel_psr_activate(struct intel_dp
*intel_dp
)
355 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
356 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
359 WARN_ON(I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
);
360 WARN_ON(dev_priv
->psr
.active
);
361 lockdep_assert_held(&dev_priv
->psr
.lock
);
363 /* Enable/Re-enable PSR on the host */
365 /* On HSW+ after we enable PSR on source it will activate it
366 * as soon as it match configure idle_frame count. So
367 * we just actually enable it here on activation time.
369 hsw_psr_enable_source(intel_dp
);
371 vlv_psr_activate(intel_dp
);
373 dev_priv
->psr
.active
= true;
377 * intel_psr_enable - Enable PSR
378 * @intel_dp: Intel DP
380 * This function can only be called after the pipe is fully trained and enabled.
382 void intel_psr_enable(struct intel_dp
*intel_dp
)
384 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
385 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
387 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
390 DRM_DEBUG_KMS("PSR not supported on this platform\n");
394 if (!is_edp_psr(intel_dp
)) {
395 DRM_DEBUG_KMS("PSR not supported by this panel\n");
399 mutex_lock(&dev_priv
->psr
.lock
);
400 if (dev_priv
->psr
.enabled
) {
401 DRM_DEBUG_KMS("PSR already in use\n");
405 if (!intel_psr_match_conditions(intel_dp
))
408 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
411 hsw_psr_setup_vsc(intel_dp
);
413 if (dev_priv
->psr
.psr2_support
) {
414 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
415 if (crtc
->config
->pipe_src_w
> 3200 ||
416 crtc
->config
->pipe_src_h
> 2000)
417 dev_priv
->psr
.psr2_support
= false;
419 skl_psr_setup_su_vsc(intel_dp
);
422 /* Avoid continuous PSR exit by masking memup and hpd */
423 I915_WRITE(EDP_PSR_DEBUG_CTL
, EDP_PSR_DEBUG_MASK_MEMUP
|
424 EDP_PSR_DEBUG_MASK_HPD
);
426 /* Enable PSR on the panel */
427 hsw_psr_enable_sink(intel_dp
);
429 if (INTEL_INFO(dev
)->gen
>= 9)
430 intel_psr_activate(intel_dp
);
432 vlv_psr_setup_vsc(intel_dp
);
434 /* Enable PSR on the panel */
435 vlv_psr_enable_sink(intel_dp
);
437 /* On HSW+ enable_source also means go to PSR entry/active
438 * state as soon as idle_frame achieved and here would be
439 * to soon. However on VLV enable_source just enable PSR
440 * but let it on inactive state. So we might do this prior
441 * to active transition, i.e. here.
443 vlv_psr_enable_source(intel_dp
);
446 dev_priv
->psr
.enabled
= intel_dp
;
448 mutex_unlock(&dev_priv
->psr
.lock
);
451 static void vlv_psr_disable(struct intel_dp
*intel_dp
)
453 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
454 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 struct intel_crtc
*intel_crtc
=
457 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
460 if (dev_priv
->psr
.active
) {
461 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
462 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc
->pipe
)) &
463 VLV_EDP_PSR_IN_TRANS
) == 0, 1))
464 WARN(1, "PSR transition took longer than expected\n");
466 val
= I915_READ(VLV_PSRCTL(intel_crtc
->pipe
));
467 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
468 val
&= ~VLV_EDP_PSR_ENABLE
;
469 val
&= ~VLV_EDP_PSR_MODE_MASK
;
470 I915_WRITE(VLV_PSRCTL(intel_crtc
->pipe
), val
);
472 dev_priv
->psr
.active
= false;
474 WARN_ON(vlv_is_psr_active_on_pipe(dev
, intel_crtc
->pipe
));
478 static void hsw_psr_disable(struct intel_dp
*intel_dp
)
480 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
481 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 if (dev_priv
->psr
.active
) {
485 I915_WRITE(EDP_PSR_CTL
,
486 I915_READ(EDP_PSR_CTL
) & ~EDP_PSR_ENABLE
);
488 /* Wait till PSR is idle */
489 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL
) &
490 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
491 DRM_ERROR("Timed out waiting for PSR Idle State\n");
493 dev_priv
->psr
.active
= false;
495 WARN_ON(I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
);
500 * intel_psr_disable - Disable PSR
501 * @intel_dp: Intel DP
503 * This function needs to be called before disabling pipe.
505 void intel_psr_disable(struct intel_dp
*intel_dp
)
507 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
508 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
511 mutex_lock(&dev_priv
->psr
.lock
);
512 if (!dev_priv
->psr
.enabled
) {
513 mutex_unlock(&dev_priv
->psr
.lock
);
518 hsw_psr_disable(intel_dp
);
520 vlv_psr_disable(intel_dp
);
522 dev_priv
->psr
.enabled
= NULL
;
523 mutex_unlock(&dev_priv
->psr
.lock
);
525 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
528 static void intel_psr_work(struct work_struct
*work
)
530 struct drm_i915_private
*dev_priv
=
531 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
532 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
533 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
534 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
536 /* We have to make sure PSR is ready for re-enable
537 * otherwise it keeps disabled until next full enable/disable cycle.
538 * PSR might take some time to get fully disabled
539 * and be ready for re-enable.
541 if (HAS_DDI(dev_priv
->dev
)) {
542 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL
) &
543 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
544 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
548 if (wait_for((I915_READ(VLV_PSRSTAT(pipe
)) &
549 VLV_EDP_PSR_IN_TRANS
) == 0, 1)) {
550 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
554 mutex_lock(&dev_priv
->psr
.lock
);
555 intel_dp
= dev_priv
->psr
.enabled
;
561 * The delayed work can race with an invalidate hence we need to
562 * recheck. Since psr_flush first clears this and then reschedules we
563 * won't ever miss a flush when bailing out here.
565 if (dev_priv
->psr
.busy_frontbuffer_bits
)
568 intel_psr_activate(intel_dp
);
570 mutex_unlock(&dev_priv
->psr
.lock
);
573 static void intel_psr_exit(struct drm_device
*dev
)
575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
576 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
577 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
578 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
581 if (!dev_priv
->psr
.active
)
585 val
= I915_READ(EDP_PSR_CTL
);
587 WARN_ON(!(val
& EDP_PSR_ENABLE
));
589 I915_WRITE(EDP_PSR_CTL
, val
& ~EDP_PSR_ENABLE
);
591 val
= I915_READ(VLV_PSRCTL(pipe
));
593 /* Here we do the transition from PSR_state 3 to PSR_state 5
594 * directly once PSR State 4 that is active with single frame
595 * update can be skipped. PSR_state 5 that is PSR exit then
596 * Hardware is responsible to transition back to PSR_state 1
597 * that is PSR inactive. Same state after
598 * vlv_edp_psr_enable_source.
600 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
601 I915_WRITE(VLV_PSRCTL(pipe
), val
);
603 /* Send AUX wake up - Spec says after transitioning to PSR
604 * active we have to send AUX wake up by writing 01h in DPCD
605 * 600h of sink device.
606 * XXX: This might slow down the transition, but without this
607 * HW doesn't complete the transition to PSR_state 1 and we
608 * never get the screen updated.
610 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
614 dev_priv
->psr
.active
= false;
618 * intel_psr_single_frame_update - Single Frame Update
620 * @frontbuffer_bits: frontbuffer plane tracking bits
622 * Some platforms support a single frame update feature that is used to
623 * send and update only one frame on Remote Frame Buffer.
624 * So far it is only implemented for Valleyview and Cherryview because
625 * hardware requires this to be done before a page flip.
627 void intel_psr_single_frame_update(struct drm_device
*dev
,
628 unsigned frontbuffer_bits
)
630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
631 struct drm_crtc
*crtc
;
636 * Single frame update is already supported on BDW+ but it requires
637 * many W/A and it isn't really needed.
639 if (!IS_VALLEYVIEW(dev
))
642 mutex_lock(&dev_priv
->psr
.lock
);
643 if (!dev_priv
->psr
.enabled
) {
644 mutex_unlock(&dev_priv
->psr
.lock
);
648 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
649 pipe
= to_intel_crtc(crtc
)->pipe
;
651 if (frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)) {
652 val
= I915_READ(VLV_PSRCTL(pipe
));
655 * We need to set this bit before writing registers for a flip.
656 * This bit will be self-clear when it gets to the PSR active state.
658 I915_WRITE(VLV_PSRCTL(pipe
), val
| VLV_EDP_PSR_SINGLE_FRAME_UPDATE
);
660 mutex_unlock(&dev_priv
->psr
.lock
);
664 * intel_psr_invalidate - Invalidade PSR
666 * @frontbuffer_bits: frontbuffer plane tracking bits
668 * Since the hardware frontbuffer tracking has gaps we need to integrate
669 * with the software frontbuffer tracking. This function gets called every
670 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
671 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
673 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
675 void intel_psr_invalidate(struct drm_device
*dev
,
676 unsigned frontbuffer_bits
)
678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
679 struct drm_crtc
*crtc
;
682 mutex_lock(&dev_priv
->psr
.lock
);
683 if (!dev_priv
->psr
.enabled
) {
684 mutex_unlock(&dev_priv
->psr
.lock
);
688 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
689 pipe
= to_intel_crtc(crtc
)->pipe
;
691 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
692 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
694 if (frontbuffer_bits
)
697 mutex_unlock(&dev_priv
->psr
.lock
);
701 * intel_psr_flush - Flush PSR
703 * @frontbuffer_bits: frontbuffer plane tracking bits
704 * @origin: which operation caused the flush
706 * Since the hardware frontbuffer tracking has gaps we need to integrate
707 * with the software frontbuffer tracking. This function gets called every
708 * time frontbuffer rendering has completed and flushed out to memory. PSR
709 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
711 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
713 void intel_psr_flush(struct drm_device
*dev
,
714 unsigned frontbuffer_bits
, enum fb_op_origin origin
)
716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
717 struct drm_crtc
*crtc
;
719 int delay_ms
= HAS_DDI(dev
) ? 100 : 500;
721 mutex_lock(&dev_priv
->psr
.lock
);
722 if (!dev_priv
->psr
.enabled
) {
723 mutex_unlock(&dev_priv
->psr
.lock
);
727 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
728 pipe
= to_intel_crtc(crtc
)->pipe
;
730 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
731 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
735 * By definition every flush should mean invalidate + flush,
736 * however on core platforms let's minimize the
737 * disable/re-enable so we can avoid the invalidate when flip
738 * originated the flush.
740 if (frontbuffer_bits
&& origin
!= ORIGIN_FLIP
)
744 * On Valleyview and Cherryview we don't use hardware tracking
745 * so any plane updates or cursor moves don't result in a PSR
746 * invalidating. Which means we need to manually fake this in
747 * software for all flushes.
749 if (frontbuffer_bits
)
753 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
754 schedule_delayed_work(&dev_priv
->psr
.work
,
755 msecs_to_jiffies(delay_ms
));
756 mutex_unlock(&dev_priv
->psr
.lock
);
760 * intel_psr_init - Init basic PSR work and mutex.
763 * This function is called only once at driver load to initialize basic
766 void intel_psr_init(struct drm_device
*dev
)
768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
770 dev_priv
->psr_mmio_base
= IS_HASWELL(dev_priv
) ?
771 HSW_EDP_PSR_BASE
: BDW_EDP_PSR_BASE
;
773 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_psr_work
);
774 mutex_init(&dev_priv
->psr
.lock
);