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drm/i915/chv: Combine GEN8_ROW_CHICKEN w/a
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - (tail + I915_RING_FREE_SPACE);
56 if (space < 0)
57 space += size;
58 return space;
59 }
60
61 int intel_ring_space(struct intel_ringbuffer *ringbuf)
62 {
63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
65 }
66
67 bool intel_ring_stopped(struct intel_engine_cs *ring)
68 {
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71 }
72
73 void __intel_ring_advance(struct intel_engine_cs *ring)
74 {
75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
77 if (intel_ring_stopped(ring))
78 return;
79 ring->write_tail(ring, ringbuf->tail);
80 }
81
82 static int
83 gen2_render_ring_flush(struct intel_engine_cs *ring,
84 u32 invalidate_domains,
85 u32 flush_domains)
86 {
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106 }
107
108 static int
109 gen4_render_ring_flush(struct intel_engine_cs *ring,
110 u32 invalidate_domains,
111 u32 flush_domains)
112 {
113 struct drm_device *dev = ring->dev;
114 u32 cmd;
115 int ret;
116
117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
147 cmd &= ~MI_NO_WRITE_FLUSH;
148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
150
151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
154
155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
158
159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
162
163 return 0;
164 }
165
166 /**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203 static int
204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
205 {
206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236 }
237
238 static int
239 gen6_render_ring_flush(struct intel_engine_cs *ring,
240 u32 invalidate_domains, u32 flush_domains)
241 {
242 u32 flags = 0;
243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
244 int ret;
245
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
262 flags |= PIPE_CONTROL_CS_STALL;
263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
275 }
276
277 ret = intel_ring_begin(ring, 4);
278 if (ret)
279 return ret;
280
281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
284 intel_ring_emit(ring, 0);
285 intel_ring_advance(ring);
286
287 return 0;
288 }
289
290 static int
291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
292 {
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307 }
308
309 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
310 {
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
316 ret = intel_ring_begin(ring, 6);
317 if (ret)
318 return ret;
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330 }
331
332 static int
333 gen7_render_ring_flush(struct intel_engine_cs *ring,
334 u32 invalidate_domains, u32 flush_domains)
335 {
336 u32 flags = 0;
337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
338 int ret;
339
340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
365 /*
366 * TLB invalidate requires a post-sync write.
367 */
368 flags |= PIPE_CONTROL_QW_WRITE;
369 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
370
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring);
375 }
376
377 ret = intel_ring_begin(ring, 4);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring, flags);
383 intel_ring_emit(ring, scratch_addr);
384 intel_ring_emit(ring, 0);
385 intel_ring_advance(ring);
386
387 if (!invalidate_domains && flush_domains)
388 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
389
390 return 0;
391 }
392
393 static int
394 gen8_emit_pipe_control(struct intel_engine_cs *ring,
395 u32 flags, u32 scratch_addr)
396 {
397 int ret;
398
399 ret = intel_ring_begin(ring, 6);
400 if (ret)
401 return ret;
402
403 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring, flags);
405 intel_ring_emit(ring, scratch_addr);
406 intel_ring_emit(ring, 0);
407 intel_ring_emit(ring, 0);
408 intel_ring_emit(ring, 0);
409 intel_ring_advance(ring);
410
411 return 0;
412 }
413
414 static int
415 gen8_render_ring_flush(struct intel_engine_cs *ring,
416 u32 invalidate_domains, u32 flush_domains)
417 {
418 u32 flags = 0;
419 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
420 int ret;
421
422 flags |= PIPE_CONTROL_CS_STALL;
423
424 if (flush_domains) {
425 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
426 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
427 }
428 if (invalidate_domains) {
429 flags |= PIPE_CONTROL_TLB_INVALIDATE;
430 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_QW_WRITE;
436 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
437
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret = gen8_emit_pipe_control(ring,
440 PIPE_CONTROL_CS_STALL |
441 PIPE_CONTROL_STALL_AT_SCOREBOARD,
442 0);
443 if (ret)
444 return ret;
445 }
446
447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
448 if (ret)
449 return ret;
450
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
453
454 return 0;
455 }
456
457 static void ring_write_tail(struct intel_engine_cs *ring,
458 u32 value)
459 {
460 struct drm_i915_private *dev_priv = ring->dev->dev_private;
461 I915_WRITE_TAIL(ring, value);
462 }
463
464 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
465 {
466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
467 u64 acthd;
468
469 if (INTEL_INFO(ring->dev)->gen >= 8)
470 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
471 RING_ACTHD_UDW(ring->mmio_base));
472 else if (INTEL_INFO(ring->dev)->gen >= 4)
473 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
474 else
475 acthd = I915_READ(ACTHD);
476
477 return acthd;
478 }
479
480 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
481 {
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 addr;
484
485 addr = dev_priv->status_page_dmah->busaddr;
486 if (INTEL_INFO(ring->dev)->gen >= 4)
487 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
488 I915_WRITE(HWS_PGA, addr);
489 }
490
491 static bool stop_ring(struct intel_engine_cs *ring)
492 {
493 struct drm_i915_private *dev_priv = to_i915(ring->dev);
494
495 if (!IS_GEN2(ring->dev)) {
496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
497 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
502 */
503 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
504 return false;
505 }
506 }
507
508 I915_WRITE_CTL(ring, 0);
509 I915_WRITE_HEAD(ring, 0);
510 ring->write_tail(ring, 0);
511
512 if (!IS_GEN2(ring->dev)) {
513 (void)I915_READ_CTL(ring);
514 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
515 }
516
517 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
518 }
519
520 static int init_ring_common(struct intel_engine_cs *ring)
521 {
522 struct drm_device *dev = ring->dev;
523 struct drm_i915_private *dev_priv = dev->dev_private;
524 struct intel_ringbuffer *ringbuf = ring->buffer;
525 struct drm_i915_gem_object *obj = ringbuf->obj;
526 int ret = 0;
527
528 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
529
530 if (!stop_ring(ring)) {
531 /* G45 ring initialization often fails to reset head to zero */
532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
534 ring->name,
535 I915_READ_CTL(ring),
536 I915_READ_HEAD(ring),
537 I915_READ_TAIL(ring),
538 I915_READ_START(ring));
539
540 if (!stop_ring(ring)) {
541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
543 ring->name,
544 I915_READ_CTL(ring),
545 I915_READ_HEAD(ring),
546 I915_READ_TAIL(ring),
547 I915_READ_START(ring));
548 ret = -EIO;
549 goto out;
550 }
551 }
552
553 if (I915_NEED_GFX_HWS(dev))
554 intel_ring_setup_status_page(ring);
555 else
556 ring_setup_phys_status_page(ring);
557
558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring);
560
561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
566
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
573
574 I915_WRITE_CTL(ring,
575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
576 | RING_VALID);
577
578 /* If the head is still not zero, the ring is dead */
579 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
580 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
581 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
582 DRM_ERROR("%s initialization failed "
583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
584 ring->name,
585 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
586 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
587 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
588 ret = -EIO;
589 goto out;
590 }
591
592 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
593 i915_kernel_lost_context(ring->dev);
594 else {
595 ringbuf->head = I915_READ_HEAD(ring);
596 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
597 ringbuf->space = intel_ring_space(ringbuf);
598 ringbuf->last_retired_head = -1;
599 }
600
601 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
602
603 out:
604 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
605
606 return ret;
607 }
608
609 void
610 intel_fini_pipe_control(struct intel_engine_cs *ring)
611 {
612 struct drm_device *dev = ring->dev;
613
614 if (ring->scratch.obj == NULL)
615 return;
616
617 if (INTEL_INFO(dev)->gen >= 5) {
618 kunmap(sg_page(ring->scratch.obj->pages->sgl));
619 i915_gem_object_ggtt_unpin(ring->scratch.obj);
620 }
621
622 drm_gem_object_unreference(&ring->scratch.obj->base);
623 ring->scratch.obj = NULL;
624 }
625
626 int
627 intel_init_pipe_control(struct intel_engine_cs *ring)
628 {
629 int ret;
630
631 if (ring->scratch.obj)
632 return 0;
633
634 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
635 if (ring->scratch.obj == NULL) {
636 DRM_ERROR("Failed to allocate seqno page\n");
637 ret = -ENOMEM;
638 goto err;
639 }
640
641 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
642 if (ret)
643 goto err_unref;
644
645 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
646 if (ret)
647 goto err_unref;
648
649 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
650 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
651 if (ring->scratch.cpu_page == NULL) {
652 ret = -ENOMEM;
653 goto err_unpin;
654 }
655
656 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
657 ring->name, ring->scratch.gtt_offset);
658 return 0;
659
660 err_unpin:
661 i915_gem_object_ggtt_unpin(ring->scratch.obj);
662 err_unref:
663 drm_gem_object_unreference(&ring->scratch.obj->base);
664 err:
665 return ret;
666 }
667
668 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
669 {
670 int ret, i;
671 struct drm_device *dev = ring->dev;
672 struct drm_i915_private *dev_priv = dev->dev_private;
673 struct i915_workarounds *w = &dev_priv->workarounds;
674
675 if (WARN_ON(w->count == 0))
676 return 0;
677
678 ring->gpu_caches_dirty = true;
679 ret = intel_ring_flush_all_caches(ring);
680 if (ret)
681 return ret;
682
683 ret = intel_ring_begin(ring, (w->count * 2 + 2));
684 if (ret)
685 return ret;
686
687 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
688 for (i = 0; i < w->count; i++) {
689 intel_ring_emit(ring, w->reg[i].addr);
690 intel_ring_emit(ring, w->reg[i].value);
691 }
692 intel_ring_emit(ring, MI_NOOP);
693
694 intel_ring_advance(ring);
695
696 ring->gpu_caches_dirty = true;
697 ret = intel_ring_flush_all_caches(ring);
698 if (ret)
699 return ret;
700
701 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
702
703 return 0;
704 }
705
706 static int wa_add(struct drm_i915_private *dev_priv,
707 const u32 addr, const u32 val, const u32 mask)
708 {
709 const u32 idx = dev_priv->workarounds.count;
710
711 if (WARN_ON(idx >= I915_MAX_WA_REGS))
712 return -ENOSPC;
713
714 dev_priv->workarounds.reg[idx].addr = addr;
715 dev_priv->workarounds.reg[idx].value = val;
716 dev_priv->workarounds.reg[idx].mask = mask;
717
718 dev_priv->workarounds.count++;
719
720 return 0;
721 }
722
723 #define WA_REG(addr, val, mask) { \
724 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
725 if (r) \
726 return r; \
727 }
728
729 #define WA_SET_BIT_MASKED(addr, mask) \
730 WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
731
732 #define WA_CLR_BIT_MASKED(addr, mask) \
733 WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
734
735 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
736 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
737
738 #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
739
740 static int bdw_init_workarounds(struct intel_engine_cs *ring)
741 {
742 struct drm_device *dev = ring->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744
745 /* WaDisablePartialInstShootdown:bdw */
746 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
747 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
748 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
749 STALL_DOP_GATING_DISABLE);
750
751 /* WaDisableDopClockGating:bdw */
752 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
753 DOP_CLOCK_GATING_DISABLE);
754
755 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
756 GEN8_SAMPLER_POWER_BYPASS_DIS);
757
758 /* Use Force Non-Coherent whenever executing a 3D context. This is a
759 * workaround for for a possible hang in the unlikely event a TLB
760 * invalidation occurs during a PSD flush.
761 */
762 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
763 WA_SET_BIT_MASKED(HDC_CHICKEN0,
764 HDC_FORCE_NON_COHERENT |
765 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
766
767 /* Wa4x4STCOptimizationDisable:bdw */
768 WA_SET_BIT_MASKED(CACHE_MODE_1,
769 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
770
771 /*
772 * BSpec recommends 8x4 when MSAA is used,
773 * however in practice 16x4 seems fastest.
774 *
775 * Note that PS/WM thread counts depend on the WIZ hashing
776 * disable bit, which we don't touch here, but it's good
777 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
778 */
779 WA_SET_BIT_MASKED(GEN7_GT_MODE,
780 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
781
782 return 0;
783 }
784
785 static int chv_init_workarounds(struct intel_engine_cs *ring)
786 {
787 struct drm_device *dev = ring->dev;
788 struct drm_i915_private *dev_priv = dev->dev_private;
789
790 /* WaDisablePartialInstShootdown:chv */
791 /* WaDisableThreadStallDopClockGating:chv */
792 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
793 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
794 STALL_DOP_GATING_DISABLE);
795
796 return 0;
797 }
798
799 static int init_workarounds_ring(struct intel_engine_cs *ring)
800 {
801 struct drm_device *dev = ring->dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803
804 WARN_ON(ring->id != RCS);
805
806 dev_priv->workarounds.count = 0;
807
808 if (IS_BROADWELL(dev))
809 return bdw_init_workarounds(ring);
810
811 if (IS_CHERRYVIEW(dev))
812 return chv_init_workarounds(ring);
813
814 return 0;
815 }
816
817 static int init_render_ring(struct intel_engine_cs *ring)
818 {
819 struct drm_device *dev = ring->dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 int ret = init_ring_common(ring);
822 if (ret)
823 return ret;
824
825 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
826 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
827 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
828
829 /* We need to disable the AsyncFlip performance optimisations in order
830 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
831 * programmed to '1' on all products.
832 *
833 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
834 */
835 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
836 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
837
838 /* Required for the hardware to program scanline values for waiting */
839 /* WaEnableFlushTlbInvalidationMode:snb */
840 if (INTEL_INFO(dev)->gen == 6)
841 I915_WRITE(GFX_MODE,
842 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
843
844 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
845 if (IS_GEN7(dev))
846 I915_WRITE(GFX_MODE_GEN7,
847 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
848 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
849
850 if (INTEL_INFO(dev)->gen >= 5) {
851 ret = intel_init_pipe_control(ring);
852 if (ret)
853 return ret;
854 }
855
856 if (IS_GEN6(dev)) {
857 /* From the Sandybridge PRM, volume 1 part 3, page 24:
858 * "If this bit is set, STCunit will have LRA as replacement
859 * policy. [...] This bit must be reset. LRA replacement
860 * policy is not supported."
861 */
862 I915_WRITE(CACHE_MODE_0,
863 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
864 }
865
866 if (INTEL_INFO(dev)->gen >= 6)
867 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
868
869 if (HAS_L3_DPF(dev))
870 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
871
872 return init_workarounds_ring(ring);
873 }
874
875 static void render_ring_cleanup(struct intel_engine_cs *ring)
876 {
877 struct drm_device *dev = ring->dev;
878 struct drm_i915_private *dev_priv = dev->dev_private;
879
880 if (dev_priv->semaphore_obj) {
881 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
882 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
883 dev_priv->semaphore_obj = NULL;
884 }
885
886 intel_fini_pipe_control(ring);
887 }
888
889 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
890 unsigned int num_dwords)
891 {
892 #define MBOX_UPDATE_DWORDS 8
893 struct drm_device *dev = signaller->dev;
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 struct intel_engine_cs *waiter;
896 int i, ret, num_rings;
897
898 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
899 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
900 #undef MBOX_UPDATE_DWORDS
901
902 ret = intel_ring_begin(signaller, num_dwords);
903 if (ret)
904 return ret;
905
906 for_each_ring(waiter, dev_priv, i) {
907 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
908 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
909 continue;
910
911 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
912 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
913 PIPE_CONTROL_QW_WRITE |
914 PIPE_CONTROL_FLUSH_ENABLE);
915 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
916 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
917 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
918 intel_ring_emit(signaller, 0);
919 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
920 MI_SEMAPHORE_TARGET(waiter->id));
921 intel_ring_emit(signaller, 0);
922 }
923
924 return 0;
925 }
926
927 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
928 unsigned int num_dwords)
929 {
930 #define MBOX_UPDATE_DWORDS 6
931 struct drm_device *dev = signaller->dev;
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 struct intel_engine_cs *waiter;
934 int i, ret, num_rings;
935
936 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
937 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
938 #undef MBOX_UPDATE_DWORDS
939
940 ret = intel_ring_begin(signaller, num_dwords);
941 if (ret)
942 return ret;
943
944 for_each_ring(waiter, dev_priv, i) {
945 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
946 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
947 continue;
948
949 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
950 MI_FLUSH_DW_OP_STOREDW);
951 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
952 MI_FLUSH_DW_USE_GTT);
953 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
954 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
955 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
956 MI_SEMAPHORE_TARGET(waiter->id));
957 intel_ring_emit(signaller, 0);
958 }
959
960 return 0;
961 }
962
963 static int gen6_signal(struct intel_engine_cs *signaller,
964 unsigned int num_dwords)
965 {
966 struct drm_device *dev = signaller->dev;
967 struct drm_i915_private *dev_priv = dev->dev_private;
968 struct intel_engine_cs *useless;
969 int i, ret, num_rings;
970
971 #define MBOX_UPDATE_DWORDS 3
972 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
973 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
974 #undef MBOX_UPDATE_DWORDS
975
976 ret = intel_ring_begin(signaller, num_dwords);
977 if (ret)
978 return ret;
979
980 for_each_ring(useless, dev_priv, i) {
981 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
982 if (mbox_reg != GEN6_NOSYNC) {
983 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
984 intel_ring_emit(signaller, mbox_reg);
985 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
986 }
987 }
988
989 /* If num_dwords was rounded, make sure the tail pointer is correct */
990 if (num_rings % 2 == 0)
991 intel_ring_emit(signaller, MI_NOOP);
992
993 return 0;
994 }
995
996 /**
997 * gen6_add_request - Update the semaphore mailbox registers
998 *
999 * @ring - ring that is adding a request
1000 * @seqno - return seqno stuck into the ring
1001 *
1002 * Update the mailbox registers in the *other* rings with the current seqno.
1003 * This acts like a signal in the canonical semaphore.
1004 */
1005 static int
1006 gen6_add_request(struct intel_engine_cs *ring)
1007 {
1008 int ret;
1009
1010 if (ring->semaphore.signal)
1011 ret = ring->semaphore.signal(ring, 4);
1012 else
1013 ret = intel_ring_begin(ring, 4);
1014
1015 if (ret)
1016 return ret;
1017
1018 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1019 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1020 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1021 intel_ring_emit(ring, MI_USER_INTERRUPT);
1022 __intel_ring_advance(ring);
1023
1024 return 0;
1025 }
1026
1027 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1028 u32 seqno)
1029 {
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 return dev_priv->last_seqno < seqno;
1032 }
1033
1034 /**
1035 * intel_ring_sync - sync the waiter to the signaller on seqno
1036 *
1037 * @waiter - ring that is waiting
1038 * @signaller - ring which has, or will signal
1039 * @seqno - seqno which the waiter will block on
1040 */
1041
1042 static int
1043 gen8_ring_sync(struct intel_engine_cs *waiter,
1044 struct intel_engine_cs *signaller,
1045 u32 seqno)
1046 {
1047 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1048 int ret;
1049
1050 ret = intel_ring_begin(waiter, 4);
1051 if (ret)
1052 return ret;
1053
1054 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1055 MI_SEMAPHORE_GLOBAL_GTT |
1056 MI_SEMAPHORE_POLL |
1057 MI_SEMAPHORE_SAD_GTE_SDD);
1058 intel_ring_emit(waiter, seqno);
1059 intel_ring_emit(waiter,
1060 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1061 intel_ring_emit(waiter,
1062 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1063 intel_ring_advance(waiter);
1064 return 0;
1065 }
1066
1067 static int
1068 gen6_ring_sync(struct intel_engine_cs *waiter,
1069 struct intel_engine_cs *signaller,
1070 u32 seqno)
1071 {
1072 u32 dw1 = MI_SEMAPHORE_MBOX |
1073 MI_SEMAPHORE_COMPARE |
1074 MI_SEMAPHORE_REGISTER;
1075 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1076 int ret;
1077
1078 /* Throughout all of the GEM code, seqno passed implies our current
1079 * seqno is >= the last seqno executed. However for hardware the
1080 * comparison is strictly greater than.
1081 */
1082 seqno -= 1;
1083
1084 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1085
1086 ret = intel_ring_begin(waiter, 4);
1087 if (ret)
1088 return ret;
1089
1090 /* If seqno wrap happened, omit the wait with no-ops */
1091 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1092 intel_ring_emit(waiter, dw1 | wait_mbox);
1093 intel_ring_emit(waiter, seqno);
1094 intel_ring_emit(waiter, 0);
1095 intel_ring_emit(waiter, MI_NOOP);
1096 } else {
1097 intel_ring_emit(waiter, MI_NOOP);
1098 intel_ring_emit(waiter, MI_NOOP);
1099 intel_ring_emit(waiter, MI_NOOP);
1100 intel_ring_emit(waiter, MI_NOOP);
1101 }
1102 intel_ring_advance(waiter);
1103
1104 return 0;
1105 }
1106
1107 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1108 do { \
1109 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1110 PIPE_CONTROL_DEPTH_STALL); \
1111 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1112 intel_ring_emit(ring__, 0); \
1113 intel_ring_emit(ring__, 0); \
1114 } while (0)
1115
1116 static int
1117 pc_render_add_request(struct intel_engine_cs *ring)
1118 {
1119 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1120 int ret;
1121
1122 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1123 * incoherent with writes to memory, i.e. completely fubar,
1124 * so we need to use PIPE_NOTIFY instead.
1125 *
1126 * However, we also need to workaround the qword write
1127 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1128 * memory before requesting an interrupt.
1129 */
1130 ret = intel_ring_begin(ring, 32);
1131 if (ret)
1132 return ret;
1133
1134 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1135 PIPE_CONTROL_WRITE_FLUSH |
1136 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1137 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1138 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1139 intel_ring_emit(ring, 0);
1140 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1141 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1142 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1143 scratch_addr += 2 * CACHELINE_BYTES;
1144 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1145 scratch_addr += 2 * CACHELINE_BYTES;
1146 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1147 scratch_addr += 2 * CACHELINE_BYTES;
1148 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1149 scratch_addr += 2 * CACHELINE_BYTES;
1150 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1151
1152 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1153 PIPE_CONTROL_WRITE_FLUSH |
1154 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1155 PIPE_CONTROL_NOTIFY);
1156 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1157 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1158 intel_ring_emit(ring, 0);
1159 __intel_ring_advance(ring);
1160
1161 return 0;
1162 }
1163
1164 static u32
1165 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1166 {
1167 /* Workaround to force correct ordering between irq and seqno writes on
1168 * ivb (and maybe also on snb) by reading from a CS register (like
1169 * ACTHD) before reading the status page. */
1170 if (!lazy_coherency) {
1171 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1172 POSTING_READ(RING_ACTHD(ring->mmio_base));
1173 }
1174
1175 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1176 }
1177
1178 static u32
1179 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1180 {
1181 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1182 }
1183
1184 static void
1185 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1186 {
1187 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1188 }
1189
1190 static u32
1191 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1192 {
1193 return ring->scratch.cpu_page[0];
1194 }
1195
1196 static void
1197 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1198 {
1199 ring->scratch.cpu_page[0] = seqno;
1200 }
1201
1202 static bool
1203 gen5_ring_get_irq(struct intel_engine_cs *ring)
1204 {
1205 struct drm_device *dev = ring->dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 unsigned long flags;
1208
1209 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1210 return false;
1211
1212 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1213 if (ring->irq_refcount++ == 0)
1214 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1215 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1216
1217 return true;
1218 }
1219
1220 static void
1221 gen5_ring_put_irq(struct intel_engine_cs *ring)
1222 {
1223 struct drm_device *dev = ring->dev;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1225 unsigned long flags;
1226
1227 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1228 if (--ring->irq_refcount == 0)
1229 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1230 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1231 }
1232
1233 static bool
1234 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1235 {
1236 struct drm_device *dev = ring->dev;
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1238 unsigned long flags;
1239
1240 if (!intel_irqs_enabled(dev_priv))
1241 return false;
1242
1243 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1244 if (ring->irq_refcount++ == 0) {
1245 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1246 I915_WRITE(IMR, dev_priv->irq_mask);
1247 POSTING_READ(IMR);
1248 }
1249 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1250
1251 return true;
1252 }
1253
1254 static void
1255 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1256 {
1257 struct drm_device *dev = ring->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1262 if (--ring->irq_refcount == 0) {
1263 dev_priv->irq_mask |= ring->irq_enable_mask;
1264 I915_WRITE(IMR, dev_priv->irq_mask);
1265 POSTING_READ(IMR);
1266 }
1267 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1268 }
1269
1270 static bool
1271 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1272 {
1273 struct drm_device *dev = ring->dev;
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 unsigned long flags;
1276
1277 if (!intel_irqs_enabled(dev_priv))
1278 return false;
1279
1280 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1281 if (ring->irq_refcount++ == 0) {
1282 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1283 I915_WRITE16(IMR, dev_priv->irq_mask);
1284 POSTING_READ16(IMR);
1285 }
1286 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1287
1288 return true;
1289 }
1290
1291 static void
1292 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1293 {
1294 struct drm_device *dev = ring->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 unsigned long flags;
1297
1298 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1299 if (--ring->irq_refcount == 0) {
1300 dev_priv->irq_mask |= ring->irq_enable_mask;
1301 I915_WRITE16(IMR, dev_priv->irq_mask);
1302 POSTING_READ16(IMR);
1303 }
1304 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1305 }
1306
1307 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1308 {
1309 struct drm_device *dev = ring->dev;
1310 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1311 u32 mmio = 0;
1312
1313 /* The ring status page addresses are no longer next to the rest of
1314 * the ring registers as of gen7.
1315 */
1316 if (IS_GEN7(dev)) {
1317 switch (ring->id) {
1318 case RCS:
1319 mmio = RENDER_HWS_PGA_GEN7;
1320 break;
1321 case BCS:
1322 mmio = BLT_HWS_PGA_GEN7;
1323 break;
1324 /*
1325 * VCS2 actually doesn't exist on Gen7. Only shut up
1326 * gcc switch check warning
1327 */
1328 case VCS2:
1329 case VCS:
1330 mmio = BSD_HWS_PGA_GEN7;
1331 break;
1332 case VECS:
1333 mmio = VEBOX_HWS_PGA_GEN7;
1334 break;
1335 }
1336 } else if (IS_GEN6(ring->dev)) {
1337 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1338 } else {
1339 /* XXX: gen8 returns to sanity */
1340 mmio = RING_HWS_PGA(ring->mmio_base);
1341 }
1342
1343 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1344 POSTING_READ(mmio);
1345
1346 /*
1347 * Flush the TLB for this page
1348 *
1349 * FIXME: These two bits have disappeared on gen8, so a question
1350 * arises: do we still need this and if so how should we go about
1351 * invalidating the TLB?
1352 */
1353 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1354 u32 reg = RING_INSTPM(ring->mmio_base);
1355
1356 /* ring should be idle before issuing a sync flush*/
1357 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1358
1359 I915_WRITE(reg,
1360 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1361 INSTPM_SYNC_FLUSH));
1362 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1363 1000))
1364 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1365 ring->name);
1366 }
1367 }
1368
1369 static int
1370 bsd_ring_flush(struct intel_engine_cs *ring,
1371 u32 invalidate_domains,
1372 u32 flush_domains)
1373 {
1374 int ret;
1375
1376 ret = intel_ring_begin(ring, 2);
1377 if (ret)
1378 return ret;
1379
1380 intel_ring_emit(ring, MI_FLUSH);
1381 intel_ring_emit(ring, MI_NOOP);
1382 intel_ring_advance(ring);
1383 return 0;
1384 }
1385
1386 static int
1387 i9xx_add_request(struct intel_engine_cs *ring)
1388 {
1389 int ret;
1390
1391 ret = intel_ring_begin(ring, 4);
1392 if (ret)
1393 return ret;
1394
1395 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1396 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1397 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1398 intel_ring_emit(ring, MI_USER_INTERRUPT);
1399 __intel_ring_advance(ring);
1400
1401 return 0;
1402 }
1403
1404 static bool
1405 gen6_ring_get_irq(struct intel_engine_cs *ring)
1406 {
1407 struct drm_device *dev = ring->dev;
1408 struct drm_i915_private *dev_priv = dev->dev_private;
1409 unsigned long flags;
1410
1411 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1412 return false;
1413
1414 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1415 if (ring->irq_refcount++ == 0) {
1416 if (HAS_L3_DPF(dev) && ring->id == RCS)
1417 I915_WRITE_IMR(ring,
1418 ~(ring->irq_enable_mask |
1419 GT_PARITY_ERROR(dev)));
1420 else
1421 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1422 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1423 }
1424 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1425
1426 return true;
1427 }
1428
1429 static void
1430 gen6_ring_put_irq(struct intel_engine_cs *ring)
1431 {
1432 struct drm_device *dev = ring->dev;
1433 struct drm_i915_private *dev_priv = dev->dev_private;
1434 unsigned long flags;
1435
1436 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1437 if (--ring->irq_refcount == 0) {
1438 if (HAS_L3_DPF(dev) && ring->id == RCS)
1439 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1440 else
1441 I915_WRITE_IMR(ring, ~0);
1442 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1443 }
1444 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1445 }
1446
1447 static bool
1448 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1449 {
1450 struct drm_device *dev = ring->dev;
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452 unsigned long flags;
1453
1454 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1455 return false;
1456
1457 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1458 if (ring->irq_refcount++ == 0) {
1459 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1460 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1461 }
1462 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1463
1464 return true;
1465 }
1466
1467 static void
1468 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1469 {
1470 struct drm_device *dev = ring->dev;
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 unsigned long flags;
1473
1474 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1475 if (--ring->irq_refcount == 0) {
1476 I915_WRITE_IMR(ring, ~0);
1477 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1478 }
1479 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1480 }
1481
1482 static bool
1483 gen8_ring_get_irq(struct intel_engine_cs *ring)
1484 {
1485 struct drm_device *dev = ring->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 unsigned long flags;
1488
1489 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1490 return false;
1491
1492 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1493 if (ring->irq_refcount++ == 0) {
1494 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1495 I915_WRITE_IMR(ring,
1496 ~(ring->irq_enable_mask |
1497 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1498 } else {
1499 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1500 }
1501 POSTING_READ(RING_IMR(ring->mmio_base));
1502 }
1503 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1504
1505 return true;
1506 }
1507
1508 static void
1509 gen8_ring_put_irq(struct intel_engine_cs *ring)
1510 {
1511 struct drm_device *dev = ring->dev;
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1513 unsigned long flags;
1514
1515 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1516 if (--ring->irq_refcount == 0) {
1517 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1518 I915_WRITE_IMR(ring,
1519 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1520 } else {
1521 I915_WRITE_IMR(ring, ~0);
1522 }
1523 POSTING_READ(RING_IMR(ring->mmio_base));
1524 }
1525 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1526 }
1527
1528 static int
1529 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1530 u64 offset, u32 length,
1531 unsigned flags)
1532 {
1533 int ret;
1534
1535 ret = intel_ring_begin(ring, 2);
1536 if (ret)
1537 return ret;
1538
1539 intel_ring_emit(ring,
1540 MI_BATCH_BUFFER_START |
1541 MI_BATCH_GTT |
1542 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1543 intel_ring_emit(ring, offset);
1544 intel_ring_advance(ring);
1545
1546 return 0;
1547 }
1548
1549 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1550 #define I830_BATCH_LIMIT (256*1024)
1551 #define I830_TLB_ENTRIES (2)
1552 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1553 static int
1554 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1555 u64 offset, u32 len,
1556 unsigned flags)
1557 {
1558 u32 cs_offset = ring->scratch.gtt_offset;
1559 int ret;
1560
1561 ret = intel_ring_begin(ring, 6);
1562 if (ret)
1563 return ret;
1564
1565 /* Evict the invalid PTE TLBs */
1566 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1567 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1568 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1569 intel_ring_emit(ring, cs_offset);
1570 intel_ring_emit(ring, 0xdeadbeef);
1571 intel_ring_emit(ring, MI_NOOP);
1572 intel_ring_advance(ring);
1573
1574 if ((flags & I915_DISPATCH_PINNED) == 0) {
1575 if (len > I830_BATCH_LIMIT)
1576 return -ENOSPC;
1577
1578 ret = intel_ring_begin(ring, 6 + 2);
1579 if (ret)
1580 return ret;
1581
1582 /* Blit the batch (which has now all relocs applied) to the
1583 * stable batch scratch bo area (so that the CS never
1584 * stumbles over its tlb invalidation bug) ...
1585 */
1586 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1587 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1588 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1589 intel_ring_emit(ring, cs_offset);
1590 intel_ring_emit(ring, 4096);
1591 intel_ring_emit(ring, offset);
1592
1593 intel_ring_emit(ring, MI_FLUSH);
1594 intel_ring_emit(ring, MI_NOOP);
1595 intel_ring_advance(ring);
1596
1597 /* ... and execute it. */
1598 offset = cs_offset;
1599 }
1600
1601 ret = intel_ring_begin(ring, 4);
1602 if (ret)
1603 return ret;
1604
1605 intel_ring_emit(ring, MI_BATCH_BUFFER);
1606 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1607 intel_ring_emit(ring, offset + len - 8);
1608 intel_ring_emit(ring, MI_NOOP);
1609 intel_ring_advance(ring);
1610
1611 return 0;
1612 }
1613
1614 static int
1615 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1616 u64 offset, u32 len,
1617 unsigned flags)
1618 {
1619 int ret;
1620
1621 ret = intel_ring_begin(ring, 2);
1622 if (ret)
1623 return ret;
1624
1625 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1626 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1627 intel_ring_advance(ring);
1628
1629 return 0;
1630 }
1631
1632 static void cleanup_status_page(struct intel_engine_cs *ring)
1633 {
1634 struct drm_i915_gem_object *obj;
1635
1636 obj = ring->status_page.obj;
1637 if (obj == NULL)
1638 return;
1639
1640 kunmap(sg_page(obj->pages->sgl));
1641 i915_gem_object_ggtt_unpin(obj);
1642 drm_gem_object_unreference(&obj->base);
1643 ring->status_page.obj = NULL;
1644 }
1645
1646 static int init_status_page(struct intel_engine_cs *ring)
1647 {
1648 struct drm_i915_gem_object *obj;
1649
1650 if ((obj = ring->status_page.obj) == NULL) {
1651 unsigned flags;
1652 int ret;
1653
1654 obj = i915_gem_alloc_object(ring->dev, 4096);
1655 if (obj == NULL) {
1656 DRM_ERROR("Failed to allocate status page\n");
1657 return -ENOMEM;
1658 }
1659
1660 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1661 if (ret)
1662 goto err_unref;
1663
1664 flags = 0;
1665 if (!HAS_LLC(ring->dev))
1666 /* On g33, we cannot place HWS above 256MiB, so
1667 * restrict its pinning to the low mappable arena.
1668 * Though this restriction is not documented for
1669 * gen4, gen5, or byt, they also behave similarly
1670 * and hang if the HWS is placed at the top of the
1671 * GTT. To generalise, it appears that all !llc
1672 * platforms have issues with us placing the HWS
1673 * above the mappable region (even though we never
1674 * actualy map it).
1675 */
1676 flags |= PIN_MAPPABLE;
1677 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1678 if (ret) {
1679 err_unref:
1680 drm_gem_object_unreference(&obj->base);
1681 return ret;
1682 }
1683
1684 ring->status_page.obj = obj;
1685 }
1686
1687 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1688 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1689 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1690
1691 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1692 ring->name, ring->status_page.gfx_addr);
1693
1694 return 0;
1695 }
1696
1697 static int init_phys_status_page(struct intel_engine_cs *ring)
1698 {
1699 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1700
1701 if (!dev_priv->status_page_dmah) {
1702 dev_priv->status_page_dmah =
1703 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1704 if (!dev_priv->status_page_dmah)
1705 return -ENOMEM;
1706 }
1707
1708 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1709 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1710
1711 return 0;
1712 }
1713
1714 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1715 {
1716 if (!ringbuf->obj)
1717 return;
1718
1719 iounmap(ringbuf->virtual_start);
1720 i915_gem_object_ggtt_unpin(ringbuf->obj);
1721 drm_gem_object_unreference(&ringbuf->obj->base);
1722 ringbuf->obj = NULL;
1723 }
1724
1725 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1726 struct intel_ringbuffer *ringbuf)
1727 {
1728 struct drm_i915_private *dev_priv = to_i915(dev);
1729 struct drm_i915_gem_object *obj;
1730 int ret;
1731
1732 if (ringbuf->obj)
1733 return 0;
1734
1735 obj = NULL;
1736 if (!HAS_LLC(dev))
1737 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1738 if (obj == NULL)
1739 obj = i915_gem_alloc_object(dev, ringbuf->size);
1740 if (obj == NULL)
1741 return -ENOMEM;
1742
1743 /* mark ring buffers as read-only from GPU side by default */
1744 obj->gt_ro = 1;
1745
1746 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1747 if (ret)
1748 goto err_unref;
1749
1750 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1751 if (ret)
1752 goto err_unpin;
1753
1754 ringbuf->virtual_start =
1755 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1756 ringbuf->size);
1757 if (ringbuf->virtual_start == NULL) {
1758 ret = -EINVAL;
1759 goto err_unpin;
1760 }
1761
1762 ringbuf->obj = obj;
1763 return 0;
1764
1765 err_unpin:
1766 i915_gem_object_ggtt_unpin(obj);
1767 err_unref:
1768 drm_gem_object_unreference(&obj->base);
1769 return ret;
1770 }
1771
1772 static int intel_init_ring_buffer(struct drm_device *dev,
1773 struct intel_engine_cs *ring)
1774 {
1775 struct intel_ringbuffer *ringbuf = ring->buffer;
1776 int ret;
1777
1778 if (ringbuf == NULL) {
1779 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1780 if (!ringbuf)
1781 return -ENOMEM;
1782 ring->buffer = ringbuf;
1783 }
1784
1785 ring->dev = dev;
1786 INIT_LIST_HEAD(&ring->active_list);
1787 INIT_LIST_HEAD(&ring->request_list);
1788 INIT_LIST_HEAD(&ring->execlist_queue);
1789 ringbuf->size = 32 * PAGE_SIZE;
1790 ringbuf->ring = ring;
1791 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1792
1793 init_waitqueue_head(&ring->irq_queue);
1794
1795 if (I915_NEED_GFX_HWS(dev)) {
1796 ret = init_status_page(ring);
1797 if (ret)
1798 goto error;
1799 } else {
1800 BUG_ON(ring->id != RCS);
1801 ret = init_phys_status_page(ring);
1802 if (ret)
1803 goto error;
1804 }
1805
1806 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1807 if (ret) {
1808 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1809 goto error;
1810 }
1811
1812 /* Workaround an erratum on the i830 which causes a hang if
1813 * the TAIL pointer points to within the last 2 cachelines
1814 * of the buffer.
1815 */
1816 ringbuf->effective_size = ringbuf->size;
1817 if (IS_I830(dev) || IS_845G(dev))
1818 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1819
1820 ret = i915_cmd_parser_init_ring(ring);
1821 if (ret)
1822 goto error;
1823
1824 ret = ring->init(ring);
1825 if (ret)
1826 goto error;
1827
1828 return 0;
1829
1830 error:
1831 kfree(ringbuf);
1832 ring->buffer = NULL;
1833 return ret;
1834 }
1835
1836 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1837 {
1838 struct drm_i915_private *dev_priv;
1839 struct intel_ringbuffer *ringbuf;
1840
1841 if (!intel_ring_initialized(ring))
1842 return;
1843
1844 dev_priv = to_i915(ring->dev);
1845 ringbuf = ring->buffer;
1846
1847 intel_stop_ring_buffer(ring);
1848 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1849
1850 intel_destroy_ringbuffer_obj(ringbuf);
1851 ring->preallocated_lazy_request = NULL;
1852 ring->outstanding_lazy_seqno = 0;
1853
1854 if (ring->cleanup)
1855 ring->cleanup(ring);
1856
1857 cleanup_status_page(ring);
1858
1859 i915_cmd_parser_fini_ring(ring);
1860
1861 kfree(ringbuf);
1862 ring->buffer = NULL;
1863 }
1864
1865 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1866 {
1867 struct intel_ringbuffer *ringbuf = ring->buffer;
1868 struct drm_i915_gem_request *request;
1869 u32 seqno = 0;
1870 int ret;
1871
1872 if (ringbuf->last_retired_head != -1) {
1873 ringbuf->head = ringbuf->last_retired_head;
1874 ringbuf->last_retired_head = -1;
1875
1876 ringbuf->space = intel_ring_space(ringbuf);
1877 if (ringbuf->space >= n)
1878 return 0;
1879 }
1880
1881 list_for_each_entry(request, &ring->request_list, list) {
1882 if (__intel_ring_space(request->tail, ringbuf->tail,
1883 ringbuf->size) >= n) {
1884 seqno = request->seqno;
1885 break;
1886 }
1887 }
1888
1889 if (seqno == 0)
1890 return -ENOSPC;
1891
1892 ret = i915_wait_seqno(ring, seqno);
1893 if (ret)
1894 return ret;
1895
1896 i915_gem_retire_requests_ring(ring);
1897 ringbuf->head = ringbuf->last_retired_head;
1898 ringbuf->last_retired_head = -1;
1899
1900 ringbuf->space = intel_ring_space(ringbuf);
1901 return 0;
1902 }
1903
1904 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1905 {
1906 struct drm_device *dev = ring->dev;
1907 struct drm_i915_private *dev_priv = dev->dev_private;
1908 struct intel_ringbuffer *ringbuf = ring->buffer;
1909 unsigned long end;
1910 int ret;
1911
1912 ret = intel_ring_wait_request(ring, n);
1913 if (ret != -ENOSPC)
1914 return ret;
1915
1916 /* force the tail write in case we have been skipping them */
1917 __intel_ring_advance(ring);
1918
1919 /* With GEM the hangcheck timer should kick us out of the loop,
1920 * leaving it early runs the risk of corrupting GEM state (due
1921 * to running on almost untested codepaths). But on resume
1922 * timers don't work yet, so prevent a complete hang in that
1923 * case by choosing an insanely large timeout. */
1924 end = jiffies + 60 * HZ;
1925
1926 trace_i915_ring_wait_begin(ring);
1927 do {
1928 ringbuf->head = I915_READ_HEAD(ring);
1929 ringbuf->space = intel_ring_space(ringbuf);
1930 if (ringbuf->space >= n) {
1931 ret = 0;
1932 break;
1933 }
1934
1935 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1936 dev->primary->master) {
1937 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1938 if (master_priv->sarea_priv)
1939 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1940 }
1941
1942 msleep(1);
1943
1944 if (dev_priv->mm.interruptible && signal_pending(current)) {
1945 ret = -ERESTARTSYS;
1946 break;
1947 }
1948
1949 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1950 dev_priv->mm.interruptible);
1951 if (ret)
1952 break;
1953
1954 if (time_after(jiffies, end)) {
1955 ret = -EBUSY;
1956 break;
1957 }
1958 } while (1);
1959 trace_i915_ring_wait_end(ring);
1960 return ret;
1961 }
1962
1963 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1964 {
1965 uint32_t __iomem *virt;
1966 struct intel_ringbuffer *ringbuf = ring->buffer;
1967 int rem = ringbuf->size - ringbuf->tail;
1968
1969 if (ringbuf->space < rem) {
1970 int ret = ring_wait_for_space(ring, rem);
1971 if (ret)
1972 return ret;
1973 }
1974
1975 virt = ringbuf->virtual_start + ringbuf->tail;
1976 rem /= 4;
1977 while (rem--)
1978 iowrite32(MI_NOOP, virt++);
1979
1980 ringbuf->tail = 0;
1981 ringbuf->space = intel_ring_space(ringbuf);
1982
1983 return 0;
1984 }
1985
1986 int intel_ring_idle(struct intel_engine_cs *ring)
1987 {
1988 u32 seqno;
1989 int ret;
1990
1991 /* We need to add any requests required to flush the objects and ring */
1992 if (ring->outstanding_lazy_seqno) {
1993 ret = i915_add_request(ring, NULL);
1994 if (ret)
1995 return ret;
1996 }
1997
1998 /* Wait upon the last request to be completed */
1999 if (list_empty(&ring->request_list))
2000 return 0;
2001
2002 seqno = list_entry(ring->request_list.prev,
2003 struct drm_i915_gem_request,
2004 list)->seqno;
2005
2006 return i915_wait_seqno(ring, seqno);
2007 }
2008
2009 static int
2010 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
2011 {
2012 if (ring->outstanding_lazy_seqno)
2013 return 0;
2014
2015 if (ring->preallocated_lazy_request == NULL) {
2016 struct drm_i915_gem_request *request;
2017
2018 request = kmalloc(sizeof(*request), GFP_KERNEL);
2019 if (request == NULL)
2020 return -ENOMEM;
2021
2022 ring->preallocated_lazy_request = request;
2023 }
2024
2025 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
2026 }
2027
2028 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2029 int bytes)
2030 {
2031 struct intel_ringbuffer *ringbuf = ring->buffer;
2032 int ret;
2033
2034 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2035 ret = intel_wrap_ring_buffer(ring);
2036 if (unlikely(ret))
2037 return ret;
2038 }
2039
2040 if (unlikely(ringbuf->space < bytes)) {
2041 ret = ring_wait_for_space(ring, bytes);
2042 if (unlikely(ret))
2043 return ret;
2044 }
2045
2046 return 0;
2047 }
2048
2049 int intel_ring_begin(struct intel_engine_cs *ring,
2050 int num_dwords)
2051 {
2052 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2053 int ret;
2054
2055 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2056 dev_priv->mm.interruptible);
2057 if (ret)
2058 return ret;
2059
2060 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2061 if (ret)
2062 return ret;
2063
2064 /* Preallocate the olr before touching the ring */
2065 ret = intel_ring_alloc_seqno(ring);
2066 if (ret)
2067 return ret;
2068
2069 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2070 return 0;
2071 }
2072
2073 /* Align the ring tail to a cacheline boundary */
2074 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2075 {
2076 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2077 int ret;
2078
2079 if (num_dwords == 0)
2080 return 0;
2081
2082 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2083 ret = intel_ring_begin(ring, num_dwords);
2084 if (ret)
2085 return ret;
2086
2087 while (num_dwords--)
2088 intel_ring_emit(ring, MI_NOOP);
2089
2090 intel_ring_advance(ring);
2091
2092 return 0;
2093 }
2094
2095 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2096 {
2097 struct drm_device *dev = ring->dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099
2100 BUG_ON(ring->outstanding_lazy_seqno);
2101
2102 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2103 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2104 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2105 if (HAS_VEBOX(dev))
2106 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2107 }
2108
2109 ring->set_seqno(ring, seqno);
2110 ring->hangcheck.seqno = seqno;
2111 }
2112
2113 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2114 u32 value)
2115 {
2116 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2117
2118 /* Every tail move must follow the sequence below */
2119
2120 /* Disable notification that the ring is IDLE. The GT
2121 * will then assume that it is busy and bring it out of rc6.
2122 */
2123 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2124 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2125
2126 /* Clear the context id. Here be magic! */
2127 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2128
2129 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2130 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2131 GEN6_BSD_SLEEP_INDICATOR) == 0,
2132 50))
2133 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2134
2135 /* Now that the ring is fully powered up, update the tail */
2136 I915_WRITE_TAIL(ring, value);
2137 POSTING_READ(RING_TAIL(ring->mmio_base));
2138
2139 /* Let the ring send IDLE messages to the GT again,
2140 * and so let it sleep to conserve power when idle.
2141 */
2142 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2143 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2144 }
2145
2146 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2147 u32 invalidate, u32 flush)
2148 {
2149 uint32_t cmd;
2150 int ret;
2151
2152 ret = intel_ring_begin(ring, 4);
2153 if (ret)
2154 return ret;
2155
2156 cmd = MI_FLUSH_DW;
2157 if (INTEL_INFO(ring->dev)->gen >= 8)
2158 cmd += 1;
2159 /*
2160 * Bspec vol 1c.5 - video engine command streamer:
2161 * "If ENABLED, all TLBs will be invalidated once the flush
2162 * operation is complete. This bit is only valid when the
2163 * Post-Sync Operation field is a value of 1h or 3h."
2164 */
2165 if (invalidate & I915_GEM_GPU_DOMAINS)
2166 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2167 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2168 intel_ring_emit(ring, cmd);
2169 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2170 if (INTEL_INFO(ring->dev)->gen >= 8) {
2171 intel_ring_emit(ring, 0); /* upper addr */
2172 intel_ring_emit(ring, 0); /* value */
2173 } else {
2174 intel_ring_emit(ring, 0);
2175 intel_ring_emit(ring, MI_NOOP);
2176 }
2177 intel_ring_advance(ring);
2178 return 0;
2179 }
2180
2181 static int
2182 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2183 u64 offset, u32 len,
2184 unsigned flags)
2185 {
2186 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2187 int ret;
2188
2189 ret = intel_ring_begin(ring, 4);
2190 if (ret)
2191 return ret;
2192
2193 /* FIXME(BDW): Address space and security selectors. */
2194 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2195 intel_ring_emit(ring, lower_32_bits(offset));
2196 intel_ring_emit(ring, upper_32_bits(offset));
2197 intel_ring_emit(ring, MI_NOOP);
2198 intel_ring_advance(ring);
2199
2200 return 0;
2201 }
2202
2203 static int
2204 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2205 u64 offset, u32 len,
2206 unsigned flags)
2207 {
2208 int ret;
2209
2210 ret = intel_ring_begin(ring, 2);
2211 if (ret)
2212 return ret;
2213
2214 intel_ring_emit(ring,
2215 MI_BATCH_BUFFER_START |
2216 (flags & I915_DISPATCH_SECURE ?
2217 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2218 /* bit0-7 is the length on GEN6+ */
2219 intel_ring_emit(ring, offset);
2220 intel_ring_advance(ring);
2221
2222 return 0;
2223 }
2224
2225 static int
2226 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2227 u64 offset, u32 len,
2228 unsigned flags)
2229 {
2230 int ret;
2231
2232 ret = intel_ring_begin(ring, 2);
2233 if (ret)
2234 return ret;
2235
2236 intel_ring_emit(ring,
2237 MI_BATCH_BUFFER_START |
2238 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2239 /* bit0-7 is the length on GEN6+ */
2240 intel_ring_emit(ring, offset);
2241 intel_ring_advance(ring);
2242
2243 return 0;
2244 }
2245
2246 /* Blitter support (SandyBridge+) */
2247
2248 static int gen6_ring_flush(struct intel_engine_cs *ring,
2249 u32 invalidate, u32 flush)
2250 {
2251 struct drm_device *dev = ring->dev;
2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 uint32_t cmd;
2254 int ret;
2255
2256 ret = intel_ring_begin(ring, 4);
2257 if (ret)
2258 return ret;
2259
2260 cmd = MI_FLUSH_DW;
2261 if (INTEL_INFO(ring->dev)->gen >= 8)
2262 cmd += 1;
2263 /*
2264 * Bspec vol 1c.3 - blitter engine command streamer:
2265 * "If ENABLED, all TLBs will be invalidated once the flush
2266 * operation is complete. This bit is only valid when the
2267 * Post-Sync Operation field is a value of 1h or 3h."
2268 */
2269 if (invalidate & I915_GEM_DOMAIN_RENDER)
2270 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2271 MI_FLUSH_DW_OP_STOREDW;
2272 intel_ring_emit(ring, cmd);
2273 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2274 if (INTEL_INFO(ring->dev)->gen >= 8) {
2275 intel_ring_emit(ring, 0); /* upper addr */
2276 intel_ring_emit(ring, 0); /* value */
2277 } else {
2278 intel_ring_emit(ring, 0);
2279 intel_ring_emit(ring, MI_NOOP);
2280 }
2281 intel_ring_advance(ring);
2282
2283 if (!invalidate && flush) {
2284 if (IS_GEN7(dev))
2285 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2286 else if (IS_BROADWELL(dev))
2287 dev_priv->fbc.need_sw_cache_clean = true;
2288 }
2289
2290 return 0;
2291 }
2292
2293 int intel_init_render_ring_buffer(struct drm_device *dev)
2294 {
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2297 struct drm_i915_gem_object *obj;
2298 int ret;
2299
2300 ring->name = "render ring";
2301 ring->id = RCS;
2302 ring->mmio_base = RENDER_RING_BASE;
2303
2304 if (INTEL_INFO(dev)->gen >= 8) {
2305 if (i915_semaphore_is_enabled(dev)) {
2306 obj = i915_gem_alloc_object(dev, 4096);
2307 if (obj == NULL) {
2308 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2309 i915.semaphores = 0;
2310 } else {
2311 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2312 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2313 if (ret != 0) {
2314 drm_gem_object_unreference(&obj->base);
2315 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2316 i915.semaphores = 0;
2317 } else
2318 dev_priv->semaphore_obj = obj;
2319 }
2320 }
2321
2322 ring->init_context = intel_ring_workarounds_emit;
2323 ring->add_request = gen6_add_request;
2324 ring->flush = gen8_render_ring_flush;
2325 ring->irq_get = gen8_ring_get_irq;
2326 ring->irq_put = gen8_ring_put_irq;
2327 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2328 ring->get_seqno = gen6_ring_get_seqno;
2329 ring->set_seqno = ring_set_seqno;
2330 if (i915_semaphore_is_enabled(dev)) {
2331 WARN_ON(!dev_priv->semaphore_obj);
2332 ring->semaphore.sync_to = gen8_ring_sync;
2333 ring->semaphore.signal = gen8_rcs_signal;
2334 GEN8_RING_SEMAPHORE_INIT;
2335 }
2336 } else if (INTEL_INFO(dev)->gen >= 6) {
2337 ring->add_request = gen6_add_request;
2338 ring->flush = gen7_render_ring_flush;
2339 if (INTEL_INFO(dev)->gen == 6)
2340 ring->flush = gen6_render_ring_flush;
2341 ring->irq_get = gen6_ring_get_irq;
2342 ring->irq_put = gen6_ring_put_irq;
2343 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2344 ring->get_seqno = gen6_ring_get_seqno;
2345 ring->set_seqno = ring_set_seqno;
2346 if (i915_semaphore_is_enabled(dev)) {
2347 ring->semaphore.sync_to = gen6_ring_sync;
2348 ring->semaphore.signal = gen6_signal;
2349 /*
2350 * The current semaphore is only applied on pre-gen8
2351 * platform. And there is no VCS2 ring on the pre-gen8
2352 * platform. So the semaphore between RCS and VCS2 is
2353 * initialized as INVALID. Gen8 will initialize the
2354 * sema between VCS2 and RCS later.
2355 */
2356 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2357 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2358 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2359 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2360 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2361 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2362 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2363 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2364 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2365 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2366 }
2367 } else if (IS_GEN5(dev)) {
2368 ring->add_request = pc_render_add_request;
2369 ring->flush = gen4_render_ring_flush;
2370 ring->get_seqno = pc_render_get_seqno;
2371 ring->set_seqno = pc_render_set_seqno;
2372 ring->irq_get = gen5_ring_get_irq;
2373 ring->irq_put = gen5_ring_put_irq;
2374 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2375 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2376 } else {
2377 ring->add_request = i9xx_add_request;
2378 if (INTEL_INFO(dev)->gen < 4)
2379 ring->flush = gen2_render_ring_flush;
2380 else
2381 ring->flush = gen4_render_ring_flush;
2382 ring->get_seqno = ring_get_seqno;
2383 ring->set_seqno = ring_set_seqno;
2384 if (IS_GEN2(dev)) {
2385 ring->irq_get = i8xx_ring_get_irq;
2386 ring->irq_put = i8xx_ring_put_irq;
2387 } else {
2388 ring->irq_get = i9xx_ring_get_irq;
2389 ring->irq_put = i9xx_ring_put_irq;
2390 }
2391 ring->irq_enable_mask = I915_USER_INTERRUPT;
2392 }
2393 ring->write_tail = ring_write_tail;
2394
2395 if (IS_HASWELL(dev))
2396 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2397 else if (IS_GEN8(dev))
2398 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2399 else if (INTEL_INFO(dev)->gen >= 6)
2400 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2401 else if (INTEL_INFO(dev)->gen >= 4)
2402 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2403 else if (IS_I830(dev) || IS_845G(dev))
2404 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2405 else
2406 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2407 ring->init = init_render_ring;
2408 ring->cleanup = render_ring_cleanup;
2409
2410 /* Workaround batchbuffer to combat CS tlb bug. */
2411 if (HAS_BROKEN_CS_TLB(dev)) {
2412 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2413 if (obj == NULL) {
2414 DRM_ERROR("Failed to allocate batch bo\n");
2415 return -ENOMEM;
2416 }
2417
2418 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2419 if (ret != 0) {
2420 drm_gem_object_unreference(&obj->base);
2421 DRM_ERROR("Failed to ping batch bo\n");
2422 return ret;
2423 }
2424
2425 ring->scratch.obj = obj;
2426 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2427 }
2428
2429 return intel_init_ring_buffer(dev, ring);
2430 }
2431
2432 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2433 {
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2436 struct intel_ringbuffer *ringbuf = ring->buffer;
2437 int ret;
2438
2439 if (ringbuf == NULL) {
2440 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2441 if (!ringbuf)
2442 return -ENOMEM;
2443 ring->buffer = ringbuf;
2444 }
2445
2446 ring->name = "render ring";
2447 ring->id = RCS;
2448 ring->mmio_base = RENDER_RING_BASE;
2449
2450 if (INTEL_INFO(dev)->gen >= 6) {
2451 /* non-kms not supported on gen6+ */
2452 ret = -ENODEV;
2453 goto err_ringbuf;
2454 }
2455
2456 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2457 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2458 * the special gen5 functions. */
2459 ring->add_request = i9xx_add_request;
2460 if (INTEL_INFO(dev)->gen < 4)
2461 ring->flush = gen2_render_ring_flush;
2462 else
2463 ring->flush = gen4_render_ring_flush;
2464 ring->get_seqno = ring_get_seqno;
2465 ring->set_seqno = ring_set_seqno;
2466 if (IS_GEN2(dev)) {
2467 ring->irq_get = i8xx_ring_get_irq;
2468 ring->irq_put = i8xx_ring_put_irq;
2469 } else {
2470 ring->irq_get = i9xx_ring_get_irq;
2471 ring->irq_put = i9xx_ring_put_irq;
2472 }
2473 ring->irq_enable_mask = I915_USER_INTERRUPT;
2474 ring->write_tail = ring_write_tail;
2475 if (INTEL_INFO(dev)->gen >= 4)
2476 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2477 else if (IS_I830(dev) || IS_845G(dev))
2478 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2479 else
2480 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2481 ring->init = init_render_ring;
2482 ring->cleanup = render_ring_cleanup;
2483
2484 ring->dev = dev;
2485 INIT_LIST_HEAD(&ring->active_list);
2486 INIT_LIST_HEAD(&ring->request_list);
2487
2488 ringbuf->size = size;
2489 ringbuf->effective_size = ringbuf->size;
2490 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2491 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2492
2493 ringbuf->virtual_start = ioremap_wc(start, size);
2494 if (ringbuf->virtual_start == NULL) {
2495 DRM_ERROR("can not ioremap virtual address for"
2496 " ring buffer\n");
2497 ret = -ENOMEM;
2498 goto err_ringbuf;
2499 }
2500
2501 if (!I915_NEED_GFX_HWS(dev)) {
2502 ret = init_phys_status_page(ring);
2503 if (ret)
2504 goto err_vstart;
2505 }
2506
2507 return 0;
2508
2509 err_vstart:
2510 iounmap(ringbuf->virtual_start);
2511 err_ringbuf:
2512 kfree(ringbuf);
2513 ring->buffer = NULL;
2514 return ret;
2515 }
2516
2517 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2518 {
2519 struct drm_i915_private *dev_priv = dev->dev_private;
2520 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2521
2522 ring->name = "bsd ring";
2523 ring->id = VCS;
2524
2525 ring->write_tail = ring_write_tail;
2526 if (INTEL_INFO(dev)->gen >= 6) {
2527 ring->mmio_base = GEN6_BSD_RING_BASE;
2528 /* gen6 bsd needs a special wa for tail updates */
2529 if (IS_GEN6(dev))
2530 ring->write_tail = gen6_bsd_ring_write_tail;
2531 ring->flush = gen6_bsd_ring_flush;
2532 ring->add_request = gen6_add_request;
2533 ring->get_seqno = gen6_ring_get_seqno;
2534 ring->set_seqno = ring_set_seqno;
2535 if (INTEL_INFO(dev)->gen >= 8) {
2536 ring->irq_enable_mask =
2537 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2538 ring->irq_get = gen8_ring_get_irq;
2539 ring->irq_put = gen8_ring_put_irq;
2540 ring->dispatch_execbuffer =
2541 gen8_ring_dispatch_execbuffer;
2542 if (i915_semaphore_is_enabled(dev)) {
2543 ring->semaphore.sync_to = gen8_ring_sync;
2544 ring->semaphore.signal = gen8_xcs_signal;
2545 GEN8_RING_SEMAPHORE_INIT;
2546 }
2547 } else {
2548 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2549 ring->irq_get = gen6_ring_get_irq;
2550 ring->irq_put = gen6_ring_put_irq;
2551 ring->dispatch_execbuffer =
2552 gen6_ring_dispatch_execbuffer;
2553 if (i915_semaphore_is_enabled(dev)) {
2554 ring->semaphore.sync_to = gen6_ring_sync;
2555 ring->semaphore.signal = gen6_signal;
2556 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2557 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2558 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2559 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2560 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2561 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2562 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2563 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2564 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2565 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2566 }
2567 }
2568 } else {
2569 ring->mmio_base = BSD_RING_BASE;
2570 ring->flush = bsd_ring_flush;
2571 ring->add_request = i9xx_add_request;
2572 ring->get_seqno = ring_get_seqno;
2573 ring->set_seqno = ring_set_seqno;
2574 if (IS_GEN5(dev)) {
2575 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2576 ring->irq_get = gen5_ring_get_irq;
2577 ring->irq_put = gen5_ring_put_irq;
2578 } else {
2579 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2580 ring->irq_get = i9xx_ring_get_irq;
2581 ring->irq_put = i9xx_ring_put_irq;
2582 }
2583 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2584 }
2585 ring->init = init_ring_common;
2586
2587 return intel_init_ring_buffer(dev, ring);
2588 }
2589
2590 /**
2591 * Initialize the second BSD ring for Broadwell GT3.
2592 * It is noted that this only exists on Broadwell GT3.
2593 */
2594 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2595 {
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2598
2599 if ((INTEL_INFO(dev)->gen != 8)) {
2600 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2601 return -EINVAL;
2602 }
2603
2604 ring->name = "bsd2 ring";
2605 ring->id = VCS2;
2606
2607 ring->write_tail = ring_write_tail;
2608 ring->mmio_base = GEN8_BSD2_RING_BASE;
2609 ring->flush = gen6_bsd_ring_flush;
2610 ring->add_request = gen6_add_request;
2611 ring->get_seqno = gen6_ring_get_seqno;
2612 ring->set_seqno = ring_set_seqno;
2613 ring->irq_enable_mask =
2614 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2615 ring->irq_get = gen8_ring_get_irq;
2616 ring->irq_put = gen8_ring_put_irq;
2617 ring->dispatch_execbuffer =
2618 gen8_ring_dispatch_execbuffer;
2619 if (i915_semaphore_is_enabled(dev)) {
2620 ring->semaphore.sync_to = gen8_ring_sync;
2621 ring->semaphore.signal = gen8_xcs_signal;
2622 GEN8_RING_SEMAPHORE_INIT;
2623 }
2624 ring->init = init_ring_common;
2625
2626 return intel_init_ring_buffer(dev, ring);
2627 }
2628
2629 int intel_init_blt_ring_buffer(struct drm_device *dev)
2630 {
2631 struct drm_i915_private *dev_priv = dev->dev_private;
2632 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2633
2634 ring->name = "blitter ring";
2635 ring->id = BCS;
2636
2637 ring->mmio_base = BLT_RING_BASE;
2638 ring->write_tail = ring_write_tail;
2639 ring->flush = gen6_ring_flush;
2640 ring->add_request = gen6_add_request;
2641 ring->get_seqno = gen6_ring_get_seqno;
2642 ring->set_seqno = ring_set_seqno;
2643 if (INTEL_INFO(dev)->gen >= 8) {
2644 ring->irq_enable_mask =
2645 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2646 ring->irq_get = gen8_ring_get_irq;
2647 ring->irq_put = gen8_ring_put_irq;
2648 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2649 if (i915_semaphore_is_enabled(dev)) {
2650 ring->semaphore.sync_to = gen8_ring_sync;
2651 ring->semaphore.signal = gen8_xcs_signal;
2652 GEN8_RING_SEMAPHORE_INIT;
2653 }
2654 } else {
2655 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2656 ring->irq_get = gen6_ring_get_irq;
2657 ring->irq_put = gen6_ring_put_irq;
2658 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2659 if (i915_semaphore_is_enabled(dev)) {
2660 ring->semaphore.signal = gen6_signal;
2661 ring->semaphore.sync_to = gen6_ring_sync;
2662 /*
2663 * The current semaphore is only applied on pre-gen8
2664 * platform. And there is no VCS2 ring on the pre-gen8
2665 * platform. So the semaphore between BCS and VCS2 is
2666 * initialized as INVALID. Gen8 will initialize the
2667 * sema between BCS and VCS2 later.
2668 */
2669 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2670 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2671 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2672 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2673 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2674 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2675 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2676 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2677 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2678 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2679 }
2680 }
2681 ring->init = init_ring_common;
2682
2683 return intel_init_ring_buffer(dev, ring);
2684 }
2685
2686 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2687 {
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2690
2691 ring->name = "video enhancement ring";
2692 ring->id = VECS;
2693
2694 ring->mmio_base = VEBOX_RING_BASE;
2695 ring->write_tail = ring_write_tail;
2696 ring->flush = gen6_ring_flush;
2697 ring->add_request = gen6_add_request;
2698 ring->get_seqno = gen6_ring_get_seqno;
2699 ring->set_seqno = ring_set_seqno;
2700
2701 if (INTEL_INFO(dev)->gen >= 8) {
2702 ring->irq_enable_mask =
2703 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2704 ring->irq_get = gen8_ring_get_irq;
2705 ring->irq_put = gen8_ring_put_irq;
2706 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2707 if (i915_semaphore_is_enabled(dev)) {
2708 ring->semaphore.sync_to = gen8_ring_sync;
2709 ring->semaphore.signal = gen8_xcs_signal;
2710 GEN8_RING_SEMAPHORE_INIT;
2711 }
2712 } else {
2713 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2714 ring->irq_get = hsw_vebox_get_irq;
2715 ring->irq_put = hsw_vebox_put_irq;
2716 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2717 if (i915_semaphore_is_enabled(dev)) {
2718 ring->semaphore.sync_to = gen6_ring_sync;
2719 ring->semaphore.signal = gen6_signal;
2720 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2721 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2722 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2723 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2724 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2725 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2726 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2727 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2728 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2729 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2730 }
2731 }
2732 ring->init = init_ring_common;
2733
2734 return intel_init_ring_buffer(dev, ring);
2735 }
2736
2737 int
2738 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2739 {
2740 int ret;
2741
2742 if (!ring->gpu_caches_dirty)
2743 return 0;
2744
2745 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2746 if (ret)
2747 return ret;
2748
2749 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2750
2751 ring->gpu_caches_dirty = false;
2752 return 0;
2753 }
2754
2755 int
2756 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2757 {
2758 uint32_t flush_domains;
2759 int ret;
2760
2761 flush_domains = 0;
2762 if (ring->gpu_caches_dirty)
2763 flush_domains = I915_GEM_GPU_DOMAINS;
2764
2765 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2766 if (ret)
2767 return ret;
2768
2769 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2770
2771 ring->gpu_caches_dirty = false;
2772 return 0;
2773 }
2774
2775 void
2776 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2777 {
2778 int ret;
2779
2780 if (!intel_ring_initialized(ring))
2781 return;
2782
2783 ret = intel_ring_idle(ring);
2784 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2785 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2786 ring->name, ret);
2787
2788 stop_ring(ring);
2789 }
Linux kernel - Deliverables
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