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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - tail;
56 if (space <= 0)
57 space += size;
58 return space - I915_RING_FREE_SPACE;
59 }
60
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62 {
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70 }
71
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
73 {
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
76 }
77
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
79 {
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82 }
83
84 void __intel_ring_advance(struct intel_engine_cs *ring)
85 {
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
89 return;
90 ring->write_tail(ring, ringbuf->tail);
91 }
92
93 static int
94 gen2_render_ring_flush(struct intel_engine_cs *ring,
95 u32 invalidate_domains,
96 u32 flush_domains)
97 {
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117 }
118
119 static int
120 gen4_render_ring_flush(struct intel_engine_cs *ring,
121 u32 invalidate_domains,
122 u32 flush_domains)
123 {
124 struct drm_device *dev = ring->dev;
125 u32 cmd;
126 int ret;
127
128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
158 cmd &= ~MI_NO_WRITE_FLUSH;
159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
161
162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
165
166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
169
170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
173
174 return 0;
175 }
176
177 /**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214 static int
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
216 {
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247 }
248
249 static int
250 gen6_render_ring_flush(struct intel_engine_cs *ring,
251 u32 invalidate_domains, u32 flush_domains)
252 {
253 u32 flags = 0;
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
255 int ret;
256
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
273 flags |= PIPE_CONTROL_CS_STALL;
274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
286 }
287
288 ret = intel_ring_begin(ring, 4);
289 if (ret)
290 return ret;
291
292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
295 intel_ring_emit(ring, 0);
296 intel_ring_advance(ring);
297
298 return 0;
299 }
300
301 static int
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
303 {
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318 }
319
320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
321 {
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
327 ret = intel_ring_begin(ring, 6);
328 if (ret)
329 return ret;
330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341 }
342
343 static int
344 gen7_render_ring_flush(struct intel_engine_cs *ring,
345 u32 invalidate_domains, u32 flush_domains)
346 {
347 u32 flags = 0;
348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
349 int ret;
350
351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
382
383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
397 intel_ring_emit(ring, scratch_addr);
398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
401 if (!invalidate_domains && flush_domains)
402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
404 return 0;
405 }
406
407 static int
408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410 {
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426 }
427
428 static int
429 gen8_render_ring_flush(struct intel_engine_cs *ring,
430 u32 invalidate_domains, u32 flush_domains)
431 {
432 u32 flags = 0;
433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
434 int ret;
435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
459 }
460
461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
469 }
470
471 static void ring_write_tail(struct intel_engine_cs *ring,
472 u32 value)
473 {
474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
475 I915_WRITE_TAIL(ring, value);
476 }
477
478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
479 {
480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
481 u64 acthd;
482
483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
492 }
493
494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
495 {
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503 }
504
505 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
506 {
507 struct drm_device *dev = ring->dev;
508 struct drm_i915_private *dev_priv = ring->dev->dev_private;
509 u32 mmio = 0;
510
511 /* The ring status page addresses are no longer next to the rest of
512 * the ring registers as of gen7.
513 */
514 if (IS_GEN7(dev)) {
515 switch (ring->id) {
516 case RCS:
517 mmio = RENDER_HWS_PGA_GEN7;
518 break;
519 case BCS:
520 mmio = BLT_HWS_PGA_GEN7;
521 break;
522 /*
523 * VCS2 actually doesn't exist on Gen7. Only shut up
524 * gcc switch check warning
525 */
526 case VCS2:
527 case VCS:
528 mmio = BSD_HWS_PGA_GEN7;
529 break;
530 case VECS:
531 mmio = VEBOX_HWS_PGA_GEN7;
532 break;
533 }
534 } else if (IS_GEN6(ring->dev)) {
535 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
536 } else {
537 /* XXX: gen8 returns to sanity */
538 mmio = RING_HWS_PGA(ring->mmio_base);
539 }
540
541 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
542 POSTING_READ(mmio);
543
544 /*
545 * Flush the TLB for this page
546 *
547 * FIXME: These two bits have disappeared on gen8, so a question
548 * arises: do we still need this and if so how should we go about
549 * invalidating the TLB?
550 */
551 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
552 u32 reg = RING_INSTPM(ring->mmio_base);
553
554 /* ring should be idle before issuing a sync flush*/
555 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
556
557 I915_WRITE(reg,
558 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
559 INSTPM_SYNC_FLUSH));
560 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
561 1000))
562 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
563 ring->name);
564 }
565 }
566
567 static bool stop_ring(struct intel_engine_cs *ring)
568 {
569 struct drm_i915_private *dev_priv = to_i915(ring->dev);
570
571 if (!IS_GEN2(ring->dev)) {
572 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
573 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
574 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
575 /* Sometimes we observe that the idle flag is not
576 * set even though the ring is empty. So double
577 * check before giving up.
578 */
579 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
580 return false;
581 }
582 }
583
584 I915_WRITE_CTL(ring, 0);
585 I915_WRITE_HEAD(ring, 0);
586 ring->write_tail(ring, 0);
587
588 if (!IS_GEN2(ring->dev)) {
589 (void)I915_READ_CTL(ring);
590 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
591 }
592
593 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
594 }
595
596 static int init_ring_common(struct intel_engine_cs *ring)
597 {
598 struct drm_device *dev = ring->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
600 struct intel_ringbuffer *ringbuf = ring->buffer;
601 struct drm_i915_gem_object *obj = ringbuf->obj;
602 int ret = 0;
603
604 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
605
606 if (!stop_ring(ring)) {
607 /* G45 ring initialization often fails to reset head to zero */
608 DRM_DEBUG_KMS("%s head not reset to zero "
609 "ctl %08x head %08x tail %08x start %08x\n",
610 ring->name,
611 I915_READ_CTL(ring),
612 I915_READ_HEAD(ring),
613 I915_READ_TAIL(ring),
614 I915_READ_START(ring));
615
616 if (!stop_ring(ring)) {
617 DRM_ERROR("failed to set %s head to zero "
618 "ctl %08x head %08x tail %08x start %08x\n",
619 ring->name,
620 I915_READ_CTL(ring),
621 I915_READ_HEAD(ring),
622 I915_READ_TAIL(ring),
623 I915_READ_START(ring));
624 ret = -EIO;
625 goto out;
626 }
627 }
628
629 if (I915_NEED_GFX_HWS(dev))
630 intel_ring_setup_status_page(ring);
631 else
632 ring_setup_phys_status_page(ring);
633
634 /* Enforce ordering by reading HEAD register back */
635 I915_READ_HEAD(ring);
636
637 /* Initialize the ring. This must happen _after_ we've cleared the ring
638 * registers with the above sequence (the readback of the HEAD registers
639 * also enforces ordering), otherwise the hw might lose the new ring
640 * register values. */
641 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
642
643 /* WaClearRingBufHeadRegAtInit:ctg,elk */
644 if (I915_READ_HEAD(ring))
645 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
646 ring->name, I915_READ_HEAD(ring));
647 I915_WRITE_HEAD(ring, 0);
648 (void)I915_READ_HEAD(ring);
649
650 I915_WRITE_CTL(ring,
651 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
652 | RING_VALID);
653
654 /* If the head is still not zero, the ring is dead */
655 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
656 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
657 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
658 DRM_ERROR("%s initialization failed "
659 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
660 ring->name,
661 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
662 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
663 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
664 ret = -EIO;
665 goto out;
666 }
667
668 ringbuf->last_retired_head = -1;
669 ringbuf->head = I915_READ_HEAD(ring);
670 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
671 intel_ring_update_space(ringbuf);
672
673 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
674
675 out:
676 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
677
678 return ret;
679 }
680
681 void
682 intel_fini_pipe_control(struct intel_engine_cs *ring)
683 {
684 struct drm_device *dev = ring->dev;
685
686 if (ring->scratch.obj == NULL)
687 return;
688
689 if (INTEL_INFO(dev)->gen >= 5) {
690 kunmap(sg_page(ring->scratch.obj->pages->sgl));
691 i915_gem_object_ggtt_unpin(ring->scratch.obj);
692 }
693
694 drm_gem_object_unreference(&ring->scratch.obj->base);
695 ring->scratch.obj = NULL;
696 }
697
698 int
699 intel_init_pipe_control(struct intel_engine_cs *ring)
700 {
701 int ret;
702
703 WARN_ON(ring->scratch.obj);
704
705 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
706 if (ring->scratch.obj == NULL) {
707 DRM_ERROR("Failed to allocate seqno page\n");
708 ret = -ENOMEM;
709 goto err;
710 }
711
712 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
713 if (ret)
714 goto err_unref;
715
716 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
717 if (ret)
718 goto err_unref;
719
720 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
721 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
722 if (ring->scratch.cpu_page == NULL) {
723 ret = -ENOMEM;
724 goto err_unpin;
725 }
726
727 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
728 ring->name, ring->scratch.gtt_offset);
729 return 0;
730
731 err_unpin:
732 i915_gem_object_ggtt_unpin(ring->scratch.obj);
733 err_unref:
734 drm_gem_object_unreference(&ring->scratch.obj->base);
735 err:
736 return ret;
737 }
738
739 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
740 struct intel_context *ctx)
741 {
742 int ret, i;
743 struct drm_device *dev = ring->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 struct i915_workarounds *w = &dev_priv->workarounds;
746
747 if (WARN_ON_ONCE(w->count == 0))
748 return 0;
749
750 ring->gpu_caches_dirty = true;
751 ret = intel_ring_flush_all_caches(ring);
752 if (ret)
753 return ret;
754
755 ret = intel_ring_begin(ring, (w->count * 2 + 2));
756 if (ret)
757 return ret;
758
759 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
760 for (i = 0; i < w->count; i++) {
761 intel_ring_emit(ring, w->reg[i].addr);
762 intel_ring_emit(ring, w->reg[i].value);
763 }
764 intel_ring_emit(ring, MI_NOOP);
765
766 intel_ring_advance(ring);
767
768 ring->gpu_caches_dirty = true;
769 ret = intel_ring_flush_all_caches(ring);
770 if (ret)
771 return ret;
772
773 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
774
775 return 0;
776 }
777
778 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
779 struct intel_context *ctx)
780 {
781 int ret;
782
783 ret = intel_ring_workarounds_emit(ring, ctx);
784 if (ret != 0)
785 return ret;
786
787 ret = i915_gem_render_state_init(ring);
788 if (ret)
789 DRM_ERROR("init render state: %d\n", ret);
790
791 return ret;
792 }
793
794 static int wa_add(struct drm_i915_private *dev_priv,
795 const u32 addr, const u32 mask, const u32 val)
796 {
797 const u32 idx = dev_priv->workarounds.count;
798
799 if (WARN_ON(idx >= I915_MAX_WA_REGS))
800 return -ENOSPC;
801
802 dev_priv->workarounds.reg[idx].addr = addr;
803 dev_priv->workarounds.reg[idx].value = val;
804 dev_priv->workarounds.reg[idx].mask = mask;
805
806 dev_priv->workarounds.count++;
807
808 return 0;
809 }
810
811 #define WA_REG(addr, mask, val) { \
812 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
813 if (r) \
814 return r; \
815 }
816
817 #define WA_SET_BIT_MASKED(addr, mask) \
818 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
819
820 #define WA_CLR_BIT_MASKED(addr, mask) \
821 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
822
823 #define WA_SET_FIELD_MASKED(addr, mask, value) \
824 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
825
826 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
827 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
828
829 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
830
831 static int bdw_init_workarounds(struct intel_engine_cs *ring)
832 {
833 struct drm_device *dev = ring->dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
835
836 /* WaDisablePartialInstShootdown:bdw */
837 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
838 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
839 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
840 STALL_DOP_GATING_DISABLE);
841
842 /* WaDisableDopClockGating:bdw */
843 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
844 DOP_CLOCK_GATING_DISABLE);
845
846 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
847 GEN8_SAMPLER_POWER_BYPASS_DIS);
848
849 /* Use Force Non-Coherent whenever executing a 3D context. This is a
850 * workaround for for a possible hang in the unlikely event a TLB
851 * invalidation occurs during a PSD flush.
852 */
853 WA_SET_BIT_MASKED(HDC_CHICKEN0,
854 /* WaForceEnableNonCoherent:bdw */
855 HDC_FORCE_NON_COHERENT |
856 /* WaForceContextSaveRestoreNonCoherent:bdw */
857 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
858 /* WaHdcDisableFetchWhenMasked:bdw */
859 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
860 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
861 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
862
863 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
864 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
865 * polygons in the same 8x4 pixel/sample area to be processed without
866 * stalling waiting for the earlier ones to write to Hierarchical Z
867 * buffer."
868 *
869 * This optimization is off by default for Broadwell; turn it on.
870 */
871 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
872
873 /* Wa4x4STCOptimizationDisable:bdw */
874 WA_SET_BIT_MASKED(CACHE_MODE_1,
875 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
876
877 /*
878 * BSpec recommends 8x4 when MSAA is used,
879 * however in practice 16x4 seems fastest.
880 *
881 * Note that PS/WM thread counts depend on the WIZ hashing
882 * disable bit, which we don't touch here, but it's good
883 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
884 */
885 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
886 GEN6_WIZ_HASHING_MASK,
887 GEN6_WIZ_HASHING_16x4);
888
889 return 0;
890 }
891
892 static int chv_init_workarounds(struct intel_engine_cs *ring)
893 {
894 struct drm_device *dev = ring->dev;
895 struct drm_i915_private *dev_priv = dev->dev_private;
896
897 /* WaDisablePartialInstShootdown:chv */
898 /* WaDisableThreadStallDopClockGating:chv */
899 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
900 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
901 STALL_DOP_GATING_DISABLE);
902
903 /* Use Force Non-Coherent whenever executing a 3D context. This is a
904 * workaround for a possible hang in the unlikely event a TLB
905 * invalidation occurs during a PSD flush.
906 */
907 /* WaForceEnableNonCoherent:chv */
908 /* WaHdcDisableFetchWhenMasked:chv */
909 WA_SET_BIT_MASKED(HDC_CHICKEN0,
910 HDC_FORCE_NON_COHERENT |
911 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
912
913 /* According to the CACHE_MODE_0 default value documentation, some
914 * CHV platforms disable this optimization by default. Turn it on.
915 */
916 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
917
918 /* Wa4x4STCOptimizationDisable:chv */
919 WA_SET_BIT_MASKED(CACHE_MODE_1,
920 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
921
922 /* Improve HiZ throughput on CHV. */
923 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
924
925 /*
926 * BSpec recommends 8x4 when MSAA is used,
927 * however in practice 16x4 seems fastest.
928 *
929 * Note that PS/WM thread counts depend on the WIZ hashing
930 * disable bit, which we don't touch here, but it's good
931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
932 */
933 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
934 GEN6_WIZ_HASHING_MASK,
935 GEN6_WIZ_HASHING_16x4);
936
937 return 0;
938 }
939
940 static int gen9_init_workarounds(struct intel_engine_cs *ring)
941 {
942 struct drm_device *dev = ring->dev;
943 struct drm_i915_private *dev_priv = dev->dev_private;
944
945 /* WaDisablePartialInstShootdown:skl */
946 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
947 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
948
949 /* Syncing dependencies between camera and graphics */
950 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
951 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
952
953 if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
954 INTEL_REVID(dev) <= SKL_REVID_B0) {
955 /*
956 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
957 * This is a pre-production w/a.
958 */
959 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
960 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
961 ~GEN9_DG_MIRROR_FIX_ENABLE);
962 }
963
964 if (INTEL_REVID(dev) >= SKL_REVID_C0) {
965 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
966 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
967 GEN9_ENABLE_YV12_BUGFIX);
968 }
969
970 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
971 /*
972 *Use Force Non-Coherent whenever executing a 3D context. This
973 * is a workaround for a possible hang in the unlikely event
974 * a TLB invalidation occurs during a PSD flush.
975 */
976 /* WaForceEnableNonCoherent:skl */
977 WA_SET_BIT_MASKED(HDC_CHICKEN0,
978 HDC_FORCE_NON_COHERENT);
979 }
980
981 /* Wa4x4STCOptimizationDisable:skl */
982 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
983
984 /* WaDisablePartialResolveInVc:skl */
985 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
986
987 /* WaCcsTlbPrefetchDisable:skl */
988 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
989 GEN9_CCS_TLB_PREFETCH_ENABLE);
990
991 return 0;
992 }
993
994 static int skl_init_workarounds(struct intel_engine_cs *ring)
995 {
996 gen9_init_workarounds(ring);
997
998 return 0;
999 }
1000
1001 int init_workarounds_ring(struct intel_engine_cs *ring)
1002 {
1003 struct drm_device *dev = ring->dev;
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005
1006 WARN_ON(ring->id != RCS);
1007
1008 dev_priv->workarounds.count = 0;
1009
1010 if (IS_BROADWELL(dev))
1011 return bdw_init_workarounds(ring);
1012
1013 if (IS_CHERRYVIEW(dev))
1014 return chv_init_workarounds(ring);
1015
1016 if (IS_SKYLAKE(dev))
1017 return skl_init_workarounds(ring);
1018 else if (IS_GEN9(dev))
1019 return gen9_init_workarounds(ring);
1020
1021 return 0;
1022 }
1023
1024 static int init_render_ring(struct intel_engine_cs *ring)
1025 {
1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 int ret = init_ring_common(ring);
1029 if (ret)
1030 return ret;
1031
1032 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1033 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1034 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1035
1036 /* We need to disable the AsyncFlip performance optimisations in order
1037 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1038 * programmed to '1' on all products.
1039 *
1040 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1041 */
1042 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1043 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1044
1045 /* Required for the hardware to program scanline values for waiting */
1046 /* WaEnableFlushTlbInvalidationMode:snb */
1047 if (INTEL_INFO(dev)->gen == 6)
1048 I915_WRITE(GFX_MODE,
1049 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1050
1051 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1052 if (IS_GEN7(dev))
1053 I915_WRITE(GFX_MODE_GEN7,
1054 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1055 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1056
1057 if (IS_GEN6(dev)) {
1058 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1059 * "If this bit is set, STCunit will have LRA as replacement
1060 * policy. [...] This bit must be reset. LRA replacement
1061 * policy is not supported."
1062 */
1063 I915_WRITE(CACHE_MODE_0,
1064 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1065 }
1066
1067 if (INTEL_INFO(dev)->gen >= 6)
1068 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1069
1070 if (HAS_L3_DPF(dev))
1071 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1072
1073 return init_workarounds_ring(ring);
1074 }
1075
1076 static void render_ring_cleanup(struct intel_engine_cs *ring)
1077 {
1078 struct drm_device *dev = ring->dev;
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080
1081 if (dev_priv->semaphore_obj) {
1082 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1083 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1084 dev_priv->semaphore_obj = NULL;
1085 }
1086
1087 intel_fini_pipe_control(ring);
1088 }
1089
1090 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1091 unsigned int num_dwords)
1092 {
1093 #define MBOX_UPDATE_DWORDS 8
1094 struct drm_device *dev = signaller->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct intel_engine_cs *waiter;
1097 int i, ret, num_rings;
1098
1099 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1100 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1101 #undef MBOX_UPDATE_DWORDS
1102
1103 ret = intel_ring_begin(signaller, num_dwords);
1104 if (ret)
1105 return ret;
1106
1107 for_each_ring(waiter, dev_priv, i) {
1108 u32 seqno;
1109 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1110 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1111 continue;
1112
1113 seqno = i915_gem_request_get_seqno(
1114 signaller->outstanding_lazy_request);
1115 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1116 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1117 PIPE_CONTROL_QW_WRITE |
1118 PIPE_CONTROL_FLUSH_ENABLE);
1119 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1120 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1121 intel_ring_emit(signaller, seqno);
1122 intel_ring_emit(signaller, 0);
1123 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1124 MI_SEMAPHORE_TARGET(waiter->id));
1125 intel_ring_emit(signaller, 0);
1126 }
1127
1128 return 0;
1129 }
1130
1131 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1132 unsigned int num_dwords)
1133 {
1134 #define MBOX_UPDATE_DWORDS 6
1135 struct drm_device *dev = signaller->dev;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 struct intel_engine_cs *waiter;
1138 int i, ret, num_rings;
1139
1140 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1141 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1142 #undef MBOX_UPDATE_DWORDS
1143
1144 ret = intel_ring_begin(signaller, num_dwords);
1145 if (ret)
1146 return ret;
1147
1148 for_each_ring(waiter, dev_priv, i) {
1149 u32 seqno;
1150 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1151 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1152 continue;
1153
1154 seqno = i915_gem_request_get_seqno(
1155 signaller->outstanding_lazy_request);
1156 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1157 MI_FLUSH_DW_OP_STOREDW);
1158 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1159 MI_FLUSH_DW_USE_GTT);
1160 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1161 intel_ring_emit(signaller, seqno);
1162 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1163 MI_SEMAPHORE_TARGET(waiter->id));
1164 intel_ring_emit(signaller, 0);
1165 }
1166
1167 return 0;
1168 }
1169
1170 static int gen6_signal(struct intel_engine_cs *signaller,
1171 unsigned int num_dwords)
1172 {
1173 struct drm_device *dev = signaller->dev;
1174 struct drm_i915_private *dev_priv = dev->dev_private;
1175 struct intel_engine_cs *useless;
1176 int i, ret, num_rings;
1177
1178 #define MBOX_UPDATE_DWORDS 3
1179 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1180 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1181 #undef MBOX_UPDATE_DWORDS
1182
1183 ret = intel_ring_begin(signaller, num_dwords);
1184 if (ret)
1185 return ret;
1186
1187 for_each_ring(useless, dev_priv, i) {
1188 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1189 if (mbox_reg != GEN6_NOSYNC) {
1190 u32 seqno = i915_gem_request_get_seqno(
1191 signaller->outstanding_lazy_request);
1192 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1193 intel_ring_emit(signaller, mbox_reg);
1194 intel_ring_emit(signaller, seqno);
1195 }
1196 }
1197
1198 /* If num_dwords was rounded, make sure the tail pointer is correct */
1199 if (num_rings % 2 == 0)
1200 intel_ring_emit(signaller, MI_NOOP);
1201
1202 return 0;
1203 }
1204
1205 /**
1206 * gen6_add_request - Update the semaphore mailbox registers
1207 *
1208 * @ring - ring that is adding a request
1209 * @seqno - return seqno stuck into the ring
1210 *
1211 * Update the mailbox registers in the *other* rings with the current seqno.
1212 * This acts like a signal in the canonical semaphore.
1213 */
1214 static int
1215 gen6_add_request(struct intel_engine_cs *ring)
1216 {
1217 int ret;
1218
1219 if (ring->semaphore.signal)
1220 ret = ring->semaphore.signal(ring, 4);
1221 else
1222 ret = intel_ring_begin(ring, 4);
1223
1224 if (ret)
1225 return ret;
1226
1227 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1228 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1229 intel_ring_emit(ring,
1230 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1231 intel_ring_emit(ring, MI_USER_INTERRUPT);
1232 __intel_ring_advance(ring);
1233
1234 return 0;
1235 }
1236
1237 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1238 u32 seqno)
1239 {
1240 struct drm_i915_private *dev_priv = dev->dev_private;
1241 return dev_priv->last_seqno < seqno;
1242 }
1243
1244 /**
1245 * intel_ring_sync - sync the waiter to the signaller on seqno
1246 *
1247 * @waiter - ring that is waiting
1248 * @signaller - ring which has, or will signal
1249 * @seqno - seqno which the waiter will block on
1250 */
1251
1252 static int
1253 gen8_ring_sync(struct intel_engine_cs *waiter,
1254 struct intel_engine_cs *signaller,
1255 u32 seqno)
1256 {
1257 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1258 int ret;
1259
1260 ret = intel_ring_begin(waiter, 4);
1261 if (ret)
1262 return ret;
1263
1264 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1265 MI_SEMAPHORE_GLOBAL_GTT |
1266 MI_SEMAPHORE_POLL |
1267 MI_SEMAPHORE_SAD_GTE_SDD);
1268 intel_ring_emit(waiter, seqno);
1269 intel_ring_emit(waiter,
1270 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1271 intel_ring_emit(waiter,
1272 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1273 intel_ring_advance(waiter);
1274 return 0;
1275 }
1276
1277 static int
1278 gen6_ring_sync(struct intel_engine_cs *waiter,
1279 struct intel_engine_cs *signaller,
1280 u32 seqno)
1281 {
1282 u32 dw1 = MI_SEMAPHORE_MBOX |
1283 MI_SEMAPHORE_COMPARE |
1284 MI_SEMAPHORE_REGISTER;
1285 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1286 int ret;
1287
1288 /* Throughout all of the GEM code, seqno passed implies our current
1289 * seqno is >= the last seqno executed. However for hardware the
1290 * comparison is strictly greater than.
1291 */
1292 seqno -= 1;
1293
1294 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1295
1296 ret = intel_ring_begin(waiter, 4);
1297 if (ret)
1298 return ret;
1299
1300 /* If seqno wrap happened, omit the wait with no-ops */
1301 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1302 intel_ring_emit(waiter, dw1 | wait_mbox);
1303 intel_ring_emit(waiter, seqno);
1304 intel_ring_emit(waiter, 0);
1305 intel_ring_emit(waiter, MI_NOOP);
1306 } else {
1307 intel_ring_emit(waiter, MI_NOOP);
1308 intel_ring_emit(waiter, MI_NOOP);
1309 intel_ring_emit(waiter, MI_NOOP);
1310 intel_ring_emit(waiter, MI_NOOP);
1311 }
1312 intel_ring_advance(waiter);
1313
1314 return 0;
1315 }
1316
1317 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1318 do { \
1319 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1320 PIPE_CONTROL_DEPTH_STALL); \
1321 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1322 intel_ring_emit(ring__, 0); \
1323 intel_ring_emit(ring__, 0); \
1324 } while (0)
1325
1326 static int
1327 pc_render_add_request(struct intel_engine_cs *ring)
1328 {
1329 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1330 int ret;
1331
1332 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1333 * incoherent with writes to memory, i.e. completely fubar,
1334 * so we need to use PIPE_NOTIFY instead.
1335 *
1336 * However, we also need to workaround the qword write
1337 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1338 * memory before requesting an interrupt.
1339 */
1340 ret = intel_ring_begin(ring, 32);
1341 if (ret)
1342 return ret;
1343
1344 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1345 PIPE_CONTROL_WRITE_FLUSH |
1346 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1347 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1348 intel_ring_emit(ring,
1349 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1350 intel_ring_emit(ring, 0);
1351 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1352 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1353 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1354 scratch_addr += 2 * CACHELINE_BYTES;
1355 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1356 scratch_addr += 2 * CACHELINE_BYTES;
1357 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1358 scratch_addr += 2 * CACHELINE_BYTES;
1359 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1360 scratch_addr += 2 * CACHELINE_BYTES;
1361 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1362
1363 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1364 PIPE_CONTROL_WRITE_FLUSH |
1365 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1366 PIPE_CONTROL_NOTIFY);
1367 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1368 intel_ring_emit(ring,
1369 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1370 intel_ring_emit(ring, 0);
1371 __intel_ring_advance(ring);
1372
1373 return 0;
1374 }
1375
1376 static u32
1377 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1378 {
1379 /* Workaround to force correct ordering between irq and seqno writes on
1380 * ivb (and maybe also on snb) by reading from a CS register (like
1381 * ACTHD) before reading the status page. */
1382 if (!lazy_coherency) {
1383 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1384 POSTING_READ(RING_ACTHD(ring->mmio_base));
1385 }
1386
1387 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1388 }
1389
1390 static u32
1391 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1392 {
1393 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1394 }
1395
1396 static void
1397 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1398 {
1399 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1400 }
1401
1402 static u32
1403 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1404 {
1405 return ring->scratch.cpu_page[0];
1406 }
1407
1408 static void
1409 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1410 {
1411 ring->scratch.cpu_page[0] = seqno;
1412 }
1413
1414 static bool
1415 gen5_ring_get_irq(struct intel_engine_cs *ring)
1416 {
1417 struct drm_device *dev = ring->dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 unsigned long flags;
1420
1421 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1422 return false;
1423
1424 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1425 if (ring->irq_refcount++ == 0)
1426 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1427 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1428
1429 return true;
1430 }
1431
1432 static void
1433 gen5_ring_put_irq(struct intel_engine_cs *ring)
1434 {
1435 struct drm_device *dev = ring->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 unsigned long flags;
1438
1439 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1440 if (--ring->irq_refcount == 0)
1441 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1442 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1443 }
1444
1445 static bool
1446 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1447 {
1448 struct drm_device *dev = ring->dev;
1449 struct drm_i915_private *dev_priv = dev->dev_private;
1450 unsigned long flags;
1451
1452 if (!intel_irqs_enabled(dev_priv))
1453 return false;
1454
1455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1456 if (ring->irq_refcount++ == 0) {
1457 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1458 I915_WRITE(IMR, dev_priv->irq_mask);
1459 POSTING_READ(IMR);
1460 }
1461 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1462
1463 return true;
1464 }
1465
1466 static void
1467 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1468 {
1469 struct drm_device *dev = ring->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 unsigned long flags;
1472
1473 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1474 if (--ring->irq_refcount == 0) {
1475 dev_priv->irq_mask |= ring->irq_enable_mask;
1476 I915_WRITE(IMR, dev_priv->irq_mask);
1477 POSTING_READ(IMR);
1478 }
1479 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1480 }
1481
1482 static bool
1483 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1484 {
1485 struct drm_device *dev = ring->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 unsigned long flags;
1488
1489 if (!intel_irqs_enabled(dev_priv))
1490 return false;
1491
1492 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1493 if (ring->irq_refcount++ == 0) {
1494 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1495 I915_WRITE16(IMR, dev_priv->irq_mask);
1496 POSTING_READ16(IMR);
1497 }
1498 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1499
1500 return true;
1501 }
1502
1503 static void
1504 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1505 {
1506 struct drm_device *dev = ring->dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508 unsigned long flags;
1509
1510 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1511 if (--ring->irq_refcount == 0) {
1512 dev_priv->irq_mask |= ring->irq_enable_mask;
1513 I915_WRITE16(IMR, dev_priv->irq_mask);
1514 POSTING_READ16(IMR);
1515 }
1516 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1517 }
1518
1519 static int
1520 bsd_ring_flush(struct intel_engine_cs *ring,
1521 u32 invalidate_domains,
1522 u32 flush_domains)
1523 {
1524 int ret;
1525
1526 ret = intel_ring_begin(ring, 2);
1527 if (ret)
1528 return ret;
1529
1530 intel_ring_emit(ring, MI_FLUSH);
1531 intel_ring_emit(ring, MI_NOOP);
1532 intel_ring_advance(ring);
1533 return 0;
1534 }
1535
1536 static int
1537 i9xx_add_request(struct intel_engine_cs *ring)
1538 {
1539 int ret;
1540
1541 ret = intel_ring_begin(ring, 4);
1542 if (ret)
1543 return ret;
1544
1545 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1546 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1547 intel_ring_emit(ring,
1548 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1549 intel_ring_emit(ring, MI_USER_INTERRUPT);
1550 __intel_ring_advance(ring);
1551
1552 return 0;
1553 }
1554
1555 static bool
1556 gen6_ring_get_irq(struct intel_engine_cs *ring)
1557 {
1558 struct drm_device *dev = ring->dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 unsigned long flags;
1561
1562 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1563 return false;
1564
1565 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1566 if (ring->irq_refcount++ == 0) {
1567 if (HAS_L3_DPF(dev) && ring->id == RCS)
1568 I915_WRITE_IMR(ring,
1569 ~(ring->irq_enable_mask |
1570 GT_PARITY_ERROR(dev)));
1571 else
1572 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1573 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1574 }
1575 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1576
1577 return true;
1578 }
1579
1580 static void
1581 gen6_ring_put_irq(struct intel_engine_cs *ring)
1582 {
1583 struct drm_device *dev = ring->dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 unsigned long flags;
1586
1587 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1588 if (--ring->irq_refcount == 0) {
1589 if (HAS_L3_DPF(dev) && ring->id == RCS)
1590 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1591 else
1592 I915_WRITE_IMR(ring, ~0);
1593 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1594 }
1595 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1596 }
1597
1598 static bool
1599 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1600 {
1601 struct drm_device *dev = ring->dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 unsigned long flags;
1604
1605 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1606 return false;
1607
1608 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1609 if (ring->irq_refcount++ == 0) {
1610 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1611 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1612 }
1613 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1614
1615 return true;
1616 }
1617
1618 static void
1619 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1620 {
1621 struct drm_device *dev = ring->dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 unsigned long flags;
1624
1625 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1626 if (--ring->irq_refcount == 0) {
1627 I915_WRITE_IMR(ring, ~0);
1628 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1629 }
1630 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1631 }
1632
1633 static bool
1634 gen8_ring_get_irq(struct intel_engine_cs *ring)
1635 {
1636 struct drm_device *dev = ring->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 unsigned long flags;
1639
1640 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1641 return false;
1642
1643 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1644 if (ring->irq_refcount++ == 0) {
1645 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1646 I915_WRITE_IMR(ring,
1647 ~(ring->irq_enable_mask |
1648 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1649 } else {
1650 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1651 }
1652 POSTING_READ(RING_IMR(ring->mmio_base));
1653 }
1654 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1655
1656 return true;
1657 }
1658
1659 static void
1660 gen8_ring_put_irq(struct intel_engine_cs *ring)
1661 {
1662 struct drm_device *dev = ring->dev;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 unsigned long flags;
1665
1666 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1667 if (--ring->irq_refcount == 0) {
1668 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1669 I915_WRITE_IMR(ring,
1670 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1671 } else {
1672 I915_WRITE_IMR(ring, ~0);
1673 }
1674 POSTING_READ(RING_IMR(ring->mmio_base));
1675 }
1676 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1677 }
1678
1679 static int
1680 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1681 u64 offset, u32 length,
1682 unsigned flags)
1683 {
1684 int ret;
1685
1686 ret = intel_ring_begin(ring, 2);
1687 if (ret)
1688 return ret;
1689
1690 intel_ring_emit(ring,
1691 MI_BATCH_BUFFER_START |
1692 MI_BATCH_GTT |
1693 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1694 intel_ring_emit(ring, offset);
1695 intel_ring_advance(ring);
1696
1697 return 0;
1698 }
1699
1700 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1701 #define I830_BATCH_LIMIT (256*1024)
1702 #define I830_TLB_ENTRIES (2)
1703 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1704 static int
1705 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1706 u64 offset, u32 len,
1707 unsigned flags)
1708 {
1709 u32 cs_offset = ring->scratch.gtt_offset;
1710 int ret;
1711
1712 ret = intel_ring_begin(ring, 6);
1713 if (ret)
1714 return ret;
1715
1716 /* Evict the invalid PTE TLBs */
1717 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1718 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1719 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1720 intel_ring_emit(ring, cs_offset);
1721 intel_ring_emit(ring, 0xdeadbeef);
1722 intel_ring_emit(ring, MI_NOOP);
1723 intel_ring_advance(ring);
1724
1725 if ((flags & I915_DISPATCH_PINNED) == 0) {
1726 if (len > I830_BATCH_LIMIT)
1727 return -ENOSPC;
1728
1729 ret = intel_ring_begin(ring, 6 + 2);
1730 if (ret)
1731 return ret;
1732
1733 /* Blit the batch (which has now all relocs applied) to the
1734 * stable batch scratch bo area (so that the CS never
1735 * stumbles over its tlb invalidation bug) ...
1736 */
1737 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1738 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1739 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1740 intel_ring_emit(ring, cs_offset);
1741 intel_ring_emit(ring, 4096);
1742 intel_ring_emit(ring, offset);
1743
1744 intel_ring_emit(ring, MI_FLUSH);
1745 intel_ring_emit(ring, MI_NOOP);
1746 intel_ring_advance(ring);
1747
1748 /* ... and execute it. */
1749 offset = cs_offset;
1750 }
1751
1752 ret = intel_ring_begin(ring, 4);
1753 if (ret)
1754 return ret;
1755
1756 intel_ring_emit(ring, MI_BATCH_BUFFER);
1757 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1758 intel_ring_emit(ring, offset + len - 8);
1759 intel_ring_emit(ring, MI_NOOP);
1760 intel_ring_advance(ring);
1761
1762 return 0;
1763 }
1764
1765 static int
1766 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1767 u64 offset, u32 len,
1768 unsigned flags)
1769 {
1770 int ret;
1771
1772 ret = intel_ring_begin(ring, 2);
1773 if (ret)
1774 return ret;
1775
1776 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1777 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1778 intel_ring_advance(ring);
1779
1780 return 0;
1781 }
1782
1783 static void cleanup_status_page(struct intel_engine_cs *ring)
1784 {
1785 struct drm_i915_gem_object *obj;
1786
1787 obj = ring->status_page.obj;
1788 if (obj == NULL)
1789 return;
1790
1791 kunmap(sg_page(obj->pages->sgl));
1792 i915_gem_object_ggtt_unpin(obj);
1793 drm_gem_object_unreference(&obj->base);
1794 ring->status_page.obj = NULL;
1795 }
1796
1797 static int init_status_page(struct intel_engine_cs *ring)
1798 {
1799 struct drm_i915_gem_object *obj;
1800
1801 if ((obj = ring->status_page.obj) == NULL) {
1802 unsigned flags;
1803 int ret;
1804
1805 obj = i915_gem_alloc_object(ring->dev, 4096);
1806 if (obj == NULL) {
1807 DRM_ERROR("Failed to allocate status page\n");
1808 return -ENOMEM;
1809 }
1810
1811 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1812 if (ret)
1813 goto err_unref;
1814
1815 flags = 0;
1816 if (!HAS_LLC(ring->dev))
1817 /* On g33, we cannot place HWS above 256MiB, so
1818 * restrict its pinning to the low mappable arena.
1819 * Though this restriction is not documented for
1820 * gen4, gen5, or byt, they also behave similarly
1821 * and hang if the HWS is placed at the top of the
1822 * GTT. To generalise, it appears that all !llc
1823 * platforms have issues with us placing the HWS
1824 * above the mappable region (even though we never
1825 * actualy map it).
1826 */
1827 flags |= PIN_MAPPABLE;
1828 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1829 if (ret) {
1830 err_unref:
1831 drm_gem_object_unreference(&obj->base);
1832 return ret;
1833 }
1834
1835 ring->status_page.obj = obj;
1836 }
1837
1838 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1839 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1840 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1841
1842 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1843 ring->name, ring->status_page.gfx_addr);
1844
1845 return 0;
1846 }
1847
1848 static int init_phys_status_page(struct intel_engine_cs *ring)
1849 {
1850 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1851
1852 if (!dev_priv->status_page_dmah) {
1853 dev_priv->status_page_dmah =
1854 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1855 if (!dev_priv->status_page_dmah)
1856 return -ENOMEM;
1857 }
1858
1859 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1860 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1861
1862 return 0;
1863 }
1864
1865 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1866 {
1867 iounmap(ringbuf->virtual_start);
1868 ringbuf->virtual_start = NULL;
1869 i915_gem_object_ggtt_unpin(ringbuf->obj);
1870 }
1871
1872 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1873 struct intel_ringbuffer *ringbuf)
1874 {
1875 struct drm_i915_private *dev_priv = to_i915(dev);
1876 struct drm_i915_gem_object *obj = ringbuf->obj;
1877 int ret;
1878
1879 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1880 if (ret)
1881 return ret;
1882
1883 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1884 if (ret) {
1885 i915_gem_object_ggtt_unpin(obj);
1886 return ret;
1887 }
1888
1889 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1890 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1891 if (ringbuf->virtual_start == NULL) {
1892 i915_gem_object_ggtt_unpin(obj);
1893 return -EINVAL;
1894 }
1895
1896 return 0;
1897 }
1898
1899 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1900 {
1901 drm_gem_object_unreference(&ringbuf->obj->base);
1902 ringbuf->obj = NULL;
1903 }
1904
1905 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1906 struct intel_ringbuffer *ringbuf)
1907 {
1908 struct drm_i915_gem_object *obj;
1909
1910 obj = NULL;
1911 if (!HAS_LLC(dev))
1912 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1913 if (obj == NULL)
1914 obj = i915_gem_alloc_object(dev, ringbuf->size);
1915 if (obj == NULL)
1916 return -ENOMEM;
1917
1918 /* mark ring buffers as read-only from GPU side by default */
1919 obj->gt_ro = 1;
1920
1921 ringbuf->obj = obj;
1922
1923 return 0;
1924 }
1925
1926 static int intel_init_ring_buffer(struct drm_device *dev,
1927 struct intel_engine_cs *ring)
1928 {
1929 struct intel_ringbuffer *ringbuf;
1930 int ret;
1931
1932 WARN_ON(ring->buffer);
1933
1934 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1935 if (!ringbuf)
1936 return -ENOMEM;
1937 ring->buffer = ringbuf;
1938
1939 ring->dev = dev;
1940 INIT_LIST_HEAD(&ring->active_list);
1941 INIT_LIST_HEAD(&ring->request_list);
1942 INIT_LIST_HEAD(&ring->execlist_queue);
1943 ringbuf->size = 32 * PAGE_SIZE;
1944 ringbuf->ring = ring;
1945 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1946
1947 init_waitqueue_head(&ring->irq_queue);
1948
1949 if (I915_NEED_GFX_HWS(dev)) {
1950 ret = init_status_page(ring);
1951 if (ret)
1952 goto error;
1953 } else {
1954 BUG_ON(ring->id != RCS);
1955 ret = init_phys_status_page(ring);
1956 if (ret)
1957 goto error;
1958 }
1959
1960 WARN_ON(ringbuf->obj);
1961
1962 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1963 if (ret) {
1964 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1965 ring->name, ret);
1966 goto error;
1967 }
1968
1969 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1970 if (ret) {
1971 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1972 ring->name, ret);
1973 intel_destroy_ringbuffer_obj(ringbuf);
1974 goto error;
1975 }
1976
1977 /* Workaround an erratum on the i830 which causes a hang if
1978 * the TAIL pointer points to within the last 2 cachelines
1979 * of the buffer.
1980 */
1981 ringbuf->effective_size = ringbuf->size;
1982 if (IS_I830(dev) || IS_845G(dev))
1983 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1984
1985 ret = i915_cmd_parser_init_ring(ring);
1986 if (ret)
1987 goto error;
1988
1989 return 0;
1990
1991 error:
1992 kfree(ringbuf);
1993 ring->buffer = NULL;
1994 return ret;
1995 }
1996
1997 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1998 {
1999 struct drm_i915_private *dev_priv;
2000 struct intel_ringbuffer *ringbuf;
2001
2002 if (!intel_ring_initialized(ring))
2003 return;
2004
2005 dev_priv = to_i915(ring->dev);
2006 ringbuf = ring->buffer;
2007
2008 intel_stop_ring_buffer(ring);
2009 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2010
2011 intel_unpin_ringbuffer_obj(ringbuf);
2012 intel_destroy_ringbuffer_obj(ringbuf);
2013 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2014
2015 if (ring->cleanup)
2016 ring->cleanup(ring);
2017
2018 cleanup_status_page(ring);
2019
2020 i915_cmd_parser_fini_ring(ring);
2021
2022 kfree(ringbuf);
2023 ring->buffer = NULL;
2024 }
2025
2026 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
2027 {
2028 struct intel_ringbuffer *ringbuf = ring->buffer;
2029 struct drm_i915_gem_request *request;
2030 int ret;
2031
2032 if (intel_ring_space(ringbuf) >= n)
2033 return 0;
2034
2035 list_for_each_entry(request, &ring->request_list, list) {
2036 if (__intel_ring_space(request->postfix, ringbuf->tail,
2037 ringbuf->size) >= n) {
2038 break;
2039 }
2040 }
2041
2042 if (&request->list == &ring->request_list)
2043 return -ENOSPC;
2044
2045 ret = i915_wait_request(request);
2046 if (ret)
2047 return ret;
2048
2049 i915_gem_retire_requests_ring(ring);
2050
2051 return 0;
2052 }
2053
2054 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2055 {
2056 struct drm_device *dev = ring->dev;
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058 struct intel_ringbuffer *ringbuf = ring->buffer;
2059 unsigned long end;
2060 int ret;
2061
2062 ret = intel_ring_wait_request(ring, n);
2063 if (ret != -ENOSPC)
2064 return ret;
2065
2066 /* force the tail write in case we have been skipping them */
2067 __intel_ring_advance(ring);
2068
2069 /* With GEM the hangcheck timer should kick us out of the loop,
2070 * leaving it early runs the risk of corrupting GEM state (due
2071 * to running on almost untested codepaths). But on resume
2072 * timers don't work yet, so prevent a complete hang in that
2073 * case by choosing an insanely large timeout. */
2074 end = jiffies + 60 * HZ;
2075
2076 ret = 0;
2077 trace_i915_ring_wait_begin(ring);
2078 do {
2079 if (intel_ring_space(ringbuf) >= n)
2080 break;
2081 ringbuf->head = I915_READ_HEAD(ring);
2082 if (intel_ring_space(ringbuf) >= n)
2083 break;
2084
2085 msleep(1);
2086
2087 if (dev_priv->mm.interruptible && signal_pending(current)) {
2088 ret = -ERESTARTSYS;
2089 break;
2090 }
2091
2092 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2093 dev_priv->mm.interruptible);
2094 if (ret)
2095 break;
2096
2097 if (time_after(jiffies, end)) {
2098 ret = -EBUSY;
2099 break;
2100 }
2101 } while (1);
2102 trace_i915_ring_wait_end(ring);
2103 return ret;
2104 }
2105
2106 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2107 {
2108 uint32_t __iomem *virt;
2109 struct intel_ringbuffer *ringbuf = ring->buffer;
2110 int rem = ringbuf->size - ringbuf->tail;
2111
2112 if (ringbuf->space < rem) {
2113 int ret = ring_wait_for_space(ring, rem);
2114 if (ret)
2115 return ret;
2116 }
2117
2118 virt = ringbuf->virtual_start + ringbuf->tail;
2119 rem /= 4;
2120 while (rem--)
2121 iowrite32(MI_NOOP, virt++);
2122
2123 ringbuf->tail = 0;
2124 intel_ring_update_space(ringbuf);
2125
2126 return 0;
2127 }
2128
2129 int intel_ring_idle(struct intel_engine_cs *ring)
2130 {
2131 struct drm_i915_gem_request *req;
2132 int ret;
2133
2134 /* We need to add any requests required to flush the objects and ring */
2135 if (ring->outstanding_lazy_request) {
2136 ret = i915_add_request(ring);
2137 if (ret)
2138 return ret;
2139 }
2140
2141 /* Wait upon the last request to be completed */
2142 if (list_empty(&ring->request_list))
2143 return 0;
2144
2145 req = list_entry(ring->request_list.prev,
2146 struct drm_i915_gem_request,
2147 list);
2148
2149 return i915_wait_request(req);
2150 }
2151
2152 static int
2153 intel_ring_alloc_request(struct intel_engine_cs *ring)
2154 {
2155 int ret;
2156 struct drm_i915_gem_request *request;
2157 struct drm_i915_private *dev_private = ring->dev->dev_private;
2158
2159 if (ring->outstanding_lazy_request)
2160 return 0;
2161
2162 request = kzalloc(sizeof(*request), GFP_KERNEL);
2163 if (request == NULL)
2164 return -ENOMEM;
2165
2166 kref_init(&request->ref);
2167 request->ring = ring;
2168 request->uniq = dev_private->request_uniq++;
2169
2170 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2171 if (ret) {
2172 kfree(request);
2173 return ret;
2174 }
2175
2176 ring->outstanding_lazy_request = request;
2177 return 0;
2178 }
2179
2180 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2181 int bytes)
2182 {
2183 struct intel_ringbuffer *ringbuf = ring->buffer;
2184 int ret;
2185
2186 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2187 ret = intel_wrap_ring_buffer(ring);
2188 if (unlikely(ret))
2189 return ret;
2190 }
2191
2192 if (unlikely(ringbuf->space < bytes)) {
2193 ret = ring_wait_for_space(ring, bytes);
2194 if (unlikely(ret))
2195 return ret;
2196 }
2197
2198 return 0;
2199 }
2200
2201 int intel_ring_begin(struct intel_engine_cs *ring,
2202 int num_dwords)
2203 {
2204 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2205 int ret;
2206
2207 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2208 dev_priv->mm.interruptible);
2209 if (ret)
2210 return ret;
2211
2212 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2213 if (ret)
2214 return ret;
2215
2216 /* Preallocate the olr before touching the ring */
2217 ret = intel_ring_alloc_request(ring);
2218 if (ret)
2219 return ret;
2220
2221 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2222 return 0;
2223 }
2224
2225 /* Align the ring tail to a cacheline boundary */
2226 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2227 {
2228 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2229 int ret;
2230
2231 if (num_dwords == 0)
2232 return 0;
2233
2234 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2235 ret = intel_ring_begin(ring, num_dwords);
2236 if (ret)
2237 return ret;
2238
2239 while (num_dwords--)
2240 intel_ring_emit(ring, MI_NOOP);
2241
2242 intel_ring_advance(ring);
2243
2244 return 0;
2245 }
2246
2247 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2248 {
2249 struct drm_device *dev = ring->dev;
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251
2252 BUG_ON(ring->outstanding_lazy_request);
2253
2254 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2255 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2256 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2257 if (HAS_VEBOX(dev))
2258 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2259 }
2260
2261 ring->set_seqno(ring, seqno);
2262 ring->hangcheck.seqno = seqno;
2263 }
2264
2265 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2266 u32 value)
2267 {
2268 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2269
2270 /* Every tail move must follow the sequence below */
2271
2272 /* Disable notification that the ring is IDLE. The GT
2273 * will then assume that it is busy and bring it out of rc6.
2274 */
2275 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2276 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2277
2278 /* Clear the context id. Here be magic! */
2279 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2280
2281 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2282 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2283 GEN6_BSD_SLEEP_INDICATOR) == 0,
2284 50))
2285 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2286
2287 /* Now that the ring is fully powered up, update the tail */
2288 I915_WRITE_TAIL(ring, value);
2289 POSTING_READ(RING_TAIL(ring->mmio_base));
2290
2291 /* Let the ring send IDLE messages to the GT again,
2292 * and so let it sleep to conserve power when idle.
2293 */
2294 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2295 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2296 }
2297
2298 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2299 u32 invalidate, u32 flush)
2300 {
2301 uint32_t cmd;
2302 int ret;
2303
2304 ret = intel_ring_begin(ring, 4);
2305 if (ret)
2306 return ret;
2307
2308 cmd = MI_FLUSH_DW;
2309 if (INTEL_INFO(ring->dev)->gen >= 8)
2310 cmd += 1;
2311 /*
2312 * Bspec vol 1c.5 - video engine command streamer:
2313 * "If ENABLED, all TLBs will be invalidated once the flush
2314 * operation is complete. This bit is only valid when the
2315 * Post-Sync Operation field is a value of 1h or 3h."
2316 */
2317 if (invalidate & I915_GEM_GPU_DOMAINS)
2318 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2319 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2320 intel_ring_emit(ring, cmd);
2321 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2322 if (INTEL_INFO(ring->dev)->gen >= 8) {
2323 intel_ring_emit(ring, 0); /* upper addr */
2324 intel_ring_emit(ring, 0); /* value */
2325 } else {
2326 intel_ring_emit(ring, 0);
2327 intel_ring_emit(ring, MI_NOOP);
2328 }
2329 intel_ring_advance(ring);
2330 return 0;
2331 }
2332
2333 static int
2334 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2335 u64 offset, u32 len,
2336 unsigned flags)
2337 {
2338 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2339 int ret;
2340
2341 ret = intel_ring_begin(ring, 4);
2342 if (ret)
2343 return ret;
2344
2345 /* FIXME(BDW): Address space and security selectors. */
2346 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2347 intel_ring_emit(ring, lower_32_bits(offset));
2348 intel_ring_emit(ring, upper_32_bits(offset));
2349 intel_ring_emit(ring, MI_NOOP);
2350 intel_ring_advance(ring);
2351
2352 return 0;
2353 }
2354
2355 static int
2356 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2357 u64 offset, u32 len,
2358 unsigned flags)
2359 {
2360 int ret;
2361
2362 ret = intel_ring_begin(ring, 2);
2363 if (ret)
2364 return ret;
2365
2366 intel_ring_emit(ring,
2367 MI_BATCH_BUFFER_START |
2368 (flags & I915_DISPATCH_SECURE ?
2369 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2370 /* bit0-7 is the length on GEN6+ */
2371 intel_ring_emit(ring, offset);
2372 intel_ring_advance(ring);
2373
2374 return 0;
2375 }
2376
2377 static int
2378 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2379 u64 offset, u32 len,
2380 unsigned flags)
2381 {
2382 int ret;
2383
2384 ret = intel_ring_begin(ring, 2);
2385 if (ret)
2386 return ret;
2387
2388 intel_ring_emit(ring,
2389 MI_BATCH_BUFFER_START |
2390 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2391 /* bit0-7 is the length on GEN6+ */
2392 intel_ring_emit(ring, offset);
2393 intel_ring_advance(ring);
2394
2395 return 0;
2396 }
2397
2398 /* Blitter support (SandyBridge+) */
2399
2400 static int gen6_ring_flush(struct intel_engine_cs *ring,
2401 u32 invalidate, u32 flush)
2402 {
2403 struct drm_device *dev = ring->dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405 uint32_t cmd;
2406 int ret;
2407
2408 ret = intel_ring_begin(ring, 4);
2409 if (ret)
2410 return ret;
2411
2412 cmd = MI_FLUSH_DW;
2413 if (INTEL_INFO(ring->dev)->gen >= 8)
2414 cmd += 1;
2415 /*
2416 * Bspec vol 1c.3 - blitter engine command streamer:
2417 * "If ENABLED, all TLBs will be invalidated once the flush
2418 * operation is complete. This bit is only valid when the
2419 * Post-Sync Operation field is a value of 1h or 3h."
2420 */
2421 if (invalidate & I915_GEM_DOMAIN_RENDER)
2422 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2423 MI_FLUSH_DW_OP_STOREDW;
2424 intel_ring_emit(ring, cmd);
2425 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2426 if (INTEL_INFO(ring->dev)->gen >= 8) {
2427 intel_ring_emit(ring, 0); /* upper addr */
2428 intel_ring_emit(ring, 0); /* value */
2429 } else {
2430 intel_ring_emit(ring, 0);
2431 intel_ring_emit(ring, MI_NOOP);
2432 }
2433 intel_ring_advance(ring);
2434
2435 if (!invalidate && flush) {
2436 if (IS_GEN7(dev))
2437 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2438 else if (IS_BROADWELL(dev))
2439 dev_priv->fbc.need_sw_cache_clean = true;
2440 }
2441
2442 return 0;
2443 }
2444
2445 int intel_init_render_ring_buffer(struct drm_device *dev)
2446 {
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2449 struct drm_i915_gem_object *obj;
2450 int ret;
2451
2452 ring->name = "render ring";
2453 ring->id = RCS;
2454 ring->mmio_base = RENDER_RING_BASE;
2455
2456 if (INTEL_INFO(dev)->gen >= 8) {
2457 if (i915_semaphore_is_enabled(dev)) {
2458 obj = i915_gem_alloc_object(dev, 4096);
2459 if (obj == NULL) {
2460 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2461 i915.semaphores = 0;
2462 } else {
2463 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2464 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2465 if (ret != 0) {
2466 drm_gem_object_unreference(&obj->base);
2467 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2468 i915.semaphores = 0;
2469 } else
2470 dev_priv->semaphore_obj = obj;
2471 }
2472 }
2473
2474 ring->init_context = intel_rcs_ctx_init;
2475 ring->add_request = gen6_add_request;
2476 ring->flush = gen8_render_ring_flush;
2477 ring->irq_get = gen8_ring_get_irq;
2478 ring->irq_put = gen8_ring_put_irq;
2479 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2480 ring->get_seqno = gen6_ring_get_seqno;
2481 ring->set_seqno = ring_set_seqno;
2482 if (i915_semaphore_is_enabled(dev)) {
2483 WARN_ON(!dev_priv->semaphore_obj);
2484 ring->semaphore.sync_to = gen8_ring_sync;
2485 ring->semaphore.signal = gen8_rcs_signal;
2486 GEN8_RING_SEMAPHORE_INIT;
2487 }
2488 } else if (INTEL_INFO(dev)->gen >= 6) {
2489 ring->add_request = gen6_add_request;
2490 ring->flush = gen7_render_ring_flush;
2491 if (INTEL_INFO(dev)->gen == 6)
2492 ring->flush = gen6_render_ring_flush;
2493 ring->irq_get = gen6_ring_get_irq;
2494 ring->irq_put = gen6_ring_put_irq;
2495 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2496 ring->get_seqno = gen6_ring_get_seqno;
2497 ring->set_seqno = ring_set_seqno;
2498 if (i915_semaphore_is_enabled(dev)) {
2499 ring->semaphore.sync_to = gen6_ring_sync;
2500 ring->semaphore.signal = gen6_signal;
2501 /*
2502 * The current semaphore is only applied on pre-gen8
2503 * platform. And there is no VCS2 ring on the pre-gen8
2504 * platform. So the semaphore between RCS and VCS2 is
2505 * initialized as INVALID. Gen8 will initialize the
2506 * sema between VCS2 and RCS later.
2507 */
2508 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2509 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2510 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2511 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2512 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2513 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2514 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2515 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2516 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2517 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2518 }
2519 } else if (IS_GEN5(dev)) {
2520 ring->add_request = pc_render_add_request;
2521 ring->flush = gen4_render_ring_flush;
2522 ring->get_seqno = pc_render_get_seqno;
2523 ring->set_seqno = pc_render_set_seqno;
2524 ring->irq_get = gen5_ring_get_irq;
2525 ring->irq_put = gen5_ring_put_irq;
2526 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2527 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2528 } else {
2529 ring->add_request = i9xx_add_request;
2530 if (INTEL_INFO(dev)->gen < 4)
2531 ring->flush = gen2_render_ring_flush;
2532 else
2533 ring->flush = gen4_render_ring_flush;
2534 ring->get_seqno = ring_get_seqno;
2535 ring->set_seqno = ring_set_seqno;
2536 if (IS_GEN2(dev)) {
2537 ring->irq_get = i8xx_ring_get_irq;
2538 ring->irq_put = i8xx_ring_put_irq;
2539 } else {
2540 ring->irq_get = i9xx_ring_get_irq;
2541 ring->irq_put = i9xx_ring_put_irq;
2542 }
2543 ring->irq_enable_mask = I915_USER_INTERRUPT;
2544 }
2545 ring->write_tail = ring_write_tail;
2546
2547 if (IS_HASWELL(dev))
2548 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2549 else if (IS_GEN8(dev))
2550 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2551 else if (INTEL_INFO(dev)->gen >= 6)
2552 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2553 else if (INTEL_INFO(dev)->gen >= 4)
2554 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2555 else if (IS_I830(dev) || IS_845G(dev))
2556 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2557 else
2558 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2559 ring->init_hw = init_render_ring;
2560 ring->cleanup = render_ring_cleanup;
2561
2562 /* Workaround batchbuffer to combat CS tlb bug. */
2563 if (HAS_BROKEN_CS_TLB(dev)) {
2564 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2565 if (obj == NULL) {
2566 DRM_ERROR("Failed to allocate batch bo\n");
2567 return -ENOMEM;
2568 }
2569
2570 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2571 if (ret != 0) {
2572 drm_gem_object_unreference(&obj->base);
2573 DRM_ERROR("Failed to ping batch bo\n");
2574 return ret;
2575 }
2576
2577 ring->scratch.obj = obj;
2578 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2579 }
2580
2581 ret = intel_init_ring_buffer(dev, ring);
2582 if (ret)
2583 return ret;
2584
2585 if (INTEL_INFO(dev)->gen >= 5) {
2586 ret = intel_init_pipe_control(ring);
2587 if (ret)
2588 return ret;
2589 }
2590
2591 return 0;
2592 }
2593
2594 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2595 {
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2598
2599 ring->name = "bsd ring";
2600 ring->id = VCS;
2601
2602 ring->write_tail = ring_write_tail;
2603 if (INTEL_INFO(dev)->gen >= 6) {
2604 ring->mmio_base = GEN6_BSD_RING_BASE;
2605 /* gen6 bsd needs a special wa for tail updates */
2606 if (IS_GEN6(dev))
2607 ring->write_tail = gen6_bsd_ring_write_tail;
2608 ring->flush = gen6_bsd_ring_flush;
2609 ring->add_request = gen6_add_request;
2610 ring->get_seqno = gen6_ring_get_seqno;
2611 ring->set_seqno = ring_set_seqno;
2612 if (INTEL_INFO(dev)->gen >= 8) {
2613 ring->irq_enable_mask =
2614 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2615 ring->irq_get = gen8_ring_get_irq;
2616 ring->irq_put = gen8_ring_put_irq;
2617 ring->dispatch_execbuffer =
2618 gen8_ring_dispatch_execbuffer;
2619 if (i915_semaphore_is_enabled(dev)) {
2620 ring->semaphore.sync_to = gen8_ring_sync;
2621 ring->semaphore.signal = gen8_xcs_signal;
2622 GEN8_RING_SEMAPHORE_INIT;
2623 }
2624 } else {
2625 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2626 ring->irq_get = gen6_ring_get_irq;
2627 ring->irq_put = gen6_ring_put_irq;
2628 ring->dispatch_execbuffer =
2629 gen6_ring_dispatch_execbuffer;
2630 if (i915_semaphore_is_enabled(dev)) {
2631 ring->semaphore.sync_to = gen6_ring_sync;
2632 ring->semaphore.signal = gen6_signal;
2633 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2634 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2635 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2636 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2637 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2638 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2639 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2640 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2641 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2642 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2643 }
2644 }
2645 } else {
2646 ring->mmio_base = BSD_RING_BASE;
2647 ring->flush = bsd_ring_flush;
2648 ring->add_request = i9xx_add_request;
2649 ring->get_seqno = ring_get_seqno;
2650 ring->set_seqno = ring_set_seqno;
2651 if (IS_GEN5(dev)) {
2652 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2653 ring->irq_get = gen5_ring_get_irq;
2654 ring->irq_put = gen5_ring_put_irq;
2655 } else {
2656 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2657 ring->irq_get = i9xx_ring_get_irq;
2658 ring->irq_put = i9xx_ring_put_irq;
2659 }
2660 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2661 }
2662 ring->init_hw = init_ring_common;
2663
2664 return intel_init_ring_buffer(dev, ring);
2665 }
2666
2667 /**
2668 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2669 */
2670 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2671 {
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2674
2675 ring->name = "bsd2 ring";
2676 ring->id = VCS2;
2677
2678 ring->write_tail = ring_write_tail;
2679 ring->mmio_base = GEN8_BSD2_RING_BASE;
2680 ring->flush = gen6_bsd_ring_flush;
2681 ring->add_request = gen6_add_request;
2682 ring->get_seqno = gen6_ring_get_seqno;
2683 ring->set_seqno = ring_set_seqno;
2684 ring->irq_enable_mask =
2685 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2686 ring->irq_get = gen8_ring_get_irq;
2687 ring->irq_put = gen8_ring_put_irq;
2688 ring->dispatch_execbuffer =
2689 gen8_ring_dispatch_execbuffer;
2690 if (i915_semaphore_is_enabled(dev)) {
2691 ring->semaphore.sync_to = gen8_ring_sync;
2692 ring->semaphore.signal = gen8_xcs_signal;
2693 GEN8_RING_SEMAPHORE_INIT;
2694 }
2695 ring->init_hw = init_ring_common;
2696
2697 return intel_init_ring_buffer(dev, ring);
2698 }
2699
2700 int intel_init_blt_ring_buffer(struct drm_device *dev)
2701 {
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2704
2705 ring->name = "blitter ring";
2706 ring->id = BCS;
2707
2708 ring->mmio_base = BLT_RING_BASE;
2709 ring->write_tail = ring_write_tail;
2710 ring->flush = gen6_ring_flush;
2711 ring->add_request = gen6_add_request;
2712 ring->get_seqno = gen6_ring_get_seqno;
2713 ring->set_seqno = ring_set_seqno;
2714 if (INTEL_INFO(dev)->gen >= 8) {
2715 ring->irq_enable_mask =
2716 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2717 ring->irq_get = gen8_ring_get_irq;
2718 ring->irq_put = gen8_ring_put_irq;
2719 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2720 if (i915_semaphore_is_enabled(dev)) {
2721 ring->semaphore.sync_to = gen8_ring_sync;
2722 ring->semaphore.signal = gen8_xcs_signal;
2723 GEN8_RING_SEMAPHORE_INIT;
2724 }
2725 } else {
2726 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2727 ring->irq_get = gen6_ring_get_irq;
2728 ring->irq_put = gen6_ring_put_irq;
2729 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2730 if (i915_semaphore_is_enabled(dev)) {
2731 ring->semaphore.signal = gen6_signal;
2732 ring->semaphore.sync_to = gen6_ring_sync;
2733 /*
2734 * The current semaphore is only applied on pre-gen8
2735 * platform. And there is no VCS2 ring on the pre-gen8
2736 * platform. So the semaphore between BCS and VCS2 is
2737 * initialized as INVALID. Gen8 will initialize the
2738 * sema between BCS and VCS2 later.
2739 */
2740 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2741 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2742 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2743 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2744 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2745 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2746 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2747 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2748 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2749 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2750 }
2751 }
2752 ring->init_hw = init_ring_common;
2753
2754 return intel_init_ring_buffer(dev, ring);
2755 }
2756
2757 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2758 {
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2761
2762 ring->name = "video enhancement ring";
2763 ring->id = VECS;
2764
2765 ring->mmio_base = VEBOX_RING_BASE;
2766 ring->write_tail = ring_write_tail;
2767 ring->flush = gen6_ring_flush;
2768 ring->add_request = gen6_add_request;
2769 ring->get_seqno = gen6_ring_get_seqno;
2770 ring->set_seqno = ring_set_seqno;
2771
2772 if (INTEL_INFO(dev)->gen >= 8) {
2773 ring->irq_enable_mask =
2774 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2775 ring->irq_get = gen8_ring_get_irq;
2776 ring->irq_put = gen8_ring_put_irq;
2777 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2778 if (i915_semaphore_is_enabled(dev)) {
2779 ring->semaphore.sync_to = gen8_ring_sync;
2780 ring->semaphore.signal = gen8_xcs_signal;
2781 GEN8_RING_SEMAPHORE_INIT;
2782 }
2783 } else {
2784 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2785 ring->irq_get = hsw_vebox_get_irq;
2786 ring->irq_put = hsw_vebox_put_irq;
2787 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2788 if (i915_semaphore_is_enabled(dev)) {
2789 ring->semaphore.sync_to = gen6_ring_sync;
2790 ring->semaphore.signal = gen6_signal;
2791 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2792 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2793 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2794 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2795 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2796 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2797 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2798 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2799 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2800 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2801 }
2802 }
2803 ring->init_hw = init_ring_common;
2804
2805 return intel_init_ring_buffer(dev, ring);
2806 }
2807
2808 int
2809 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2810 {
2811 int ret;
2812
2813 if (!ring->gpu_caches_dirty)
2814 return 0;
2815
2816 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2817 if (ret)
2818 return ret;
2819
2820 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2821
2822 ring->gpu_caches_dirty = false;
2823 return 0;
2824 }
2825
2826 int
2827 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2828 {
2829 uint32_t flush_domains;
2830 int ret;
2831
2832 flush_domains = 0;
2833 if (ring->gpu_caches_dirty)
2834 flush_domains = I915_GEM_GPU_DOMAINS;
2835
2836 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2837 if (ret)
2838 return ret;
2839
2840 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2841
2842 ring->gpu_caches_dirty = false;
2843 return 0;
2844 }
2845
2846 void
2847 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2848 {
2849 int ret;
2850
2851 if (!intel_ring_initialized(ring))
2852 return;
2853
2854 ret = intel_ring_idle(ring);
2855 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2856 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2857 ring->name, ret);
2858
2859 stop_ring(ring);
2860 }
Linux kernel - Deliverables
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