2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 int __intel_ring_space(int head
, int tail
, int size
)
39 int space
= head
- tail
;
42 return space
- I915_RING_FREE_SPACE
;
45 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
47 if (ringbuf
->last_retired_head
!= -1) {
48 ringbuf
->head
= ringbuf
->last_retired_head
;
49 ringbuf
->last_retired_head
= -1;
52 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
53 ringbuf
->tail
, ringbuf
->size
);
56 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
58 intel_ring_update_space(ringbuf
);
59 return ringbuf
->space
;
62 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
64 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
65 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
68 static void __intel_ring_advance(struct intel_engine_cs
*ring
)
70 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
71 ringbuf
->tail
&= ringbuf
->size
- 1;
72 if (intel_ring_stopped(ring
))
74 ring
->write_tail(ring
, ringbuf
->tail
);
78 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
79 u32 invalidate_domains
,
82 struct intel_engine_cs
*ring
= req
->ring
;
87 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
88 cmd
|= MI_NO_WRITE_FLUSH
;
90 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
93 ret
= intel_ring_begin(req
, 2);
97 intel_ring_emit(ring
, cmd
);
98 intel_ring_emit(ring
, MI_NOOP
);
99 intel_ring_advance(ring
);
105 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
106 u32 invalidate_domains
,
109 struct intel_engine_cs
*ring
= req
->ring
;
110 struct drm_device
*dev
= ring
->dev
;
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
126 * I915_GEM_DOMAIN_COMMAND may not exist?
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
142 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
143 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
144 cmd
&= ~MI_NO_WRITE_FLUSH
;
145 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
148 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
149 (IS_G4X(dev
) || IS_GEN5(dev
)))
150 cmd
|= MI_INVALIDATE_ISP
;
152 ret
= intel_ring_begin(req
, 2);
156 intel_ring_emit(ring
, cmd
);
157 intel_ring_emit(ring
, MI_NOOP
);
158 intel_ring_advance(ring
);
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
176 * And the workaround for these two requires this workaround first:
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
203 struct intel_engine_cs
*ring
= req
->ring
;
204 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
207 ret
= intel_ring_begin(req
, 6);
211 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
213 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
214 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
215 intel_ring_emit(ring
, 0); /* low dword */
216 intel_ring_emit(ring
, 0); /* high dword */
217 intel_ring_emit(ring
, MI_NOOP
);
218 intel_ring_advance(ring
);
220 ret
= intel_ring_begin(req
, 6);
224 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
226 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
227 intel_ring_emit(ring
, 0);
228 intel_ring_emit(ring
, 0);
229 intel_ring_emit(ring
, MI_NOOP
);
230 intel_ring_advance(ring
);
236 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
237 u32 invalidate_domains
, u32 flush_domains
)
239 struct intel_engine_cs
*ring
= req
->ring
;
241 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
244 /* Force SNB workarounds for PIPE_CONTROL flushes */
245 ret
= intel_emit_post_sync_nonzero_flush(req
);
249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
254 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
255 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
260 flags
|= PIPE_CONTROL_CS_STALL
;
262 if (invalidate_domains
) {
263 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
264 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
265 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
266 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
267 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
268 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
270 * TLB invalidate requires a post-sync write.
272 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
275 ret
= intel_ring_begin(req
, 4);
279 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(ring
, flags
);
281 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
282 intel_ring_emit(ring
, 0);
283 intel_ring_advance(ring
);
289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
291 struct intel_engine_cs
*ring
= req
->ring
;
294 ret
= intel_ring_begin(req
, 4);
298 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
300 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
301 intel_ring_emit(ring
, 0);
302 intel_ring_emit(ring
, 0);
303 intel_ring_advance(ring
);
309 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
310 u32 invalidate_domains
, u32 flush_domains
)
312 struct intel_engine_cs
*ring
= req
->ring
;
314 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
325 flags
|= PIPE_CONTROL_CS_STALL
;
327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
332 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
333 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
334 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
335 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
337 if (invalidate_domains
) {
338 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
339 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
340 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
341 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
342 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
343 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
344 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
346 * TLB invalidate requires a post-sync write.
348 flags
|= PIPE_CONTROL_QW_WRITE
;
349 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
351 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
356 gen7_render_ring_cs_stall_wa(req
);
359 ret
= intel_ring_begin(req
, 4);
363 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(ring
, flags
);
365 intel_ring_emit(ring
, scratch_addr
);
366 intel_ring_emit(ring
, 0);
367 intel_ring_advance(ring
);
373 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
374 u32 flags
, u32 scratch_addr
)
376 struct intel_engine_cs
*ring
= req
->ring
;
379 ret
= intel_ring_begin(req
, 6);
383 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(ring
, flags
);
385 intel_ring_emit(ring
, scratch_addr
);
386 intel_ring_emit(ring
, 0);
387 intel_ring_emit(ring
, 0);
388 intel_ring_emit(ring
, 0);
389 intel_ring_advance(ring
);
395 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
396 u32 invalidate_domains
, u32 flush_domains
)
399 u32 scratch_addr
= req
->ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
402 flags
|= PIPE_CONTROL_CS_STALL
;
405 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
406 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
407 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
408 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
410 if (invalidate_domains
) {
411 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
412 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
413 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
414 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
415 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
416 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
417 flags
|= PIPE_CONTROL_QW_WRITE
;
418 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
421 ret
= gen8_emit_pipe_control(req
,
422 PIPE_CONTROL_CS_STALL
|
423 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
429 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
432 static void ring_write_tail(struct intel_engine_cs
*ring
,
435 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
436 I915_WRITE_TAIL(ring
, value
);
439 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
441 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
444 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
445 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
446 RING_ACTHD_UDW(ring
->mmio_base
));
447 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
448 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
450 acthd
= I915_READ(ACTHD
);
455 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
457 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
460 addr
= dev_priv
->status_page_dmah
->busaddr
;
461 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
462 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
463 I915_WRITE(HWS_PGA
, addr
);
466 static void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
468 struct drm_device
*dev
= ring
->dev
;
469 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
478 mmio
= RENDER_HWS_PGA_GEN7
;
481 mmio
= BLT_HWS_PGA_GEN7
;
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
489 mmio
= BSD_HWS_PGA_GEN7
;
492 mmio
= VEBOX_HWS_PGA_GEN7
;
495 } else if (IS_GEN6(ring
->dev
)) {
496 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
498 /* XXX: gen8 returns to sanity */
499 mmio
= RING_HWS_PGA(ring
->mmio_base
);
502 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
506 * Flush the TLB for this page
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
512 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
513 i915_reg_t reg
= RING_INSTPM(ring
->mmio_base
);
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
521 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
528 static bool stop_ring(struct intel_engine_cs
*ring
)
530 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
532 if (!IS_GEN2(ring
->dev
)) {
533 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
534 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
536 /* Sometimes we observe that the idle flag is not
537 * set even though the ring is empty. So double
538 * check before giving up.
540 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
545 I915_WRITE_CTL(ring
, 0);
546 I915_WRITE_HEAD(ring
, 0);
547 ring
->write_tail(ring
, 0);
549 if (!IS_GEN2(ring
->dev
)) {
550 (void)I915_READ_CTL(ring
);
551 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
554 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
557 static int init_ring_common(struct intel_engine_cs
*ring
)
559 struct drm_device
*dev
= ring
->dev
;
560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
562 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
565 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
567 if (!stop_ring(ring
)) {
568 /* G45 ring initialization often fails to reset head to zero */
569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
573 I915_READ_HEAD(ring
),
574 I915_READ_TAIL(ring
),
575 I915_READ_START(ring
));
577 if (!stop_ring(ring
)) {
578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
582 I915_READ_HEAD(ring
),
583 I915_READ_TAIL(ring
),
584 I915_READ_START(ring
));
590 if (I915_NEED_GFX_HWS(dev
))
591 intel_ring_setup_status_page(ring
);
593 ring_setup_phys_status_page(ring
);
595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(ring
);
598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
602 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(ring
))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 ring
->name
, I915_READ_HEAD(ring
));
608 I915_WRITE_HEAD(ring
, 0);
609 (void)I915_READ_HEAD(ring
);
612 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
615 /* If the head is still not zero, the ring is dead */
616 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
617 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
618 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
619 DRM_ERROR("%s initialization failed "
620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
622 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
623 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
624 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
629 ringbuf
->last_retired_head
= -1;
630 ringbuf
->head
= I915_READ_HEAD(ring
);
631 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
632 intel_ring_update_space(ringbuf
);
634 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
637 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
643 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
645 struct drm_device
*dev
= ring
->dev
;
647 if (ring
->scratch
.obj
== NULL
)
650 if (INTEL_INFO(dev
)->gen
>= 5) {
651 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
652 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
655 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
656 ring
->scratch
.obj
= NULL
;
660 intel_init_pipe_control(struct intel_engine_cs
*ring
)
664 WARN_ON(ring
->scratch
.obj
);
666 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
667 if (ring
->scratch
.obj
== NULL
) {
668 DRM_ERROR("Failed to allocate seqno page\n");
673 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
677 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
681 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
682 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
683 if (ring
->scratch
.cpu_page
== NULL
) {
688 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
689 ring
->name
, ring
->scratch
.gtt_offset
);
693 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
695 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
700 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
703 struct intel_engine_cs
*ring
= req
->ring
;
704 struct drm_device
*dev
= ring
->dev
;
705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
706 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
711 ring
->gpu_caches_dirty
= true;
712 ret
= intel_ring_flush_all_caches(req
);
716 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
720 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
721 for (i
= 0; i
< w
->count
; i
++) {
722 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
723 intel_ring_emit(ring
, w
->reg
[i
].value
);
725 intel_ring_emit(ring
, MI_NOOP
);
727 intel_ring_advance(ring
);
729 ring
->gpu_caches_dirty
= true;
730 ret
= intel_ring_flush_all_caches(req
);
734 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
739 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
743 ret
= intel_ring_workarounds_emit(req
);
747 ret
= i915_gem_render_state_init(req
);
749 DRM_ERROR("init render state: %d\n", ret
);
754 static int wa_add(struct drm_i915_private
*dev_priv
,
756 const u32 mask
, const u32 val
)
758 const u32 idx
= dev_priv
->workarounds
.count
;
760 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
763 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
764 dev_priv
->workarounds
.reg
[idx
].value
= val
;
765 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
767 dev_priv
->workarounds
.count
++;
772 #define WA_REG(addr, mask, val) do { \
773 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
778 #define WA_SET_BIT_MASKED(addr, mask) \
779 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
781 #define WA_CLR_BIT_MASKED(addr, mask) \
782 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
784 #define WA_SET_FIELD_MASKED(addr, mask, value) \
785 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
787 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
788 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
790 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
792 static int wa_ring_whitelist_reg(struct intel_engine_cs
*ring
, i915_reg_t reg
)
794 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
795 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
796 const uint32_t index
= wa
->hw_whitelist_count
[ring
->id
];
798 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
801 WA_WRITE(RING_FORCE_TO_NONPRIV(ring
->mmio_base
, index
),
802 i915_mmio_reg_offset(reg
));
803 wa
->hw_whitelist_count
[ring
->id
]++;
808 static int gen8_init_workarounds(struct intel_engine_cs
*ring
)
810 struct drm_device
*dev
= ring
->dev
;
811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
815 /* WaDisableAsyncFlipPerfMode:bdw,chv */
816 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
818 /* WaDisablePartialInstShootdown:bdw,chv */
819 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
820 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
822 /* Use Force Non-Coherent whenever executing a 3D context. This is a
823 * workaround for for a possible hang in the unlikely event a TLB
824 * invalidation occurs during a PSD flush.
826 /* WaForceEnableNonCoherent:bdw,chv */
827 /* WaHdcDisableFetchWhenMasked:bdw,chv */
828 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
829 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
830 HDC_FORCE_NON_COHERENT
);
832 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
833 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
834 * polygons in the same 8x4 pixel/sample area to be processed without
835 * stalling waiting for the earlier ones to write to Hierarchical Z
838 * This optimization is off by default for BDW and CHV; turn it on.
840 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
842 /* Wa4x4STCOptimizationDisable:bdw,chv */
843 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
846 * BSpec recommends 8x4 when MSAA is used,
847 * however in practice 16x4 seems fastest.
849 * Note that PS/WM thread counts depend on the WIZ hashing
850 * disable bit, which we don't touch here, but it's good
851 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
853 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
854 GEN6_WIZ_HASHING_MASK
,
855 GEN6_WIZ_HASHING_16x4
);
860 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
863 struct drm_device
*dev
= ring
->dev
;
864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
866 ret
= gen8_init_workarounds(ring
);
870 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
871 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
873 /* WaDisableDopClockGating:bdw */
874 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
875 DOP_CLOCK_GATING_DISABLE
);
877 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
878 GEN8_SAMPLER_POWER_BYPASS_DIS
);
880 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
881 /* WaForceContextSaveRestoreNonCoherent:bdw */
882 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
883 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
884 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
889 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
892 struct drm_device
*dev
= ring
->dev
;
893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
895 ret
= gen8_init_workarounds(ring
);
899 /* WaDisableThreadStallDopClockGating:chv */
900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
908 static int gen9_init_workarounds(struct intel_engine_cs
*ring
)
910 struct drm_device
*dev
= ring
->dev
;
911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
914 /* WaEnableLbsSlaRetryTimerDecrement:skl */
915 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
916 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
918 /* WaDisableKillLogic:bxt,skl */
919 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
922 /* WaDisablePartialInstShootdown:skl,bxt */
923 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
924 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
926 /* Syncing dependencies between camera and graphics:skl,bxt */
927 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
928 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
930 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
931 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
932 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
933 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
934 GEN9_DG_MIRROR_FIX_ENABLE
);
936 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
937 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
938 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
939 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
940 GEN9_RHWO_OPTIMIZATION_DISABLE
);
942 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
943 * but we do that in per ctx batchbuffer as there is an issue
944 * with this register not getting restored on ctx restore
948 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
949 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
) || IS_BROXTON(dev
))
950 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
951 GEN9_ENABLE_YV12_BUGFIX
);
953 /* Wa4x4STCOptimizationDisable:skl,bxt */
954 /* WaDisablePartialResolveInVc:skl,bxt */
955 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
956 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
958 /* WaCcsTlbPrefetchDisable:skl,bxt */
959 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
960 GEN9_CCS_TLB_PREFETCH_ENABLE
);
962 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
963 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_C0
) ||
964 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
965 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
966 PIXEL_MASK_CAMMING_DISABLE
);
968 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
969 tmp
= HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
;
970 if (IS_SKL_REVID(dev
, SKL_REVID_F0
, SKL_REVID_F0
) ||
971 IS_BXT_REVID(dev
, BXT_REVID_B0
, REVID_FOREVER
))
972 tmp
|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
;
973 WA_SET_BIT_MASKED(HDC_CHICKEN0
, tmp
);
975 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
976 if (IS_SKYLAKE(dev
) || IS_BXT_REVID(dev
, 0, BXT_REVID_B0
))
977 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
978 GEN8_SAMPLER_POWER_BYPASS_DIS
);
980 /* WaDisableSTUnitPowerOptimization:skl,bxt */
981 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
986 static int skl_tune_iz_hashing(struct intel_engine_cs
*ring
)
988 struct drm_device
*dev
= ring
->dev
;
989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
990 u8 vals
[3] = { 0, 0, 0 };
993 for (i
= 0; i
< 3; i
++) {
997 * Only consider slices where one, and only one, subslice has 7
1000 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1004 * subslice_7eu[i] != 0 (because of the check above) and
1005 * ss_max == 4 (maximum number of subslices possible per slice)
1009 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1013 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1016 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1017 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1018 GEN9_IZ_HASHING_MASK(2) |
1019 GEN9_IZ_HASHING_MASK(1) |
1020 GEN9_IZ_HASHING_MASK(0),
1021 GEN9_IZ_HASHING(2, vals
[2]) |
1022 GEN9_IZ_HASHING(1, vals
[1]) |
1023 GEN9_IZ_HASHING(0, vals
[0]));
1028 static int skl_init_workarounds(struct intel_engine_cs
*ring
)
1031 struct drm_device
*dev
= ring
->dev
;
1032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1034 ret
= gen9_init_workarounds(ring
);
1038 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
)) {
1039 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1040 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1041 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1044 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1045 * involving this register should also be added to WA batch as required.
1047 if (IS_SKL_REVID(dev
, 0, SKL_REVID_E0
))
1048 /* WaDisableLSQCROPERFforOCL:skl */
1049 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1050 GEN8_LQSC_RO_PERF_DIS
);
1052 /* WaEnableGapsTsvCreditFix:skl */
1053 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
)) {
1054 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1055 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1058 /* WaDisablePowerCompilerClockGating:skl */
1059 if (IS_SKL_REVID(dev
, SKL_REVID_B0
, SKL_REVID_B0
))
1060 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1061 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1063 if (IS_SKL_REVID(dev
, 0, SKL_REVID_F0
)) {
1065 *Use Force Non-Coherent whenever executing a 3D context. This
1066 * is a workaround for a possible hang in the unlikely event
1067 * a TLB invalidation occurs during a PSD flush.
1069 /* WaForceEnableNonCoherent:skl */
1070 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1071 HDC_FORCE_NON_COHERENT
);
1073 /* WaDisableHDCInvalidation:skl */
1074 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
1075 BDW_DISABLE_HDC_INVALIDATION
);
1078 /* WaBarrierPerformanceFixDisable:skl */
1079 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_D0
))
1080 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1081 HDC_FENCE_DEST_SLM_DISABLE
|
1082 HDC_BARRIER_PERFORMANCE_DISABLE
);
1084 /* WaDisableSbeCacheDispatchPortSharing:skl */
1085 if (IS_SKL_REVID(dev
, 0, SKL_REVID_F0
))
1087 GEN7_HALF_SLICE_CHICKEN1
,
1088 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1090 return skl_tune_iz_hashing(ring
);
1093 static int bxt_init_workarounds(struct intel_engine_cs
*ring
)
1096 struct drm_device
*dev
= ring
->dev
;
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 ret
= gen9_init_workarounds(ring
);
1103 /* WaStoreMultiplePTEenable:bxt */
1104 /* This is a requirement according to Hardware specification */
1105 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1106 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1108 /* WaSetClckGatingDisableMedia:bxt */
1109 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1110 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1111 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1114 /* WaDisableThreadStallDopClockGating:bxt */
1115 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1116 STALL_DOP_GATING_DISABLE
);
1118 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1119 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1121 GEN7_HALF_SLICE_CHICKEN1
,
1122 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1128 int init_workarounds_ring(struct intel_engine_cs
*ring
)
1130 struct drm_device
*dev
= ring
->dev
;
1131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1133 WARN_ON(ring
->id
!= RCS
);
1135 dev_priv
->workarounds
.count
= 0;
1136 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1138 if (IS_BROADWELL(dev
))
1139 return bdw_init_workarounds(ring
);
1141 if (IS_CHERRYVIEW(dev
))
1142 return chv_init_workarounds(ring
);
1144 if (IS_SKYLAKE(dev
))
1145 return skl_init_workarounds(ring
);
1147 if (IS_BROXTON(dev
))
1148 return bxt_init_workarounds(ring
);
1153 static int init_render_ring(struct intel_engine_cs
*ring
)
1155 struct drm_device
*dev
= ring
->dev
;
1156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1157 int ret
= init_ring_common(ring
);
1161 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1162 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1163 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1165 /* We need to disable the AsyncFlip performance optimisations in order
1166 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1167 * programmed to '1' on all products.
1169 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1171 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1172 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1174 /* Required for the hardware to program scanline values for waiting */
1175 /* WaEnableFlushTlbInvalidationMode:snb */
1176 if (INTEL_INFO(dev
)->gen
== 6)
1177 I915_WRITE(GFX_MODE
,
1178 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1180 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1182 I915_WRITE(GFX_MODE_GEN7
,
1183 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1184 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1187 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1188 * "If this bit is set, STCunit will have LRA as replacement
1189 * policy. [...] This bit must be reset. LRA replacement
1190 * policy is not supported."
1192 I915_WRITE(CACHE_MODE_0
,
1193 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1196 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1197 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1199 if (HAS_L3_DPF(dev
))
1200 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1202 return init_workarounds_ring(ring
);
1205 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
1207 struct drm_device
*dev
= ring
->dev
;
1208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1210 if (dev_priv
->semaphore_obj
) {
1211 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1212 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1213 dev_priv
->semaphore_obj
= NULL
;
1216 intel_fini_pipe_control(ring
);
1219 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1220 unsigned int num_dwords
)
1222 #define MBOX_UPDATE_DWORDS 8
1223 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1224 struct drm_device
*dev
= signaller
->dev
;
1225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1226 struct intel_engine_cs
*waiter
;
1227 int i
, ret
, num_rings
;
1229 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1230 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1231 #undef MBOX_UPDATE_DWORDS
1233 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1237 for_each_ring(waiter
, dev_priv
, i
) {
1239 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1240 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1243 seqno
= i915_gem_request_get_seqno(signaller_req
);
1244 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1245 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1246 PIPE_CONTROL_QW_WRITE
|
1247 PIPE_CONTROL_FLUSH_ENABLE
);
1248 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1249 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1250 intel_ring_emit(signaller
, seqno
);
1251 intel_ring_emit(signaller
, 0);
1252 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1253 MI_SEMAPHORE_TARGET(waiter
->id
));
1254 intel_ring_emit(signaller
, 0);
1260 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1261 unsigned int num_dwords
)
1263 #define MBOX_UPDATE_DWORDS 6
1264 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1265 struct drm_device
*dev
= signaller
->dev
;
1266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1267 struct intel_engine_cs
*waiter
;
1268 int i
, ret
, num_rings
;
1270 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1271 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1272 #undef MBOX_UPDATE_DWORDS
1274 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1278 for_each_ring(waiter
, dev_priv
, i
) {
1280 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1281 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1284 seqno
= i915_gem_request_get_seqno(signaller_req
);
1285 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1286 MI_FLUSH_DW_OP_STOREDW
);
1287 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1288 MI_FLUSH_DW_USE_GTT
);
1289 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1290 intel_ring_emit(signaller
, seqno
);
1291 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1292 MI_SEMAPHORE_TARGET(waiter
->id
));
1293 intel_ring_emit(signaller
, 0);
1299 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1300 unsigned int num_dwords
)
1302 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1303 struct drm_device
*dev
= signaller
->dev
;
1304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1305 struct intel_engine_cs
*useless
;
1306 int i
, ret
, num_rings
;
1308 #define MBOX_UPDATE_DWORDS 3
1309 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1310 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1311 #undef MBOX_UPDATE_DWORDS
1313 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1317 for_each_ring(useless
, dev_priv
, i
) {
1318 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1320 if (i915_mmio_reg_valid(mbox_reg
)) {
1321 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1323 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1324 intel_ring_emit_reg(signaller
, mbox_reg
);
1325 intel_ring_emit(signaller
, seqno
);
1329 /* If num_dwords was rounded, make sure the tail pointer is correct */
1330 if (num_rings
% 2 == 0)
1331 intel_ring_emit(signaller
, MI_NOOP
);
1337 * gen6_add_request - Update the semaphore mailbox registers
1339 * @request - request to write to the ring
1341 * Update the mailbox registers in the *other* rings with the current seqno.
1342 * This acts like a signal in the canonical semaphore.
1345 gen6_add_request(struct drm_i915_gem_request
*req
)
1347 struct intel_engine_cs
*ring
= req
->ring
;
1350 if (ring
->semaphore
.signal
)
1351 ret
= ring
->semaphore
.signal(req
, 4);
1353 ret
= intel_ring_begin(req
, 4);
1358 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1359 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1360 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1361 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1362 __intel_ring_advance(ring
);
1367 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1371 return dev_priv
->last_seqno
< seqno
;
1375 * intel_ring_sync - sync the waiter to the signaller on seqno
1377 * @waiter - ring that is waiting
1378 * @signaller - ring which has, or will signal
1379 * @seqno - seqno which the waiter will block on
1383 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1384 struct intel_engine_cs
*signaller
,
1387 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1388 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1391 ret
= intel_ring_begin(waiter_req
, 4);
1395 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1396 MI_SEMAPHORE_GLOBAL_GTT
|
1398 MI_SEMAPHORE_SAD_GTE_SDD
);
1399 intel_ring_emit(waiter
, seqno
);
1400 intel_ring_emit(waiter
,
1401 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1402 intel_ring_emit(waiter
,
1403 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1404 intel_ring_advance(waiter
);
1409 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1410 struct intel_engine_cs
*signaller
,
1413 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1414 u32 dw1
= MI_SEMAPHORE_MBOX
|
1415 MI_SEMAPHORE_COMPARE
|
1416 MI_SEMAPHORE_REGISTER
;
1417 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1420 /* Throughout all of the GEM code, seqno passed implies our current
1421 * seqno is >= the last seqno executed. However for hardware the
1422 * comparison is strictly greater than.
1426 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1428 ret
= intel_ring_begin(waiter_req
, 4);
1432 /* If seqno wrap happened, omit the wait with no-ops */
1433 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1434 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1435 intel_ring_emit(waiter
, seqno
);
1436 intel_ring_emit(waiter
, 0);
1437 intel_ring_emit(waiter
, MI_NOOP
);
1439 intel_ring_emit(waiter
, MI_NOOP
);
1440 intel_ring_emit(waiter
, MI_NOOP
);
1441 intel_ring_emit(waiter
, MI_NOOP
);
1442 intel_ring_emit(waiter
, MI_NOOP
);
1444 intel_ring_advance(waiter
);
1449 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1451 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1452 PIPE_CONTROL_DEPTH_STALL); \
1453 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1454 intel_ring_emit(ring__, 0); \
1455 intel_ring_emit(ring__, 0); \
1459 pc_render_add_request(struct drm_i915_gem_request
*req
)
1461 struct intel_engine_cs
*ring
= req
->ring
;
1462 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1465 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1466 * incoherent with writes to memory, i.e. completely fubar,
1467 * so we need to use PIPE_NOTIFY instead.
1469 * However, we also need to workaround the qword write
1470 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1471 * memory before requesting an interrupt.
1473 ret
= intel_ring_begin(req
, 32);
1477 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1478 PIPE_CONTROL_WRITE_FLUSH
|
1479 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1480 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1481 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1482 intel_ring_emit(ring
, 0);
1483 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1484 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1485 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1486 scratch_addr
+= 2 * CACHELINE_BYTES
;
1487 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1488 scratch_addr
+= 2 * CACHELINE_BYTES
;
1489 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1490 scratch_addr
+= 2 * CACHELINE_BYTES
;
1491 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1492 scratch_addr
+= 2 * CACHELINE_BYTES
;
1493 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1495 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1496 PIPE_CONTROL_WRITE_FLUSH
|
1497 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1498 PIPE_CONTROL_NOTIFY
);
1499 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1500 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1501 intel_ring_emit(ring
, 0);
1502 __intel_ring_advance(ring
);
1508 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1510 /* Workaround to force correct ordering between irq and seqno writes on
1511 * ivb (and maybe also on snb) by reading from a CS register (like
1512 * ACTHD) before reading the status page. */
1513 if (!lazy_coherency
) {
1514 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1515 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1518 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1522 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1524 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1528 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1530 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1534 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1536 return ring
->scratch
.cpu_page
[0];
1540 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1542 ring
->scratch
.cpu_page
[0] = seqno
;
1546 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1548 struct drm_device
*dev
= ring
->dev
;
1549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1550 unsigned long flags
;
1552 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1555 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1556 if (ring
->irq_refcount
++ == 0)
1557 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1558 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1564 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1566 struct drm_device
*dev
= ring
->dev
;
1567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1568 unsigned long flags
;
1570 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1571 if (--ring
->irq_refcount
== 0)
1572 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1573 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1577 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1579 struct drm_device
*dev
= ring
->dev
;
1580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 unsigned long flags
;
1583 if (!intel_irqs_enabled(dev_priv
))
1586 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1587 if (ring
->irq_refcount
++ == 0) {
1588 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1589 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1592 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1598 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1600 struct drm_device
*dev
= ring
->dev
;
1601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1602 unsigned long flags
;
1604 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1605 if (--ring
->irq_refcount
== 0) {
1606 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1607 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1610 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1614 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1616 struct drm_device
*dev
= ring
->dev
;
1617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1618 unsigned long flags
;
1620 if (!intel_irqs_enabled(dev_priv
))
1623 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1624 if (ring
->irq_refcount
++ == 0) {
1625 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1626 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1627 POSTING_READ16(IMR
);
1629 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1635 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1637 struct drm_device
*dev
= ring
->dev
;
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 unsigned long flags
;
1641 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1642 if (--ring
->irq_refcount
== 0) {
1643 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1644 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1645 POSTING_READ16(IMR
);
1647 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1651 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1652 u32 invalidate_domains
,
1655 struct intel_engine_cs
*ring
= req
->ring
;
1658 ret
= intel_ring_begin(req
, 2);
1662 intel_ring_emit(ring
, MI_FLUSH
);
1663 intel_ring_emit(ring
, MI_NOOP
);
1664 intel_ring_advance(ring
);
1669 i9xx_add_request(struct drm_i915_gem_request
*req
)
1671 struct intel_engine_cs
*ring
= req
->ring
;
1674 ret
= intel_ring_begin(req
, 4);
1678 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1679 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1680 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1681 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1682 __intel_ring_advance(ring
);
1688 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1690 struct drm_device
*dev
= ring
->dev
;
1691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1692 unsigned long flags
;
1694 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1697 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1698 if (ring
->irq_refcount
++ == 0) {
1699 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1700 I915_WRITE_IMR(ring
,
1701 ~(ring
->irq_enable_mask
|
1702 GT_PARITY_ERROR(dev
)));
1704 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1705 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1707 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1713 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1715 struct drm_device
*dev
= ring
->dev
;
1716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1717 unsigned long flags
;
1719 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1720 if (--ring
->irq_refcount
== 0) {
1721 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1722 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1724 I915_WRITE_IMR(ring
, ~0);
1725 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1727 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1731 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1733 struct drm_device
*dev
= ring
->dev
;
1734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1735 unsigned long flags
;
1737 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1740 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1741 if (ring
->irq_refcount
++ == 0) {
1742 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1743 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1745 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1751 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1753 struct drm_device
*dev
= ring
->dev
;
1754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1755 unsigned long flags
;
1757 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1758 if (--ring
->irq_refcount
== 0) {
1759 I915_WRITE_IMR(ring
, ~0);
1760 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1762 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1766 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1768 struct drm_device
*dev
= ring
->dev
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 unsigned long flags
;
1772 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1775 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1776 if (ring
->irq_refcount
++ == 0) {
1777 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1778 I915_WRITE_IMR(ring
,
1779 ~(ring
->irq_enable_mask
|
1780 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1782 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1784 POSTING_READ(RING_IMR(ring
->mmio_base
));
1786 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1792 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1794 struct drm_device
*dev
= ring
->dev
;
1795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1796 unsigned long flags
;
1798 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1799 if (--ring
->irq_refcount
== 0) {
1800 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1801 I915_WRITE_IMR(ring
,
1802 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1804 I915_WRITE_IMR(ring
, ~0);
1806 POSTING_READ(RING_IMR(ring
->mmio_base
));
1808 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1812 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1813 u64 offset
, u32 length
,
1814 unsigned dispatch_flags
)
1816 struct intel_engine_cs
*ring
= req
->ring
;
1819 ret
= intel_ring_begin(req
, 2);
1823 intel_ring_emit(ring
,
1824 MI_BATCH_BUFFER_START
|
1826 (dispatch_flags
& I915_DISPATCH_SECURE
?
1827 0 : MI_BATCH_NON_SECURE_I965
));
1828 intel_ring_emit(ring
, offset
);
1829 intel_ring_advance(ring
);
1834 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1835 #define I830_BATCH_LIMIT (256*1024)
1836 #define I830_TLB_ENTRIES (2)
1837 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1839 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1840 u64 offset
, u32 len
,
1841 unsigned dispatch_flags
)
1843 struct intel_engine_cs
*ring
= req
->ring
;
1844 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1847 ret
= intel_ring_begin(req
, 6);
1851 /* Evict the invalid PTE TLBs */
1852 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1853 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1854 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1855 intel_ring_emit(ring
, cs_offset
);
1856 intel_ring_emit(ring
, 0xdeadbeef);
1857 intel_ring_emit(ring
, MI_NOOP
);
1858 intel_ring_advance(ring
);
1860 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1861 if (len
> I830_BATCH_LIMIT
)
1864 ret
= intel_ring_begin(req
, 6 + 2);
1868 /* Blit the batch (which has now all relocs applied) to the
1869 * stable batch scratch bo area (so that the CS never
1870 * stumbles over its tlb invalidation bug) ...
1872 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1873 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1874 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1875 intel_ring_emit(ring
, cs_offset
);
1876 intel_ring_emit(ring
, 4096);
1877 intel_ring_emit(ring
, offset
);
1879 intel_ring_emit(ring
, MI_FLUSH
);
1880 intel_ring_emit(ring
, MI_NOOP
);
1881 intel_ring_advance(ring
);
1883 /* ... and execute it. */
1887 ret
= intel_ring_begin(req
, 2);
1891 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1892 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1893 0 : MI_BATCH_NON_SECURE
));
1894 intel_ring_advance(ring
);
1900 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1901 u64 offset
, u32 len
,
1902 unsigned dispatch_flags
)
1904 struct intel_engine_cs
*ring
= req
->ring
;
1907 ret
= intel_ring_begin(req
, 2);
1911 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1912 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1913 0 : MI_BATCH_NON_SECURE
));
1914 intel_ring_advance(ring
);
1919 static void cleanup_phys_status_page(struct intel_engine_cs
*ring
)
1921 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
1923 if (!dev_priv
->status_page_dmah
)
1926 drm_pci_free(ring
->dev
, dev_priv
->status_page_dmah
);
1927 ring
->status_page
.page_addr
= NULL
;
1930 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1932 struct drm_i915_gem_object
*obj
;
1934 obj
= ring
->status_page
.obj
;
1938 kunmap(sg_page(obj
->pages
->sgl
));
1939 i915_gem_object_ggtt_unpin(obj
);
1940 drm_gem_object_unreference(&obj
->base
);
1941 ring
->status_page
.obj
= NULL
;
1944 static int init_status_page(struct intel_engine_cs
*ring
)
1946 struct drm_i915_gem_object
*obj
= ring
->status_page
.obj
;
1952 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1954 DRM_ERROR("Failed to allocate status page\n");
1958 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1963 if (!HAS_LLC(ring
->dev
))
1964 /* On g33, we cannot place HWS above 256MiB, so
1965 * restrict its pinning to the low mappable arena.
1966 * Though this restriction is not documented for
1967 * gen4, gen5, or byt, they also behave similarly
1968 * and hang if the HWS is placed at the top of the
1969 * GTT. To generalise, it appears that all !llc
1970 * platforms have issues with us placing the HWS
1971 * above the mappable region (even though we never
1974 flags
|= PIN_MAPPABLE
;
1975 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1978 drm_gem_object_unreference(&obj
->base
);
1982 ring
->status_page
.obj
= obj
;
1985 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1986 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1987 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1989 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1990 ring
->name
, ring
->status_page
.gfx_addr
);
1995 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1997 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1999 if (!dev_priv
->status_page_dmah
) {
2000 dev_priv
->status_page_dmah
=
2001 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
2002 if (!dev_priv
->status_page_dmah
)
2006 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
2007 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
2012 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2014 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
2015 vunmap(ringbuf
->virtual_start
);
2017 iounmap(ringbuf
->virtual_start
);
2018 ringbuf
->virtual_start
= NULL
;
2019 ringbuf
->vma
= NULL
;
2020 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2023 static u32
*vmap_obj(struct drm_i915_gem_object
*obj
)
2025 struct sg_page_iter sg_iter
;
2026 struct page
**pages
;
2030 pages
= drm_malloc_ab(obj
->base
.size
>> PAGE_SHIFT
, sizeof(*pages
));
2035 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0)
2036 pages
[i
++] = sg_page_iter_page(&sg_iter
);
2038 addr
= vmap(pages
, i
, 0, PAGE_KERNEL
);
2039 drm_free_large(pages
);
2044 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
2045 struct intel_ringbuffer
*ringbuf
)
2047 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2048 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2051 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2052 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, 0);
2056 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2058 i915_gem_object_ggtt_unpin(obj
);
2062 ringbuf
->virtual_start
= vmap_obj(obj
);
2063 if (ringbuf
->virtual_start
== NULL
) {
2064 i915_gem_object_ggtt_unpin(obj
);
2068 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
2072 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2074 i915_gem_object_ggtt_unpin(obj
);
2078 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
2079 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
2080 if (ringbuf
->virtual_start
== NULL
) {
2081 i915_gem_object_ggtt_unpin(obj
);
2086 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2091 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2093 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2094 ringbuf
->obj
= NULL
;
2097 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2098 struct intel_ringbuffer
*ringbuf
)
2100 struct drm_i915_gem_object
*obj
;
2104 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2106 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
2110 /* mark ring buffers as read-only from GPU side by default */
2118 struct intel_ringbuffer
*
2119 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2121 struct intel_ringbuffer
*ring
;
2124 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2126 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2128 return ERR_PTR(-ENOMEM
);
2131 ring
->ring
= engine
;
2132 list_add(&ring
->link
, &engine
->buffers
);
2135 /* Workaround an erratum on the i830 which causes a hang if
2136 * the TAIL pointer points to within the last 2 cachelines
2139 ring
->effective_size
= size
;
2140 if (IS_I830(engine
->dev
) || IS_845G(engine
->dev
))
2141 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2143 ring
->last_retired_head
= -1;
2144 intel_ring_update_space(ring
);
2146 ret
= intel_alloc_ringbuffer_obj(engine
->dev
, ring
);
2148 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2150 list_del(&ring
->link
);
2152 return ERR_PTR(ret
);
2159 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2161 intel_destroy_ringbuffer_obj(ring
);
2162 list_del(&ring
->link
);
2166 static int intel_init_ring_buffer(struct drm_device
*dev
,
2167 struct intel_engine_cs
*ring
)
2169 struct intel_ringbuffer
*ringbuf
;
2172 WARN_ON(ring
->buffer
);
2175 INIT_LIST_HEAD(&ring
->active_list
);
2176 INIT_LIST_HEAD(&ring
->request_list
);
2177 INIT_LIST_HEAD(&ring
->execlist_queue
);
2178 INIT_LIST_HEAD(&ring
->buffers
);
2179 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2180 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
2182 init_waitqueue_head(&ring
->irq_queue
);
2184 ringbuf
= intel_engine_create_ringbuffer(ring
, 32 * PAGE_SIZE
);
2185 if (IS_ERR(ringbuf
)) {
2186 ret
= PTR_ERR(ringbuf
);
2189 ring
->buffer
= ringbuf
;
2191 if (I915_NEED_GFX_HWS(dev
)) {
2192 ret
= init_status_page(ring
);
2196 WARN_ON(ring
->id
!= RCS
);
2197 ret
= init_phys_status_page(ring
);
2202 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2204 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2206 intel_destroy_ringbuffer_obj(ringbuf
);
2210 ret
= i915_cmd_parser_init_ring(ring
);
2217 intel_cleanup_ring_buffer(ring
);
2221 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
2223 struct drm_i915_private
*dev_priv
;
2225 if (!intel_ring_initialized(ring
))
2228 dev_priv
= to_i915(ring
->dev
);
2231 intel_stop_ring_buffer(ring
);
2232 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
2234 intel_unpin_ringbuffer_obj(ring
->buffer
);
2235 intel_ringbuffer_free(ring
->buffer
);
2236 ring
->buffer
= NULL
;
2240 ring
->cleanup(ring
);
2242 if (I915_NEED_GFX_HWS(ring
->dev
)) {
2243 cleanup_status_page(ring
);
2245 WARN_ON(ring
->id
!= RCS
);
2246 cleanup_phys_status_page(ring
);
2249 i915_cmd_parser_fini_ring(ring
);
2250 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2254 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
2256 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2257 struct drm_i915_gem_request
*request
;
2261 if (intel_ring_space(ringbuf
) >= n
)
2264 /* The whole point of reserving space is to not wait! */
2265 WARN_ON(ringbuf
->reserved_in_use
);
2267 list_for_each_entry(request
, &ring
->request_list
, list
) {
2268 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
2274 if (WARN_ON(&request
->list
== &ring
->request_list
))
2277 ret
= i915_wait_request(request
);
2281 ringbuf
->space
= space
;
2285 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
2287 uint32_t __iomem
*virt
;
2288 int rem
= ringbuf
->size
- ringbuf
->tail
;
2290 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2293 iowrite32(MI_NOOP
, virt
++);
2296 intel_ring_update_space(ringbuf
);
2299 int intel_ring_idle(struct intel_engine_cs
*ring
)
2301 struct drm_i915_gem_request
*req
;
2303 /* Wait upon the last request to be completed */
2304 if (list_empty(&ring
->request_list
))
2307 req
= list_entry(ring
->request_list
.prev
,
2308 struct drm_i915_gem_request
,
2311 /* Make sure we do not trigger any retires */
2312 return __i915_wait_request(req
,
2313 atomic_read(&to_i915(ring
->dev
)->gpu_error
.reset_counter
),
2314 to_i915(ring
->dev
)->mm
.interruptible
,
2318 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2320 request
->ringbuf
= request
->ring
->buffer
;
2324 int intel_ring_reserve_space(struct drm_i915_gem_request
*request
)
2327 * The first call merely notes the reserve request and is common for
2328 * all back ends. The subsequent localised _begin() call actually
2329 * ensures that the reservation is available. Without the begin, if
2330 * the request creator immediately submitted the request without
2331 * adding any commands to it then there might not actually be
2332 * sufficient room for the submission commands.
2334 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
2336 return intel_ring_begin(request
, 0);
2339 void intel_ring_reserved_space_reserve(struct intel_ringbuffer
*ringbuf
, int size
)
2341 WARN_ON(ringbuf
->reserved_size
);
2342 WARN_ON(ringbuf
->reserved_in_use
);
2344 ringbuf
->reserved_size
= size
;
2347 void intel_ring_reserved_space_cancel(struct intel_ringbuffer
*ringbuf
)
2349 WARN_ON(ringbuf
->reserved_in_use
);
2351 ringbuf
->reserved_size
= 0;
2352 ringbuf
->reserved_in_use
= false;
2355 void intel_ring_reserved_space_use(struct intel_ringbuffer
*ringbuf
)
2357 WARN_ON(ringbuf
->reserved_in_use
);
2359 ringbuf
->reserved_in_use
= true;
2360 ringbuf
->reserved_tail
= ringbuf
->tail
;
2363 void intel_ring_reserved_space_end(struct intel_ringbuffer
*ringbuf
)
2365 WARN_ON(!ringbuf
->reserved_in_use
);
2366 if (ringbuf
->tail
> ringbuf
->reserved_tail
) {
2367 WARN(ringbuf
->tail
> ringbuf
->reserved_tail
+ ringbuf
->reserved_size
,
2368 "request reserved size too small: %d vs %d!\n",
2369 ringbuf
->tail
- ringbuf
->reserved_tail
, ringbuf
->reserved_size
);
2372 * The ring was wrapped while the reserved space was in use.
2373 * That means that some unknown amount of the ring tail was
2374 * no-op filled and skipped. Thus simply adding the ring size
2375 * to the tail and doing the above space check will not work.
2376 * Rather than attempt to track how much tail was skipped,
2377 * it is much simpler to say that also skipping the sanity
2378 * check every once in a while is not a big issue.
2382 ringbuf
->reserved_size
= 0;
2383 ringbuf
->reserved_in_use
= false;
2386 static int __intel_ring_prepare(struct intel_engine_cs
*ring
, int bytes
)
2388 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2389 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2390 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2391 int ret
, total_bytes
, wait_bytes
= 0;
2392 bool need_wrap
= false;
2394 if (ringbuf
->reserved_in_use
)
2395 total_bytes
= bytes
;
2397 total_bytes
= bytes
+ ringbuf
->reserved_size
;
2399 if (unlikely(bytes
> remain_usable
)) {
2401 * Not enough space for the basic request. So need to flush
2402 * out the remainder and then wait for base + reserved.
2404 wait_bytes
= remain_actual
+ total_bytes
;
2407 if (unlikely(total_bytes
> remain_usable
)) {
2409 * The base request will fit but the reserved space
2410 * falls off the end. So only need to to wait for the
2411 * reserved size after flushing out the remainder.
2413 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
2415 } else if (total_bytes
> ringbuf
->space
) {
2416 /* No wrapping required, just waiting. */
2417 wait_bytes
= total_bytes
;
2422 ret
= ring_wait_for_space(ring
, wait_bytes
);
2427 __wrap_ring_buffer(ringbuf
);
2433 int intel_ring_begin(struct drm_i915_gem_request
*req
,
2436 struct intel_engine_cs
*ring
;
2437 struct drm_i915_private
*dev_priv
;
2440 WARN_ON(req
== NULL
);
2442 dev_priv
= ring
->dev
->dev_private
;
2444 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2445 dev_priv
->mm
.interruptible
);
2449 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2453 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2457 /* Align the ring tail to a cacheline boundary */
2458 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2460 struct intel_engine_cs
*ring
= req
->ring
;
2461 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2464 if (num_dwords
== 0)
2467 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2468 ret
= intel_ring_begin(req
, num_dwords
);
2472 while (num_dwords
--)
2473 intel_ring_emit(ring
, MI_NOOP
);
2475 intel_ring_advance(ring
);
2480 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2482 struct drm_device
*dev
= ring
->dev
;
2483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2485 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2486 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2487 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2489 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2492 ring
->set_seqno(ring
, seqno
);
2493 ring
->hangcheck
.seqno
= seqno
;
2496 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2499 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2501 /* Every tail move must follow the sequence below */
2503 /* Disable notification that the ring is IDLE. The GT
2504 * will then assume that it is busy and bring it out of rc6.
2506 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2507 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2509 /* Clear the context id. Here be magic! */
2510 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2512 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2513 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2514 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2516 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2518 /* Now that the ring is fully powered up, update the tail */
2519 I915_WRITE_TAIL(ring
, value
);
2520 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2522 /* Let the ring send IDLE messages to the GT again,
2523 * and so let it sleep to conserve power when idle.
2525 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2526 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2529 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2530 u32 invalidate
, u32 flush
)
2532 struct intel_engine_cs
*ring
= req
->ring
;
2536 ret
= intel_ring_begin(req
, 4);
2541 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2544 /* We always require a command barrier so that subsequent
2545 * commands, such as breadcrumb interrupts, are strictly ordered
2546 * wrt the contents of the write cache being flushed to memory
2547 * (and thus being coherent from the CPU).
2549 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2552 * Bspec vol 1c.5 - video engine command streamer:
2553 * "If ENABLED, all TLBs will be invalidated once the flush
2554 * operation is complete. This bit is only valid when the
2555 * Post-Sync Operation field is a value of 1h or 3h."
2557 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2558 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2560 intel_ring_emit(ring
, cmd
);
2561 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2562 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2563 intel_ring_emit(ring
, 0); /* upper addr */
2564 intel_ring_emit(ring
, 0); /* value */
2566 intel_ring_emit(ring
, 0);
2567 intel_ring_emit(ring
, MI_NOOP
);
2569 intel_ring_advance(ring
);
2574 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2575 u64 offset
, u32 len
,
2576 unsigned dispatch_flags
)
2578 struct intel_engine_cs
*ring
= req
->ring
;
2579 bool ppgtt
= USES_PPGTT(ring
->dev
) &&
2580 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2583 ret
= intel_ring_begin(req
, 4);
2587 /* FIXME(BDW): Address space and security selectors. */
2588 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2589 (dispatch_flags
& I915_DISPATCH_RS
?
2590 MI_BATCH_RESOURCE_STREAMER
: 0));
2591 intel_ring_emit(ring
, lower_32_bits(offset
));
2592 intel_ring_emit(ring
, upper_32_bits(offset
));
2593 intel_ring_emit(ring
, MI_NOOP
);
2594 intel_ring_advance(ring
);
2600 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2601 u64 offset
, u32 len
,
2602 unsigned dispatch_flags
)
2604 struct intel_engine_cs
*ring
= req
->ring
;
2607 ret
= intel_ring_begin(req
, 2);
2611 intel_ring_emit(ring
,
2612 MI_BATCH_BUFFER_START
|
2613 (dispatch_flags
& I915_DISPATCH_SECURE
?
2614 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2615 (dispatch_flags
& I915_DISPATCH_RS
?
2616 MI_BATCH_RESOURCE_STREAMER
: 0));
2617 /* bit0-7 is the length on GEN6+ */
2618 intel_ring_emit(ring
, offset
);
2619 intel_ring_advance(ring
);
2625 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2626 u64 offset
, u32 len
,
2627 unsigned dispatch_flags
)
2629 struct intel_engine_cs
*ring
= req
->ring
;
2632 ret
= intel_ring_begin(req
, 2);
2636 intel_ring_emit(ring
,
2637 MI_BATCH_BUFFER_START
|
2638 (dispatch_flags
& I915_DISPATCH_SECURE
?
2639 0 : MI_BATCH_NON_SECURE_I965
));
2640 /* bit0-7 is the length on GEN6+ */
2641 intel_ring_emit(ring
, offset
);
2642 intel_ring_advance(ring
);
2647 /* Blitter support (SandyBridge+) */
2649 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2650 u32 invalidate
, u32 flush
)
2652 struct intel_engine_cs
*ring
= req
->ring
;
2653 struct drm_device
*dev
= ring
->dev
;
2657 ret
= intel_ring_begin(req
, 4);
2662 if (INTEL_INFO(dev
)->gen
>= 8)
2665 /* We always require a command barrier so that subsequent
2666 * commands, such as breadcrumb interrupts, are strictly ordered
2667 * wrt the contents of the write cache being flushed to memory
2668 * (and thus being coherent from the CPU).
2670 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2673 * Bspec vol 1c.3 - blitter engine command streamer:
2674 * "If ENABLED, all TLBs will be invalidated once the flush
2675 * operation is complete. This bit is only valid when the
2676 * Post-Sync Operation field is a value of 1h or 3h."
2678 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2679 cmd
|= MI_INVALIDATE_TLB
;
2680 intel_ring_emit(ring
, cmd
);
2681 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2682 if (INTEL_INFO(dev
)->gen
>= 8) {
2683 intel_ring_emit(ring
, 0); /* upper addr */
2684 intel_ring_emit(ring
, 0); /* value */
2686 intel_ring_emit(ring
, 0);
2687 intel_ring_emit(ring
, MI_NOOP
);
2689 intel_ring_advance(ring
);
2694 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2698 struct drm_i915_gem_object
*obj
;
2701 ring
->name
= "render ring";
2703 ring
->exec_id
= I915_EXEC_RENDER
;
2704 ring
->mmio_base
= RENDER_RING_BASE
;
2706 if (INTEL_INFO(dev
)->gen
>= 8) {
2707 if (i915_semaphore_is_enabled(dev
)) {
2708 obj
= i915_gem_alloc_object(dev
, 4096);
2710 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2711 i915
.semaphores
= 0;
2713 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2714 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2716 drm_gem_object_unreference(&obj
->base
);
2717 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2718 i915
.semaphores
= 0;
2720 dev_priv
->semaphore_obj
= obj
;
2724 ring
->init_context
= intel_rcs_ctx_init
;
2725 ring
->add_request
= gen6_add_request
;
2726 ring
->flush
= gen8_render_ring_flush
;
2727 ring
->irq_get
= gen8_ring_get_irq
;
2728 ring
->irq_put
= gen8_ring_put_irq
;
2729 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2730 ring
->get_seqno
= gen6_ring_get_seqno
;
2731 ring
->set_seqno
= ring_set_seqno
;
2732 if (i915_semaphore_is_enabled(dev
)) {
2733 WARN_ON(!dev_priv
->semaphore_obj
);
2734 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2735 ring
->semaphore
.signal
= gen8_rcs_signal
;
2736 GEN8_RING_SEMAPHORE_INIT
;
2738 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2739 ring
->init_context
= intel_rcs_ctx_init
;
2740 ring
->add_request
= gen6_add_request
;
2741 ring
->flush
= gen7_render_ring_flush
;
2742 if (INTEL_INFO(dev
)->gen
== 6)
2743 ring
->flush
= gen6_render_ring_flush
;
2744 ring
->irq_get
= gen6_ring_get_irq
;
2745 ring
->irq_put
= gen6_ring_put_irq
;
2746 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2747 ring
->get_seqno
= gen6_ring_get_seqno
;
2748 ring
->set_seqno
= ring_set_seqno
;
2749 if (i915_semaphore_is_enabled(dev
)) {
2750 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2751 ring
->semaphore
.signal
= gen6_signal
;
2753 * The current semaphore is only applied on pre-gen8
2754 * platform. And there is no VCS2 ring on the pre-gen8
2755 * platform. So the semaphore between RCS and VCS2 is
2756 * initialized as INVALID. Gen8 will initialize the
2757 * sema between VCS2 and RCS later.
2759 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2760 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2761 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2762 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2763 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2764 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2765 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2766 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2767 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2768 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2770 } else if (IS_GEN5(dev
)) {
2771 ring
->add_request
= pc_render_add_request
;
2772 ring
->flush
= gen4_render_ring_flush
;
2773 ring
->get_seqno
= pc_render_get_seqno
;
2774 ring
->set_seqno
= pc_render_set_seqno
;
2775 ring
->irq_get
= gen5_ring_get_irq
;
2776 ring
->irq_put
= gen5_ring_put_irq
;
2777 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2778 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2780 ring
->add_request
= i9xx_add_request
;
2781 if (INTEL_INFO(dev
)->gen
< 4)
2782 ring
->flush
= gen2_render_ring_flush
;
2784 ring
->flush
= gen4_render_ring_flush
;
2785 ring
->get_seqno
= ring_get_seqno
;
2786 ring
->set_seqno
= ring_set_seqno
;
2788 ring
->irq_get
= i8xx_ring_get_irq
;
2789 ring
->irq_put
= i8xx_ring_put_irq
;
2791 ring
->irq_get
= i9xx_ring_get_irq
;
2792 ring
->irq_put
= i9xx_ring_put_irq
;
2794 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2796 ring
->write_tail
= ring_write_tail
;
2798 if (IS_HASWELL(dev
))
2799 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2800 else if (IS_GEN8(dev
))
2801 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2802 else if (INTEL_INFO(dev
)->gen
>= 6)
2803 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2804 else if (INTEL_INFO(dev
)->gen
>= 4)
2805 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2806 else if (IS_I830(dev
) || IS_845G(dev
))
2807 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2809 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2810 ring
->init_hw
= init_render_ring
;
2811 ring
->cleanup
= render_ring_cleanup
;
2813 /* Workaround batchbuffer to combat CS tlb bug. */
2814 if (HAS_BROKEN_CS_TLB(dev
)) {
2815 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2817 DRM_ERROR("Failed to allocate batch bo\n");
2821 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2823 drm_gem_object_unreference(&obj
->base
);
2824 DRM_ERROR("Failed to ping batch bo\n");
2828 ring
->scratch
.obj
= obj
;
2829 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2832 ret
= intel_init_ring_buffer(dev
, ring
);
2836 if (INTEL_INFO(dev
)->gen
>= 5) {
2837 ret
= intel_init_pipe_control(ring
);
2845 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2848 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2850 ring
->name
= "bsd ring";
2852 ring
->exec_id
= I915_EXEC_BSD
;
2854 ring
->write_tail
= ring_write_tail
;
2855 if (INTEL_INFO(dev
)->gen
>= 6) {
2856 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2857 /* gen6 bsd needs a special wa for tail updates */
2859 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2860 ring
->flush
= gen6_bsd_ring_flush
;
2861 ring
->add_request
= gen6_add_request
;
2862 ring
->get_seqno
= gen6_ring_get_seqno
;
2863 ring
->set_seqno
= ring_set_seqno
;
2864 if (INTEL_INFO(dev
)->gen
>= 8) {
2865 ring
->irq_enable_mask
=
2866 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2867 ring
->irq_get
= gen8_ring_get_irq
;
2868 ring
->irq_put
= gen8_ring_put_irq
;
2869 ring
->dispatch_execbuffer
=
2870 gen8_ring_dispatch_execbuffer
;
2871 if (i915_semaphore_is_enabled(dev
)) {
2872 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2873 ring
->semaphore
.signal
= gen8_xcs_signal
;
2874 GEN8_RING_SEMAPHORE_INIT
;
2877 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2878 ring
->irq_get
= gen6_ring_get_irq
;
2879 ring
->irq_put
= gen6_ring_put_irq
;
2880 ring
->dispatch_execbuffer
=
2881 gen6_ring_dispatch_execbuffer
;
2882 if (i915_semaphore_is_enabled(dev
)) {
2883 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2884 ring
->semaphore
.signal
= gen6_signal
;
2885 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2886 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2887 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2888 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2889 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2890 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2891 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2892 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2893 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2894 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2898 ring
->mmio_base
= BSD_RING_BASE
;
2899 ring
->flush
= bsd_ring_flush
;
2900 ring
->add_request
= i9xx_add_request
;
2901 ring
->get_seqno
= ring_get_seqno
;
2902 ring
->set_seqno
= ring_set_seqno
;
2904 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2905 ring
->irq_get
= gen5_ring_get_irq
;
2906 ring
->irq_put
= gen5_ring_put_irq
;
2908 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2909 ring
->irq_get
= i9xx_ring_get_irq
;
2910 ring
->irq_put
= i9xx_ring_put_irq
;
2912 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2914 ring
->init_hw
= init_ring_common
;
2916 return intel_init_ring_buffer(dev
, ring
);
2920 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2922 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2925 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2927 ring
->name
= "bsd2 ring";
2929 ring
->exec_id
= I915_EXEC_BSD
;
2931 ring
->write_tail
= ring_write_tail
;
2932 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2933 ring
->flush
= gen6_bsd_ring_flush
;
2934 ring
->add_request
= gen6_add_request
;
2935 ring
->get_seqno
= gen6_ring_get_seqno
;
2936 ring
->set_seqno
= ring_set_seqno
;
2937 ring
->irq_enable_mask
=
2938 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2939 ring
->irq_get
= gen8_ring_get_irq
;
2940 ring
->irq_put
= gen8_ring_put_irq
;
2941 ring
->dispatch_execbuffer
=
2942 gen8_ring_dispatch_execbuffer
;
2943 if (i915_semaphore_is_enabled(dev
)) {
2944 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2945 ring
->semaphore
.signal
= gen8_xcs_signal
;
2946 GEN8_RING_SEMAPHORE_INIT
;
2948 ring
->init_hw
= init_ring_common
;
2950 return intel_init_ring_buffer(dev
, ring
);
2953 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2956 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2958 ring
->name
= "blitter ring";
2960 ring
->exec_id
= I915_EXEC_BLT
;
2962 ring
->mmio_base
= BLT_RING_BASE
;
2963 ring
->write_tail
= ring_write_tail
;
2964 ring
->flush
= gen6_ring_flush
;
2965 ring
->add_request
= gen6_add_request
;
2966 ring
->get_seqno
= gen6_ring_get_seqno
;
2967 ring
->set_seqno
= ring_set_seqno
;
2968 if (INTEL_INFO(dev
)->gen
>= 8) {
2969 ring
->irq_enable_mask
=
2970 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2971 ring
->irq_get
= gen8_ring_get_irq
;
2972 ring
->irq_put
= gen8_ring_put_irq
;
2973 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2974 if (i915_semaphore_is_enabled(dev
)) {
2975 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2976 ring
->semaphore
.signal
= gen8_xcs_signal
;
2977 GEN8_RING_SEMAPHORE_INIT
;
2980 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2981 ring
->irq_get
= gen6_ring_get_irq
;
2982 ring
->irq_put
= gen6_ring_put_irq
;
2983 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2984 if (i915_semaphore_is_enabled(dev
)) {
2985 ring
->semaphore
.signal
= gen6_signal
;
2986 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2988 * The current semaphore is only applied on pre-gen8
2989 * platform. And there is no VCS2 ring on the pre-gen8
2990 * platform. So the semaphore between BCS and VCS2 is
2991 * initialized as INVALID. Gen8 will initialize the
2992 * sema between BCS and VCS2 later.
2994 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2995 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2996 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2997 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2998 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2999 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
3000 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
3001 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
3002 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
3003 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3006 ring
->init_hw
= init_ring_common
;
3008 return intel_init_ring_buffer(dev
, ring
);
3011 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
3013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3014 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
3016 ring
->name
= "video enhancement ring";
3018 ring
->exec_id
= I915_EXEC_VEBOX
;
3020 ring
->mmio_base
= VEBOX_RING_BASE
;
3021 ring
->write_tail
= ring_write_tail
;
3022 ring
->flush
= gen6_ring_flush
;
3023 ring
->add_request
= gen6_add_request
;
3024 ring
->get_seqno
= gen6_ring_get_seqno
;
3025 ring
->set_seqno
= ring_set_seqno
;
3027 if (INTEL_INFO(dev
)->gen
>= 8) {
3028 ring
->irq_enable_mask
=
3029 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3030 ring
->irq_get
= gen8_ring_get_irq
;
3031 ring
->irq_put
= gen8_ring_put_irq
;
3032 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3033 if (i915_semaphore_is_enabled(dev
)) {
3034 ring
->semaphore
.sync_to
= gen8_ring_sync
;
3035 ring
->semaphore
.signal
= gen8_xcs_signal
;
3036 GEN8_RING_SEMAPHORE_INIT
;
3039 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3040 ring
->irq_get
= hsw_vebox_get_irq
;
3041 ring
->irq_put
= hsw_vebox_put_irq
;
3042 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3043 if (i915_semaphore_is_enabled(dev
)) {
3044 ring
->semaphore
.sync_to
= gen6_ring_sync
;
3045 ring
->semaphore
.signal
= gen6_signal
;
3046 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
3047 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
3048 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
3049 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
3050 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3051 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
3052 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
3053 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
3054 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
3055 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3058 ring
->init_hw
= init_ring_common
;
3060 return intel_init_ring_buffer(dev
, ring
);
3064 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3066 struct intel_engine_cs
*ring
= req
->ring
;
3069 if (!ring
->gpu_caches_dirty
)
3072 ret
= ring
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3076 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3078 ring
->gpu_caches_dirty
= false;
3083 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3085 struct intel_engine_cs
*ring
= req
->ring
;
3086 uint32_t flush_domains
;
3090 if (ring
->gpu_caches_dirty
)
3091 flush_domains
= I915_GEM_GPU_DOMAINS
;
3093 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3097 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3099 ring
->gpu_caches_dirty
= false;
3104 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
3108 if (!intel_ring_initialized(ring
))
3111 ret
= intel_ring_idle(ring
);
3112 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
3113 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",