2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 int __intel_ring_space(int head
, int tail
, int size
)
39 int space
= head
- tail
;
42 return space
- I915_RING_FREE_SPACE
;
45 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
47 if (ringbuf
->last_retired_head
!= -1) {
48 ringbuf
->head
= ringbuf
->last_retired_head
;
49 ringbuf
->last_retired_head
= -1;
52 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
53 ringbuf
->tail
, ringbuf
->size
);
56 bool intel_engine_stopped(struct intel_engine_cs
*engine
)
58 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
59 return dev_priv
->gpu_error
.stop_rings
& intel_engine_flag(engine
);
62 static void __intel_ring_advance(struct intel_engine_cs
*engine
)
64 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
65 ringbuf
->tail
&= ringbuf
->size
- 1;
66 if (intel_engine_stopped(engine
))
68 engine
->write_tail(engine
, ringbuf
->tail
);
72 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
73 u32 invalidate_domains
,
76 struct intel_engine_cs
*engine
= req
->engine
;
81 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
82 cmd
|= MI_NO_WRITE_FLUSH
;
84 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
87 ret
= intel_ring_begin(req
, 2);
91 intel_ring_emit(engine
, cmd
);
92 intel_ring_emit(engine
, MI_NOOP
);
93 intel_ring_advance(engine
);
99 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
100 u32 invalidate_domains
,
103 struct intel_engine_cs
*engine
= req
->engine
;
104 struct drm_device
*dev
= engine
->dev
;
111 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
112 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
113 * also flushed at 2d versus 3d pipeline switches.
117 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
118 * MI_READ_FLUSH is set, and is always flushed on 965.
120 * I915_GEM_DOMAIN_COMMAND may not exist?
122 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
123 * invalidated when MI_EXE_FLUSH is set.
125 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
126 * invalidated with every MI_FLUSH.
130 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
131 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
132 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
133 * are flushed at any MI_FLUSH.
136 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
137 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
138 cmd
&= ~MI_NO_WRITE_FLUSH
;
139 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
142 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
143 (IS_G4X(dev
) || IS_GEN5(dev
)))
144 cmd
|= MI_INVALIDATE_ISP
;
146 ret
= intel_ring_begin(req
, 2);
150 intel_ring_emit(engine
, cmd
);
151 intel_ring_emit(engine
, MI_NOOP
);
152 intel_ring_advance(engine
);
158 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
159 * implementing two workarounds on gen6. From section 1.4.7.1
160 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
162 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
163 * produced by non-pipelined state commands), software needs to first
164 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
167 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
168 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
170 * And the workaround for these two requires this workaround first:
172 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
173 * BEFORE the pipe-control with a post-sync op and no write-cache
176 * And this last workaround is tricky because of the requirements on
177 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
180 * "1 of the following must also be set:
181 * - Render Target Cache Flush Enable ([12] of DW1)
182 * - Depth Cache Flush Enable ([0] of DW1)
183 * - Stall at Pixel Scoreboard ([1] of DW1)
184 * - Depth Stall ([13] of DW1)
185 * - Post-Sync Operation ([13] of DW1)
186 * - Notify Enable ([8] of DW1)"
188 * The cache flushes require the workaround flush that triggered this
189 * one, so we can't use it. Depth stall would trigger the same.
190 * Post-sync nonzero is what triggered this second workaround, so we
191 * can't use that one either. Notify enable is IRQs, which aren't
192 * really our business. That leaves only stall at scoreboard.
195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
197 struct intel_engine_cs
*engine
= req
->engine
;
198 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
201 ret
= intel_ring_begin(req
, 6);
205 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
206 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
207 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
208 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
209 intel_ring_emit(engine
, 0); /* low dword */
210 intel_ring_emit(engine
, 0); /* high dword */
211 intel_ring_emit(engine
, MI_NOOP
);
212 intel_ring_advance(engine
);
214 ret
= intel_ring_begin(req
, 6);
218 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
219 intel_ring_emit(engine
, PIPE_CONTROL_QW_WRITE
);
220 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
221 intel_ring_emit(engine
, 0);
222 intel_ring_emit(engine
, 0);
223 intel_ring_emit(engine
, MI_NOOP
);
224 intel_ring_advance(engine
);
230 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
231 u32 invalidate_domains
, u32 flush_domains
)
233 struct intel_engine_cs
*engine
= req
->engine
;
235 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
238 /* Force SNB workarounds for PIPE_CONTROL flushes */
239 ret
= intel_emit_post_sync_nonzero_flush(req
);
243 /* Just flush everything. Experiments have shown that reducing the
244 * number of bits based on the write domains has little performance
248 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
249 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
251 * Ensure that any following seqno writes only happen
252 * when the render cache is indeed flushed.
254 flags
|= PIPE_CONTROL_CS_STALL
;
256 if (invalidate_domains
) {
257 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
258 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
259 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
260 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
261 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
262 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
264 * TLB invalidate requires a post-sync write.
266 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
269 ret
= intel_ring_begin(req
, 4);
273 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(engine
, flags
);
275 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
276 intel_ring_emit(engine
, 0);
277 intel_ring_advance(engine
);
283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
285 struct intel_engine_cs
*engine
= req
->engine
;
288 ret
= intel_ring_begin(req
, 4);
292 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
294 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
295 intel_ring_emit(engine
, 0);
296 intel_ring_emit(engine
, 0);
297 intel_ring_advance(engine
);
303 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
304 u32 invalidate_domains
, u32 flush_domains
)
306 struct intel_engine_cs
*engine
= req
->engine
;
308 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
312 * Ensure that any following seqno writes only happen when the render
313 * cache is indeed flushed.
315 * Workaround: 4th PIPE_CONTROL command (except the ones with only
316 * read-cache invalidate bits set) must have the CS_STALL bit set. We
317 * don't try to be clever and just set it unconditionally.
319 flags
|= PIPE_CONTROL_CS_STALL
;
321 /* Just flush everything. Experiments have shown that reducing the
322 * number of bits based on the write domains has little performance
326 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
327 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
328 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
329 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
331 if (invalidate_domains
) {
332 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
333 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
334 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
335 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
336 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
337 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
338 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
340 * TLB invalidate requires a post-sync write.
342 flags
|= PIPE_CONTROL_QW_WRITE
;
343 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
345 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
347 /* Workaround: we must issue a pipe_control with CS-stall bit
348 * set before a pipe_control command that has the state cache
349 * invalidate bit set. */
350 gen7_render_ring_cs_stall_wa(req
);
353 ret
= intel_ring_begin(req
, 4);
357 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
358 intel_ring_emit(engine
, flags
);
359 intel_ring_emit(engine
, scratch_addr
);
360 intel_ring_emit(engine
, 0);
361 intel_ring_advance(engine
);
367 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
368 u32 flags
, u32 scratch_addr
)
370 struct intel_engine_cs
*engine
= req
->engine
;
373 ret
= intel_ring_begin(req
, 6);
377 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
378 intel_ring_emit(engine
, flags
);
379 intel_ring_emit(engine
, scratch_addr
);
380 intel_ring_emit(engine
, 0);
381 intel_ring_emit(engine
, 0);
382 intel_ring_emit(engine
, 0);
383 intel_ring_advance(engine
);
389 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
390 u32 invalidate_domains
, u32 flush_domains
)
393 u32 scratch_addr
= req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
396 flags
|= PIPE_CONTROL_CS_STALL
;
399 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
400 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
401 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
402 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
404 if (invalidate_domains
) {
405 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
406 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
407 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
408 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
409 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
410 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
411 flags
|= PIPE_CONTROL_QW_WRITE
;
412 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
414 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
415 ret
= gen8_emit_pipe_control(req
,
416 PIPE_CONTROL_CS_STALL
|
417 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
423 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
426 static void ring_write_tail(struct intel_engine_cs
*engine
,
429 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
430 I915_WRITE_TAIL(engine
, value
);
433 u64
intel_ring_get_active_head(struct intel_engine_cs
*engine
)
435 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
438 if (INTEL_INFO(engine
->dev
)->gen
>= 8)
439 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
440 RING_ACTHD_UDW(engine
->mmio_base
));
441 else if (INTEL_INFO(engine
->dev
)->gen
>= 4)
442 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
444 acthd
= I915_READ(ACTHD
);
449 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
451 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
454 addr
= dev_priv
->status_page_dmah
->busaddr
;
455 if (INTEL_INFO(engine
->dev
)->gen
>= 4)
456 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
457 I915_WRITE(HWS_PGA
, addr
);
460 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
462 struct drm_device
*dev
= engine
->dev
;
463 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
466 /* The ring status page addresses are no longer next to the rest of
467 * the ring registers as of gen7.
470 switch (engine
->id
) {
472 mmio
= RENDER_HWS_PGA_GEN7
;
475 mmio
= BLT_HWS_PGA_GEN7
;
478 * VCS2 actually doesn't exist on Gen7. Only shut up
479 * gcc switch check warning
483 mmio
= BSD_HWS_PGA_GEN7
;
486 mmio
= VEBOX_HWS_PGA_GEN7
;
489 } else if (IS_GEN6(engine
->dev
)) {
490 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
492 /* XXX: gen8 returns to sanity */
493 mmio
= RING_HWS_PGA(engine
->mmio_base
);
496 I915_WRITE(mmio
, (u32
)engine
->status_page
.gfx_addr
);
500 * Flush the TLB for this page
502 * FIXME: These two bits have disappeared on gen8, so a question
503 * arises: do we still need this and if so how should we go about
504 * invalidating the TLB?
506 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
507 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
509 /* ring should be idle before issuing a sync flush*/
510 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
513 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
515 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
517 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
522 static bool stop_ring(struct intel_engine_cs
*engine
)
524 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
526 if (!IS_GEN2(engine
->dev
)) {
527 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
528 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
529 DRM_ERROR("%s : timed out trying to stop ring\n",
531 /* Sometimes we observe that the idle flag is not
532 * set even though the ring is empty. So double
533 * check before giving up.
535 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
540 I915_WRITE_CTL(engine
, 0);
541 I915_WRITE_HEAD(engine
, 0);
542 engine
->write_tail(engine
, 0);
544 if (!IS_GEN2(engine
->dev
)) {
545 (void)I915_READ_CTL(engine
);
546 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
549 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
552 void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
)
554 memset(&engine
->hangcheck
, 0, sizeof(engine
->hangcheck
));
557 static int init_ring_common(struct intel_engine_cs
*engine
)
559 struct drm_device
*dev
= engine
->dev
;
560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
562 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
565 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
567 if (!stop_ring(engine
)) {
568 /* G45 ring initialization often fails to reset head to zero */
569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
572 I915_READ_CTL(engine
),
573 I915_READ_HEAD(engine
),
574 I915_READ_TAIL(engine
),
575 I915_READ_START(engine
));
577 if (!stop_ring(engine
)) {
578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
581 I915_READ_CTL(engine
),
582 I915_READ_HEAD(engine
),
583 I915_READ_TAIL(engine
),
584 I915_READ_START(engine
));
590 if (I915_NEED_GFX_HWS(dev
))
591 intel_ring_setup_status_page(engine
);
593 ring_setup_phys_status_page(engine
);
595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(engine
);
598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
602 I915_WRITE_START(engine
, i915_gem_obj_ggtt_offset(obj
));
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(engine
))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 engine
->name
, I915_READ_HEAD(engine
));
608 I915_WRITE_HEAD(engine
, 0);
609 (void)I915_READ_HEAD(engine
);
611 I915_WRITE_CTL(engine
,
612 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
615 /* If the head is still not zero, the ring is dead */
616 if (wait_for((I915_READ_CTL(engine
) & RING_VALID
) != 0 &&
617 I915_READ_START(engine
) == i915_gem_obj_ggtt_offset(obj
) &&
618 (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0, 50)) {
619 DRM_ERROR("%s initialization failed "
620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
622 I915_READ_CTL(engine
),
623 I915_READ_CTL(engine
) & RING_VALID
,
624 I915_READ_HEAD(engine
), I915_READ_TAIL(engine
),
625 I915_READ_START(engine
),
626 (unsigned long)i915_gem_obj_ggtt_offset(obj
));
631 ringbuf
->last_retired_head
= -1;
632 ringbuf
->head
= I915_READ_HEAD(engine
);
633 ringbuf
->tail
= I915_READ_TAIL(engine
) & TAIL_ADDR
;
634 intel_ring_update_space(ringbuf
);
636 intel_engine_init_hangcheck(engine
);
639 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
645 intel_fini_pipe_control(struct intel_engine_cs
*engine
)
647 struct drm_device
*dev
= engine
->dev
;
649 if (engine
->scratch
.obj
== NULL
)
652 if (INTEL_INFO(dev
)->gen
>= 5) {
653 kunmap(sg_page(engine
->scratch
.obj
->pages
->sgl
));
654 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
657 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
658 engine
->scratch
.obj
= NULL
;
662 intel_init_pipe_control(struct intel_engine_cs
*engine
)
666 WARN_ON(engine
->scratch
.obj
);
668 engine
->scratch
.obj
= i915_gem_alloc_object(engine
->dev
, 4096);
669 if (engine
->scratch
.obj
== NULL
) {
670 DRM_ERROR("Failed to allocate seqno page\n");
675 ret
= i915_gem_object_set_cache_level(engine
->scratch
.obj
,
680 ret
= i915_gem_obj_ggtt_pin(engine
->scratch
.obj
, 4096, 0);
684 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(engine
->scratch
.obj
);
685 engine
->scratch
.cpu_page
= kmap(sg_page(engine
->scratch
.obj
->pages
->sgl
));
686 if (engine
->scratch
.cpu_page
== NULL
) {
691 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
692 engine
->name
, engine
->scratch
.gtt_offset
);
696 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
698 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
703 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
706 struct intel_engine_cs
*engine
= req
->engine
;
707 struct drm_device
*dev
= engine
->dev
;
708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
709 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
714 engine
->gpu_caches_dirty
= true;
715 ret
= intel_ring_flush_all_caches(req
);
719 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
723 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(w
->count
));
724 for (i
= 0; i
< w
->count
; i
++) {
725 intel_ring_emit_reg(engine
, w
->reg
[i
].addr
);
726 intel_ring_emit(engine
, w
->reg
[i
].value
);
728 intel_ring_emit(engine
, MI_NOOP
);
730 intel_ring_advance(engine
);
732 engine
->gpu_caches_dirty
= true;
733 ret
= intel_ring_flush_all_caches(req
);
737 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
742 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
746 ret
= intel_ring_workarounds_emit(req
);
750 ret
= i915_gem_render_state_init(req
);
757 static int wa_add(struct drm_i915_private
*dev_priv
,
759 const u32 mask
, const u32 val
)
761 const u32 idx
= dev_priv
->workarounds
.count
;
763 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
766 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
767 dev_priv
->workarounds
.reg
[idx
].value
= val
;
768 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
770 dev_priv
->workarounds
.count
++;
775 #define WA_REG(addr, mask, val) do { \
776 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
781 #define WA_SET_BIT_MASKED(addr, mask) \
782 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
784 #define WA_CLR_BIT_MASKED(addr, mask) \
785 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
788 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
795 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
798 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
799 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
800 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
802 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
805 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
806 i915_mmio_reg_offset(reg
));
807 wa
->hw_whitelist_count
[engine
->id
]++;
812 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
814 struct drm_device
*dev
= engine
->dev
;
815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
817 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
819 /* WaDisableAsyncFlipPerfMode:bdw,chv */
820 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
822 /* WaDisablePartialInstShootdown:bdw,chv */
823 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
824 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
830 /* WaForceEnableNonCoherent:bdw,chv */
831 /* WaHdcDisableFetchWhenMasked:bdw,chv */
832 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
833 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
834 HDC_FORCE_NON_COHERENT
);
836 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
837 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
838 * polygons in the same 8x4 pixel/sample area to be processed without
839 * stalling waiting for the earlier ones to write to Hierarchical Z
842 * This optimization is off by default for BDW and CHV; turn it on.
844 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
846 /* Wa4x4STCOptimizationDisable:bdw,chv */
847 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
850 * BSpec recommends 8x4 when MSAA is used,
851 * however in practice 16x4 seems fastest.
853 * Note that PS/WM thread counts depend on the WIZ hashing
854 * disable bit, which we don't touch here, but it's good
855 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
857 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
858 GEN6_WIZ_HASHING_MASK
,
859 GEN6_WIZ_HASHING_16x4
);
864 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
867 struct drm_device
*dev
= engine
->dev
;
868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
870 ret
= gen8_init_workarounds(engine
);
874 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
875 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
877 /* WaDisableDopClockGating:bdw */
878 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
879 DOP_CLOCK_GATING_DISABLE
);
881 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
882 GEN8_SAMPLER_POWER_BYPASS_DIS
);
884 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
885 /* WaForceContextSaveRestoreNonCoherent:bdw */
886 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
887 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
888 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
893 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
896 struct drm_device
*dev
= engine
->dev
;
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
899 ret
= gen8_init_workarounds(engine
);
903 /* WaDisableThreadStallDopClockGating:chv */
904 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
906 /* Improve HiZ throughput on CHV. */
907 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
912 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
914 struct drm_device
*dev
= engine
->dev
;
915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
919 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
921 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
922 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
923 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
925 /* WaDisableKillLogic:bxt,skl,kbl */
926 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
929 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
930 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
931 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
932 FLOW_CONTROL_ENABLE
|
933 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
935 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
936 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
937 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
940 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
941 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
942 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
943 GEN9_DG_MIRROR_FIX_ENABLE
);
945 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
946 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
947 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
948 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
949 GEN9_RHWO_OPTIMIZATION_DISABLE
);
951 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
952 * but we do that in per ctx batchbuffer as there is an issue
953 * with this register not getting restored on ctx restore
957 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
958 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
959 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
960 GEN9_ENABLE_YV12_BUGFIX
|
961 GEN9_ENABLE_GPGPU_PREEMPTION
);
963 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
964 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
965 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
966 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
968 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
969 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
970 GEN9_CCS_TLB_PREFETCH_ENABLE
);
972 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
973 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_C0
) ||
974 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
975 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
976 PIXEL_MASK_CAMMING_DISABLE
);
978 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
979 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
980 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
981 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
983 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
984 * both tied to WaForceContextSaveRestoreNonCoherent
985 * in some hsds for skl. We keep the tie for all gen9. The
986 * documentation is a bit hazy and so we want to get common behaviour,
987 * even though there is no clear evidence we would need both on kbl/bxt.
988 * This area has been source of system hangs so we play it safe
989 * and mimic the skl regardless of what bspec says.
991 * Use Force Non-Coherent whenever executing a 3D context. This
992 * is a workaround for a possible hang in the unlikely event
993 * a TLB invalidation occurs during a PSD flush.
996 /* WaForceEnableNonCoherent:skl,bxt,kbl */
997 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
998 HDC_FORCE_NON_COHERENT
);
1000 /* WaDisableHDCInvalidation:skl,bxt,kbl */
1001 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
1002 BDW_DISABLE_HDC_INVALIDATION
);
1004 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1005 if (IS_SKYLAKE(dev_priv
) ||
1006 IS_KABYLAKE(dev_priv
) ||
1007 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1008 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
1009 GEN8_SAMPLER_POWER_BYPASS_DIS
);
1011 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1012 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
1014 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1015 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
1016 GEN8_LQSC_FLUSH_COHERENT_LINES
));
1018 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1019 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
1023 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1024 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
1028 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1029 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
1036 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
1038 struct drm_device
*dev
= engine
->dev
;
1039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 u8 vals
[3] = { 0, 0, 0 };
1043 for (i
= 0; i
< 3; i
++) {
1047 * Only consider slices where one, and only one, subslice has 7
1050 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1054 * subslice_7eu[i] != 0 (because of the check above) and
1055 * ss_max == 4 (maximum number of subslices possible per slice)
1059 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1063 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1066 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1067 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1068 GEN9_IZ_HASHING_MASK(2) |
1069 GEN9_IZ_HASHING_MASK(1) |
1070 GEN9_IZ_HASHING_MASK(0),
1071 GEN9_IZ_HASHING(2, vals
[2]) |
1072 GEN9_IZ_HASHING(1, vals
[1]) |
1073 GEN9_IZ_HASHING(0, vals
[0]));
1078 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
1081 struct drm_device
*dev
= engine
->dev
;
1082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1084 ret
= gen9_init_workarounds(engine
);
1089 * Actual WA is to disable percontext preemption granularity control
1090 * until D0 which is the default case so this is equivalent to
1091 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1093 if (IS_SKL_REVID(dev
, SKL_REVID_E0
, REVID_FOREVER
)) {
1094 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
1095 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
1098 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
)) {
1099 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1100 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1101 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1104 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1105 * involving this register should also be added to WA batch as required.
1107 if (IS_SKL_REVID(dev
, 0, SKL_REVID_E0
))
1108 /* WaDisableLSQCROPERFforOCL:skl */
1109 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1110 GEN8_LQSC_RO_PERF_DIS
);
1112 /* WaEnableGapsTsvCreditFix:skl */
1113 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
)) {
1114 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1115 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1118 /* WaDisablePowerCompilerClockGating:skl */
1119 if (IS_SKL_REVID(dev
, SKL_REVID_B0
, SKL_REVID_B0
))
1120 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1121 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1123 /* WaBarrierPerformanceFixDisable:skl */
1124 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_D0
))
1125 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1126 HDC_FENCE_DEST_SLM_DISABLE
|
1127 HDC_BARRIER_PERFORMANCE_DISABLE
);
1129 /* WaDisableSbeCacheDispatchPortSharing:skl */
1130 if (IS_SKL_REVID(dev
, 0, SKL_REVID_F0
))
1132 GEN7_HALF_SLICE_CHICKEN1
,
1133 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1135 /* WaDisableGafsUnitClkGating:skl */
1136 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1138 /* WaDisableLSQCROPERFforOCL:skl */
1139 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1143 return skl_tune_iz_hashing(engine
);
1146 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1149 struct drm_device
*dev
= engine
->dev
;
1150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1152 ret
= gen9_init_workarounds(engine
);
1156 /* WaStoreMultiplePTEenable:bxt */
1157 /* This is a requirement according to Hardware specification */
1158 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1159 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1161 /* WaSetClckGatingDisableMedia:bxt */
1162 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1163 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1164 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1167 /* WaDisableThreadStallDopClockGating:bxt */
1168 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1169 STALL_DOP_GATING_DISABLE
);
1171 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1172 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1174 GEN7_HALF_SLICE_CHICKEN1
,
1175 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1178 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1179 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1180 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1181 /* WaDisableLSQCROPERFforOCL:bxt */
1182 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1183 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1187 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1192 /* WaInsertDummyPushConstPs:bxt */
1193 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1194 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1195 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1200 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1202 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1205 ret
= gen9_init_workarounds(engine
);
1209 /* WaEnableGapsTsvCreditFix:kbl */
1210 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1211 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1213 /* WaDisableDynamicCreditSharing:kbl */
1214 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1215 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1216 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1218 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1219 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1220 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1221 HDC_FENCE_DEST_SLM_DISABLE
);
1223 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1224 * involving this register should also be added to WA batch as required.
1226 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1227 /* WaDisableLSQCROPERFforOCL:kbl */
1228 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1229 GEN8_LQSC_RO_PERF_DIS
);
1231 /* WaInsertDummyPushConstPs:kbl */
1232 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1233 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1234 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1236 /* WaDisableGafsUnitClkGating:kbl */
1237 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1239 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1241 GEN7_HALF_SLICE_CHICKEN1
,
1242 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1244 /* WaDisableLSQCROPERFforOCL:kbl */
1245 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1252 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1254 struct drm_device
*dev
= engine
->dev
;
1255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1257 WARN_ON(engine
->id
!= RCS
);
1259 dev_priv
->workarounds
.count
= 0;
1260 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1262 if (IS_BROADWELL(dev
))
1263 return bdw_init_workarounds(engine
);
1265 if (IS_CHERRYVIEW(dev
))
1266 return chv_init_workarounds(engine
);
1268 if (IS_SKYLAKE(dev
))
1269 return skl_init_workarounds(engine
);
1271 if (IS_BROXTON(dev
))
1272 return bxt_init_workarounds(engine
);
1274 if (IS_KABYLAKE(dev_priv
))
1275 return kbl_init_workarounds(engine
);
1280 static int init_render_ring(struct intel_engine_cs
*engine
)
1282 struct drm_device
*dev
= engine
->dev
;
1283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1284 int ret
= init_ring_common(engine
);
1288 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1289 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1290 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1292 /* We need to disable the AsyncFlip performance optimisations in order
1293 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1294 * programmed to '1' on all products.
1296 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1298 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1299 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1301 /* Required for the hardware to program scanline values for waiting */
1302 /* WaEnableFlushTlbInvalidationMode:snb */
1303 if (INTEL_INFO(dev
)->gen
== 6)
1304 I915_WRITE(GFX_MODE
,
1305 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1307 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1309 I915_WRITE(GFX_MODE_GEN7
,
1310 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1311 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1314 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1315 * "If this bit is set, STCunit will have LRA as replacement
1316 * policy. [...] This bit must be reset. LRA replacement
1317 * policy is not supported."
1319 I915_WRITE(CACHE_MODE_0
,
1320 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1323 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1324 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1326 if (HAS_L3_DPF(dev
))
1327 I915_WRITE_IMR(engine
, ~GT_PARITY_ERROR(dev
));
1329 return init_workarounds_ring(engine
);
1332 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1334 struct drm_device
*dev
= engine
->dev
;
1335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1337 if (dev_priv
->semaphore_obj
) {
1338 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1339 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1340 dev_priv
->semaphore_obj
= NULL
;
1343 intel_fini_pipe_control(engine
);
1346 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1347 unsigned int num_dwords
)
1349 #define MBOX_UPDATE_DWORDS 8
1350 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1351 struct drm_device
*dev
= signaller
->dev
;
1352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1353 struct intel_engine_cs
*waiter
;
1354 enum intel_engine_id id
;
1357 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1358 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1359 #undef MBOX_UPDATE_DWORDS
1361 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1365 for_each_engine_id(waiter
, dev_priv
, id
) {
1367 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1368 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1371 seqno
= i915_gem_request_get_seqno(signaller_req
);
1372 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1373 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1374 PIPE_CONTROL_QW_WRITE
|
1375 PIPE_CONTROL_FLUSH_ENABLE
);
1376 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1377 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1378 intel_ring_emit(signaller
, seqno
);
1379 intel_ring_emit(signaller
, 0);
1380 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1381 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1382 intel_ring_emit(signaller
, 0);
1388 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1389 unsigned int num_dwords
)
1391 #define MBOX_UPDATE_DWORDS 6
1392 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1393 struct drm_device
*dev
= signaller
->dev
;
1394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1395 struct intel_engine_cs
*waiter
;
1396 enum intel_engine_id id
;
1399 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1400 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1401 #undef MBOX_UPDATE_DWORDS
1403 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1407 for_each_engine_id(waiter
, dev_priv
, id
) {
1409 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1410 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1413 seqno
= i915_gem_request_get_seqno(signaller_req
);
1414 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1415 MI_FLUSH_DW_OP_STOREDW
);
1416 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1417 MI_FLUSH_DW_USE_GTT
);
1418 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1419 intel_ring_emit(signaller
, seqno
);
1420 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1421 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1422 intel_ring_emit(signaller
, 0);
1428 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1429 unsigned int num_dwords
)
1431 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1432 struct drm_device
*dev
= signaller
->dev
;
1433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1434 struct intel_engine_cs
*useless
;
1435 enum intel_engine_id id
;
1438 #define MBOX_UPDATE_DWORDS 3
1439 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1440 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1441 #undef MBOX_UPDATE_DWORDS
1443 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1447 for_each_engine_id(useless
, dev_priv
, id
) {
1448 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[id
];
1450 if (i915_mmio_reg_valid(mbox_reg
)) {
1451 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1453 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1454 intel_ring_emit_reg(signaller
, mbox_reg
);
1455 intel_ring_emit(signaller
, seqno
);
1459 /* If num_dwords was rounded, make sure the tail pointer is correct */
1460 if (num_rings
% 2 == 0)
1461 intel_ring_emit(signaller
, MI_NOOP
);
1467 * gen6_add_request - Update the semaphore mailbox registers
1469 * @request - request to write to the ring
1471 * Update the mailbox registers in the *other* rings with the current seqno.
1472 * This acts like a signal in the canonical semaphore.
1475 gen6_add_request(struct drm_i915_gem_request
*req
)
1477 struct intel_engine_cs
*engine
= req
->engine
;
1480 if (engine
->semaphore
.signal
)
1481 ret
= engine
->semaphore
.signal(req
, 4);
1483 ret
= intel_ring_begin(req
, 4);
1488 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1489 intel_ring_emit(engine
,
1490 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1491 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1492 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1493 __intel_ring_advance(engine
);
1498 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 return dev_priv
->last_seqno
< seqno
;
1506 * intel_ring_sync - sync the waiter to the signaller on seqno
1508 * @waiter - ring that is waiting
1509 * @signaller - ring which has, or will signal
1510 * @seqno - seqno which the waiter will block on
1514 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1515 struct intel_engine_cs
*signaller
,
1518 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1519 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1522 ret
= intel_ring_begin(waiter_req
, 4);
1526 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1527 MI_SEMAPHORE_GLOBAL_GTT
|
1529 MI_SEMAPHORE_SAD_GTE_SDD
);
1530 intel_ring_emit(waiter
, seqno
);
1531 intel_ring_emit(waiter
,
1532 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1533 intel_ring_emit(waiter
,
1534 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1535 intel_ring_advance(waiter
);
1540 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1541 struct intel_engine_cs
*signaller
,
1544 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1545 u32 dw1
= MI_SEMAPHORE_MBOX
|
1546 MI_SEMAPHORE_COMPARE
|
1547 MI_SEMAPHORE_REGISTER
;
1548 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1551 /* Throughout all of the GEM code, seqno passed implies our current
1552 * seqno is >= the last seqno executed. However for hardware the
1553 * comparison is strictly greater than.
1557 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1559 ret
= intel_ring_begin(waiter_req
, 4);
1563 /* If seqno wrap happened, omit the wait with no-ops */
1564 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1565 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1566 intel_ring_emit(waiter
, seqno
);
1567 intel_ring_emit(waiter
, 0);
1568 intel_ring_emit(waiter
, MI_NOOP
);
1570 intel_ring_emit(waiter
, MI_NOOP
);
1571 intel_ring_emit(waiter
, MI_NOOP
);
1572 intel_ring_emit(waiter
, MI_NOOP
);
1573 intel_ring_emit(waiter
, MI_NOOP
);
1575 intel_ring_advance(waiter
);
1580 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1582 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1583 PIPE_CONTROL_DEPTH_STALL); \
1584 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1585 intel_ring_emit(ring__, 0); \
1586 intel_ring_emit(ring__, 0); \
1590 pc_render_add_request(struct drm_i915_gem_request
*req
)
1592 struct intel_engine_cs
*engine
= req
->engine
;
1593 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1596 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1597 * incoherent with writes to memory, i.e. completely fubar,
1598 * so we need to use PIPE_NOTIFY instead.
1600 * However, we also need to workaround the qword write
1601 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1602 * memory before requesting an interrupt.
1604 ret
= intel_ring_begin(req
, 32);
1608 intel_ring_emit(engine
,
1609 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1610 PIPE_CONTROL_WRITE_FLUSH
|
1611 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1612 intel_ring_emit(engine
,
1613 engine
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1614 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1615 intel_ring_emit(engine
, 0);
1616 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1617 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1618 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1619 scratch_addr
+= 2 * CACHELINE_BYTES
;
1620 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1621 scratch_addr
+= 2 * CACHELINE_BYTES
;
1622 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1623 scratch_addr
+= 2 * CACHELINE_BYTES
;
1624 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1625 scratch_addr
+= 2 * CACHELINE_BYTES
;
1626 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1628 intel_ring_emit(engine
,
1629 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1630 PIPE_CONTROL_WRITE_FLUSH
|
1631 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1632 PIPE_CONTROL_NOTIFY
);
1633 intel_ring_emit(engine
,
1634 engine
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1635 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1636 intel_ring_emit(engine
, 0);
1637 __intel_ring_advance(engine
);
1643 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1645 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1647 /* Workaround to force correct ordering between irq and seqno writes on
1648 * ivb (and maybe also on snb) by reading from a CS register (like
1649 * ACTHD) before reading the status page.
1651 * Note that this effectively stalls the read by the time it takes to
1652 * do a memory transaction, which more or less ensures that the write
1653 * from the GPU has sufficient time to invalidate the CPU cacheline.
1654 * Alternatively we could delay the interrupt from the CS ring to give
1655 * the write time to land, but that would incur a delay after every
1656 * batch i.e. much more frequent than a delay when waiting for the
1657 * interrupt (with the same net latency).
1659 * Also note that to prevent whole machine hangs on gen7, we have to
1660 * take the spinlock to guard against concurrent cacheline access.
1662 spin_lock_irq(&dev_priv
->uncore
.lock
);
1663 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1664 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1668 ring_get_seqno(struct intel_engine_cs
*engine
)
1670 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1674 ring_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1676 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1680 pc_render_get_seqno(struct intel_engine_cs
*engine
)
1682 return engine
->scratch
.cpu_page
[0];
1686 pc_render_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1688 engine
->scratch
.cpu_page
[0] = seqno
;
1692 gen5_ring_get_irq(struct intel_engine_cs
*engine
)
1694 struct drm_device
*dev
= engine
->dev
;
1695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1696 unsigned long flags
;
1698 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1701 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1702 if (engine
->irq_refcount
++ == 0)
1703 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1704 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1710 gen5_ring_put_irq(struct intel_engine_cs
*engine
)
1712 struct drm_device
*dev
= engine
->dev
;
1713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1714 unsigned long flags
;
1716 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1717 if (--engine
->irq_refcount
== 0)
1718 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1719 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1723 i9xx_ring_get_irq(struct intel_engine_cs
*engine
)
1725 struct drm_device
*dev
= engine
->dev
;
1726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1727 unsigned long flags
;
1729 if (!intel_irqs_enabled(dev_priv
))
1732 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1733 if (engine
->irq_refcount
++ == 0) {
1734 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1735 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1738 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1744 i9xx_ring_put_irq(struct intel_engine_cs
*engine
)
1746 struct drm_device
*dev
= engine
->dev
;
1747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1748 unsigned long flags
;
1750 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1751 if (--engine
->irq_refcount
== 0) {
1752 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1753 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1756 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1760 i8xx_ring_get_irq(struct intel_engine_cs
*engine
)
1762 struct drm_device
*dev
= engine
->dev
;
1763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1764 unsigned long flags
;
1766 if (!intel_irqs_enabled(dev_priv
))
1769 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1770 if (engine
->irq_refcount
++ == 0) {
1771 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1772 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1773 POSTING_READ16(IMR
);
1775 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1781 i8xx_ring_put_irq(struct intel_engine_cs
*engine
)
1783 struct drm_device
*dev
= engine
->dev
;
1784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1785 unsigned long flags
;
1787 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1788 if (--engine
->irq_refcount
== 0) {
1789 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1790 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1791 POSTING_READ16(IMR
);
1793 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1797 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1798 u32 invalidate_domains
,
1801 struct intel_engine_cs
*engine
= req
->engine
;
1804 ret
= intel_ring_begin(req
, 2);
1808 intel_ring_emit(engine
, MI_FLUSH
);
1809 intel_ring_emit(engine
, MI_NOOP
);
1810 intel_ring_advance(engine
);
1815 i9xx_add_request(struct drm_i915_gem_request
*req
)
1817 struct intel_engine_cs
*engine
= req
->engine
;
1820 ret
= intel_ring_begin(req
, 4);
1824 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1825 intel_ring_emit(engine
,
1826 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1827 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1828 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1829 __intel_ring_advance(engine
);
1835 gen6_ring_get_irq(struct intel_engine_cs
*engine
)
1837 struct drm_device
*dev
= engine
->dev
;
1838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1839 unsigned long flags
;
1841 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1844 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1845 if (engine
->irq_refcount
++ == 0) {
1846 if (HAS_L3_DPF(dev
) && engine
->id
== RCS
)
1847 I915_WRITE_IMR(engine
,
1848 ~(engine
->irq_enable_mask
|
1849 GT_PARITY_ERROR(dev
)));
1851 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1852 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1854 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1860 gen6_ring_put_irq(struct intel_engine_cs
*engine
)
1862 struct drm_device
*dev
= engine
->dev
;
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 unsigned long flags
;
1866 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1867 if (--engine
->irq_refcount
== 0) {
1868 if (HAS_L3_DPF(dev
) && engine
->id
== RCS
)
1869 I915_WRITE_IMR(engine
, ~GT_PARITY_ERROR(dev
));
1871 I915_WRITE_IMR(engine
, ~0);
1872 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1874 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1878 hsw_vebox_get_irq(struct intel_engine_cs
*engine
)
1880 struct drm_device
*dev
= engine
->dev
;
1881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1882 unsigned long flags
;
1884 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1887 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1888 if (engine
->irq_refcount
++ == 0) {
1889 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1890 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1892 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1898 hsw_vebox_put_irq(struct intel_engine_cs
*engine
)
1900 struct drm_device
*dev
= engine
->dev
;
1901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1902 unsigned long flags
;
1904 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1905 if (--engine
->irq_refcount
== 0) {
1906 I915_WRITE_IMR(engine
, ~0);
1907 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1909 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1913 gen8_ring_get_irq(struct intel_engine_cs
*engine
)
1915 struct drm_device
*dev
= engine
->dev
;
1916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1917 unsigned long flags
;
1919 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1922 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1923 if (engine
->irq_refcount
++ == 0) {
1924 if (HAS_L3_DPF(dev
) && engine
->id
== RCS
) {
1925 I915_WRITE_IMR(engine
,
1926 ~(engine
->irq_enable_mask
|
1927 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1929 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1931 POSTING_READ(RING_IMR(engine
->mmio_base
));
1933 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1939 gen8_ring_put_irq(struct intel_engine_cs
*engine
)
1941 struct drm_device
*dev
= engine
->dev
;
1942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 unsigned long flags
;
1945 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1946 if (--engine
->irq_refcount
== 0) {
1947 if (HAS_L3_DPF(dev
) && engine
->id
== RCS
) {
1948 I915_WRITE_IMR(engine
,
1949 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1951 I915_WRITE_IMR(engine
, ~0);
1953 POSTING_READ(RING_IMR(engine
->mmio_base
));
1955 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1959 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1960 u64 offset
, u32 length
,
1961 unsigned dispatch_flags
)
1963 struct intel_engine_cs
*engine
= req
->engine
;
1966 ret
= intel_ring_begin(req
, 2);
1970 intel_ring_emit(engine
,
1971 MI_BATCH_BUFFER_START
|
1973 (dispatch_flags
& I915_DISPATCH_SECURE
?
1974 0 : MI_BATCH_NON_SECURE_I965
));
1975 intel_ring_emit(engine
, offset
);
1976 intel_ring_advance(engine
);
1981 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1982 #define I830_BATCH_LIMIT (256*1024)
1983 #define I830_TLB_ENTRIES (2)
1984 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1986 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1987 u64 offset
, u32 len
,
1988 unsigned dispatch_flags
)
1990 struct intel_engine_cs
*engine
= req
->engine
;
1991 u32 cs_offset
= engine
->scratch
.gtt_offset
;
1994 ret
= intel_ring_begin(req
, 6);
1998 /* Evict the invalid PTE TLBs */
1999 intel_ring_emit(engine
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
2000 intel_ring_emit(engine
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
2001 intel_ring_emit(engine
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
2002 intel_ring_emit(engine
, cs_offset
);
2003 intel_ring_emit(engine
, 0xdeadbeef);
2004 intel_ring_emit(engine
, MI_NOOP
);
2005 intel_ring_advance(engine
);
2007 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
2008 if (len
> I830_BATCH_LIMIT
)
2011 ret
= intel_ring_begin(req
, 6 + 2);
2015 /* Blit the batch (which has now all relocs applied) to the
2016 * stable batch scratch bo area (so that the CS never
2017 * stumbles over its tlb invalidation bug) ...
2019 intel_ring_emit(engine
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
2020 intel_ring_emit(engine
,
2021 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
2022 intel_ring_emit(engine
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
2023 intel_ring_emit(engine
, cs_offset
);
2024 intel_ring_emit(engine
, 4096);
2025 intel_ring_emit(engine
, offset
);
2027 intel_ring_emit(engine
, MI_FLUSH
);
2028 intel_ring_emit(engine
, MI_NOOP
);
2029 intel_ring_advance(engine
);
2031 /* ... and execute it. */
2035 ret
= intel_ring_begin(req
, 2);
2039 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
2040 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
2041 0 : MI_BATCH_NON_SECURE
));
2042 intel_ring_advance(engine
);
2048 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2049 u64 offset
, u32 len
,
2050 unsigned dispatch_flags
)
2052 struct intel_engine_cs
*engine
= req
->engine
;
2055 ret
= intel_ring_begin(req
, 2);
2059 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
2060 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
2061 0 : MI_BATCH_NON_SECURE
));
2062 intel_ring_advance(engine
);
2067 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
2069 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
2071 if (!dev_priv
->status_page_dmah
)
2074 drm_pci_free(engine
->dev
, dev_priv
->status_page_dmah
);
2075 engine
->status_page
.page_addr
= NULL
;
2078 static void cleanup_status_page(struct intel_engine_cs
*engine
)
2080 struct drm_i915_gem_object
*obj
;
2082 obj
= engine
->status_page
.obj
;
2086 kunmap(sg_page(obj
->pages
->sgl
));
2087 i915_gem_object_ggtt_unpin(obj
);
2088 drm_gem_object_unreference(&obj
->base
);
2089 engine
->status_page
.obj
= NULL
;
2092 static int init_status_page(struct intel_engine_cs
*engine
)
2094 struct drm_i915_gem_object
*obj
= engine
->status_page
.obj
;
2100 obj
= i915_gem_alloc_object(engine
->dev
, 4096);
2102 DRM_ERROR("Failed to allocate status page\n");
2106 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2111 if (!HAS_LLC(engine
->dev
))
2112 /* On g33, we cannot place HWS above 256MiB, so
2113 * restrict its pinning to the low mappable arena.
2114 * Though this restriction is not documented for
2115 * gen4, gen5, or byt, they also behave similarly
2116 * and hang if the HWS is placed at the top of the
2117 * GTT. To generalise, it appears that all !llc
2118 * platforms have issues with us placing the HWS
2119 * above the mappable region (even though we never
2122 flags
|= PIN_MAPPABLE
;
2123 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
2126 drm_gem_object_unreference(&obj
->base
);
2130 engine
->status_page
.obj
= obj
;
2133 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
2134 engine
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
2135 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
2137 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2138 engine
->name
, engine
->status_page
.gfx_addr
);
2143 static int init_phys_status_page(struct intel_engine_cs
*engine
)
2145 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2147 if (!dev_priv
->status_page_dmah
) {
2148 dev_priv
->status_page_dmah
=
2149 drm_pci_alloc(engine
->dev
, PAGE_SIZE
, PAGE_SIZE
);
2150 if (!dev_priv
->status_page_dmah
)
2154 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
2155 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
2160 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2162 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
2163 i915_gem_object_unpin_map(ringbuf
->obj
);
2165 iounmap(ringbuf
->virtual_start
);
2166 ringbuf
->virtual_start
= NULL
;
2167 ringbuf
->vma
= NULL
;
2168 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2171 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
2172 struct intel_ringbuffer
*ringbuf
)
2174 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2175 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2176 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2177 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2178 unsigned flags
= PIN_OFFSET_BIAS
| 4096;
2182 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2183 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, flags
);
2187 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2191 addr
= i915_gem_object_pin_map(obj
);
2193 ret
= PTR_ERR(addr
);
2197 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
2198 flags
| PIN_MAPPABLE
);
2202 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2206 /* Access through the GTT requires the device to be awake. */
2207 assert_rpm_wakelock_held(dev_priv
);
2209 addr
= ioremap_wc(ggtt
->mappable_base
+
2210 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
2217 ringbuf
->virtual_start
= addr
;
2218 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2222 i915_gem_object_ggtt_unpin(obj
);
2226 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2228 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2229 ringbuf
->obj
= NULL
;
2232 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2233 struct intel_ringbuffer
*ringbuf
)
2235 struct drm_i915_gem_object
*obj
;
2239 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2241 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
2245 /* mark ring buffers as read-only from GPU side by default */
2253 struct intel_ringbuffer
*
2254 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2256 struct intel_ringbuffer
*ring
;
2259 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2261 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2263 return ERR_PTR(-ENOMEM
);
2266 ring
->engine
= engine
;
2267 list_add(&ring
->link
, &engine
->buffers
);
2270 /* Workaround an erratum on the i830 which causes a hang if
2271 * the TAIL pointer points to within the last 2 cachelines
2274 ring
->effective_size
= size
;
2275 if (IS_I830(engine
->dev
) || IS_845G(engine
->dev
))
2276 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2278 ring
->last_retired_head
= -1;
2279 intel_ring_update_space(ring
);
2281 ret
= intel_alloc_ringbuffer_obj(engine
->dev
, ring
);
2283 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2285 list_del(&ring
->link
);
2287 return ERR_PTR(ret
);
2294 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2296 intel_destroy_ringbuffer_obj(ring
);
2297 list_del(&ring
->link
);
2301 static int intel_init_ring_buffer(struct drm_device
*dev
,
2302 struct intel_engine_cs
*engine
)
2304 struct intel_ringbuffer
*ringbuf
;
2307 WARN_ON(engine
->buffer
);
2310 INIT_LIST_HEAD(&engine
->active_list
);
2311 INIT_LIST_HEAD(&engine
->request_list
);
2312 INIT_LIST_HEAD(&engine
->execlist_queue
);
2313 INIT_LIST_HEAD(&engine
->buffers
);
2314 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2315 memset(engine
->semaphore
.sync_seqno
, 0,
2316 sizeof(engine
->semaphore
.sync_seqno
));
2318 init_waitqueue_head(&engine
->irq_queue
);
2320 ringbuf
= intel_engine_create_ringbuffer(engine
, 32 * PAGE_SIZE
);
2321 if (IS_ERR(ringbuf
)) {
2322 ret
= PTR_ERR(ringbuf
);
2325 engine
->buffer
= ringbuf
;
2327 if (I915_NEED_GFX_HWS(dev
)) {
2328 ret
= init_status_page(engine
);
2332 WARN_ON(engine
->id
!= RCS
);
2333 ret
= init_phys_status_page(engine
);
2338 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2340 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2342 intel_destroy_ringbuffer_obj(ringbuf
);
2346 ret
= i915_cmd_parser_init_ring(engine
);
2353 intel_cleanup_engine(engine
);
2357 void intel_cleanup_engine(struct intel_engine_cs
*engine
)
2359 struct drm_i915_private
*dev_priv
;
2361 if (!intel_engine_initialized(engine
))
2364 dev_priv
= to_i915(engine
->dev
);
2366 if (engine
->buffer
) {
2367 intel_stop_engine(engine
);
2368 WARN_ON(!IS_GEN2(engine
->dev
) && (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2370 intel_unpin_ringbuffer_obj(engine
->buffer
);
2371 intel_ringbuffer_free(engine
->buffer
);
2372 engine
->buffer
= NULL
;
2375 if (engine
->cleanup
)
2376 engine
->cleanup(engine
);
2378 if (I915_NEED_GFX_HWS(engine
->dev
)) {
2379 cleanup_status_page(engine
);
2381 WARN_ON(engine
->id
!= RCS
);
2382 cleanup_phys_status_page(engine
);
2385 i915_cmd_parser_fini_ring(engine
);
2386 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2390 int intel_engine_idle(struct intel_engine_cs
*engine
)
2392 struct drm_i915_gem_request
*req
;
2394 /* Wait upon the last request to be completed */
2395 if (list_empty(&engine
->request_list
))
2398 req
= list_entry(engine
->request_list
.prev
,
2399 struct drm_i915_gem_request
,
2402 /* Make sure we do not trigger any retires */
2403 return __i915_wait_request(req
,
2404 req
->i915
->mm
.interruptible
,
2408 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2410 request
->ringbuf
= request
->engine
->buffer
;
2414 int intel_ring_reserve_space(struct drm_i915_gem_request
*request
)
2417 * The first call merely notes the reserve request and is common for
2418 * all back ends. The subsequent localised _begin() call actually
2419 * ensures that the reservation is available. Without the begin, if
2420 * the request creator immediately submitted the request without
2421 * adding any commands to it then there might not actually be
2422 * sufficient room for the submission commands.
2424 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
2426 return intel_ring_begin(request
, 0);
2429 void intel_ring_reserved_space_reserve(struct intel_ringbuffer
*ringbuf
, int size
)
2431 GEM_BUG_ON(ringbuf
->reserved_size
);
2432 ringbuf
->reserved_size
= size
;
2435 void intel_ring_reserved_space_cancel(struct intel_ringbuffer
*ringbuf
)
2437 GEM_BUG_ON(!ringbuf
->reserved_size
);
2438 ringbuf
->reserved_size
= 0;
2441 void intel_ring_reserved_space_use(struct intel_ringbuffer
*ringbuf
)
2443 GEM_BUG_ON(!ringbuf
->reserved_size
);
2444 ringbuf
->reserved_size
= 0;
2447 void intel_ring_reserved_space_end(struct intel_ringbuffer
*ringbuf
)
2449 GEM_BUG_ON(ringbuf
->reserved_size
);
2452 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2454 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2455 struct intel_engine_cs
*engine
= req
->engine
;
2456 struct drm_i915_gem_request
*target
;
2458 intel_ring_update_space(ringbuf
);
2459 if (ringbuf
->space
>= bytes
)
2463 * Space is reserved in the ringbuffer for finalising the request,
2464 * as that cannot be allowed to fail. During request finalisation,
2465 * reserved_space is set to 0 to stop the overallocation and the
2466 * assumption is that then we never need to wait (which has the
2467 * risk of failing with EINTR).
2469 * See also i915_gem_request_alloc() and i915_add_request().
2471 GEM_BUG_ON(!ringbuf
->reserved_size
);
2473 list_for_each_entry(target
, &engine
->request_list
, list
) {
2477 * The request queue is per-engine, so can contain requests
2478 * from multiple ringbuffers. Here, we must ignore any that
2479 * aren't from the ringbuffer we're considering.
2481 if (target
->ringbuf
!= ringbuf
)
2484 /* Would completion of this request free enough space? */
2485 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
2491 if (WARN_ON(&target
->list
== &engine
->request_list
))
2494 return i915_wait_request(target
);
2497 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2499 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2500 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2501 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2502 int bytes
= num_dwords
* sizeof(u32
);
2503 int total_bytes
, wait_bytes
;
2504 bool need_wrap
= false;
2506 total_bytes
= bytes
+ ringbuf
->reserved_size
;
2508 if (unlikely(bytes
> remain_usable
)) {
2510 * Not enough space for the basic request. So need to flush
2511 * out the remainder and then wait for base + reserved.
2513 wait_bytes
= remain_actual
+ total_bytes
;
2515 } else if (unlikely(total_bytes
> remain_usable
)) {
2517 * The base request will fit but the reserved space
2518 * falls off the end. So we don't need an immediate wrap
2519 * and only need to effectively wait for the reserved
2520 * size space from the start of ringbuffer.
2522 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
2524 /* No wrapping required, just waiting. */
2525 wait_bytes
= total_bytes
;
2528 if (wait_bytes
> ringbuf
->space
) {
2529 int ret
= wait_for_space(req
, wait_bytes
);
2533 intel_ring_update_space(ringbuf
);
2534 if (unlikely(ringbuf
->space
< wait_bytes
))
2538 if (unlikely(need_wrap
)) {
2539 GEM_BUG_ON(remain_actual
> ringbuf
->space
);
2540 GEM_BUG_ON(ringbuf
->tail
+ remain_actual
> ringbuf
->size
);
2542 /* Fill the tail with MI_NOOP */
2543 memset(ringbuf
->virtual_start
+ ringbuf
->tail
,
2546 ringbuf
->space
-= remain_actual
;
2549 ringbuf
->space
-= bytes
;
2550 GEM_BUG_ON(ringbuf
->space
< 0);
2554 /* Align the ring tail to a cacheline boundary */
2555 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2557 struct intel_engine_cs
*engine
= req
->engine
;
2558 int num_dwords
= (engine
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2561 if (num_dwords
== 0)
2564 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2565 ret
= intel_ring_begin(req
, num_dwords
);
2569 while (num_dwords
--)
2570 intel_ring_emit(engine
, MI_NOOP
);
2572 intel_ring_advance(engine
);
2577 void intel_ring_init_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
2579 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
2581 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2582 * so long as the semaphore value in the register/page is greater
2583 * than the sync value), so whenever we reset the seqno,
2584 * so long as we reset the tracking semaphore value to 0, it will
2585 * always be before the next request's seqno. If we don't reset
2586 * the semaphore value, then when the seqno moves backwards all
2587 * future waits will complete instantly (causing rendering corruption).
2589 if (INTEL_INFO(dev_priv
)->gen
== 6 || INTEL_INFO(dev_priv
)->gen
== 7) {
2590 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
2591 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
2592 if (HAS_VEBOX(dev_priv
))
2593 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
2595 if (dev_priv
->semaphore_obj
) {
2596 struct drm_i915_gem_object
*obj
= dev_priv
->semaphore_obj
;
2597 struct page
*page
= i915_gem_object_get_dirty_page(obj
, 0);
2598 void *semaphores
= kmap(page
);
2599 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
2600 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
2603 memset(engine
->semaphore
.sync_seqno
, 0,
2604 sizeof(engine
->semaphore
.sync_seqno
));
2606 engine
->set_seqno(engine
, seqno
);
2607 engine
->last_submitted_seqno
= seqno
;
2609 engine
->hangcheck
.seqno
= seqno
;
2612 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*engine
,
2615 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2617 /* Every tail move must follow the sequence below */
2619 /* Disable notification that the ring is IDLE. The GT
2620 * will then assume that it is busy and bring it out of rc6.
2622 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2623 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2625 /* Clear the context id. Here be magic! */
2626 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2628 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2629 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2630 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2632 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2634 /* Now that the ring is fully powered up, update the tail */
2635 I915_WRITE_TAIL(engine
, value
);
2636 POSTING_READ(RING_TAIL(engine
->mmio_base
));
2638 /* Let the ring send IDLE messages to the GT again,
2639 * and so let it sleep to conserve power when idle.
2641 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2642 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2645 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2646 u32 invalidate
, u32 flush
)
2648 struct intel_engine_cs
*engine
= req
->engine
;
2652 ret
= intel_ring_begin(req
, 4);
2657 if (INTEL_INFO(engine
->dev
)->gen
>= 8)
2660 /* We always require a command barrier so that subsequent
2661 * commands, such as breadcrumb interrupts, are strictly ordered
2662 * wrt the contents of the write cache being flushed to memory
2663 * (and thus being coherent from the CPU).
2665 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2668 * Bspec vol 1c.5 - video engine command streamer:
2669 * "If ENABLED, all TLBs will be invalidated once the flush
2670 * operation is complete. This bit is only valid when the
2671 * Post-Sync Operation field is a value of 1h or 3h."
2673 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2674 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2676 intel_ring_emit(engine
, cmd
);
2677 intel_ring_emit(engine
,
2678 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2679 if (INTEL_INFO(engine
->dev
)->gen
>= 8) {
2680 intel_ring_emit(engine
, 0); /* upper addr */
2681 intel_ring_emit(engine
, 0); /* value */
2683 intel_ring_emit(engine
, 0);
2684 intel_ring_emit(engine
, MI_NOOP
);
2686 intel_ring_advance(engine
);
2691 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2692 u64 offset
, u32 len
,
2693 unsigned dispatch_flags
)
2695 struct intel_engine_cs
*engine
= req
->engine
;
2696 bool ppgtt
= USES_PPGTT(engine
->dev
) &&
2697 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2700 ret
= intel_ring_begin(req
, 4);
2704 /* FIXME(BDW): Address space and security selectors. */
2705 intel_ring_emit(engine
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2706 (dispatch_flags
& I915_DISPATCH_RS
?
2707 MI_BATCH_RESOURCE_STREAMER
: 0));
2708 intel_ring_emit(engine
, lower_32_bits(offset
));
2709 intel_ring_emit(engine
, upper_32_bits(offset
));
2710 intel_ring_emit(engine
, MI_NOOP
);
2711 intel_ring_advance(engine
);
2717 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2718 u64 offset
, u32 len
,
2719 unsigned dispatch_flags
)
2721 struct intel_engine_cs
*engine
= req
->engine
;
2724 ret
= intel_ring_begin(req
, 2);
2728 intel_ring_emit(engine
,
2729 MI_BATCH_BUFFER_START
|
2730 (dispatch_flags
& I915_DISPATCH_SECURE
?
2731 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2732 (dispatch_flags
& I915_DISPATCH_RS
?
2733 MI_BATCH_RESOURCE_STREAMER
: 0));
2734 /* bit0-7 is the length on GEN6+ */
2735 intel_ring_emit(engine
, offset
);
2736 intel_ring_advance(engine
);
2742 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2743 u64 offset
, u32 len
,
2744 unsigned dispatch_flags
)
2746 struct intel_engine_cs
*engine
= req
->engine
;
2749 ret
= intel_ring_begin(req
, 2);
2753 intel_ring_emit(engine
,
2754 MI_BATCH_BUFFER_START
|
2755 (dispatch_flags
& I915_DISPATCH_SECURE
?
2756 0 : MI_BATCH_NON_SECURE_I965
));
2757 /* bit0-7 is the length on GEN6+ */
2758 intel_ring_emit(engine
, offset
);
2759 intel_ring_advance(engine
);
2764 /* Blitter support (SandyBridge+) */
2766 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2767 u32 invalidate
, u32 flush
)
2769 struct intel_engine_cs
*engine
= req
->engine
;
2770 struct drm_device
*dev
= engine
->dev
;
2774 ret
= intel_ring_begin(req
, 4);
2779 if (INTEL_INFO(dev
)->gen
>= 8)
2782 /* We always require a command barrier so that subsequent
2783 * commands, such as breadcrumb interrupts, are strictly ordered
2784 * wrt the contents of the write cache being flushed to memory
2785 * (and thus being coherent from the CPU).
2787 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2790 * Bspec vol 1c.3 - blitter engine command streamer:
2791 * "If ENABLED, all TLBs will be invalidated once the flush
2792 * operation is complete. This bit is only valid when the
2793 * Post-Sync Operation field is a value of 1h or 3h."
2795 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2796 cmd
|= MI_INVALIDATE_TLB
;
2797 intel_ring_emit(engine
, cmd
);
2798 intel_ring_emit(engine
,
2799 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2800 if (INTEL_INFO(dev
)->gen
>= 8) {
2801 intel_ring_emit(engine
, 0); /* upper addr */
2802 intel_ring_emit(engine
, 0); /* value */
2804 intel_ring_emit(engine
, 0);
2805 intel_ring_emit(engine
, MI_NOOP
);
2807 intel_ring_advance(engine
);
2812 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2816 struct drm_i915_gem_object
*obj
;
2819 engine
->name
= "render ring";
2821 engine
->exec_id
= I915_EXEC_RENDER
;
2823 engine
->mmio_base
= RENDER_RING_BASE
;
2825 if (INTEL_INFO(dev
)->gen
>= 8) {
2826 if (i915_semaphore_is_enabled(dev
)) {
2827 obj
= i915_gem_alloc_object(dev
, 4096);
2829 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2830 i915
.semaphores
= 0;
2832 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2833 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2835 drm_gem_object_unreference(&obj
->base
);
2836 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2837 i915
.semaphores
= 0;
2839 dev_priv
->semaphore_obj
= obj
;
2843 engine
->init_context
= intel_rcs_ctx_init
;
2844 engine
->add_request
= gen6_add_request
;
2845 engine
->flush
= gen8_render_ring_flush
;
2846 engine
->irq_get
= gen8_ring_get_irq
;
2847 engine
->irq_put
= gen8_ring_put_irq
;
2848 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2849 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2850 engine
->get_seqno
= ring_get_seqno
;
2851 engine
->set_seqno
= ring_set_seqno
;
2852 if (i915_semaphore_is_enabled(dev
)) {
2853 WARN_ON(!dev_priv
->semaphore_obj
);
2854 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2855 engine
->semaphore
.signal
= gen8_rcs_signal
;
2856 GEN8_RING_SEMAPHORE_INIT(engine
);
2858 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2859 engine
->init_context
= intel_rcs_ctx_init
;
2860 engine
->add_request
= gen6_add_request
;
2861 engine
->flush
= gen7_render_ring_flush
;
2862 if (INTEL_INFO(dev
)->gen
== 6)
2863 engine
->flush
= gen6_render_ring_flush
;
2864 engine
->irq_get
= gen6_ring_get_irq
;
2865 engine
->irq_put
= gen6_ring_put_irq
;
2866 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2867 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2868 engine
->get_seqno
= ring_get_seqno
;
2869 engine
->set_seqno
= ring_set_seqno
;
2870 if (i915_semaphore_is_enabled(dev
)) {
2871 engine
->semaphore
.sync_to
= gen6_ring_sync
;
2872 engine
->semaphore
.signal
= gen6_signal
;
2874 * The current semaphore is only applied on pre-gen8
2875 * platform. And there is no VCS2 ring on the pre-gen8
2876 * platform. So the semaphore between RCS and VCS2 is
2877 * initialized as INVALID. Gen8 will initialize the
2878 * sema between VCS2 and RCS later.
2880 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2881 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2882 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2883 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2884 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2885 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2886 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2887 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2888 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2889 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2891 } else if (IS_GEN5(dev
)) {
2892 engine
->add_request
= pc_render_add_request
;
2893 engine
->flush
= gen4_render_ring_flush
;
2894 engine
->get_seqno
= pc_render_get_seqno
;
2895 engine
->set_seqno
= pc_render_set_seqno
;
2896 engine
->irq_get
= gen5_ring_get_irq
;
2897 engine
->irq_put
= gen5_ring_put_irq
;
2898 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2899 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2901 engine
->add_request
= i9xx_add_request
;
2902 if (INTEL_INFO(dev
)->gen
< 4)
2903 engine
->flush
= gen2_render_ring_flush
;
2905 engine
->flush
= gen4_render_ring_flush
;
2906 engine
->get_seqno
= ring_get_seqno
;
2907 engine
->set_seqno
= ring_set_seqno
;
2909 engine
->irq_get
= i8xx_ring_get_irq
;
2910 engine
->irq_put
= i8xx_ring_put_irq
;
2912 engine
->irq_get
= i9xx_ring_get_irq
;
2913 engine
->irq_put
= i9xx_ring_put_irq
;
2915 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2917 engine
->write_tail
= ring_write_tail
;
2919 if (IS_HASWELL(dev
))
2920 engine
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2921 else if (IS_GEN8(dev
))
2922 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2923 else if (INTEL_INFO(dev
)->gen
>= 6)
2924 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2925 else if (INTEL_INFO(dev
)->gen
>= 4)
2926 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2927 else if (IS_I830(dev
) || IS_845G(dev
))
2928 engine
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2930 engine
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2931 engine
->init_hw
= init_render_ring
;
2932 engine
->cleanup
= render_ring_cleanup
;
2934 /* Workaround batchbuffer to combat CS tlb bug. */
2935 if (HAS_BROKEN_CS_TLB(dev
)) {
2936 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2938 DRM_ERROR("Failed to allocate batch bo\n");
2942 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2944 drm_gem_object_unreference(&obj
->base
);
2945 DRM_ERROR("Failed to ping batch bo\n");
2949 engine
->scratch
.obj
= obj
;
2950 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2953 ret
= intel_init_ring_buffer(dev
, engine
);
2957 if (INTEL_INFO(dev
)->gen
>= 5) {
2958 ret
= intel_init_pipe_control(engine
);
2966 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2969 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2971 engine
->name
= "bsd ring";
2973 engine
->exec_id
= I915_EXEC_BSD
;
2976 engine
->write_tail
= ring_write_tail
;
2977 if (INTEL_INFO(dev
)->gen
>= 6) {
2978 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2979 /* gen6 bsd needs a special wa for tail updates */
2981 engine
->write_tail
= gen6_bsd_ring_write_tail
;
2982 engine
->flush
= gen6_bsd_ring_flush
;
2983 engine
->add_request
= gen6_add_request
;
2984 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2985 engine
->get_seqno
= ring_get_seqno
;
2986 engine
->set_seqno
= ring_set_seqno
;
2987 if (INTEL_INFO(dev
)->gen
>= 8) {
2988 engine
->irq_enable_mask
=
2989 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2990 engine
->irq_get
= gen8_ring_get_irq
;
2991 engine
->irq_put
= gen8_ring_put_irq
;
2992 engine
->dispatch_execbuffer
=
2993 gen8_ring_dispatch_execbuffer
;
2994 if (i915_semaphore_is_enabled(dev
)) {
2995 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2996 engine
->semaphore
.signal
= gen8_xcs_signal
;
2997 GEN8_RING_SEMAPHORE_INIT(engine
);
3000 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
3001 engine
->irq_get
= gen6_ring_get_irq
;
3002 engine
->irq_put
= gen6_ring_put_irq
;
3003 engine
->dispatch_execbuffer
=
3004 gen6_ring_dispatch_execbuffer
;
3005 if (i915_semaphore_is_enabled(dev
)) {
3006 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3007 engine
->semaphore
.signal
= gen6_signal
;
3008 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
3009 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
3010 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
3011 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
3012 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3013 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
3014 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
3015 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
3016 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
3017 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3021 engine
->mmio_base
= BSD_RING_BASE
;
3022 engine
->flush
= bsd_ring_flush
;
3023 engine
->add_request
= i9xx_add_request
;
3024 engine
->get_seqno
= ring_get_seqno
;
3025 engine
->set_seqno
= ring_set_seqno
;
3027 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
3028 engine
->irq_get
= gen5_ring_get_irq
;
3029 engine
->irq_put
= gen5_ring_put_irq
;
3031 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
3032 engine
->irq_get
= i9xx_ring_get_irq
;
3033 engine
->irq_put
= i9xx_ring_put_irq
;
3035 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
3037 engine
->init_hw
= init_ring_common
;
3039 return intel_init_ring_buffer(dev
, engine
);
3043 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3045 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
3047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3048 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
3050 engine
->name
= "bsd2 ring";
3052 engine
->exec_id
= I915_EXEC_BSD
;
3055 engine
->write_tail
= ring_write_tail
;
3056 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
3057 engine
->flush
= gen6_bsd_ring_flush
;
3058 engine
->add_request
= gen6_add_request
;
3059 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3060 engine
->get_seqno
= ring_get_seqno
;
3061 engine
->set_seqno
= ring_set_seqno
;
3062 engine
->irq_enable_mask
=
3063 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
3064 engine
->irq_get
= gen8_ring_get_irq
;
3065 engine
->irq_put
= gen8_ring_put_irq
;
3066 engine
->dispatch_execbuffer
=
3067 gen8_ring_dispatch_execbuffer
;
3068 if (i915_semaphore_is_enabled(dev
)) {
3069 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3070 engine
->semaphore
.signal
= gen8_xcs_signal
;
3071 GEN8_RING_SEMAPHORE_INIT(engine
);
3073 engine
->init_hw
= init_ring_common
;
3075 return intel_init_ring_buffer(dev
, engine
);
3078 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
3080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3081 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
3083 engine
->name
= "blitter ring";
3085 engine
->exec_id
= I915_EXEC_BLT
;
3088 engine
->mmio_base
= BLT_RING_BASE
;
3089 engine
->write_tail
= ring_write_tail
;
3090 engine
->flush
= gen6_ring_flush
;
3091 engine
->add_request
= gen6_add_request
;
3092 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3093 engine
->get_seqno
= ring_get_seqno
;
3094 engine
->set_seqno
= ring_set_seqno
;
3095 if (INTEL_INFO(dev
)->gen
>= 8) {
3096 engine
->irq_enable_mask
=
3097 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
3098 engine
->irq_get
= gen8_ring_get_irq
;
3099 engine
->irq_put
= gen8_ring_put_irq
;
3100 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3101 if (i915_semaphore_is_enabled(dev
)) {
3102 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3103 engine
->semaphore
.signal
= gen8_xcs_signal
;
3104 GEN8_RING_SEMAPHORE_INIT(engine
);
3107 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
3108 engine
->irq_get
= gen6_ring_get_irq
;
3109 engine
->irq_put
= gen6_ring_put_irq
;
3110 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3111 if (i915_semaphore_is_enabled(dev
)) {
3112 engine
->semaphore
.signal
= gen6_signal
;
3113 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3115 * The current semaphore is only applied on pre-gen8
3116 * platform. And there is no VCS2 ring on the pre-gen8
3117 * platform. So the semaphore between BCS and VCS2 is
3118 * initialized as INVALID. Gen8 will initialize the
3119 * sema between BCS and VCS2 later.
3121 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
3122 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
3123 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
3124 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
3125 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3126 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
3127 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
3128 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
3129 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
3130 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3133 engine
->init_hw
= init_ring_common
;
3135 return intel_init_ring_buffer(dev
, engine
);
3138 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
3140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3141 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
3143 engine
->name
= "video enhancement ring";
3145 engine
->exec_id
= I915_EXEC_VEBOX
;
3148 engine
->mmio_base
= VEBOX_RING_BASE
;
3149 engine
->write_tail
= ring_write_tail
;
3150 engine
->flush
= gen6_ring_flush
;
3151 engine
->add_request
= gen6_add_request
;
3152 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3153 engine
->get_seqno
= ring_get_seqno
;
3154 engine
->set_seqno
= ring_set_seqno
;
3156 if (INTEL_INFO(dev
)->gen
>= 8) {
3157 engine
->irq_enable_mask
=
3158 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3159 engine
->irq_get
= gen8_ring_get_irq
;
3160 engine
->irq_put
= gen8_ring_put_irq
;
3161 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3162 if (i915_semaphore_is_enabled(dev
)) {
3163 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3164 engine
->semaphore
.signal
= gen8_xcs_signal
;
3165 GEN8_RING_SEMAPHORE_INIT(engine
);
3168 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3169 engine
->irq_get
= hsw_vebox_get_irq
;
3170 engine
->irq_put
= hsw_vebox_put_irq
;
3171 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3172 if (i915_semaphore_is_enabled(dev
)) {
3173 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3174 engine
->semaphore
.signal
= gen6_signal
;
3175 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
3176 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
3177 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
3178 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
3179 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3180 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
3181 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
3182 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
3183 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
3184 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3187 engine
->init_hw
= init_ring_common
;
3189 return intel_init_ring_buffer(dev
, engine
);
3193 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3195 struct intel_engine_cs
*engine
= req
->engine
;
3198 if (!engine
->gpu_caches_dirty
)
3201 ret
= engine
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3205 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3207 engine
->gpu_caches_dirty
= false;
3212 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3214 struct intel_engine_cs
*engine
= req
->engine
;
3215 uint32_t flush_domains
;
3219 if (engine
->gpu_caches_dirty
)
3220 flush_domains
= I915_GEM_GPU_DOMAINS
;
3222 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3226 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3228 engine
->gpu_caches_dirty
= false;
3233 intel_stop_engine(struct intel_engine_cs
*engine
)
3237 if (!intel_engine_initialized(engine
))
3240 ret
= intel_engine_idle(engine
);
3242 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",