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drm/i915: Refactor execlists default context pinning
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <linux/log2.h>
31 #include <drm/drmP.h>
32 #include "i915_drv.h"
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 int __intel_ring_space(int head, int tail, int size)
38 {
39 int space = head - tail;
40 if (space <= 0)
41 space += size;
42 return space - I915_RING_FREE_SPACE;
43 }
44
45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46 {
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54 }
55
56 bool intel_engine_stopped(struct intel_engine_cs *engine)
57 {
58 struct drm_i915_private *dev_priv = engine->dev->dev_private;
59 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
60 }
61
62 static void __intel_ring_advance(struct intel_engine_cs *engine)
63 {
64 struct intel_ringbuffer *ringbuf = engine->buffer;
65 ringbuf->tail &= ringbuf->size - 1;
66 if (intel_engine_stopped(engine))
67 return;
68 engine->write_tail(engine, ringbuf->tail);
69 }
70
71 static int
72 gen2_render_ring_flush(struct drm_i915_gem_request *req,
73 u32 invalidate_domains,
74 u32 flush_domains)
75 {
76 struct intel_engine_cs *engine = req->engine;
77 u32 cmd;
78 int ret;
79
80 cmd = MI_FLUSH;
81 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
82 cmd |= MI_NO_WRITE_FLUSH;
83
84 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
85 cmd |= MI_READ_FLUSH;
86
87 ret = intel_ring_begin(req, 2);
88 if (ret)
89 return ret;
90
91 intel_ring_emit(engine, cmd);
92 intel_ring_emit(engine, MI_NOOP);
93 intel_ring_advance(engine);
94
95 return 0;
96 }
97
98 static int
99 gen4_render_ring_flush(struct drm_i915_gem_request *req,
100 u32 invalidate_domains,
101 u32 flush_domains)
102 {
103 struct intel_engine_cs *engine = req->engine;
104 struct drm_device *dev = engine->dev;
105 u32 cmd;
106 int ret;
107
108 /*
109 * read/write caches:
110 *
111 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
112 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
113 * also flushed at 2d versus 3d pipeline switches.
114 *
115 * read-only caches:
116 *
117 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
118 * MI_READ_FLUSH is set, and is always flushed on 965.
119 *
120 * I915_GEM_DOMAIN_COMMAND may not exist?
121 *
122 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
123 * invalidated when MI_EXE_FLUSH is set.
124 *
125 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
126 * invalidated with every MI_FLUSH.
127 *
128 * TLBs:
129 *
130 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
131 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
132 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
133 * are flushed at any MI_FLUSH.
134 */
135
136 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
137 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
138 cmd &= ~MI_NO_WRITE_FLUSH;
139 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
140 cmd |= MI_EXE_FLUSH;
141
142 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
143 (IS_G4X(dev) || IS_GEN5(dev)))
144 cmd |= MI_INVALIDATE_ISP;
145
146 ret = intel_ring_begin(req, 2);
147 if (ret)
148 return ret;
149
150 intel_ring_emit(engine, cmd);
151 intel_ring_emit(engine, MI_NOOP);
152 intel_ring_advance(engine);
153
154 return 0;
155 }
156
157 /**
158 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
159 * implementing two workarounds on gen6. From section 1.4.7.1
160 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
161 *
162 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
163 * produced by non-pipelined state commands), software needs to first
164 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
165 * 0.
166 *
167 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
168 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
169 *
170 * And the workaround for these two requires this workaround first:
171 *
172 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
173 * BEFORE the pipe-control with a post-sync op and no write-cache
174 * flushes.
175 *
176 * And this last workaround is tricky because of the requirements on
177 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
178 * volume 2 part 1:
179 *
180 * "1 of the following must also be set:
181 * - Render Target Cache Flush Enable ([12] of DW1)
182 * - Depth Cache Flush Enable ([0] of DW1)
183 * - Stall at Pixel Scoreboard ([1] of DW1)
184 * - Depth Stall ([13] of DW1)
185 * - Post-Sync Operation ([13] of DW1)
186 * - Notify Enable ([8] of DW1)"
187 *
188 * The cache flushes require the workaround flush that triggered this
189 * one, so we can't use it. Depth stall would trigger the same.
190 * Post-sync nonzero is what triggered this second workaround, so we
191 * can't use that one either. Notify enable is IRQs, which aren't
192 * really our business. That leaves only stall at scoreboard.
193 */
194 static int
195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
196 {
197 struct intel_engine_cs *engine = req->engine;
198 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
199 int ret;
200
201 ret = intel_ring_begin(req, 6);
202 if (ret)
203 return ret;
204
205 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
206 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
207 PIPE_CONTROL_STALL_AT_SCOREBOARD);
208 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
209 intel_ring_emit(engine, 0); /* low dword */
210 intel_ring_emit(engine, 0); /* high dword */
211 intel_ring_emit(engine, MI_NOOP);
212 intel_ring_advance(engine);
213
214 ret = intel_ring_begin(req, 6);
215 if (ret)
216 return ret;
217
218 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
219 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
220 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
221 intel_ring_emit(engine, 0);
222 intel_ring_emit(engine, 0);
223 intel_ring_emit(engine, MI_NOOP);
224 intel_ring_advance(engine);
225
226 return 0;
227 }
228
229 static int
230 gen6_render_ring_flush(struct drm_i915_gem_request *req,
231 u32 invalidate_domains, u32 flush_domains)
232 {
233 struct intel_engine_cs *engine = req->engine;
234 u32 flags = 0;
235 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
236 int ret;
237
238 /* Force SNB workarounds for PIPE_CONTROL flushes */
239 ret = intel_emit_post_sync_nonzero_flush(req);
240 if (ret)
241 return ret;
242
243 /* Just flush everything. Experiments have shown that reducing the
244 * number of bits based on the write domains has little performance
245 * impact.
246 */
247 if (flush_domains) {
248 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
249 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
250 /*
251 * Ensure that any following seqno writes only happen
252 * when the render cache is indeed flushed.
253 */
254 flags |= PIPE_CONTROL_CS_STALL;
255 }
256 if (invalidate_domains) {
257 flags |= PIPE_CONTROL_TLB_INVALIDATE;
258 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
259 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
260 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
261 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
262 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
263 /*
264 * TLB invalidate requires a post-sync write.
265 */
266 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
267 }
268
269 ret = intel_ring_begin(req, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(engine, flags);
275 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
276 intel_ring_emit(engine, 0);
277 intel_ring_advance(engine);
278
279 return 0;
280 }
281
282 static int
283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
284 {
285 struct intel_engine_cs *engine = req->engine;
286 int ret;
287
288 ret = intel_ring_begin(req, 4);
289 if (ret)
290 return ret;
291
292 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
294 PIPE_CONTROL_STALL_AT_SCOREBOARD);
295 intel_ring_emit(engine, 0);
296 intel_ring_emit(engine, 0);
297 intel_ring_advance(engine);
298
299 return 0;
300 }
301
302 static int
303 gen7_render_ring_flush(struct drm_i915_gem_request *req,
304 u32 invalidate_domains, u32 flush_domains)
305 {
306 struct intel_engine_cs *engine = req->engine;
307 u32 flags = 0;
308 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
309 int ret;
310
311 /*
312 * Ensure that any following seqno writes only happen when the render
313 * cache is indeed flushed.
314 *
315 * Workaround: 4th PIPE_CONTROL command (except the ones with only
316 * read-cache invalidate bits set) must have the CS_STALL bit set. We
317 * don't try to be clever and just set it unconditionally.
318 */
319 flags |= PIPE_CONTROL_CS_STALL;
320
321 /* Just flush everything. Experiments have shown that reducing the
322 * number of bits based on the write domains has little performance
323 * impact.
324 */
325 if (flush_domains) {
326 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
327 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
328 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
329 flags |= PIPE_CONTROL_FLUSH_ENABLE;
330 }
331 if (invalidate_domains) {
332 flags |= PIPE_CONTROL_TLB_INVALIDATE;
333 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
337 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
338 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
339 /*
340 * TLB invalidate requires a post-sync write.
341 */
342 flags |= PIPE_CONTROL_QW_WRITE;
343 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
344
345 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
346
347 /* Workaround: we must issue a pipe_control with CS-stall bit
348 * set before a pipe_control command that has the state cache
349 * invalidate bit set. */
350 gen7_render_ring_cs_stall_wa(req);
351 }
352
353 ret = intel_ring_begin(req, 4);
354 if (ret)
355 return ret;
356
357 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
358 intel_ring_emit(engine, flags);
359 intel_ring_emit(engine, scratch_addr);
360 intel_ring_emit(engine, 0);
361 intel_ring_advance(engine);
362
363 return 0;
364 }
365
366 static int
367 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
368 u32 flags, u32 scratch_addr)
369 {
370 struct intel_engine_cs *engine = req->engine;
371 int ret;
372
373 ret = intel_ring_begin(req, 6);
374 if (ret)
375 return ret;
376
377 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
378 intel_ring_emit(engine, flags);
379 intel_ring_emit(engine, scratch_addr);
380 intel_ring_emit(engine, 0);
381 intel_ring_emit(engine, 0);
382 intel_ring_emit(engine, 0);
383 intel_ring_advance(engine);
384
385 return 0;
386 }
387
388 static int
389 gen8_render_ring_flush(struct drm_i915_gem_request *req,
390 u32 invalidate_domains, u32 flush_domains)
391 {
392 u32 flags = 0;
393 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
394 int ret;
395
396 flags |= PIPE_CONTROL_CS_STALL;
397
398 if (flush_domains) {
399 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
400 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
401 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
402 flags |= PIPE_CONTROL_FLUSH_ENABLE;
403 }
404 if (invalidate_domains) {
405 flags |= PIPE_CONTROL_TLB_INVALIDATE;
406 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
407 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
408 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
409 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
410 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_QW_WRITE;
412 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
413
414 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
415 ret = gen8_emit_pipe_control(req,
416 PIPE_CONTROL_CS_STALL |
417 PIPE_CONTROL_STALL_AT_SCOREBOARD,
418 0);
419 if (ret)
420 return ret;
421 }
422
423 return gen8_emit_pipe_control(req, flags, scratch_addr);
424 }
425
426 static void ring_write_tail(struct intel_engine_cs *engine,
427 u32 value)
428 {
429 struct drm_i915_private *dev_priv = engine->dev->dev_private;
430 I915_WRITE_TAIL(engine, value);
431 }
432
433 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
434 {
435 struct drm_i915_private *dev_priv = engine->dev->dev_private;
436 u64 acthd;
437
438 if (INTEL_INFO(engine->dev)->gen >= 8)
439 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
440 RING_ACTHD_UDW(engine->mmio_base));
441 else if (INTEL_INFO(engine->dev)->gen >= 4)
442 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
443 else
444 acthd = I915_READ(ACTHD);
445
446 return acthd;
447 }
448
449 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
450 {
451 struct drm_i915_private *dev_priv = engine->dev->dev_private;
452 u32 addr;
453
454 addr = dev_priv->status_page_dmah->busaddr;
455 if (INTEL_INFO(engine->dev)->gen >= 4)
456 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
457 I915_WRITE(HWS_PGA, addr);
458 }
459
460 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
461 {
462 struct drm_device *dev = engine->dev;
463 struct drm_i915_private *dev_priv = engine->dev->dev_private;
464 i915_reg_t mmio;
465
466 /* The ring status page addresses are no longer next to the rest of
467 * the ring registers as of gen7.
468 */
469 if (IS_GEN7(dev)) {
470 switch (engine->id) {
471 case RCS:
472 mmio = RENDER_HWS_PGA_GEN7;
473 break;
474 case BCS:
475 mmio = BLT_HWS_PGA_GEN7;
476 break;
477 /*
478 * VCS2 actually doesn't exist on Gen7. Only shut up
479 * gcc switch check warning
480 */
481 case VCS2:
482 case VCS:
483 mmio = BSD_HWS_PGA_GEN7;
484 break;
485 case VECS:
486 mmio = VEBOX_HWS_PGA_GEN7;
487 break;
488 }
489 } else if (IS_GEN6(engine->dev)) {
490 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
491 } else {
492 /* XXX: gen8 returns to sanity */
493 mmio = RING_HWS_PGA(engine->mmio_base);
494 }
495
496 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
497 POSTING_READ(mmio);
498
499 /*
500 * Flush the TLB for this page
501 *
502 * FIXME: These two bits have disappeared on gen8, so a question
503 * arises: do we still need this and if so how should we go about
504 * invalidating the TLB?
505 */
506 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
507 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
508
509 /* ring should be idle before issuing a sync flush*/
510 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
511
512 I915_WRITE(reg,
513 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
514 INSTPM_SYNC_FLUSH));
515 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
516 1000))
517 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
518 engine->name);
519 }
520 }
521
522 static bool stop_ring(struct intel_engine_cs *engine)
523 {
524 struct drm_i915_private *dev_priv = to_i915(engine->dev);
525
526 if (!IS_GEN2(engine->dev)) {
527 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
528 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
529 DRM_ERROR("%s : timed out trying to stop ring\n",
530 engine->name);
531 /* Sometimes we observe that the idle flag is not
532 * set even though the ring is empty. So double
533 * check before giving up.
534 */
535 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
536 return false;
537 }
538 }
539
540 I915_WRITE_CTL(engine, 0);
541 I915_WRITE_HEAD(engine, 0);
542 engine->write_tail(engine, 0);
543
544 if (!IS_GEN2(engine->dev)) {
545 (void)I915_READ_CTL(engine);
546 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
547 }
548
549 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
550 }
551
552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
553 {
554 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
555 }
556
557 static int init_ring_common(struct intel_engine_cs *engine)
558 {
559 struct drm_device *dev = engine->dev;
560 struct drm_i915_private *dev_priv = dev->dev_private;
561 struct intel_ringbuffer *ringbuf = engine->buffer;
562 struct drm_i915_gem_object *obj = ringbuf->obj;
563 int ret = 0;
564
565 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
566
567 if (!stop_ring(engine)) {
568 /* G45 ring initialization often fails to reset head to zero */
569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
571 engine->name,
572 I915_READ_CTL(engine),
573 I915_READ_HEAD(engine),
574 I915_READ_TAIL(engine),
575 I915_READ_START(engine));
576
577 if (!stop_ring(engine)) {
578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
580 engine->name,
581 I915_READ_CTL(engine),
582 I915_READ_HEAD(engine),
583 I915_READ_TAIL(engine),
584 I915_READ_START(engine));
585 ret = -EIO;
586 goto out;
587 }
588 }
589
590 if (I915_NEED_GFX_HWS(dev))
591 intel_ring_setup_status_page(engine);
592 else
593 ring_setup_phys_status_page(engine);
594
595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(engine);
597
598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
602 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
603
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(engine))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 engine->name, I915_READ_HEAD(engine));
608 I915_WRITE_HEAD(engine, 0);
609 (void)I915_READ_HEAD(engine);
610
611 I915_WRITE_CTL(engine,
612 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
613 | RING_VALID);
614
615 /* If the head is still not zero, the ring is dead */
616 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
617 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
618 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
619 DRM_ERROR("%s initialization failed "
620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
621 engine->name,
622 I915_READ_CTL(engine),
623 I915_READ_CTL(engine) & RING_VALID,
624 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
625 I915_READ_START(engine),
626 (unsigned long)i915_gem_obj_ggtt_offset(obj));
627 ret = -EIO;
628 goto out;
629 }
630
631 ringbuf->last_retired_head = -1;
632 ringbuf->head = I915_READ_HEAD(engine);
633 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
634 intel_ring_update_space(ringbuf);
635
636 intel_engine_init_hangcheck(engine);
637
638 out:
639 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
640
641 return ret;
642 }
643
644 void
645 intel_fini_pipe_control(struct intel_engine_cs *engine)
646 {
647 struct drm_device *dev = engine->dev;
648
649 if (engine->scratch.obj == NULL)
650 return;
651
652 if (INTEL_INFO(dev)->gen >= 5) {
653 kunmap(sg_page(engine->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(engine->scratch.obj);
655 }
656
657 drm_gem_object_unreference(&engine->scratch.obj->base);
658 engine->scratch.obj = NULL;
659 }
660
661 int
662 intel_init_pipe_control(struct intel_engine_cs *engine)
663 {
664 int ret;
665
666 WARN_ON(engine->scratch.obj);
667
668 engine->scratch.obj = i915_gem_object_create(engine->dev, 4096);
669 if (IS_ERR(engine->scratch.obj)) {
670 DRM_ERROR("Failed to allocate seqno page\n");
671 ret = PTR_ERR(engine->scratch.obj);
672 engine->scratch.obj = NULL;
673 goto err;
674 }
675
676 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
677 I915_CACHE_LLC);
678 if (ret)
679 goto err_unref;
680
681 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
682 if (ret)
683 goto err_unref;
684
685 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
686 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
687 if (engine->scratch.cpu_page == NULL) {
688 ret = -ENOMEM;
689 goto err_unpin;
690 }
691
692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
693 engine->name, engine->scratch.gtt_offset);
694 return 0;
695
696 err_unpin:
697 i915_gem_object_ggtt_unpin(engine->scratch.obj);
698 err_unref:
699 drm_gem_object_unreference(&engine->scratch.obj->base);
700 err:
701 return ret;
702 }
703
704 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
705 {
706 int ret, i;
707 struct intel_engine_cs *engine = req->engine;
708 struct drm_device *dev = engine->dev;
709 struct drm_i915_private *dev_priv = dev->dev_private;
710 struct i915_workarounds *w = &dev_priv->workarounds;
711
712 if (w->count == 0)
713 return 0;
714
715 engine->gpu_caches_dirty = true;
716 ret = intel_ring_flush_all_caches(req);
717 if (ret)
718 return ret;
719
720 ret = intel_ring_begin(req, (w->count * 2 + 2));
721 if (ret)
722 return ret;
723
724 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
725 for (i = 0; i < w->count; i++) {
726 intel_ring_emit_reg(engine, w->reg[i].addr);
727 intel_ring_emit(engine, w->reg[i].value);
728 }
729 intel_ring_emit(engine, MI_NOOP);
730
731 intel_ring_advance(engine);
732
733 engine->gpu_caches_dirty = true;
734 ret = intel_ring_flush_all_caches(req);
735 if (ret)
736 return ret;
737
738 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
739
740 return 0;
741 }
742
743 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
744 {
745 int ret;
746
747 ret = intel_ring_workarounds_emit(req);
748 if (ret != 0)
749 return ret;
750
751 ret = i915_gem_render_state_init(req);
752 if (ret)
753 return ret;
754
755 return 0;
756 }
757
758 static int wa_add(struct drm_i915_private *dev_priv,
759 i915_reg_t addr,
760 const u32 mask, const u32 val)
761 {
762 const u32 idx = dev_priv->workarounds.count;
763
764 if (WARN_ON(idx >= I915_MAX_WA_REGS))
765 return -ENOSPC;
766
767 dev_priv->workarounds.reg[idx].addr = addr;
768 dev_priv->workarounds.reg[idx].value = val;
769 dev_priv->workarounds.reg[idx].mask = mask;
770
771 dev_priv->workarounds.count++;
772
773 return 0;
774 }
775
776 #define WA_REG(addr, mask, val) do { \
777 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
778 if (r) \
779 return r; \
780 } while (0)
781
782 #define WA_SET_BIT_MASKED(addr, mask) \
783 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
784
785 #define WA_CLR_BIT_MASKED(addr, mask) \
786 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
787
788 #define WA_SET_FIELD_MASKED(addr, mask, value) \
789 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
790
791 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
792 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
793
794 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
795
796 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
797 i915_reg_t reg)
798 {
799 struct drm_i915_private *dev_priv = engine->dev->dev_private;
800 struct i915_workarounds *wa = &dev_priv->workarounds;
801 const uint32_t index = wa->hw_whitelist_count[engine->id];
802
803 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
804 return -EINVAL;
805
806 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
807 i915_mmio_reg_offset(reg));
808 wa->hw_whitelist_count[engine->id]++;
809
810 return 0;
811 }
812
813 static int gen8_init_workarounds(struct intel_engine_cs *engine)
814 {
815 struct drm_device *dev = engine->dev;
816 struct drm_i915_private *dev_priv = dev->dev_private;
817
818 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
819
820 /* WaDisableAsyncFlipPerfMode:bdw,chv */
821 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
822
823 /* WaDisablePartialInstShootdown:bdw,chv */
824 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
825 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
826
827 /* Use Force Non-Coherent whenever executing a 3D context. This is a
828 * workaround for for a possible hang in the unlikely event a TLB
829 * invalidation occurs during a PSD flush.
830 */
831 /* WaForceEnableNonCoherent:bdw,chv */
832 /* WaHdcDisableFetchWhenMasked:bdw,chv */
833 WA_SET_BIT_MASKED(HDC_CHICKEN0,
834 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
835 HDC_FORCE_NON_COHERENT);
836
837 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
838 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
839 * polygons in the same 8x4 pixel/sample area to be processed without
840 * stalling waiting for the earlier ones to write to Hierarchical Z
841 * buffer."
842 *
843 * This optimization is off by default for BDW and CHV; turn it on.
844 */
845 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
846
847 /* Wa4x4STCOptimizationDisable:bdw,chv */
848 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
849
850 /*
851 * BSpec recommends 8x4 when MSAA is used,
852 * however in practice 16x4 seems fastest.
853 *
854 * Note that PS/WM thread counts depend on the WIZ hashing
855 * disable bit, which we don't touch here, but it's good
856 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
857 */
858 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
859 GEN6_WIZ_HASHING_MASK,
860 GEN6_WIZ_HASHING_16x4);
861
862 return 0;
863 }
864
865 static int bdw_init_workarounds(struct intel_engine_cs *engine)
866 {
867 int ret;
868 struct drm_device *dev = engine->dev;
869 struct drm_i915_private *dev_priv = dev->dev_private;
870
871 ret = gen8_init_workarounds(engine);
872 if (ret)
873 return ret;
874
875 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
876 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
877
878 /* WaDisableDopClockGating:bdw */
879 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
880 DOP_CLOCK_GATING_DISABLE);
881
882 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
883 GEN8_SAMPLER_POWER_BYPASS_DIS);
884
885 WA_SET_BIT_MASKED(HDC_CHICKEN0,
886 /* WaForceContextSaveRestoreNonCoherent:bdw */
887 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
888 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
889 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
890
891 return 0;
892 }
893
894 static int chv_init_workarounds(struct intel_engine_cs *engine)
895 {
896 int ret;
897 struct drm_device *dev = engine->dev;
898 struct drm_i915_private *dev_priv = dev->dev_private;
899
900 ret = gen8_init_workarounds(engine);
901 if (ret)
902 return ret;
903
904 /* WaDisableThreadStallDopClockGating:chv */
905 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
906
907 /* Improve HiZ throughput on CHV. */
908 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
909
910 return 0;
911 }
912
913 static int gen9_init_workarounds(struct intel_engine_cs *engine)
914 {
915 struct drm_device *dev = engine->dev;
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 uint32_t tmp;
918 int ret;
919
920 /* WaEnableLbsSlaRetryTimerDecrement:skl */
921 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
922 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
923
924 /* WaDisableKillLogic:bxt,skl */
925 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
926 ECOCHK_DIS_TLB);
927
928 /* WaClearFlowControlGpgpuContextSave:skl,bxt */
929 /* WaDisablePartialInstShootdown:skl,bxt */
930 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
931 FLOW_CONTROL_ENABLE |
932 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
933
934 /* Syncing dependencies between camera and graphics:skl,bxt */
935 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
936 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
937
938 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
939 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
940 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
941 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
942 GEN9_DG_MIRROR_FIX_ENABLE);
943
944 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
945 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
946 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
948 GEN9_RHWO_OPTIMIZATION_DISABLE);
949 /*
950 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
951 * but we do that in per ctx batchbuffer as there is an issue
952 * with this register not getting restored on ctx restore
953 */
954 }
955
956 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
957 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
958 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
959 GEN9_ENABLE_YV12_BUGFIX |
960 GEN9_ENABLE_GPGPU_PREEMPTION);
961
962 /* Wa4x4STCOptimizationDisable:skl,bxt */
963 /* WaDisablePartialResolveInVc:skl,bxt */
964 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
965 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
966
967 /* WaCcsTlbPrefetchDisable:skl,bxt */
968 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
969 GEN9_CCS_TLB_PREFETCH_ENABLE);
970
971 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
972 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
973 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
974 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
975 PIXEL_MASK_CAMMING_DISABLE);
976
977 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
978 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
979 if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
980 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
981 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
982 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
983
984 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
985 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
986 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
987 GEN8_SAMPLER_POWER_BYPASS_DIS);
988
989 /* WaDisableSTUnitPowerOptimization:skl,bxt */
990 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
991
992 /* WaOCLCoherentLineFlush:skl,bxt */
993 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
994 GEN8_LQSC_FLUSH_COHERENT_LINES));
995
996 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
997 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
998 if (ret)
999 return ret;
1000
1001 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1002 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1003 if (ret)
1004 return ret;
1005
1006 return 0;
1007 }
1008
1009 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1010 {
1011 struct drm_device *dev = engine->dev;
1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 u8 vals[3] = { 0, 0, 0 };
1014 unsigned int i;
1015
1016 for (i = 0; i < 3; i++) {
1017 u8 ss;
1018
1019 /*
1020 * Only consider slices where one, and only one, subslice has 7
1021 * EUs
1022 */
1023 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1024 continue;
1025
1026 /*
1027 * subslice_7eu[i] != 0 (because of the check above) and
1028 * ss_max == 4 (maximum number of subslices possible per slice)
1029 *
1030 * -> 0 <= ss <= 3;
1031 */
1032 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1033 vals[i] = 3 - ss;
1034 }
1035
1036 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1037 return 0;
1038
1039 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1040 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1041 GEN9_IZ_HASHING_MASK(2) |
1042 GEN9_IZ_HASHING_MASK(1) |
1043 GEN9_IZ_HASHING_MASK(0),
1044 GEN9_IZ_HASHING(2, vals[2]) |
1045 GEN9_IZ_HASHING(1, vals[1]) |
1046 GEN9_IZ_HASHING(0, vals[0]));
1047
1048 return 0;
1049 }
1050
1051 static int skl_init_workarounds(struct intel_engine_cs *engine)
1052 {
1053 int ret;
1054 struct drm_device *dev = engine->dev;
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056
1057 ret = gen9_init_workarounds(engine);
1058 if (ret)
1059 return ret;
1060
1061 /*
1062 * Actual WA is to disable percontext preemption granularity control
1063 * until D0 which is the default case so this is equivalent to
1064 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1065 */
1066 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1067 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1068 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1069 }
1070
1071 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1072 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1073 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1074 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1075 }
1076
1077 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1078 * involving this register should also be added to WA batch as required.
1079 */
1080 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1081 /* WaDisableLSQCROPERFforOCL:skl */
1082 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1083 GEN8_LQSC_RO_PERF_DIS);
1084
1085 /* WaEnableGapsTsvCreditFix:skl */
1086 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1087 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1088 GEN9_GAPS_TSV_CREDIT_DISABLE));
1089 }
1090
1091 /* WaDisablePowerCompilerClockGating:skl */
1092 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1093 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1094 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1095
1096 /* This is tied to WaForceContextSaveRestoreNonCoherent */
1097 if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1098 /*
1099 *Use Force Non-Coherent whenever executing a 3D context. This
1100 * is a workaround for a possible hang in the unlikely event
1101 * a TLB invalidation occurs during a PSD flush.
1102 */
1103 /* WaForceEnableNonCoherent:skl */
1104 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1105 HDC_FORCE_NON_COHERENT);
1106
1107 /* WaDisableHDCInvalidation:skl */
1108 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1109 BDW_DISABLE_HDC_INVALIDATION);
1110 }
1111
1112 /* WaBarrierPerformanceFixDisable:skl */
1113 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1114 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1115 HDC_FENCE_DEST_SLM_DISABLE |
1116 HDC_BARRIER_PERFORMANCE_DISABLE);
1117
1118 /* WaDisableSbeCacheDispatchPortSharing:skl */
1119 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1120 WA_SET_BIT_MASKED(
1121 GEN7_HALF_SLICE_CHICKEN1,
1122 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1123
1124 /* WaDisableLSQCROPERFforOCL:skl */
1125 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1126 if (ret)
1127 return ret;
1128
1129 return skl_tune_iz_hashing(engine);
1130 }
1131
1132 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1133 {
1134 int ret;
1135 struct drm_device *dev = engine->dev;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137
1138 ret = gen9_init_workarounds(engine);
1139 if (ret)
1140 return ret;
1141
1142 /* WaStoreMultiplePTEenable:bxt */
1143 /* This is a requirement according to Hardware specification */
1144 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1145 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1146
1147 /* WaSetClckGatingDisableMedia:bxt */
1148 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1149 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1150 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1151 }
1152
1153 /* WaDisableThreadStallDopClockGating:bxt */
1154 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1155 STALL_DOP_GATING_DISABLE);
1156
1157 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1158 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1159 WA_SET_BIT_MASKED(
1160 GEN7_HALF_SLICE_CHICKEN1,
1161 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1162 }
1163
1164 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1165 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1166 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1167 /* WaDisableLSQCROPERFforOCL:bxt */
1168 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1169 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1170 if (ret)
1171 return ret;
1172
1173 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1174 if (ret)
1175 return ret;
1176 }
1177
1178 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1179 if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
1180 I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT);
1181
1182 return 0;
1183 }
1184
1185 int init_workarounds_ring(struct intel_engine_cs *engine)
1186 {
1187 struct drm_device *dev = engine->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189
1190 WARN_ON(engine->id != RCS);
1191
1192 dev_priv->workarounds.count = 0;
1193 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1194
1195 if (IS_BROADWELL(dev))
1196 return bdw_init_workarounds(engine);
1197
1198 if (IS_CHERRYVIEW(dev))
1199 return chv_init_workarounds(engine);
1200
1201 if (IS_SKYLAKE(dev))
1202 return skl_init_workarounds(engine);
1203
1204 if (IS_BROXTON(dev))
1205 return bxt_init_workarounds(engine);
1206
1207 return 0;
1208 }
1209
1210 static int init_render_ring(struct intel_engine_cs *engine)
1211 {
1212 struct drm_device *dev = engine->dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 int ret = init_ring_common(engine);
1215 if (ret)
1216 return ret;
1217
1218 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1219 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1220 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1221
1222 /* We need to disable the AsyncFlip performance optimisations in order
1223 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1224 * programmed to '1' on all products.
1225 *
1226 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1227 */
1228 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1229 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1230
1231 /* Required for the hardware to program scanline values for waiting */
1232 /* WaEnableFlushTlbInvalidationMode:snb */
1233 if (INTEL_INFO(dev)->gen == 6)
1234 I915_WRITE(GFX_MODE,
1235 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1236
1237 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1238 if (IS_GEN7(dev))
1239 I915_WRITE(GFX_MODE_GEN7,
1240 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1241 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1242
1243 if (IS_GEN6(dev)) {
1244 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1245 * "If this bit is set, STCunit will have LRA as replacement
1246 * policy. [...] This bit must be reset. LRA replacement
1247 * policy is not supported."
1248 */
1249 I915_WRITE(CACHE_MODE_0,
1250 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1251 }
1252
1253 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1254 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1255
1256 if (HAS_L3_DPF(dev))
1257 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1258
1259 return init_workarounds_ring(engine);
1260 }
1261
1262 static void render_ring_cleanup(struct intel_engine_cs *engine)
1263 {
1264 struct drm_device *dev = engine->dev;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267 if (dev_priv->semaphore_obj) {
1268 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1269 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1270 dev_priv->semaphore_obj = NULL;
1271 }
1272
1273 intel_fini_pipe_control(engine);
1274 }
1275
1276 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1277 unsigned int num_dwords)
1278 {
1279 #define MBOX_UPDATE_DWORDS 8
1280 struct intel_engine_cs *signaller = signaller_req->engine;
1281 struct drm_device *dev = signaller->dev;
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 struct intel_engine_cs *waiter;
1284 enum intel_engine_id id;
1285 int ret, num_rings;
1286
1287 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1288 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1289 #undef MBOX_UPDATE_DWORDS
1290
1291 ret = intel_ring_begin(signaller_req, num_dwords);
1292 if (ret)
1293 return ret;
1294
1295 for_each_engine_id(waiter, dev_priv, id) {
1296 u32 seqno;
1297 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1298 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1299 continue;
1300
1301 seqno = i915_gem_request_get_seqno(signaller_req);
1302 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1303 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1304 PIPE_CONTROL_QW_WRITE |
1305 PIPE_CONTROL_FLUSH_ENABLE);
1306 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1307 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1308 intel_ring_emit(signaller, seqno);
1309 intel_ring_emit(signaller, 0);
1310 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1311 MI_SEMAPHORE_TARGET(waiter->id));
1312 intel_ring_emit(signaller, 0);
1313 }
1314
1315 return 0;
1316 }
1317
1318 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1319 unsigned int num_dwords)
1320 {
1321 #define MBOX_UPDATE_DWORDS 6
1322 struct intel_engine_cs *signaller = signaller_req->engine;
1323 struct drm_device *dev = signaller->dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct intel_engine_cs *waiter;
1326 enum intel_engine_id id;
1327 int ret, num_rings;
1328
1329 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1330 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1331 #undef MBOX_UPDATE_DWORDS
1332
1333 ret = intel_ring_begin(signaller_req, num_dwords);
1334 if (ret)
1335 return ret;
1336
1337 for_each_engine_id(waiter, dev_priv, id) {
1338 u32 seqno;
1339 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1340 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1341 continue;
1342
1343 seqno = i915_gem_request_get_seqno(signaller_req);
1344 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1345 MI_FLUSH_DW_OP_STOREDW);
1346 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1347 MI_FLUSH_DW_USE_GTT);
1348 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1349 intel_ring_emit(signaller, seqno);
1350 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1351 MI_SEMAPHORE_TARGET(waiter->id));
1352 intel_ring_emit(signaller, 0);
1353 }
1354
1355 return 0;
1356 }
1357
1358 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1359 unsigned int num_dwords)
1360 {
1361 struct intel_engine_cs *signaller = signaller_req->engine;
1362 struct drm_device *dev = signaller->dev;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 struct intel_engine_cs *useless;
1365 enum intel_engine_id id;
1366 int ret, num_rings;
1367
1368 #define MBOX_UPDATE_DWORDS 3
1369 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1370 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1371 #undef MBOX_UPDATE_DWORDS
1372
1373 ret = intel_ring_begin(signaller_req, num_dwords);
1374 if (ret)
1375 return ret;
1376
1377 for_each_engine_id(useless, dev_priv, id) {
1378 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1379
1380 if (i915_mmio_reg_valid(mbox_reg)) {
1381 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1382
1383 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1384 intel_ring_emit_reg(signaller, mbox_reg);
1385 intel_ring_emit(signaller, seqno);
1386 }
1387 }
1388
1389 /* If num_dwords was rounded, make sure the tail pointer is correct */
1390 if (num_rings % 2 == 0)
1391 intel_ring_emit(signaller, MI_NOOP);
1392
1393 return 0;
1394 }
1395
1396 /**
1397 * gen6_add_request - Update the semaphore mailbox registers
1398 *
1399 * @request - request to write to the ring
1400 *
1401 * Update the mailbox registers in the *other* rings with the current seqno.
1402 * This acts like a signal in the canonical semaphore.
1403 */
1404 static int
1405 gen6_add_request(struct drm_i915_gem_request *req)
1406 {
1407 struct intel_engine_cs *engine = req->engine;
1408 int ret;
1409
1410 if (engine->semaphore.signal)
1411 ret = engine->semaphore.signal(req, 4);
1412 else
1413 ret = intel_ring_begin(req, 4);
1414
1415 if (ret)
1416 return ret;
1417
1418 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1419 intel_ring_emit(engine,
1420 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1421 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1422 intel_ring_emit(engine, MI_USER_INTERRUPT);
1423 __intel_ring_advance(engine);
1424
1425 return 0;
1426 }
1427
1428 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1429 u32 seqno)
1430 {
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 return dev_priv->last_seqno < seqno;
1433 }
1434
1435 /**
1436 * intel_ring_sync - sync the waiter to the signaller on seqno
1437 *
1438 * @waiter - ring that is waiting
1439 * @signaller - ring which has, or will signal
1440 * @seqno - seqno which the waiter will block on
1441 */
1442
1443 static int
1444 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1445 struct intel_engine_cs *signaller,
1446 u32 seqno)
1447 {
1448 struct intel_engine_cs *waiter = waiter_req->engine;
1449 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1450 int ret;
1451
1452 ret = intel_ring_begin(waiter_req, 4);
1453 if (ret)
1454 return ret;
1455
1456 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1457 MI_SEMAPHORE_GLOBAL_GTT |
1458 MI_SEMAPHORE_POLL |
1459 MI_SEMAPHORE_SAD_GTE_SDD);
1460 intel_ring_emit(waiter, seqno);
1461 intel_ring_emit(waiter,
1462 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1463 intel_ring_emit(waiter,
1464 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1465 intel_ring_advance(waiter);
1466 return 0;
1467 }
1468
1469 static int
1470 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1471 struct intel_engine_cs *signaller,
1472 u32 seqno)
1473 {
1474 struct intel_engine_cs *waiter = waiter_req->engine;
1475 u32 dw1 = MI_SEMAPHORE_MBOX |
1476 MI_SEMAPHORE_COMPARE |
1477 MI_SEMAPHORE_REGISTER;
1478 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1479 int ret;
1480
1481 /* Throughout all of the GEM code, seqno passed implies our current
1482 * seqno is >= the last seqno executed. However for hardware the
1483 * comparison is strictly greater than.
1484 */
1485 seqno -= 1;
1486
1487 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1488
1489 ret = intel_ring_begin(waiter_req, 4);
1490 if (ret)
1491 return ret;
1492
1493 /* If seqno wrap happened, omit the wait with no-ops */
1494 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1495 intel_ring_emit(waiter, dw1 | wait_mbox);
1496 intel_ring_emit(waiter, seqno);
1497 intel_ring_emit(waiter, 0);
1498 intel_ring_emit(waiter, MI_NOOP);
1499 } else {
1500 intel_ring_emit(waiter, MI_NOOP);
1501 intel_ring_emit(waiter, MI_NOOP);
1502 intel_ring_emit(waiter, MI_NOOP);
1503 intel_ring_emit(waiter, MI_NOOP);
1504 }
1505 intel_ring_advance(waiter);
1506
1507 return 0;
1508 }
1509
1510 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1511 do { \
1512 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1513 PIPE_CONTROL_DEPTH_STALL); \
1514 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1515 intel_ring_emit(ring__, 0); \
1516 intel_ring_emit(ring__, 0); \
1517 } while (0)
1518
1519 static int
1520 pc_render_add_request(struct drm_i915_gem_request *req)
1521 {
1522 struct intel_engine_cs *engine = req->engine;
1523 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1524 int ret;
1525
1526 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1527 * incoherent with writes to memory, i.e. completely fubar,
1528 * so we need to use PIPE_NOTIFY instead.
1529 *
1530 * However, we also need to workaround the qword write
1531 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1532 * memory before requesting an interrupt.
1533 */
1534 ret = intel_ring_begin(req, 32);
1535 if (ret)
1536 return ret;
1537
1538 intel_ring_emit(engine,
1539 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1540 PIPE_CONTROL_WRITE_FLUSH |
1541 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1542 intel_ring_emit(engine,
1543 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1544 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1545 intel_ring_emit(engine, 0);
1546 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1547 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1548 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1549 scratch_addr += 2 * CACHELINE_BYTES;
1550 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1551 scratch_addr += 2 * CACHELINE_BYTES;
1552 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1553 scratch_addr += 2 * CACHELINE_BYTES;
1554 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1555 scratch_addr += 2 * CACHELINE_BYTES;
1556 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1557
1558 intel_ring_emit(engine,
1559 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1560 PIPE_CONTROL_WRITE_FLUSH |
1561 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1562 PIPE_CONTROL_NOTIFY);
1563 intel_ring_emit(engine,
1564 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1565 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1566 intel_ring_emit(engine, 0);
1567 __intel_ring_advance(engine);
1568
1569 return 0;
1570 }
1571
1572 static void
1573 gen6_seqno_barrier(struct intel_engine_cs *engine)
1574 {
1575 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1576
1577 /* Workaround to force correct ordering between irq and seqno writes on
1578 * ivb (and maybe also on snb) by reading from a CS register (like
1579 * ACTHD) before reading the status page.
1580 *
1581 * Note that this effectively stalls the read by the time it takes to
1582 * do a memory transaction, which more or less ensures that the write
1583 * from the GPU has sufficient time to invalidate the CPU cacheline.
1584 * Alternatively we could delay the interrupt from the CS ring to give
1585 * the write time to land, but that would incur a delay after every
1586 * batch i.e. much more frequent than a delay when waiting for the
1587 * interrupt (with the same net latency).
1588 *
1589 * Also note that to prevent whole machine hangs on gen7, we have to
1590 * take the spinlock to guard against concurrent cacheline access.
1591 */
1592 spin_lock_irq(&dev_priv->uncore.lock);
1593 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1594 spin_unlock_irq(&dev_priv->uncore.lock);
1595 }
1596
1597 static u32
1598 ring_get_seqno(struct intel_engine_cs *engine)
1599 {
1600 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1601 }
1602
1603 static void
1604 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1605 {
1606 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1607 }
1608
1609 static u32
1610 pc_render_get_seqno(struct intel_engine_cs *engine)
1611 {
1612 return engine->scratch.cpu_page[0];
1613 }
1614
1615 static void
1616 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1617 {
1618 engine->scratch.cpu_page[0] = seqno;
1619 }
1620
1621 static bool
1622 gen5_ring_get_irq(struct intel_engine_cs *engine)
1623 {
1624 struct drm_device *dev = engine->dev;
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 unsigned long flags;
1627
1628 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1629 return false;
1630
1631 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1632 if (engine->irq_refcount++ == 0)
1633 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1634 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1635
1636 return true;
1637 }
1638
1639 static void
1640 gen5_ring_put_irq(struct intel_engine_cs *engine)
1641 {
1642 struct drm_device *dev = engine->dev;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 unsigned long flags;
1645
1646 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1647 if (--engine->irq_refcount == 0)
1648 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1649 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1650 }
1651
1652 static bool
1653 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1654 {
1655 struct drm_device *dev = engine->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 unsigned long flags;
1658
1659 if (!intel_irqs_enabled(dev_priv))
1660 return false;
1661
1662 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1663 if (engine->irq_refcount++ == 0) {
1664 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1665 I915_WRITE(IMR, dev_priv->irq_mask);
1666 POSTING_READ(IMR);
1667 }
1668 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1669
1670 return true;
1671 }
1672
1673 static void
1674 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1675 {
1676 struct drm_device *dev = engine->dev;
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678 unsigned long flags;
1679
1680 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1681 if (--engine->irq_refcount == 0) {
1682 dev_priv->irq_mask |= engine->irq_enable_mask;
1683 I915_WRITE(IMR, dev_priv->irq_mask);
1684 POSTING_READ(IMR);
1685 }
1686 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1687 }
1688
1689 static bool
1690 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1691 {
1692 struct drm_device *dev = engine->dev;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 unsigned long flags;
1695
1696 if (!intel_irqs_enabled(dev_priv))
1697 return false;
1698
1699 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1700 if (engine->irq_refcount++ == 0) {
1701 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1702 I915_WRITE16(IMR, dev_priv->irq_mask);
1703 POSTING_READ16(IMR);
1704 }
1705 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1706
1707 return true;
1708 }
1709
1710 static void
1711 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1712 {
1713 struct drm_device *dev = engine->dev;
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1718 if (--engine->irq_refcount == 0) {
1719 dev_priv->irq_mask |= engine->irq_enable_mask;
1720 I915_WRITE16(IMR, dev_priv->irq_mask);
1721 POSTING_READ16(IMR);
1722 }
1723 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1724 }
1725
1726 static int
1727 bsd_ring_flush(struct drm_i915_gem_request *req,
1728 u32 invalidate_domains,
1729 u32 flush_domains)
1730 {
1731 struct intel_engine_cs *engine = req->engine;
1732 int ret;
1733
1734 ret = intel_ring_begin(req, 2);
1735 if (ret)
1736 return ret;
1737
1738 intel_ring_emit(engine, MI_FLUSH);
1739 intel_ring_emit(engine, MI_NOOP);
1740 intel_ring_advance(engine);
1741 return 0;
1742 }
1743
1744 static int
1745 i9xx_add_request(struct drm_i915_gem_request *req)
1746 {
1747 struct intel_engine_cs *engine = req->engine;
1748 int ret;
1749
1750 ret = intel_ring_begin(req, 4);
1751 if (ret)
1752 return ret;
1753
1754 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1755 intel_ring_emit(engine,
1756 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1757 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1758 intel_ring_emit(engine, MI_USER_INTERRUPT);
1759 __intel_ring_advance(engine);
1760
1761 return 0;
1762 }
1763
1764 static bool
1765 gen6_ring_get_irq(struct intel_engine_cs *engine)
1766 {
1767 struct drm_device *dev = engine->dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 unsigned long flags;
1770
1771 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1772 return false;
1773
1774 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1775 if (engine->irq_refcount++ == 0) {
1776 if (HAS_L3_DPF(dev) && engine->id == RCS)
1777 I915_WRITE_IMR(engine,
1778 ~(engine->irq_enable_mask |
1779 GT_PARITY_ERROR(dev)));
1780 else
1781 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1782 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1783 }
1784 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1785
1786 return true;
1787 }
1788
1789 static void
1790 gen6_ring_put_irq(struct intel_engine_cs *engine)
1791 {
1792 struct drm_device *dev = engine->dev;
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 unsigned long flags;
1795
1796 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1797 if (--engine->irq_refcount == 0) {
1798 if (HAS_L3_DPF(dev) && engine->id == RCS)
1799 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1800 else
1801 I915_WRITE_IMR(engine, ~0);
1802 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1803 }
1804 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1805 }
1806
1807 static bool
1808 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1809 {
1810 struct drm_device *dev = engine->dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 unsigned long flags;
1813
1814 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1815 return false;
1816
1817 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1818 if (engine->irq_refcount++ == 0) {
1819 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1820 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1821 }
1822 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1823
1824 return true;
1825 }
1826
1827 static void
1828 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1829 {
1830 struct drm_device *dev = engine->dev;
1831 struct drm_i915_private *dev_priv = dev->dev_private;
1832 unsigned long flags;
1833
1834 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1835 if (--engine->irq_refcount == 0) {
1836 I915_WRITE_IMR(engine, ~0);
1837 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1838 }
1839 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1840 }
1841
1842 static bool
1843 gen8_ring_get_irq(struct intel_engine_cs *engine)
1844 {
1845 struct drm_device *dev = engine->dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847 unsigned long flags;
1848
1849 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1850 return false;
1851
1852 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1853 if (engine->irq_refcount++ == 0) {
1854 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1855 I915_WRITE_IMR(engine,
1856 ~(engine->irq_enable_mask |
1857 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1858 } else {
1859 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1860 }
1861 POSTING_READ(RING_IMR(engine->mmio_base));
1862 }
1863 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1864
1865 return true;
1866 }
1867
1868 static void
1869 gen8_ring_put_irq(struct intel_engine_cs *engine)
1870 {
1871 struct drm_device *dev = engine->dev;
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 unsigned long flags;
1874
1875 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1876 if (--engine->irq_refcount == 0) {
1877 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1878 I915_WRITE_IMR(engine,
1879 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1880 } else {
1881 I915_WRITE_IMR(engine, ~0);
1882 }
1883 POSTING_READ(RING_IMR(engine->mmio_base));
1884 }
1885 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1886 }
1887
1888 static int
1889 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1890 u64 offset, u32 length,
1891 unsigned dispatch_flags)
1892 {
1893 struct intel_engine_cs *engine = req->engine;
1894 int ret;
1895
1896 ret = intel_ring_begin(req, 2);
1897 if (ret)
1898 return ret;
1899
1900 intel_ring_emit(engine,
1901 MI_BATCH_BUFFER_START |
1902 MI_BATCH_GTT |
1903 (dispatch_flags & I915_DISPATCH_SECURE ?
1904 0 : MI_BATCH_NON_SECURE_I965));
1905 intel_ring_emit(engine, offset);
1906 intel_ring_advance(engine);
1907
1908 return 0;
1909 }
1910
1911 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1912 #define I830_BATCH_LIMIT (256*1024)
1913 #define I830_TLB_ENTRIES (2)
1914 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1915 static int
1916 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1917 u64 offset, u32 len,
1918 unsigned dispatch_flags)
1919 {
1920 struct intel_engine_cs *engine = req->engine;
1921 u32 cs_offset = engine->scratch.gtt_offset;
1922 int ret;
1923
1924 ret = intel_ring_begin(req, 6);
1925 if (ret)
1926 return ret;
1927
1928 /* Evict the invalid PTE TLBs */
1929 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1930 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1931 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1932 intel_ring_emit(engine, cs_offset);
1933 intel_ring_emit(engine, 0xdeadbeef);
1934 intel_ring_emit(engine, MI_NOOP);
1935 intel_ring_advance(engine);
1936
1937 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1938 if (len > I830_BATCH_LIMIT)
1939 return -ENOSPC;
1940
1941 ret = intel_ring_begin(req, 6 + 2);
1942 if (ret)
1943 return ret;
1944
1945 /* Blit the batch (which has now all relocs applied) to the
1946 * stable batch scratch bo area (so that the CS never
1947 * stumbles over its tlb invalidation bug) ...
1948 */
1949 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1950 intel_ring_emit(engine,
1951 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1952 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1953 intel_ring_emit(engine, cs_offset);
1954 intel_ring_emit(engine, 4096);
1955 intel_ring_emit(engine, offset);
1956
1957 intel_ring_emit(engine, MI_FLUSH);
1958 intel_ring_emit(engine, MI_NOOP);
1959 intel_ring_advance(engine);
1960
1961 /* ... and execute it. */
1962 offset = cs_offset;
1963 }
1964
1965 ret = intel_ring_begin(req, 2);
1966 if (ret)
1967 return ret;
1968
1969 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1970 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1971 0 : MI_BATCH_NON_SECURE));
1972 intel_ring_advance(engine);
1973
1974 return 0;
1975 }
1976
1977 static int
1978 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1979 u64 offset, u32 len,
1980 unsigned dispatch_flags)
1981 {
1982 struct intel_engine_cs *engine = req->engine;
1983 int ret;
1984
1985 ret = intel_ring_begin(req, 2);
1986 if (ret)
1987 return ret;
1988
1989 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1990 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1991 0 : MI_BATCH_NON_SECURE));
1992 intel_ring_advance(engine);
1993
1994 return 0;
1995 }
1996
1997 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1998 {
1999 struct drm_i915_private *dev_priv = to_i915(engine->dev);
2000
2001 if (!dev_priv->status_page_dmah)
2002 return;
2003
2004 drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2005 engine->status_page.page_addr = NULL;
2006 }
2007
2008 static void cleanup_status_page(struct intel_engine_cs *engine)
2009 {
2010 struct drm_i915_gem_object *obj;
2011
2012 obj = engine->status_page.obj;
2013 if (obj == NULL)
2014 return;
2015
2016 kunmap(sg_page(obj->pages->sgl));
2017 i915_gem_object_ggtt_unpin(obj);
2018 drm_gem_object_unreference(&obj->base);
2019 engine->status_page.obj = NULL;
2020 }
2021
2022 static int init_status_page(struct intel_engine_cs *engine)
2023 {
2024 struct drm_i915_gem_object *obj = engine->status_page.obj;
2025
2026 if (obj == NULL) {
2027 unsigned flags;
2028 int ret;
2029
2030 obj = i915_gem_object_create(engine->dev, 4096);
2031 if (IS_ERR(obj)) {
2032 DRM_ERROR("Failed to allocate status page\n");
2033 return PTR_ERR(obj);
2034 }
2035
2036 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2037 if (ret)
2038 goto err_unref;
2039
2040 flags = 0;
2041 if (!HAS_LLC(engine->dev))
2042 /* On g33, we cannot place HWS above 256MiB, so
2043 * restrict its pinning to the low mappable arena.
2044 * Though this restriction is not documented for
2045 * gen4, gen5, or byt, they also behave similarly
2046 * and hang if the HWS is placed at the top of the
2047 * GTT. To generalise, it appears that all !llc
2048 * platforms have issues with us placing the HWS
2049 * above the mappable region (even though we never
2050 * actualy map it).
2051 */
2052 flags |= PIN_MAPPABLE;
2053 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2054 if (ret) {
2055 err_unref:
2056 drm_gem_object_unreference(&obj->base);
2057 return ret;
2058 }
2059
2060 engine->status_page.obj = obj;
2061 }
2062
2063 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2064 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2065 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2066
2067 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2068 engine->name, engine->status_page.gfx_addr);
2069
2070 return 0;
2071 }
2072
2073 static int init_phys_status_page(struct intel_engine_cs *engine)
2074 {
2075 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2076
2077 if (!dev_priv->status_page_dmah) {
2078 dev_priv->status_page_dmah =
2079 drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2080 if (!dev_priv->status_page_dmah)
2081 return -ENOMEM;
2082 }
2083
2084 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2085 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2086
2087 return 0;
2088 }
2089
2090 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2091 {
2092 GEM_BUG_ON(ringbuf->vma == NULL);
2093 GEM_BUG_ON(ringbuf->virtual_start == NULL);
2094
2095 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2096 i915_gem_object_unpin_map(ringbuf->obj);
2097 else
2098 i915_vma_unpin_iomap(ringbuf->vma);
2099 ringbuf->virtual_start = NULL;
2100
2101 i915_gem_object_ggtt_unpin(ringbuf->obj);
2102 ringbuf->vma = NULL;
2103 }
2104
2105 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2106 struct intel_ringbuffer *ringbuf)
2107 {
2108 struct drm_i915_private *dev_priv = to_i915(dev);
2109 struct drm_i915_gem_object *obj = ringbuf->obj;
2110 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2111 unsigned flags = PIN_OFFSET_BIAS | 4096;
2112 void *addr;
2113 int ret;
2114
2115 if (HAS_LLC(dev_priv) && !obj->stolen) {
2116 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2117 if (ret)
2118 return ret;
2119
2120 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2121 if (ret)
2122 goto err_unpin;
2123
2124 addr = i915_gem_object_pin_map(obj);
2125 if (IS_ERR(addr)) {
2126 ret = PTR_ERR(addr);
2127 goto err_unpin;
2128 }
2129 } else {
2130 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2131 flags | PIN_MAPPABLE);
2132 if (ret)
2133 return ret;
2134
2135 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2136 if (ret)
2137 goto err_unpin;
2138
2139 /* Access through the GTT requires the device to be awake. */
2140 assert_rpm_wakelock_held(dev_priv);
2141
2142 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2143 if (IS_ERR(addr)) {
2144 ret = PTR_ERR(addr);
2145 goto err_unpin;
2146 }
2147 }
2148
2149 ringbuf->virtual_start = addr;
2150 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2151 return 0;
2152
2153 err_unpin:
2154 i915_gem_object_ggtt_unpin(obj);
2155 return ret;
2156 }
2157
2158 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2159 {
2160 drm_gem_object_unreference(&ringbuf->obj->base);
2161 ringbuf->obj = NULL;
2162 }
2163
2164 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2165 struct intel_ringbuffer *ringbuf)
2166 {
2167 struct drm_i915_gem_object *obj;
2168
2169 obj = NULL;
2170 if (!HAS_LLC(dev))
2171 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2172 if (obj == NULL)
2173 obj = i915_gem_object_create(dev, ringbuf->size);
2174 if (IS_ERR(obj))
2175 return PTR_ERR(obj);
2176
2177 /* mark ring buffers as read-only from GPU side by default */
2178 obj->gt_ro = 1;
2179
2180 ringbuf->obj = obj;
2181
2182 return 0;
2183 }
2184
2185 struct intel_ringbuffer *
2186 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2187 {
2188 struct intel_ringbuffer *ring;
2189 int ret;
2190
2191 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2192 if (ring == NULL) {
2193 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2194 engine->name);
2195 return ERR_PTR(-ENOMEM);
2196 }
2197
2198 ring->engine = engine;
2199 list_add(&ring->link, &engine->buffers);
2200
2201 ring->size = size;
2202 /* Workaround an erratum on the i830 which causes a hang if
2203 * the TAIL pointer points to within the last 2 cachelines
2204 * of the buffer.
2205 */
2206 ring->effective_size = size;
2207 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2208 ring->effective_size -= 2 * CACHELINE_BYTES;
2209
2210 ring->last_retired_head = -1;
2211 intel_ring_update_space(ring);
2212
2213 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2214 if (ret) {
2215 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2216 engine->name, ret);
2217 list_del(&ring->link);
2218 kfree(ring);
2219 return ERR_PTR(ret);
2220 }
2221
2222 return ring;
2223 }
2224
2225 void
2226 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2227 {
2228 intel_destroy_ringbuffer_obj(ring);
2229 list_del(&ring->link);
2230 kfree(ring);
2231 }
2232
2233 static int intel_init_ring_buffer(struct drm_device *dev,
2234 struct intel_engine_cs *engine)
2235 {
2236 struct intel_ringbuffer *ringbuf;
2237 int ret;
2238
2239 WARN_ON(engine->buffer);
2240
2241 engine->dev = dev;
2242 INIT_LIST_HEAD(&engine->active_list);
2243 INIT_LIST_HEAD(&engine->request_list);
2244 INIT_LIST_HEAD(&engine->execlist_queue);
2245 INIT_LIST_HEAD(&engine->buffers);
2246 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2247 memset(engine->semaphore.sync_seqno, 0,
2248 sizeof(engine->semaphore.sync_seqno));
2249
2250 init_waitqueue_head(&engine->irq_queue);
2251
2252 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2253 if (IS_ERR(ringbuf)) {
2254 ret = PTR_ERR(ringbuf);
2255 goto error;
2256 }
2257 engine->buffer = ringbuf;
2258
2259 if (I915_NEED_GFX_HWS(dev)) {
2260 ret = init_status_page(engine);
2261 if (ret)
2262 goto error;
2263 } else {
2264 WARN_ON(engine->id != RCS);
2265 ret = init_phys_status_page(engine);
2266 if (ret)
2267 goto error;
2268 }
2269
2270 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2271 if (ret) {
2272 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2273 engine->name, ret);
2274 intel_destroy_ringbuffer_obj(ringbuf);
2275 goto error;
2276 }
2277
2278 ret = i915_cmd_parser_init_ring(engine);
2279 if (ret)
2280 goto error;
2281
2282 return 0;
2283
2284 error:
2285 intel_cleanup_engine(engine);
2286 return ret;
2287 }
2288
2289 void intel_cleanup_engine(struct intel_engine_cs *engine)
2290 {
2291 struct drm_i915_private *dev_priv;
2292
2293 if (!intel_engine_initialized(engine))
2294 return;
2295
2296 dev_priv = to_i915(engine->dev);
2297
2298 if (engine->buffer) {
2299 intel_stop_engine(engine);
2300 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2301
2302 intel_unpin_ringbuffer_obj(engine->buffer);
2303 intel_ringbuffer_free(engine->buffer);
2304 engine->buffer = NULL;
2305 }
2306
2307 if (engine->cleanup)
2308 engine->cleanup(engine);
2309
2310 if (I915_NEED_GFX_HWS(engine->dev)) {
2311 cleanup_status_page(engine);
2312 } else {
2313 WARN_ON(engine->id != RCS);
2314 cleanup_phys_status_page(engine);
2315 }
2316
2317 i915_cmd_parser_fini_ring(engine);
2318 i915_gem_batch_pool_fini(&engine->batch_pool);
2319 engine->dev = NULL;
2320 }
2321
2322 int intel_engine_idle(struct intel_engine_cs *engine)
2323 {
2324 struct drm_i915_gem_request *req;
2325
2326 /* Wait upon the last request to be completed */
2327 if (list_empty(&engine->request_list))
2328 return 0;
2329
2330 req = list_entry(engine->request_list.prev,
2331 struct drm_i915_gem_request,
2332 list);
2333
2334 /* Make sure we do not trigger any retires */
2335 return __i915_wait_request(req,
2336 req->i915->mm.interruptible,
2337 NULL, NULL);
2338 }
2339
2340 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2341 {
2342 int ret;
2343
2344 /* Flush enough space to reduce the likelihood of waiting after
2345 * we start building the request - in which case we will just
2346 * have to repeat work.
2347 */
2348 request->reserved_space += MIN_SPACE_FOR_ADD_REQUEST;
2349
2350 request->ringbuf = request->engine->buffer;
2351
2352 ret = intel_ring_begin(request, 0);
2353 if (ret)
2354 return ret;
2355
2356 request->reserved_space -= MIN_SPACE_FOR_ADD_REQUEST;
2357 return 0;
2358 }
2359
2360 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2361 {
2362 struct intel_ringbuffer *ringbuf = req->ringbuf;
2363 struct intel_engine_cs *engine = req->engine;
2364 struct drm_i915_gem_request *target;
2365
2366 intel_ring_update_space(ringbuf);
2367 if (ringbuf->space >= bytes)
2368 return 0;
2369
2370 /*
2371 * Space is reserved in the ringbuffer for finalising the request,
2372 * as that cannot be allowed to fail. During request finalisation,
2373 * reserved_space is set to 0 to stop the overallocation and the
2374 * assumption is that then we never need to wait (which has the
2375 * risk of failing with EINTR).
2376 *
2377 * See also i915_gem_request_alloc() and i915_add_request().
2378 */
2379 GEM_BUG_ON(!req->reserved_space);
2380
2381 list_for_each_entry(target, &engine->request_list, list) {
2382 unsigned space;
2383
2384 /*
2385 * The request queue is per-engine, so can contain requests
2386 * from multiple ringbuffers. Here, we must ignore any that
2387 * aren't from the ringbuffer we're considering.
2388 */
2389 if (target->ringbuf != ringbuf)
2390 continue;
2391
2392 /* Would completion of this request free enough space? */
2393 space = __intel_ring_space(target->postfix, ringbuf->tail,
2394 ringbuf->size);
2395 if (space >= bytes)
2396 break;
2397 }
2398
2399 if (WARN_ON(&target->list == &engine->request_list))
2400 return -ENOSPC;
2401
2402 return i915_wait_request(target);
2403 }
2404
2405 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2406 {
2407 struct intel_ringbuffer *ringbuf = req->ringbuf;
2408 int remain_actual = ringbuf->size - ringbuf->tail;
2409 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2410 int bytes = num_dwords * sizeof(u32);
2411 int total_bytes, wait_bytes;
2412 bool need_wrap = false;
2413
2414 total_bytes = bytes + req->reserved_space;
2415
2416 if (unlikely(bytes > remain_usable)) {
2417 /*
2418 * Not enough space for the basic request. So need to flush
2419 * out the remainder and then wait for base + reserved.
2420 */
2421 wait_bytes = remain_actual + total_bytes;
2422 need_wrap = true;
2423 } else if (unlikely(total_bytes > remain_usable)) {
2424 /*
2425 * The base request will fit but the reserved space
2426 * falls off the end. So we don't need an immediate wrap
2427 * and only need to effectively wait for the reserved
2428 * size space from the start of ringbuffer.
2429 */
2430 wait_bytes = remain_actual + req->reserved_space;
2431 } else {
2432 /* No wrapping required, just waiting. */
2433 wait_bytes = total_bytes;
2434 }
2435
2436 if (wait_bytes > ringbuf->space) {
2437 int ret = wait_for_space(req, wait_bytes);
2438 if (unlikely(ret))
2439 return ret;
2440
2441 intel_ring_update_space(ringbuf);
2442 }
2443
2444 if (unlikely(need_wrap)) {
2445 GEM_BUG_ON(remain_actual > ringbuf->space);
2446 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2447
2448 /* Fill the tail with MI_NOOP */
2449 memset(ringbuf->virtual_start + ringbuf->tail,
2450 0, remain_actual);
2451 ringbuf->tail = 0;
2452 ringbuf->space -= remain_actual;
2453 }
2454
2455 ringbuf->space -= bytes;
2456 GEM_BUG_ON(ringbuf->space < 0);
2457 return 0;
2458 }
2459
2460 /* Align the ring tail to a cacheline boundary */
2461 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2462 {
2463 struct intel_engine_cs *engine = req->engine;
2464 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2465 int ret;
2466
2467 if (num_dwords == 0)
2468 return 0;
2469
2470 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2471 ret = intel_ring_begin(req, num_dwords);
2472 if (ret)
2473 return ret;
2474
2475 while (num_dwords--)
2476 intel_ring_emit(engine, MI_NOOP);
2477
2478 intel_ring_advance(engine);
2479
2480 return 0;
2481 }
2482
2483 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2484 {
2485 struct drm_i915_private *dev_priv = to_i915(engine->dev);
2486
2487 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2488 * so long as the semaphore value in the register/page is greater
2489 * than the sync value), so whenever we reset the seqno,
2490 * so long as we reset the tracking semaphore value to 0, it will
2491 * always be before the next request's seqno. If we don't reset
2492 * the semaphore value, then when the seqno moves backwards all
2493 * future waits will complete instantly (causing rendering corruption).
2494 */
2495 if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2496 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2497 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2498 if (HAS_VEBOX(dev_priv))
2499 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2500 }
2501 if (dev_priv->semaphore_obj) {
2502 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2503 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2504 void *semaphores = kmap(page);
2505 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2506 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2507 kunmap(page);
2508 }
2509 memset(engine->semaphore.sync_seqno, 0,
2510 sizeof(engine->semaphore.sync_seqno));
2511
2512 engine->set_seqno(engine, seqno);
2513 engine->last_submitted_seqno = seqno;
2514
2515 engine->hangcheck.seqno = seqno;
2516 }
2517
2518 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2519 u32 value)
2520 {
2521 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2522
2523 /* Every tail move must follow the sequence below */
2524
2525 /* Disable notification that the ring is IDLE. The GT
2526 * will then assume that it is busy and bring it out of rc6.
2527 */
2528 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2529 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2530
2531 /* Clear the context id. Here be magic! */
2532 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2533
2534 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2535 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2536 GEN6_BSD_SLEEP_INDICATOR) == 0,
2537 50))
2538 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2539
2540 /* Now that the ring is fully powered up, update the tail */
2541 I915_WRITE_TAIL(engine, value);
2542 POSTING_READ(RING_TAIL(engine->mmio_base));
2543
2544 /* Let the ring send IDLE messages to the GT again,
2545 * and so let it sleep to conserve power when idle.
2546 */
2547 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2548 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2549 }
2550
2551 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2552 u32 invalidate, u32 flush)
2553 {
2554 struct intel_engine_cs *engine = req->engine;
2555 uint32_t cmd;
2556 int ret;
2557
2558 ret = intel_ring_begin(req, 4);
2559 if (ret)
2560 return ret;
2561
2562 cmd = MI_FLUSH_DW;
2563 if (INTEL_INFO(engine->dev)->gen >= 8)
2564 cmd += 1;
2565
2566 /* We always require a command barrier so that subsequent
2567 * commands, such as breadcrumb interrupts, are strictly ordered
2568 * wrt the contents of the write cache being flushed to memory
2569 * (and thus being coherent from the CPU).
2570 */
2571 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2572
2573 /*
2574 * Bspec vol 1c.5 - video engine command streamer:
2575 * "If ENABLED, all TLBs will be invalidated once the flush
2576 * operation is complete. This bit is only valid when the
2577 * Post-Sync Operation field is a value of 1h or 3h."
2578 */
2579 if (invalidate & I915_GEM_GPU_DOMAINS)
2580 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2581
2582 intel_ring_emit(engine, cmd);
2583 intel_ring_emit(engine,
2584 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2585 if (INTEL_INFO(engine->dev)->gen >= 8) {
2586 intel_ring_emit(engine, 0); /* upper addr */
2587 intel_ring_emit(engine, 0); /* value */
2588 } else {
2589 intel_ring_emit(engine, 0);
2590 intel_ring_emit(engine, MI_NOOP);
2591 }
2592 intel_ring_advance(engine);
2593 return 0;
2594 }
2595
2596 static int
2597 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2598 u64 offset, u32 len,
2599 unsigned dispatch_flags)
2600 {
2601 struct intel_engine_cs *engine = req->engine;
2602 bool ppgtt = USES_PPGTT(engine->dev) &&
2603 !(dispatch_flags & I915_DISPATCH_SECURE);
2604 int ret;
2605
2606 ret = intel_ring_begin(req, 4);
2607 if (ret)
2608 return ret;
2609
2610 /* FIXME(BDW): Address space and security selectors. */
2611 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2612 (dispatch_flags & I915_DISPATCH_RS ?
2613 MI_BATCH_RESOURCE_STREAMER : 0));
2614 intel_ring_emit(engine, lower_32_bits(offset));
2615 intel_ring_emit(engine, upper_32_bits(offset));
2616 intel_ring_emit(engine, MI_NOOP);
2617 intel_ring_advance(engine);
2618
2619 return 0;
2620 }
2621
2622 static int
2623 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2624 u64 offset, u32 len,
2625 unsigned dispatch_flags)
2626 {
2627 struct intel_engine_cs *engine = req->engine;
2628 int ret;
2629
2630 ret = intel_ring_begin(req, 2);
2631 if (ret)
2632 return ret;
2633
2634 intel_ring_emit(engine,
2635 MI_BATCH_BUFFER_START |
2636 (dispatch_flags & I915_DISPATCH_SECURE ?
2637 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2638 (dispatch_flags & I915_DISPATCH_RS ?
2639 MI_BATCH_RESOURCE_STREAMER : 0));
2640 /* bit0-7 is the length on GEN6+ */
2641 intel_ring_emit(engine, offset);
2642 intel_ring_advance(engine);
2643
2644 return 0;
2645 }
2646
2647 static int
2648 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2649 u64 offset, u32 len,
2650 unsigned dispatch_flags)
2651 {
2652 struct intel_engine_cs *engine = req->engine;
2653 int ret;
2654
2655 ret = intel_ring_begin(req, 2);
2656 if (ret)
2657 return ret;
2658
2659 intel_ring_emit(engine,
2660 MI_BATCH_BUFFER_START |
2661 (dispatch_flags & I915_DISPATCH_SECURE ?
2662 0 : MI_BATCH_NON_SECURE_I965));
2663 /* bit0-7 is the length on GEN6+ */
2664 intel_ring_emit(engine, offset);
2665 intel_ring_advance(engine);
2666
2667 return 0;
2668 }
2669
2670 /* Blitter support (SandyBridge+) */
2671
2672 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2673 u32 invalidate, u32 flush)
2674 {
2675 struct intel_engine_cs *engine = req->engine;
2676 struct drm_device *dev = engine->dev;
2677 uint32_t cmd;
2678 int ret;
2679
2680 ret = intel_ring_begin(req, 4);
2681 if (ret)
2682 return ret;
2683
2684 cmd = MI_FLUSH_DW;
2685 if (INTEL_INFO(dev)->gen >= 8)
2686 cmd += 1;
2687
2688 /* We always require a command barrier so that subsequent
2689 * commands, such as breadcrumb interrupts, are strictly ordered
2690 * wrt the contents of the write cache being flushed to memory
2691 * (and thus being coherent from the CPU).
2692 */
2693 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2694
2695 /*
2696 * Bspec vol 1c.3 - blitter engine command streamer:
2697 * "If ENABLED, all TLBs will be invalidated once the flush
2698 * operation is complete. This bit is only valid when the
2699 * Post-Sync Operation field is a value of 1h or 3h."
2700 */
2701 if (invalidate & I915_GEM_DOMAIN_RENDER)
2702 cmd |= MI_INVALIDATE_TLB;
2703 intel_ring_emit(engine, cmd);
2704 intel_ring_emit(engine,
2705 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2706 if (INTEL_INFO(dev)->gen >= 8) {
2707 intel_ring_emit(engine, 0); /* upper addr */
2708 intel_ring_emit(engine, 0); /* value */
2709 } else {
2710 intel_ring_emit(engine, 0);
2711 intel_ring_emit(engine, MI_NOOP);
2712 }
2713 intel_ring_advance(engine);
2714
2715 return 0;
2716 }
2717
2718 int intel_init_render_ring_buffer(struct drm_device *dev)
2719 {
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2722 struct drm_i915_gem_object *obj;
2723 int ret;
2724
2725 engine->name = "render ring";
2726 engine->id = RCS;
2727 engine->exec_id = I915_EXEC_RENDER;
2728 engine->mmio_base = RENDER_RING_BASE;
2729
2730 if (INTEL_INFO(dev)->gen >= 8) {
2731 if (i915_semaphore_is_enabled(dev)) {
2732 obj = i915_gem_object_create(dev, 4096);
2733 if (IS_ERR(obj)) {
2734 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2735 i915.semaphores = 0;
2736 } else {
2737 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2738 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2739 if (ret != 0) {
2740 drm_gem_object_unreference(&obj->base);
2741 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2742 i915.semaphores = 0;
2743 } else
2744 dev_priv->semaphore_obj = obj;
2745 }
2746 }
2747
2748 engine->init_context = intel_rcs_ctx_init;
2749 engine->add_request = gen6_add_request;
2750 engine->flush = gen8_render_ring_flush;
2751 engine->irq_get = gen8_ring_get_irq;
2752 engine->irq_put = gen8_ring_put_irq;
2753 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2754 engine->irq_seqno_barrier = gen6_seqno_barrier;
2755 engine->get_seqno = ring_get_seqno;
2756 engine->set_seqno = ring_set_seqno;
2757 if (i915_semaphore_is_enabled(dev)) {
2758 WARN_ON(!dev_priv->semaphore_obj);
2759 engine->semaphore.sync_to = gen8_ring_sync;
2760 engine->semaphore.signal = gen8_rcs_signal;
2761 GEN8_RING_SEMAPHORE_INIT(engine);
2762 }
2763 } else if (INTEL_INFO(dev)->gen >= 6) {
2764 engine->init_context = intel_rcs_ctx_init;
2765 engine->add_request = gen6_add_request;
2766 engine->flush = gen7_render_ring_flush;
2767 if (INTEL_INFO(dev)->gen == 6)
2768 engine->flush = gen6_render_ring_flush;
2769 engine->irq_get = gen6_ring_get_irq;
2770 engine->irq_put = gen6_ring_put_irq;
2771 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2772 engine->irq_seqno_barrier = gen6_seqno_barrier;
2773 engine->get_seqno = ring_get_seqno;
2774 engine->set_seqno = ring_set_seqno;
2775 if (i915_semaphore_is_enabled(dev)) {
2776 engine->semaphore.sync_to = gen6_ring_sync;
2777 engine->semaphore.signal = gen6_signal;
2778 /*
2779 * The current semaphore is only applied on pre-gen8
2780 * platform. And there is no VCS2 ring on the pre-gen8
2781 * platform. So the semaphore between RCS and VCS2 is
2782 * initialized as INVALID. Gen8 will initialize the
2783 * sema between VCS2 and RCS later.
2784 */
2785 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2786 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2787 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2788 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2789 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2790 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2791 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2792 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2793 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2794 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2795 }
2796 } else if (IS_GEN5(dev)) {
2797 engine->add_request = pc_render_add_request;
2798 engine->flush = gen4_render_ring_flush;
2799 engine->get_seqno = pc_render_get_seqno;
2800 engine->set_seqno = pc_render_set_seqno;
2801 engine->irq_get = gen5_ring_get_irq;
2802 engine->irq_put = gen5_ring_put_irq;
2803 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2804 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2805 } else {
2806 engine->add_request = i9xx_add_request;
2807 if (INTEL_INFO(dev)->gen < 4)
2808 engine->flush = gen2_render_ring_flush;
2809 else
2810 engine->flush = gen4_render_ring_flush;
2811 engine->get_seqno = ring_get_seqno;
2812 engine->set_seqno = ring_set_seqno;
2813 if (IS_GEN2(dev)) {
2814 engine->irq_get = i8xx_ring_get_irq;
2815 engine->irq_put = i8xx_ring_put_irq;
2816 } else {
2817 engine->irq_get = i9xx_ring_get_irq;
2818 engine->irq_put = i9xx_ring_put_irq;
2819 }
2820 engine->irq_enable_mask = I915_USER_INTERRUPT;
2821 }
2822 engine->write_tail = ring_write_tail;
2823
2824 if (IS_HASWELL(dev))
2825 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2826 else if (IS_GEN8(dev))
2827 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2828 else if (INTEL_INFO(dev)->gen >= 6)
2829 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2830 else if (INTEL_INFO(dev)->gen >= 4)
2831 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2832 else if (IS_I830(dev) || IS_845G(dev))
2833 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2834 else
2835 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2836 engine->init_hw = init_render_ring;
2837 engine->cleanup = render_ring_cleanup;
2838
2839 /* Workaround batchbuffer to combat CS tlb bug. */
2840 if (HAS_BROKEN_CS_TLB(dev)) {
2841 obj = i915_gem_object_create(dev, I830_WA_SIZE);
2842 if (IS_ERR(obj)) {
2843 DRM_ERROR("Failed to allocate batch bo\n");
2844 return PTR_ERR(obj);
2845 }
2846
2847 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2848 if (ret != 0) {
2849 drm_gem_object_unreference(&obj->base);
2850 DRM_ERROR("Failed to ping batch bo\n");
2851 return ret;
2852 }
2853
2854 engine->scratch.obj = obj;
2855 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2856 }
2857
2858 ret = intel_init_ring_buffer(dev, engine);
2859 if (ret)
2860 return ret;
2861
2862 if (INTEL_INFO(dev)->gen >= 5) {
2863 ret = intel_init_pipe_control(engine);
2864 if (ret)
2865 return ret;
2866 }
2867
2868 return 0;
2869 }
2870
2871 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2872 {
2873 struct drm_i915_private *dev_priv = dev->dev_private;
2874 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2875
2876 engine->name = "bsd ring";
2877 engine->id = VCS;
2878 engine->exec_id = I915_EXEC_BSD;
2879
2880 engine->write_tail = ring_write_tail;
2881 if (INTEL_INFO(dev)->gen >= 6) {
2882 engine->mmio_base = GEN6_BSD_RING_BASE;
2883 /* gen6 bsd needs a special wa for tail updates */
2884 if (IS_GEN6(dev))
2885 engine->write_tail = gen6_bsd_ring_write_tail;
2886 engine->flush = gen6_bsd_ring_flush;
2887 engine->add_request = gen6_add_request;
2888 engine->irq_seqno_barrier = gen6_seqno_barrier;
2889 engine->get_seqno = ring_get_seqno;
2890 engine->set_seqno = ring_set_seqno;
2891 if (INTEL_INFO(dev)->gen >= 8) {
2892 engine->irq_enable_mask =
2893 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2894 engine->irq_get = gen8_ring_get_irq;
2895 engine->irq_put = gen8_ring_put_irq;
2896 engine->dispatch_execbuffer =
2897 gen8_ring_dispatch_execbuffer;
2898 if (i915_semaphore_is_enabled(dev)) {
2899 engine->semaphore.sync_to = gen8_ring_sync;
2900 engine->semaphore.signal = gen8_xcs_signal;
2901 GEN8_RING_SEMAPHORE_INIT(engine);
2902 }
2903 } else {
2904 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2905 engine->irq_get = gen6_ring_get_irq;
2906 engine->irq_put = gen6_ring_put_irq;
2907 engine->dispatch_execbuffer =
2908 gen6_ring_dispatch_execbuffer;
2909 if (i915_semaphore_is_enabled(dev)) {
2910 engine->semaphore.sync_to = gen6_ring_sync;
2911 engine->semaphore.signal = gen6_signal;
2912 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2913 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2914 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2915 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2916 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2917 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2918 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2919 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2920 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2921 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2922 }
2923 }
2924 } else {
2925 engine->mmio_base = BSD_RING_BASE;
2926 engine->flush = bsd_ring_flush;
2927 engine->add_request = i9xx_add_request;
2928 engine->get_seqno = ring_get_seqno;
2929 engine->set_seqno = ring_set_seqno;
2930 if (IS_GEN5(dev)) {
2931 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2932 engine->irq_get = gen5_ring_get_irq;
2933 engine->irq_put = gen5_ring_put_irq;
2934 } else {
2935 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2936 engine->irq_get = i9xx_ring_get_irq;
2937 engine->irq_put = i9xx_ring_put_irq;
2938 }
2939 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2940 }
2941 engine->init_hw = init_ring_common;
2942
2943 return intel_init_ring_buffer(dev, engine);
2944 }
2945
2946 /**
2947 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2948 */
2949 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2950 {
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2953
2954 engine->name = "bsd2 ring";
2955 engine->id = VCS2;
2956 engine->exec_id = I915_EXEC_BSD;
2957
2958 engine->write_tail = ring_write_tail;
2959 engine->mmio_base = GEN8_BSD2_RING_BASE;
2960 engine->flush = gen6_bsd_ring_flush;
2961 engine->add_request = gen6_add_request;
2962 engine->irq_seqno_barrier = gen6_seqno_barrier;
2963 engine->get_seqno = ring_get_seqno;
2964 engine->set_seqno = ring_set_seqno;
2965 engine->irq_enable_mask =
2966 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2967 engine->irq_get = gen8_ring_get_irq;
2968 engine->irq_put = gen8_ring_put_irq;
2969 engine->dispatch_execbuffer =
2970 gen8_ring_dispatch_execbuffer;
2971 if (i915_semaphore_is_enabled(dev)) {
2972 engine->semaphore.sync_to = gen8_ring_sync;
2973 engine->semaphore.signal = gen8_xcs_signal;
2974 GEN8_RING_SEMAPHORE_INIT(engine);
2975 }
2976 engine->init_hw = init_ring_common;
2977
2978 return intel_init_ring_buffer(dev, engine);
2979 }
2980
2981 int intel_init_blt_ring_buffer(struct drm_device *dev)
2982 {
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2985
2986 engine->name = "blitter ring";
2987 engine->id = BCS;
2988 engine->exec_id = I915_EXEC_BLT;
2989
2990 engine->mmio_base = BLT_RING_BASE;
2991 engine->write_tail = ring_write_tail;
2992 engine->flush = gen6_ring_flush;
2993 engine->add_request = gen6_add_request;
2994 engine->irq_seqno_barrier = gen6_seqno_barrier;
2995 engine->get_seqno = ring_get_seqno;
2996 engine->set_seqno = ring_set_seqno;
2997 if (INTEL_INFO(dev)->gen >= 8) {
2998 engine->irq_enable_mask =
2999 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3000 engine->irq_get = gen8_ring_get_irq;
3001 engine->irq_put = gen8_ring_put_irq;
3002 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3003 if (i915_semaphore_is_enabled(dev)) {
3004 engine->semaphore.sync_to = gen8_ring_sync;
3005 engine->semaphore.signal = gen8_xcs_signal;
3006 GEN8_RING_SEMAPHORE_INIT(engine);
3007 }
3008 } else {
3009 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3010 engine->irq_get = gen6_ring_get_irq;
3011 engine->irq_put = gen6_ring_put_irq;
3012 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3013 if (i915_semaphore_is_enabled(dev)) {
3014 engine->semaphore.signal = gen6_signal;
3015 engine->semaphore.sync_to = gen6_ring_sync;
3016 /*
3017 * The current semaphore is only applied on pre-gen8
3018 * platform. And there is no VCS2 ring on the pre-gen8
3019 * platform. So the semaphore between BCS and VCS2 is
3020 * initialized as INVALID. Gen8 will initialize the
3021 * sema between BCS and VCS2 later.
3022 */
3023 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3024 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3025 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3026 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3027 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3028 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3029 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3030 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3031 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3032 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3033 }
3034 }
3035 engine->init_hw = init_ring_common;
3036
3037 return intel_init_ring_buffer(dev, engine);
3038 }
3039
3040 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3041 {
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3044
3045 engine->name = "video enhancement ring";
3046 engine->id = VECS;
3047 engine->exec_id = I915_EXEC_VEBOX;
3048
3049 engine->mmio_base = VEBOX_RING_BASE;
3050 engine->write_tail = ring_write_tail;
3051 engine->flush = gen6_ring_flush;
3052 engine->add_request = gen6_add_request;
3053 engine->irq_seqno_barrier = gen6_seqno_barrier;
3054 engine->get_seqno = ring_get_seqno;
3055 engine->set_seqno = ring_set_seqno;
3056
3057 if (INTEL_INFO(dev)->gen >= 8) {
3058 engine->irq_enable_mask =
3059 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3060 engine->irq_get = gen8_ring_get_irq;
3061 engine->irq_put = gen8_ring_put_irq;
3062 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3063 if (i915_semaphore_is_enabled(dev)) {
3064 engine->semaphore.sync_to = gen8_ring_sync;
3065 engine->semaphore.signal = gen8_xcs_signal;
3066 GEN8_RING_SEMAPHORE_INIT(engine);
3067 }
3068 } else {
3069 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3070 engine->irq_get = hsw_vebox_get_irq;
3071 engine->irq_put = hsw_vebox_put_irq;
3072 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3073 if (i915_semaphore_is_enabled(dev)) {
3074 engine->semaphore.sync_to = gen6_ring_sync;
3075 engine->semaphore.signal = gen6_signal;
3076 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3077 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3078 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3079 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3080 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3081 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3082 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3083 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3084 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3085 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3086 }
3087 }
3088 engine->init_hw = init_ring_common;
3089
3090 return intel_init_ring_buffer(dev, engine);
3091 }
3092
3093 int
3094 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3095 {
3096 struct intel_engine_cs *engine = req->engine;
3097 int ret;
3098
3099 if (!engine->gpu_caches_dirty)
3100 return 0;
3101
3102 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3103 if (ret)
3104 return ret;
3105
3106 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3107
3108 engine->gpu_caches_dirty = false;
3109 return 0;
3110 }
3111
3112 int
3113 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3114 {
3115 struct intel_engine_cs *engine = req->engine;
3116 uint32_t flush_domains;
3117 int ret;
3118
3119 flush_domains = 0;
3120 if (engine->gpu_caches_dirty)
3121 flush_domains = I915_GEM_GPU_DOMAINS;
3122
3123 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3124 if (ret)
3125 return ret;
3126
3127 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3128
3129 engine->gpu_caches_dirty = false;
3130 return 0;
3131 }
3132
3133 void
3134 intel_stop_engine(struct intel_engine_cs *engine)
3135 {
3136 int ret;
3137
3138 if (!intel_engine_initialized(engine))
3139 return;
3140
3141 ret = intel_engine_idle(engine);
3142 if (ret)
3143 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3144 engine->name, ret);
3145
3146 stop_ring(engine);
3147 }
Linux kernel - Deliverables
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