2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head
, int tail
, int size
)
44 int space
= head
- tail
;
47 return space
- I915_RING_FREE_SPACE
;
50 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
52 if (ringbuf
->last_retired_head
!= -1) {
53 ringbuf
->head
= ringbuf
->last_retired_head
;
54 ringbuf
->last_retired_head
= -1;
57 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
58 ringbuf
->tail
, ringbuf
->size
);
61 bool intel_engine_stopped(struct intel_engine_cs
*engine
)
63 struct drm_i915_private
*dev_priv
= engine
->i915
;
64 return dev_priv
->gpu_error
.stop_rings
& intel_engine_flag(engine
);
67 static void __intel_ring_advance(struct intel_engine_cs
*engine
)
69 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
70 ringbuf
->tail
&= ringbuf
->size
- 1;
71 if (intel_engine_stopped(engine
))
73 engine
->write_tail(engine
, ringbuf
->tail
);
77 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
78 u32 invalidate_domains
,
81 struct intel_engine_cs
*engine
= req
->engine
;
86 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
87 cmd
|= MI_NO_WRITE_FLUSH
;
89 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
92 ret
= intel_ring_begin(req
, 2);
96 intel_ring_emit(engine
, cmd
);
97 intel_ring_emit(engine
, MI_NOOP
);
98 intel_ring_advance(engine
);
104 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
105 u32 invalidate_domains
,
108 struct intel_engine_cs
*engine
= req
->engine
;
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
124 * I915_GEM_DOMAIN_COMMAND may not exist?
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
140 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
141 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
142 cmd
&= ~MI_NO_WRITE_FLUSH
;
143 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
146 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
147 (IS_G4X(req
->i915
) || IS_GEN5(req
->i915
)))
148 cmd
|= MI_INVALIDATE_ISP
;
150 ret
= intel_ring_begin(req
, 2);
154 intel_ring_emit(engine
, cmd
);
155 intel_ring_emit(engine
, MI_NOOP
);
156 intel_ring_advance(engine
);
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
174 * And the workaround for these two requires this workaround first:
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
201 struct intel_engine_cs
*engine
= req
->engine
;
202 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
205 ret
= intel_ring_begin(req
, 6);
209 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
211 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
212 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
213 intel_ring_emit(engine
, 0); /* low dword */
214 intel_ring_emit(engine
, 0); /* high dword */
215 intel_ring_emit(engine
, MI_NOOP
);
216 intel_ring_advance(engine
);
218 ret
= intel_ring_begin(req
, 6);
222 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine
, PIPE_CONTROL_QW_WRITE
);
224 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
225 intel_ring_emit(engine
, 0);
226 intel_ring_emit(engine
, 0);
227 intel_ring_emit(engine
, MI_NOOP
);
228 intel_ring_advance(engine
);
234 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
235 u32 invalidate_domains
, u32 flush_domains
)
237 struct intel_engine_cs
*engine
= req
->engine
;
239 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
242 /* Force SNB workarounds for PIPE_CONTROL flushes */
243 ret
= intel_emit_post_sync_nonzero_flush(req
);
247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
252 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
253 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
258 flags
|= PIPE_CONTROL_CS_STALL
;
260 if (invalidate_domains
) {
261 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
262 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
263 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
264 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
265 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
266 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
268 * TLB invalidate requires a post-sync write.
270 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
273 ret
= intel_ring_begin(req
, 4);
277 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine
, flags
);
279 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
280 intel_ring_emit(engine
, 0);
281 intel_ring_advance(engine
);
287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
289 struct intel_engine_cs
*engine
= req
->engine
;
292 ret
= intel_ring_begin(req
, 4);
296 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
298 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
299 intel_ring_emit(engine
, 0);
300 intel_ring_emit(engine
, 0);
301 intel_ring_advance(engine
);
307 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
308 u32 invalidate_domains
, u32 flush_domains
)
310 struct intel_engine_cs
*engine
= req
->engine
;
312 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
323 flags
|= PIPE_CONTROL_CS_STALL
;
325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
330 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
331 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
332 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
333 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
335 if (invalidate_domains
) {
336 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
337 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
338 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
339 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
340 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
341 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
342 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
344 * TLB invalidate requires a post-sync write.
346 flags
|= PIPE_CONTROL_QW_WRITE
;
347 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
349 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
354 gen7_render_ring_cs_stall_wa(req
);
357 ret
= intel_ring_begin(req
, 4);
361 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine
, flags
);
363 intel_ring_emit(engine
, scratch_addr
);
364 intel_ring_emit(engine
, 0);
365 intel_ring_advance(engine
);
371 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
372 u32 flags
, u32 scratch_addr
)
374 struct intel_engine_cs
*engine
= req
->engine
;
377 ret
= intel_ring_begin(req
, 6);
381 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine
, flags
);
383 intel_ring_emit(engine
, scratch_addr
);
384 intel_ring_emit(engine
, 0);
385 intel_ring_emit(engine
, 0);
386 intel_ring_emit(engine
, 0);
387 intel_ring_advance(engine
);
393 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
394 u32 invalidate_domains
, u32 flush_domains
)
397 u32 scratch_addr
= req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
400 flags
|= PIPE_CONTROL_CS_STALL
;
403 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
404 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
405 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
406 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
408 if (invalidate_domains
) {
409 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
410 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
411 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
412 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
413 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
414 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
415 flags
|= PIPE_CONTROL_QW_WRITE
;
416 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
419 ret
= gen8_emit_pipe_control(req
,
420 PIPE_CONTROL_CS_STALL
|
421 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
427 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
430 static void ring_write_tail(struct intel_engine_cs
*engine
,
433 struct drm_i915_private
*dev_priv
= engine
->i915
;
434 I915_WRITE_TAIL(engine
, value
);
437 u64
intel_ring_get_active_head(struct intel_engine_cs
*engine
)
439 struct drm_i915_private
*dev_priv
= engine
->i915
;
442 if (INTEL_GEN(dev_priv
) >= 8)
443 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
444 RING_ACTHD_UDW(engine
->mmio_base
));
445 else if (INTEL_GEN(dev_priv
) >= 4)
446 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
448 acthd
= I915_READ(ACTHD
);
453 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
455 struct drm_i915_private
*dev_priv
= engine
->i915
;
458 addr
= dev_priv
->status_page_dmah
->busaddr
;
459 if (INTEL_GEN(dev_priv
) >= 4)
460 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
461 I915_WRITE(HWS_PGA
, addr
);
464 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
466 struct drm_i915_private
*dev_priv
= engine
->i915
;
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
472 if (IS_GEN7(dev_priv
)) {
473 switch (engine
->id
) {
475 mmio
= RENDER_HWS_PGA_GEN7
;
478 mmio
= BLT_HWS_PGA_GEN7
;
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
486 mmio
= BSD_HWS_PGA_GEN7
;
489 mmio
= VEBOX_HWS_PGA_GEN7
;
492 } else if (IS_GEN6(dev_priv
)) {
493 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
495 /* XXX: gen8 returns to sanity */
496 mmio
= RING_HWS_PGA(engine
->mmio_base
);
499 I915_WRITE(mmio
, (u32
)engine
->status_page
.gfx_addr
);
503 * Flush the TLB for this page
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
509 if (IS_GEN(dev_priv
, 6, 7)) {
510 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
512 /* ring should be idle before issuing a sync flush*/
513 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
518 if (intel_wait_for_register(dev_priv
,
519 reg
, INSTPM_SYNC_FLUSH
, 0,
521 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
526 static bool stop_ring(struct intel_engine_cs
*engine
)
528 struct drm_i915_private
*dev_priv
= engine
->i915
;
530 if (!IS_GEN2(dev_priv
)) {
531 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
532 if (intel_wait_for_register(dev_priv
,
533 RING_MI_MODE(engine
->mmio_base
),
537 DRM_ERROR("%s : timed out trying to stop ring\n",
539 /* Sometimes we observe that the idle flag is not
540 * set even though the ring is empty. So double
541 * check before giving up.
543 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
548 I915_WRITE_CTL(engine
, 0);
549 I915_WRITE_HEAD(engine
, 0);
550 engine
->write_tail(engine
, 0);
552 if (!IS_GEN2(dev_priv
)) {
553 (void)I915_READ_CTL(engine
);
554 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
557 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
560 void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
)
562 memset(&engine
->hangcheck
, 0, sizeof(engine
->hangcheck
));
565 static int init_ring_common(struct intel_engine_cs
*engine
)
567 struct drm_i915_private
*dev_priv
= engine
->i915
;
568 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
569 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
572 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
574 if (!stop_ring(engine
)) {
575 /* G45 ring initialization often fails to reset head to zero */
576 DRM_DEBUG_KMS("%s head not reset to zero "
577 "ctl %08x head %08x tail %08x start %08x\n",
579 I915_READ_CTL(engine
),
580 I915_READ_HEAD(engine
),
581 I915_READ_TAIL(engine
),
582 I915_READ_START(engine
));
584 if (!stop_ring(engine
)) {
585 DRM_ERROR("failed to set %s head to zero "
586 "ctl %08x head %08x tail %08x start %08x\n",
588 I915_READ_CTL(engine
),
589 I915_READ_HEAD(engine
),
590 I915_READ_TAIL(engine
),
591 I915_READ_START(engine
));
597 if (I915_NEED_GFX_HWS(dev_priv
))
598 intel_ring_setup_status_page(engine
);
600 ring_setup_phys_status_page(engine
);
602 /* Enforce ordering by reading HEAD register back */
603 I915_READ_HEAD(engine
);
605 /* Initialize the ring. This must happen _after_ we've cleared the ring
606 * registers with the above sequence (the readback of the HEAD registers
607 * also enforces ordering), otherwise the hw might lose the new ring
608 * register values. */
609 I915_WRITE_START(engine
, i915_gem_obj_ggtt_offset(obj
));
611 /* WaClearRingBufHeadRegAtInit:ctg,elk */
612 if (I915_READ_HEAD(engine
))
613 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
614 engine
->name
, I915_READ_HEAD(engine
));
615 I915_WRITE_HEAD(engine
, 0);
616 (void)I915_READ_HEAD(engine
);
618 I915_WRITE_CTL(engine
,
619 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
622 /* If the head is still not zero, the ring is dead */
623 if (wait_for((I915_READ_CTL(engine
) & RING_VALID
) != 0 &&
624 I915_READ_START(engine
) == i915_gem_obj_ggtt_offset(obj
) &&
625 (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0, 50)) {
626 DRM_ERROR("%s initialization failed "
627 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
629 I915_READ_CTL(engine
),
630 I915_READ_CTL(engine
) & RING_VALID
,
631 I915_READ_HEAD(engine
), I915_READ_TAIL(engine
),
632 I915_READ_START(engine
),
633 (unsigned long)i915_gem_obj_ggtt_offset(obj
));
638 ringbuf
->last_retired_head
= -1;
639 ringbuf
->head
= I915_READ_HEAD(engine
);
640 ringbuf
->tail
= I915_READ_TAIL(engine
) & TAIL_ADDR
;
641 intel_ring_update_space(ringbuf
);
643 intel_engine_init_hangcheck(engine
);
646 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
652 intel_fini_pipe_control(struct intel_engine_cs
*engine
)
654 if (engine
->scratch
.obj
== NULL
)
657 if (INTEL_GEN(engine
->i915
) >= 5) {
658 kunmap(sg_page(engine
->scratch
.obj
->pages
->sgl
));
659 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
662 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
663 engine
->scratch
.obj
= NULL
;
667 intel_init_pipe_control(struct intel_engine_cs
*engine
)
671 WARN_ON(engine
->scratch
.obj
);
673 engine
->scratch
.obj
= i915_gem_object_create(engine
->i915
->dev
, 4096);
674 if (IS_ERR(engine
->scratch
.obj
)) {
675 DRM_ERROR("Failed to allocate seqno page\n");
676 ret
= PTR_ERR(engine
->scratch
.obj
);
677 engine
->scratch
.obj
= NULL
;
681 ret
= i915_gem_object_set_cache_level(engine
->scratch
.obj
,
686 ret
= i915_gem_obj_ggtt_pin(engine
->scratch
.obj
, 4096, 0);
690 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(engine
->scratch
.obj
);
691 engine
->scratch
.cpu_page
= kmap(sg_page(engine
->scratch
.obj
->pages
->sgl
));
692 if (engine
->scratch
.cpu_page
== NULL
) {
697 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
698 engine
->name
, engine
->scratch
.gtt_offset
);
702 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
704 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
709 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
711 struct intel_engine_cs
*engine
= req
->engine
;
712 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
718 engine
->gpu_caches_dirty
= true;
719 ret
= intel_ring_flush_all_caches(req
);
723 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
727 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(w
->count
));
728 for (i
= 0; i
< w
->count
; i
++) {
729 intel_ring_emit_reg(engine
, w
->reg
[i
].addr
);
730 intel_ring_emit(engine
, w
->reg
[i
].value
);
732 intel_ring_emit(engine
, MI_NOOP
);
734 intel_ring_advance(engine
);
736 engine
->gpu_caches_dirty
= true;
737 ret
= intel_ring_flush_all_caches(req
);
741 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
746 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
750 ret
= intel_ring_workarounds_emit(req
);
754 ret
= i915_gem_render_state_init(req
);
761 static int wa_add(struct drm_i915_private
*dev_priv
,
763 const u32 mask
, const u32 val
)
765 const u32 idx
= dev_priv
->workarounds
.count
;
767 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
770 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
771 dev_priv
->workarounds
.reg
[idx
].value
= val
;
772 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
774 dev_priv
->workarounds
.count
++;
779 #define WA_REG(addr, mask, val) do { \
780 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
785 #define WA_SET_BIT_MASKED(addr, mask) \
786 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
788 #define WA_CLR_BIT_MASKED(addr, mask) \
789 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
791 #define WA_SET_FIELD_MASKED(addr, mask, value) \
792 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
794 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
795 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
797 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
799 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
802 struct drm_i915_private
*dev_priv
= engine
->i915
;
803 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
804 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
806 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
809 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
810 i915_mmio_reg_offset(reg
));
811 wa
->hw_whitelist_count
[engine
->id
]++;
816 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
818 struct drm_i915_private
*dev_priv
= engine
->i915
;
820 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
822 /* WaDisableAsyncFlipPerfMode:bdw,chv */
823 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
825 /* WaDisablePartialInstShootdown:bdw,chv */
826 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
827 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
829 /* Use Force Non-Coherent whenever executing a 3D context. This is a
830 * workaround for for a possible hang in the unlikely event a TLB
831 * invalidation occurs during a PSD flush.
833 /* WaForceEnableNonCoherent:bdw,chv */
834 /* WaHdcDisableFetchWhenMasked:bdw,chv */
835 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
836 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
837 HDC_FORCE_NON_COHERENT
);
839 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
840 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
841 * polygons in the same 8x4 pixel/sample area to be processed without
842 * stalling waiting for the earlier ones to write to Hierarchical Z
845 * This optimization is off by default for BDW and CHV; turn it on.
847 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
849 /* Wa4x4STCOptimizationDisable:bdw,chv */
850 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
853 * BSpec recommends 8x4 when MSAA is used,
854 * however in practice 16x4 seems fastest.
856 * Note that PS/WM thread counts depend on the WIZ hashing
857 * disable bit, which we don't touch here, but it's good
858 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
860 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
861 GEN6_WIZ_HASHING_MASK
,
862 GEN6_WIZ_HASHING_16x4
);
867 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
869 struct drm_i915_private
*dev_priv
= engine
->i915
;
872 ret
= gen8_init_workarounds(engine
);
876 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
877 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
879 /* WaDisableDopClockGating:bdw */
880 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
881 DOP_CLOCK_GATING_DISABLE
);
883 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
884 GEN8_SAMPLER_POWER_BYPASS_DIS
);
886 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
887 /* WaForceContextSaveRestoreNonCoherent:bdw */
888 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
889 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
890 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
895 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
897 struct drm_i915_private
*dev_priv
= engine
->i915
;
900 ret
= gen8_init_workarounds(engine
);
904 /* WaDisableThreadStallDopClockGating:chv */
905 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
907 /* Improve HiZ throughput on CHV. */
908 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
913 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
915 struct drm_i915_private
*dev_priv
= engine
->i915
;
918 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
919 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
921 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
922 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
923 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
925 /* WaDisableKillLogic:bxt,skl,kbl */
926 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
929 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
930 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
931 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
932 FLOW_CONTROL_ENABLE
|
933 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
935 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
936 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
937 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
940 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
941 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
942 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
943 GEN9_DG_MIRROR_FIX_ENABLE
);
945 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
946 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
947 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
948 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
949 GEN9_RHWO_OPTIMIZATION_DISABLE
);
951 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
952 * but we do that in per ctx batchbuffer as there is an issue
953 * with this register not getting restored on ctx restore
957 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
958 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
959 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
960 GEN9_ENABLE_YV12_BUGFIX
|
961 GEN9_ENABLE_GPGPU_PREEMPTION
);
963 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
964 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
965 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
966 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
968 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
969 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
970 GEN9_CCS_TLB_PREFETCH_ENABLE
);
972 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
973 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_C0
) ||
974 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
975 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
976 PIXEL_MASK_CAMMING_DISABLE
);
978 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
979 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
980 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
981 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
983 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
984 * both tied to WaForceContextSaveRestoreNonCoherent
985 * in some hsds for skl. We keep the tie for all gen9. The
986 * documentation is a bit hazy and so we want to get common behaviour,
987 * even though there is no clear evidence we would need both on kbl/bxt.
988 * This area has been source of system hangs so we play it safe
989 * and mimic the skl regardless of what bspec says.
991 * Use Force Non-Coherent whenever executing a 3D context. This
992 * is a workaround for a possible hang in the unlikely event
993 * a TLB invalidation occurs during a PSD flush.
996 /* WaForceEnableNonCoherent:skl,bxt,kbl */
997 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
998 HDC_FORCE_NON_COHERENT
);
1000 /* WaDisableHDCInvalidation:skl,bxt,kbl */
1001 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
1002 BDW_DISABLE_HDC_INVALIDATION
);
1004 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1005 if (IS_SKYLAKE(dev_priv
) ||
1006 IS_KABYLAKE(dev_priv
) ||
1007 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1008 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
1009 GEN8_SAMPLER_POWER_BYPASS_DIS
);
1011 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1012 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
1014 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1015 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
1016 GEN8_LQSC_FLUSH_COHERENT_LINES
));
1018 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1019 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
1023 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1024 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
1028 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1029 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
1036 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
1038 struct drm_i915_private
*dev_priv
= engine
->i915
;
1039 u8 vals
[3] = { 0, 0, 0 };
1042 for (i
= 0; i
< 3; i
++) {
1046 * Only consider slices where one, and only one, subslice has 7
1049 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1053 * subslice_7eu[i] != 0 (because of the check above) and
1054 * ss_max == 4 (maximum number of subslices possible per slice)
1058 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1062 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1065 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1066 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1067 GEN9_IZ_HASHING_MASK(2) |
1068 GEN9_IZ_HASHING_MASK(1) |
1069 GEN9_IZ_HASHING_MASK(0),
1070 GEN9_IZ_HASHING(2, vals
[2]) |
1071 GEN9_IZ_HASHING(1, vals
[1]) |
1072 GEN9_IZ_HASHING(0, vals
[0]));
1077 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
1079 struct drm_i915_private
*dev_priv
= engine
->i915
;
1082 ret
= gen9_init_workarounds(engine
);
1087 * Actual WA is to disable percontext preemption granularity control
1088 * until D0 which is the default case so this is equivalent to
1089 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1091 if (IS_SKL_REVID(dev_priv
, SKL_REVID_E0
, REVID_FOREVER
)) {
1092 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
1093 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
1096 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
)) {
1097 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1098 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1099 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1102 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1103 * involving this register should also be added to WA batch as required.
1105 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
))
1106 /* WaDisableLSQCROPERFforOCL:skl */
1107 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1108 GEN8_LQSC_RO_PERF_DIS
);
1110 /* WaEnableGapsTsvCreditFix:skl */
1111 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, REVID_FOREVER
)) {
1112 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1113 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1116 /* WaDisablePowerCompilerClockGating:skl */
1117 if (IS_SKL_REVID(dev_priv
, SKL_REVID_B0
, SKL_REVID_B0
))
1118 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1119 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1121 /* WaBarrierPerformanceFixDisable:skl */
1122 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_D0
))
1123 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1124 HDC_FENCE_DEST_SLM_DISABLE
|
1125 HDC_BARRIER_PERFORMANCE_DISABLE
);
1127 /* WaDisableSbeCacheDispatchPortSharing:skl */
1128 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
))
1130 GEN7_HALF_SLICE_CHICKEN1
,
1131 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1133 /* WaDisableGafsUnitClkGating:skl */
1134 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1136 /* WaDisableLSQCROPERFforOCL:skl */
1137 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1141 return skl_tune_iz_hashing(engine
);
1144 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1146 struct drm_i915_private
*dev_priv
= engine
->i915
;
1149 ret
= gen9_init_workarounds(engine
);
1153 /* WaStoreMultiplePTEenable:bxt */
1154 /* This is a requirement according to Hardware specification */
1155 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1156 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1158 /* WaSetClckGatingDisableMedia:bxt */
1159 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1160 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1161 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1164 /* WaDisableThreadStallDopClockGating:bxt */
1165 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1166 STALL_DOP_GATING_DISABLE
);
1168 /* WaDisablePooledEuLoadBalancingFix:bxt */
1169 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1170 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2
,
1171 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
);
1174 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1175 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1177 GEN7_HALF_SLICE_CHICKEN1
,
1178 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1181 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1182 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1183 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1184 /* WaDisableLSQCROPERFforOCL:bxt */
1185 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1186 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1190 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1195 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1196 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
1197 I915_WRITE(GEN8_L3SQCREG1
, L3_GENERAL_PRIO_CREDITS(62) |
1198 L3_HIGH_PRIO_CREDITS(2));
1200 /* WaInsertDummyPushConstPs:bxt */
1201 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1202 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1203 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1208 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1210 struct drm_i915_private
*dev_priv
= engine
->i915
;
1213 ret
= gen9_init_workarounds(engine
);
1217 /* WaEnableGapsTsvCreditFix:kbl */
1218 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1219 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1221 /* WaDisableDynamicCreditSharing:kbl */
1222 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1223 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1224 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1226 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1227 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1228 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1229 HDC_FENCE_DEST_SLM_DISABLE
);
1231 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1232 * involving this register should also be added to WA batch as required.
1234 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1235 /* WaDisableLSQCROPERFforOCL:kbl */
1236 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1237 GEN8_LQSC_RO_PERF_DIS
);
1239 /* WaInsertDummyPushConstPs:kbl */
1240 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1241 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1242 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1244 /* WaDisableGafsUnitClkGating:kbl */
1245 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1247 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1249 GEN7_HALF_SLICE_CHICKEN1
,
1250 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1252 /* WaDisableLSQCROPERFforOCL:kbl */
1253 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1260 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1262 struct drm_i915_private
*dev_priv
= engine
->i915
;
1264 WARN_ON(engine
->id
!= RCS
);
1266 dev_priv
->workarounds
.count
= 0;
1267 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1269 if (IS_BROADWELL(dev_priv
))
1270 return bdw_init_workarounds(engine
);
1272 if (IS_CHERRYVIEW(dev_priv
))
1273 return chv_init_workarounds(engine
);
1275 if (IS_SKYLAKE(dev_priv
))
1276 return skl_init_workarounds(engine
);
1278 if (IS_BROXTON(dev_priv
))
1279 return bxt_init_workarounds(engine
);
1281 if (IS_KABYLAKE(dev_priv
))
1282 return kbl_init_workarounds(engine
);
1287 static int init_render_ring(struct intel_engine_cs
*engine
)
1289 struct drm_i915_private
*dev_priv
= engine
->i915
;
1290 int ret
= init_ring_common(engine
);
1294 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1295 if (IS_GEN(dev_priv
, 4, 6))
1296 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1298 /* We need to disable the AsyncFlip performance optimisations in order
1299 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1300 * programmed to '1' on all products.
1302 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1304 if (IS_GEN(dev_priv
, 6, 7))
1305 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1307 /* Required for the hardware to program scanline values for waiting */
1308 /* WaEnableFlushTlbInvalidationMode:snb */
1309 if (IS_GEN6(dev_priv
))
1310 I915_WRITE(GFX_MODE
,
1311 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1313 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1314 if (IS_GEN7(dev_priv
))
1315 I915_WRITE(GFX_MODE_GEN7
,
1316 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1317 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1319 if (IS_GEN6(dev_priv
)) {
1320 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1321 * "If this bit is set, STCunit will have LRA as replacement
1322 * policy. [...] This bit must be reset. LRA replacement
1323 * policy is not supported."
1325 I915_WRITE(CACHE_MODE_0
,
1326 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1329 if (IS_GEN(dev_priv
, 6, 7))
1330 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1332 if (HAS_L3_DPF(dev_priv
))
1333 I915_WRITE_IMR(engine
, ~GT_PARITY_ERROR(dev_priv
));
1335 return init_workarounds_ring(engine
);
1338 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1340 struct drm_i915_private
*dev_priv
= engine
->i915
;
1342 if (dev_priv
->semaphore_obj
) {
1343 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1344 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1345 dev_priv
->semaphore_obj
= NULL
;
1348 intel_fini_pipe_control(engine
);
1351 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1352 unsigned int num_dwords
)
1354 #define MBOX_UPDATE_DWORDS 8
1355 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1356 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1357 struct intel_engine_cs
*waiter
;
1358 enum intel_engine_id id
;
1361 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1362 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1363 #undef MBOX_UPDATE_DWORDS
1365 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1369 for_each_engine_id(waiter
, dev_priv
, id
) {
1371 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1372 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1375 seqno
= i915_gem_request_get_seqno(signaller_req
);
1376 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1377 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1378 PIPE_CONTROL_QW_WRITE
|
1379 PIPE_CONTROL_CS_STALL
);
1380 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1381 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1382 intel_ring_emit(signaller
, seqno
);
1383 intel_ring_emit(signaller
, 0);
1384 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1385 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1386 intel_ring_emit(signaller
, 0);
1392 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1393 unsigned int num_dwords
)
1395 #define MBOX_UPDATE_DWORDS 6
1396 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1397 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1398 struct intel_engine_cs
*waiter
;
1399 enum intel_engine_id id
;
1402 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1403 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1404 #undef MBOX_UPDATE_DWORDS
1406 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1410 for_each_engine_id(waiter
, dev_priv
, id
) {
1412 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1413 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1416 seqno
= i915_gem_request_get_seqno(signaller_req
);
1417 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1418 MI_FLUSH_DW_OP_STOREDW
);
1419 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1420 MI_FLUSH_DW_USE_GTT
);
1421 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1422 intel_ring_emit(signaller
, seqno
);
1423 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1424 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1425 intel_ring_emit(signaller
, 0);
1431 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1432 unsigned int num_dwords
)
1434 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1435 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1436 struct intel_engine_cs
*useless
;
1437 enum intel_engine_id id
;
1440 #define MBOX_UPDATE_DWORDS 3
1441 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1442 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1443 #undef MBOX_UPDATE_DWORDS
1445 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1449 for_each_engine_id(useless
, dev_priv
, id
) {
1450 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[id
];
1452 if (i915_mmio_reg_valid(mbox_reg
)) {
1453 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1455 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1456 intel_ring_emit_reg(signaller
, mbox_reg
);
1457 intel_ring_emit(signaller
, seqno
);
1461 /* If num_dwords was rounded, make sure the tail pointer is correct */
1462 if (num_rings
% 2 == 0)
1463 intel_ring_emit(signaller
, MI_NOOP
);
1469 * gen6_add_request - Update the semaphore mailbox registers
1471 * @request - request to write to the ring
1473 * Update the mailbox registers in the *other* rings with the current seqno.
1474 * This acts like a signal in the canonical semaphore.
1477 gen6_add_request(struct drm_i915_gem_request
*req
)
1479 struct intel_engine_cs
*engine
= req
->engine
;
1482 if (engine
->semaphore
.signal
)
1483 ret
= engine
->semaphore
.signal(req
, 4);
1485 ret
= intel_ring_begin(req
, 4);
1490 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1491 intel_ring_emit(engine
,
1492 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1493 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1494 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1495 __intel_ring_advance(engine
);
1501 gen8_render_add_request(struct drm_i915_gem_request
*req
)
1503 struct intel_engine_cs
*engine
= req
->engine
;
1506 if (engine
->semaphore
.signal
)
1507 ret
= engine
->semaphore
.signal(req
, 8);
1509 ret
= intel_ring_begin(req
, 8);
1513 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
1514 intel_ring_emit(engine
, (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1515 PIPE_CONTROL_CS_STALL
|
1516 PIPE_CONTROL_QW_WRITE
));
1517 intel_ring_emit(engine
, intel_hws_seqno_address(req
->engine
));
1518 intel_ring_emit(engine
, 0);
1519 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1520 /* We're thrashing one dword of HWS. */
1521 intel_ring_emit(engine
, 0);
1522 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1523 intel_ring_emit(engine
, MI_NOOP
);
1524 __intel_ring_advance(engine
);
1529 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private
*dev_priv
,
1532 return dev_priv
->last_seqno
< seqno
;
1536 * intel_ring_sync - sync the waiter to the signaller on seqno
1538 * @waiter - ring that is waiting
1539 * @signaller - ring which has, or will signal
1540 * @seqno - seqno which the waiter will block on
1544 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1545 struct intel_engine_cs
*signaller
,
1548 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1549 struct drm_i915_private
*dev_priv
= waiter_req
->i915
;
1550 struct i915_hw_ppgtt
*ppgtt
;
1553 ret
= intel_ring_begin(waiter_req
, 4);
1557 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1558 MI_SEMAPHORE_GLOBAL_GTT
|
1559 MI_SEMAPHORE_SAD_GTE_SDD
);
1560 intel_ring_emit(waiter
, seqno
);
1561 intel_ring_emit(waiter
,
1562 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1563 intel_ring_emit(waiter
,
1564 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1565 intel_ring_advance(waiter
);
1567 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1568 * pagetables and we must reload them before executing the batch.
1569 * We do this on the i915_switch_context() following the wait and
1570 * before the dispatch.
1572 ppgtt
= waiter_req
->ctx
->ppgtt
;
1573 if (ppgtt
&& waiter_req
->engine
->id
!= RCS
)
1574 ppgtt
->pd_dirty_rings
|= intel_engine_flag(waiter_req
->engine
);
1579 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1580 struct intel_engine_cs
*signaller
,
1583 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1584 u32 dw1
= MI_SEMAPHORE_MBOX
|
1585 MI_SEMAPHORE_COMPARE
|
1586 MI_SEMAPHORE_REGISTER
;
1587 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1590 /* Throughout all of the GEM code, seqno passed implies our current
1591 * seqno is >= the last seqno executed. However for hardware the
1592 * comparison is strictly greater than.
1596 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1598 ret
= intel_ring_begin(waiter_req
, 4);
1602 /* If seqno wrap happened, omit the wait with no-ops */
1603 if (likely(!i915_gem_has_seqno_wrapped(waiter_req
->i915
, seqno
))) {
1604 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1605 intel_ring_emit(waiter
, seqno
);
1606 intel_ring_emit(waiter
, 0);
1607 intel_ring_emit(waiter
, MI_NOOP
);
1609 intel_ring_emit(waiter
, MI_NOOP
);
1610 intel_ring_emit(waiter
, MI_NOOP
);
1611 intel_ring_emit(waiter
, MI_NOOP
);
1612 intel_ring_emit(waiter
, MI_NOOP
);
1614 intel_ring_advance(waiter
);
1619 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1621 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1622 PIPE_CONTROL_DEPTH_STALL); \
1623 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1624 intel_ring_emit(ring__, 0); \
1625 intel_ring_emit(ring__, 0); \
1629 pc_render_add_request(struct drm_i915_gem_request
*req
)
1631 struct intel_engine_cs
*engine
= req
->engine
;
1632 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1635 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1636 * incoherent with writes to memory, i.e. completely fubar,
1637 * so we need to use PIPE_NOTIFY instead.
1639 * However, we also need to workaround the qword write
1640 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1641 * memory before requesting an interrupt.
1643 ret
= intel_ring_begin(req
, 32);
1647 intel_ring_emit(engine
,
1648 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1649 PIPE_CONTROL_WRITE_FLUSH
|
1650 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1651 intel_ring_emit(engine
,
1652 engine
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1653 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1654 intel_ring_emit(engine
, 0);
1655 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1656 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1657 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1658 scratch_addr
+= 2 * CACHELINE_BYTES
;
1659 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1660 scratch_addr
+= 2 * CACHELINE_BYTES
;
1661 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1662 scratch_addr
+= 2 * CACHELINE_BYTES
;
1663 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1664 scratch_addr
+= 2 * CACHELINE_BYTES
;
1665 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1667 intel_ring_emit(engine
,
1668 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1669 PIPE_CONTROL_WRITE_FLUSH
|
1670 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1671 PIPE_CONTROL_NOTIFY
);
1672 intel_ring_emit(engine
,
1673 engine
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1674 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1675 intel_ring_emit(engine
, 0);
1676 __intel_ring_advance(engine
);
1682 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1684 struct drm_i915_private
*dev_priv
= engine
->i915
;
1686 /* Workaround to force correct ordering between irq and seqno writes on
1687 * ivb (and maybe also on snb) by reading from a CS register (like
1688 * ACTHD) before reading the status page.
1690 * Note that this effectively stalls the read by the time it takes to
1691 * do a memory transaction, which more or less ensures that the write
1692 * from the GPU has sufficient time to invalidate the CPU cacheline.
1693 * Alternatively we could delay the interrupt from the CS ring to give
1694 * the write time to land, but that would incur a delay after every
1695 * batch i.e. much more frequent than a delay when waiting for the
1696 * interrupt (with the same net latency).
1698 * Also note that to prevent whole machine hangs on gen7, we have to
1699 * take the spinlock to guard against concurrent cacheline access.
1701 spin_lock_irq(&dev_priv
->uncore
.lock
);
1702 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1703 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1707 ring_get_seqno(struct intel_engine_cs
*engine
)
1709 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1713 ring_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1715 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1719 pc_render_get_seqno(struct intel_engine_cs
*engine
)
1721 return engine
->scratch
.cpu_page
[0];
1725 pc_render_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1727 engine
->scratch
.cpu_page
[0] = seqno
;
1731 gen5_ring_get_irq(struct intel_engine_cs
*engine
)
1733 struct drm_i915_private
*dev_priv
= engine
->i915
;
1734 unsigned long flags
;
1736 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1739 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1740 if (engine
->irq_refcount
++ == 0)
1741 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1742 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1748 gen5_ring_put_irq(struct intel_engine_cs
*engine
)
1750 struct drm_i915_private
*dev_priv
= engine
->i915
;
1751 unsigned long flags
;
1753 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1754 if (--engine
->irq_refcount
== 0)
1755 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1756 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1760 i9xx_ring_get_irq(struct intel_engine_cs
*engine
)
1762 struct drm_i915_private
*dev_priv
= engine
->i915
;
1763 unsigned long flags
;
1765 if (!intel_irqs_enabled(dev_priv
))
1768 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1769 if (engine
->irq_refcount
++ == 0) {
1770 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1771 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1774 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1780 i9xx_ring_put_irq(struct intel_engine_cs
*engine
)
1782 struct drm_i915_private
*dev_priv
= engine
->i915
;
1783 unsigned long flags
;
1785 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1786 if (--engine
->irq_refcount
== 0) {
1787 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1788 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1791 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1795 i8xx_ring_get_irq(struct intel_engine_cs
*engine
)
1797 struct drm_i915_private
*dev_priv
= engine
->i915
;
1798 unsigned long flags
;
1800 if (!intel_irqs_enabled(dev_priv
))
1803 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1804 if (engine
->irq_refcount
++ == 0) {
1805 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1806 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1807 POSTING_READ16(IMR
);
1809 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1815 i8xx_ring_put_irq(struct intel_engine_cs
*engine
)
1817 struct drm_i915_private
*dev_priv
= engine
->i915
;
1818 unsigned long flags
;
1820 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1821 if (--engine
->irq_refcount
== 0) {
1822 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1823 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1824 POSTING_READ16(IMR
);
1826 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1830 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1831 u32 invalidate_domains
,
1834 struct intel_engine_cs
*engine
= req
->engine
;
1837 ret
= intel_ring_begin(req
, 2);
1841 intel_ring_emit(engine
, MI_FLUSH
);
1842 intel_ring_emit(engine
, MI_NOOP
);
1843 intel_ring_advance(engine
);
1848 i9xx_add_request(struct drm_i915_gem_request
*req
)
1850 struct intel_engine_cs
*engine
= req
->engine
;
1853 ret
= intel_ring_begin(req
, 4);
1857 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1858 intel_ring_emit(engine
,
1859 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1860 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1861 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1862 __intel_ring_advance(engine
);
1868 gen6_ring_get_irq(struct intel_engine_cs
*engine
)
1870 struct drm_i915_private
*dev_priv
= engine
->i915
;
1871 unsigned long flags
;
1873 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1876 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1877 if (engine
->irq_refcount
++ == 0) {
1878 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
)
1879 I915_WRITE_IMR(engine
,
1880 ~(engine
->irq_enable_mask
|
1881 GT_PARITY_ERROR(dev_priv
)));
1883 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1884 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1886 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1892 gen6_ring_put_irq(struct intel_engine_cs
*engine
)
1894 struct drm_i915_private
*dev_priv
= engine
->i915
;
1895 unsigned long flags
;
1897 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1898 if (--engine
->irq_refcount
== 0) {
1899 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
)
1900 I915_WRITE_IMR(engine
, ~GT_PARITY_ERROR(dev_priv
));
1902 I915_WRITE_IMR(engine
, ~0);
1903 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1905 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1909 hsw_vebox_get_irq(struct intel_engine_cs
*engine
)
1911 struct drm_i915_private
*dev_priv
= engine
->i915
;
1912 unsigned long flags
;
1914 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1917 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1918 if (engine
->irq_refcount
++ == 0) {
1919 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1920 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1922 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1928 hsw_vebox_put_irq(struct intel_engine_cs
*engine
)
1930 struct drm_i915_private
*dev_priv
= engine
->i915
;
1931 unsigned long flags
;
1933 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1934 if (--engine
->irq_refcount
== 0) {
1935 I915_WRITE_IMR(engine
, ~0);
1936 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1938 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1942 gen8_ring_get_irq(struct intel_engine_cs
*engine
)
1944 struct drm_i915_private
*dev_priv
= engine
->i915
;
1945 unsigned long flags
;
1947 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1950 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1951 if (engine
->irq_refcount
++ == 0) {
1952 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
) {
1953 I915_WRITE_IMR(engine
,
1954 ~(engine
->irq_enable_mask
|
1955 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1957 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1959 POSTING_READ(RING_IMR(engine
->mmio_base
));
1961 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1967 gen8_ring_put_irq(struct intel_engine_cs
*engine
)
1969 struct drm_i915_private
*dev_priv
= engine
->i915
;
1970 unsigned long flags
;
1972 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1973 if (--engine
->irq_refcount
== 0) {
1974 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
) {
1975 I915_WRITE_IMR(engine
,
1976 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1978 I915_WRITE_IMR(engine
, ~0);
1980 POSTING_READ(RING_IMR(engine
->mmio_base
));
1982 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1986 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1987 u64 offset
, u32 length
,
1988 unsigned dispatch_flags
)
1990 struct intel_engine_cs
*engine
= req
->engine
;
1993 ret
= intel_ring_begin(req
, 2);
1997 intel_ring_emit(engine
,
1998 MI_BATCH_BUFFER_START
|
2000 (dispatch_flags
& I915_DISPATCH_SECURE
?
2001 0 : MI_BATCH_NON_SECURE_I965
));
2002 intel_ring_emit(engine
, offset
);
2003 intel_ring_advance(engine
);
2008 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
2009 #define I830_BATCH_LIMIT (256*1024)
2010 #define I830_TLB_ENTRIES (2)
2011 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
2013 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2014 u64 offset
, u32 len
,
2015 unsigned dispatch_flags
)
2017 struct intel_engine_cs
*engine
= req
->engine
;
2018 u32 cs_offset
= engine
->scratch
.gtt_offset
;
2021 ret
= intel_ring_begin(req
, 6);
2025 /* Evict the invalid PTE TLBs */
2026 intel_ring_emit(engine
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
2027 intel_ring_emit(engine
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
2028 intel_ring_emit(engine
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
2029 intel_ring_emit(engine
, cs_offset
);
2030 intel_ring_emit(engine
, 0xdeadbeef);
2031 intel_ring_emit(engine
, MI_NOOP
);
2032 intel_ring_advance(engine
);
2034 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
2035 if (len
> I830_BATCH_LIMIT
)
2038 ret
= intel_ring_begin(req
, 6 + 2);
2042 /* Blit the batch (which has now all relocs applied) to the
2043 * stable batch scratch bo area (so that the CS never
2044 * stumbles over its tlb invalidation bug) ...
2046 intel_ring_emit(engine
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
2047 intel_ring_emit(engine
,
2048 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
2049 intel_ring_emit(engine
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
2050 intel_ring_emit(engine
, cs_offset
);
2051 intel_ring_emit(engine
, 4096);
2052 intel_ring_emit(engine
, offset
);
2054 intel_ring_emit(engine
, MI_FLUSH
);
2055 intel_ring_emit(engine
, MI_NOOP
);
2056 intel_ring_advance(engine
);
2058 /* ... and execute it. */
2062 ret
= intel_ring_begin(req
, 2);
2066 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
2067 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
2068 0 : MI_BATCH_NON_SECURE
));
2069 intel_ring_advance(engine
);
2075 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2076 u64 offset
, u32 len
,
2077 unsigned dispatch_flags
)
2079 struct intel_engine_cs
*engine
= req
->engine
;
2082 ret
= intel_ring_begin(req
, 2);
2086 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
2087 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
2088 0 : MI_BATCH_NON_SECURE
));
2089 intel_ring_advance(engine
);
2094 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
2096 struct drm_i915_private
*dev_priv
= engine
->i915
;
2098 if (!dev_priv
->status_page_dmah
)
2101 drm_pci_free(dev_priv
->dev
, dev_priv
->status_page_dmah
);
2102 engine
->status_page
.page_addr
= NULL
;
2105 static void cleanup_status_page(struct intel_engine_cs
*engine
)
2107 struct drm_i915_gem_object
*obj
;
2109 obj
= engine
->status_page
.obj
;
2113 kunmap(sg_page(obj
->pages
->sgl
));
2114 i915_gem_object_ggtt_unpin(obj
);
2115 drm_gem_object_unreference(&obj
->base
);
2116 engine
->status_page
.obj
= NULL
;
2119 static int init_status_page(struct intel_engine_cs
*engine
)
2121 struct drm_i915_gem_object
*obj
= engine
->status_page
.obj
;
2127 obj
= i915_gem_object_create(engine
->i915
->dev
, 4096);
2129 DRM_ERROR("Failed to allocate status page\n");
2130 return PTR_ERR(obj
);
2133 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2138 if (!HAS_LLC(engine
->i915
))
2139 /* On g33, we cannot place HWS above 256MiB, so
2140 * restrict its pinning to the low mappable arena.
2141 * Though this restriction is not documented for
2142 * gen4, gen5, or byt, they also behave similarly
2143 * and hang if the HWS is placed at the top of the
2144 * GTT. To generalise, it appears that all !llc
2145 * platforms have issues with us placing the HWS
2146 * above the mappable region (even though we never
2149 flags
|= PIN_MAPPABLE
;
2150 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
2153 drm_gem_object_unreference(&obj
->base
);
2157 engine
->status_page
.obj
= obj
;
2160 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
2161 engine
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
2162 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
2164 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2165 engine
->name
, engine
->status_page
.gfx_addr
);
2170 static int init_phys_status_page(struct intel_engine_cs
*engine
)
2172 struct drm_i915_private
*dev_priv
= engine
->i915
;
2174 if (!dev_priv
->status_page_dmah
) {
2175 dev_priv
->status_page_dmah
=
2176 drm_pci_alloc(dev_priv
->dev
, PAGE_SIZE
, PAGE_SIZE
);
2177 if (!dev_priv
->status_page_dmah
)
2181 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
2182 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
2187 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2189 GEM_BUG_ON(ringbuf
->vma
== NULL
);
2190 GEM_BUG_ON(ringbuf
->virtual_start
== NULL
);
2192 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
2193 i915_gem_object_unpin_map(ringbuf
->obj
);
2195 i915_vma_unpin_iomap(ringbuf
->vma
);
2196 ringbuf
->virtual_start
= NULL
;
2198 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2199 ringbuf
->vma
= NULL
;
2202 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private
*dev_priv
,
2203 struct intel_ringbuffer
*ringbuf
)
2205 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2206 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2207 unsigned flags
= PIN_OFFSET_BIAS
| 4096;
2211 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2212 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, flags
);
2216 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2220 addr
= i915_gem_object_pin_map(obj
);
2222 ret
= PTR_ERR(addr
);
2226 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
2227 flags
| PIN_MAPPABLE
);
2231 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2235 /* Access through the GTT requires the device to be awake. */
2236 assert_rpm_wakelock_held(dev_priv
);
2238 addr
= i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj
));
2240 ret
= PTR_ERR(addr
);
2245 ringbuf
->virtual_start
= addr
;
2246 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2250 i915_gem_object_ggtt_unpin(obj
);
2254 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2256 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2257 ringbuf
->obj
= NULL
;
2260 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2261 struct intel_ringbuffer
*ringbuf
)
2263 struct drm_i915_gem_object
*obj
;
2267 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2269 obj
= i915_gem_object_create(dev
, ringbuf
->size
);
2271 return PTR_ERR(obj
);
2273 /* mark ring buffers as read-only from GPU side by default */
2281 struct intel_ringbuffer
*
2282 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2284 struct intel_ringbuffer
*ring
;
2287 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2289 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2291 return ERR_PTR(-ENOMEM
);
2294 ring
->engine
= engine
;
2295 list_add(&ring
->link
, &engine
->buffers
);
2298 /* Workaround an erratum on the i830 which causes a hang if
2299 * the TAIL pointer points to within the last 2 cachelines
2302 ring
->effective_size
= size
;
2303 if (IS_I830(engine
->i915
) || IS_845G(engine
->i915
))
2304 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2306 ring
->last_retired_head
= -1;
2307 intel_ring_update_space(ring
);
2309 ret
= intel_alloc_ringbuffer_obj(engine
->i915
->dev
, ring
);
2311 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2313 list_del(&ring
->link
);
2315 return ERR_PTR(ret
);
2322 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2324 intel_destroy_ringbuffer_obj(ring
);
2325 list_del(&ring
->link
);
2329 static int intel_ring_context_pin(struct i915_gem_context
*ctx
,
2330 struct intel_engine_cs
*engine
)
2332 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2335 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
2337 if (ce
->pin_count
++)
2341 ret
= i915_gem_obj_ggtt_pin(ce
->state
, ctx
->ggtt_alignment
, 0);
2346 /* The kernel context is only used as a placeholder for flushing the
2347 * active context. It is never used for submitting user rendering and
2348 * as such never requires the golden render context, and so we can skip
2349 * emitting it when we switch to the kernel context. This is required
2350 * as during eviction we cannot allocate and pin the renderstate in
2351 * order to initialise the context.
2353 if (ctx
== ctx
->i915
->kernel_context
)
2354 ce
->initialised
= true;
2356 i915_gem_context_reference(ctx
);
2364 static void intel_ring_context_unpin(struct i915_gem_context
*ctx
,
2365 struct intel_engine_cs
*engine
)
2367 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2369 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
2371 if (--ce
->pin_count
)
2375 i915_gem_object_ggtt_unpin(ce
->state
);
2377 i915_gem_context_unreference(ctx
);
2380 static int intel_init_ring_buffer(struct drm_device
*dev
,
2381 struct intel_engine_cs
*engine
)
2383 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2384 struct intel_ringbuffer
*ringbuf
;
2387 WARN_ON(engine
->buffer
);
2389 engine
->i915
= dev_priv
;
2390 INIT_LIST_HEAD(&engine
->active_list
);
2391 INIT_LIST_HEAD(&engine
->request_list
);
2392 INIT_LIST_HEAD(&engine
->execlist_queue
);
2393 INIT_LIST_HEAD(&engine
->buffers
);
2394 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2395 memset(engine
->semaphore
.sync_seqno
, 0,
2396 sizeof(engine
->semaphore
.sync_seqno
));
2398 init_waitqueue_head(&engine
->irq_queue
);
2400 /* We may need to do things with the shrinker which
2401 * require us to immediately switch back to the default
2402 * context. This can cause a problem as pinning the
2403 * default context also requires GTT space which may not
2404 * be available. To avoid this we always pin the default
2407 ret
= intel_ring_context_pin(dev_priv
->kernel_context
, engine
);
2411 ringbuf
= intel_engine_create_ringbuffer(engine
, 32 * PAGE_SIZE
);
2412 if (IS_ERR(ringbuf
)) {
2413 ret
= PTR_ERR(ringbuf
);
2416 engine
->buffer
= ringbuf
;
2418 if (I915_NEED_GFX_HWS(dev_priv
)) {
2419 ret
= init_status_page(engine
);
2423 WARN_ON(engine
->id
!= RCS
);
2424 ret
= init_phys_status_page(engine
);
2429 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ringbuf
);
2431 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2433 intel_destroy_ringbuffer_obj(ringbuf
);
2437 ret
= i915_cmd_parser_init_ring(engine
);
2444 intel_cleanup_engine(engine
);
2448 void intel_cleanup_engine(struct intel_engine_cs
*engine
)
2450 struct drm_i915_private
*dev_priv
;
2452 if (!intel_engine_initialized(engine
))
2455 dev_priv
= engine
->i915
;
2457 if (engine
->buffer
) {
2458 intel_stop_engine(engine
);
2459 WARN_ON(!IS_GEN2(dev_priv
) && (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2461 intel_unpin_ringbuffer_obj(engine
->buffer
);
2462 intel_ringbuffer_free(engine
->buffer
);
2463 engine
->buffer
= NULL
;
2466 if (engine
->cleanup
)
2467 engine
->cleanup(engine
);
2469 if (I915_NEED_GFX_HWS(dev_priv
)) {
2470 cleanup_status_page(engine
);
2472 WARN_ON(engine
->id
!= RCS
);
2473 cleanup_phys_status_page(engine
);
2476 i915_cmd_parser_fini_ring(engine
);
2477 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2479 intel_ring_context_unpin(dev_priv
->kernel_context
, engine
);
2481 engine
->i915
= NULL
;
2484 int intel_engine_idle(struct intel_engine_cs
*engine
)
2486 struct drm_i915_gem_request
*req
;
2488 /* Wait upon the last request to be completed */
2489 if (list_empty(&engine
->request_list
))
2492 req
= list_entry(engine
->request_list
.prev
,
2493 struct drm_i915_gem_request
,
2496 /* Make sure we do not trigger any retires */
2497 return __i915_wait_request(req
,
2498 req
->i915
->mm
.interruptible
,
2502 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2506 /* Flush enough space to reduce the likelihood of waiting after
2507 * we start building the request - in which case we will just
2508 * have to repeat work.
2510 request
->reserved_space
+= LEGACY_REQUEST_SIZE
;
2512 request
->ringbuf
= request
->engine
->buffer
;
2514 ret
= intel_ring_begin(request
, 0);
2518 request
->reserved_space
-= LEGACY_REQUEST_SIZE
;
2522 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2524 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2525 struct intel_engine_cs
*engine
= req
->engine
;
2526 struct drm_i915_gem_request
*target
;
2528 intel_ring_update_space(ringbuf
);
2529 if (ringbuf
->space
>= bytes
)
2533 * Space is reserved in the ringbuffer for finalising the request,
2534 * as that cannot be allowed to fail. During request finalisation,
2535 * reserved_space is set to 0 to stop the overallocation and the
2536 * assumption is that then we never need to wait (which has the
2537 * risk of failing with EINTR).
2539 * See also i915_gem_request_alloc() and i915_add_request().
2541 GEM_BUG_ON(!req
->reserved_space
);
2543 list_for_each_entry(target
, &engine
->request_list
, list
) {
2547 * The request queue is per-engine, so can contain requests
2548 * from multiple ringbuffers. Here, we must ignore any that
2549 * aren't from the ringbuffer we're considering.
2551 if (target
->ringbuf
!= ringbuf
)
2554 /* Would completion of this request free enough space? */
2555 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
2561 if (WARN_ON(&target
->list
== &engine
->request_list
))
2564 return i915_wait_request(target
);
2567 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2569 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2570 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2571 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2572 int bytes
= num_dwords
* sizeof(u32
);
2573 int total_bytes
, wait_bytes
;
2574 bool need_wrap
= false;
2576 total_bytes
= bytes
+ req
->reserved_space
;
2578 if (unlikely(bytes
> remain_usable
)) {
2580 * Not enough space for the basic request. So need to flush
2581 * out the remainder and then wait for base + reserved.
2583 wait_bytes
= remain_actual
+ total_bytes
;
2585 } else if (unlikely(total_bytes
> remain_usable
)) {
2587 * The base request will fit but the reserved space
2588 * falls off the end. So we don't need an immediate wrap
2589 * and only need to effectively wait for the reserved
2590 * size space from the start of ringbuffer.
2592 wait_bytes
= remain_actual
+ req
->reserved_space
;
2594 /* No wrapping required, just waiting. */
2595 wait_bytes
= total_bytes
;
2598 if (wait_bytes
> ringbuf
->space
) {
2599 int ret
= wait_for_space(req
, wait_bytes
);
2603 intel_ring_update_space(ringbuf
);
2604 if (unlikely(ringbuf
->space
< wait_bytes
))
2608 if (unlikely(need_wrap
)) {
2609 GEM_BUG_ON(remain_actual
> ringbuf
->space
);
2610 GEM_BUG_ON(ringbuf
->tail
+ remain_actual
> ringbuf
->size
);
2612 /* Fill the tail with MI_NOOP */
2613 memset(ringbuf
->virtual_start
+ ringbuf
->tail
,
2616 ringbuf
->space
-= remain_actual
;
2619 ringbuf
->space
-= bytes
;
2620 GEM_BUG_ON(ringbuf
->space
< 0);
2624 /* Align the ring tail to a cacheline boundary */
2625 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2627 struct intel_engine_cs
*engine
= req
->engine
;
2628 int num_dwords
= (engine
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2631 if (num_dwords
== 0)
2634 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2635 ret
= intel_ring_begin(req
, num_dwords
);
2639 while (num_dwords
--)
2640 intel_ring_emit(engine
, MI_NOOP
);
2642 intel_ring_advance(engine
);
2647 void intel_ring_init_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
2649 struct drm_i915_private
*dev_priv
= engine
->i915
;
2651 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2652 * so long as the semaphore value in the register/page is greater
2653 * than the sync value), so whenever we reset the seqno,
2654 * so long as we reset the tracking semaphore value to 0, it will
2655 * always be before the next request's seqno. If we don't reset
2656 * the semaphore value, then when the seqno moves backwards all
2657 * future waits will complete instantly (causing rendering corruption).
2659 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
2660 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
2661 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
2662 if (HAS_VEBOX(dev_priv
))
2663 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
2665 if (dev_priv
->semaphore_obj
) {
2666 struct drm_i915_gem_object
*obj
= dev_priv
->semaphore_obj
;
2667 struct page
*page
= i915_gem_object_get_dirty_page(obj
, 0);
2668 void *semaphores
= kmap(page
);
2669 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
2670 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
2673 memset(engine
->semaphore
.sync_seqno
, 0,
2674 sizeof(engine
->semaphore
.sync_seqno
));
2676 engine
->set_seqno(engine
, seqno
);
2677 engine
->last_submitted_seqno
= seqno
;
2679 engine
->hangcheck
.seqno
= seqno
;
2682 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*engine
,
2685 struct drm_i915_private
*dev_priv
= engine
->i915
;
2687 /* Every tail move must follow the sequence below */
2689 /* Disable notification that the ring is IDLE. The GT
2690 * will then assume that it is busy and bring it out of rc6.
2692 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2693 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2695 /* Clear the context id. Here be magic! */
2696 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2698 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2699 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2700 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2702 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2704 /* Now that the ring is fully powered up, update the tail */
2705 I915_WRITE_TAIL(engine
, value
);
2706 POSTING_READ(RING_TAIL(engine
->mmio_base
));
2708 /* Let the ring send IDLE messages to the GT again,
2709 * and so let it sleep to conserve power when idle.
2711 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2712 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2715 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2716 u32 invalidate
, u32 flush
)
2718 struct intel_engine_cs
*engine
= req
->engine
;
2722 ret
= intel_ring_begin(req
, 4);
2727 if (INTEL_GEN(req
->i915
) >= 8)
2730 /* We always require a command barrier so that subsequent
2731 * commands, such as breadcrumb interrupts, are strictly ordered
2732 * wrt the contents of the write cache being flushed to memory
2733 * (and thus being coherent from the CPU).
2735 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2738 * Bspec vol 1c.5 - video engine command streamer:
2739 * "If ENABLED, all TLBs will be invalidated once the flush
2740 * operation is complete. This bit is only valid when the
2741 * Post-Sync Operation field is a value of 1h or 3h."
2743 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2744 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2746 intel_ring_emit(engine
, cmd
);
2747 intel_ring_emit(engine
,
2748 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2749 if (INTEL_GEN(req
->i915
) >= 8) {
2750 intel_ring_emit(engine
, 0); /* upper addr */
2751 intel_ring_emit(engine
, 0); /* value */
2753 intel_ring_emit(engine
, 0);
2754 intel_ring_emit(engine
, MI_NOOP
);
2756 intel_ring_advance(engine
);
2761 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2762 u64 offset
, u32 len
,
2763 unsigned dispatch_flags
)
2765 struct intel_engine_cs
*engine
= req
->engine
;
2766 bool ppgtt
= USES_PPGTT(engine
->dev
) &&
2767 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2770 ret
= intel_ring_begin(req
, 4);
2774 /* FIXME(BDW): Address space and security selectors. */
2775 intel_ring_emit(engine
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2776 (dispatch_flags
& I915_DISPATCH_RS
?
2777 MI_BATCH_RESOURCE_STREAMER
: 0));
2778 intel_ring_emit(engine
, lower_32_bits(offset
));
2779 intel_ring_emit(engine
, upper_32_bits(offset
));
2780 intel_ring_emit(engine
, MI_NOOP
);
2781 intel_ring_advance(engine
);
2787 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2788 u64 offset
, u32 len
,
2789 unsigned dispatch_flags
)
2791 struct intel_engine_cs
*engine
= req
->engine
;
2794 ret
= intel_ring_begin(req
, 2);
2798 intel_ring_emit(engine
,
2799 MI_BATCH_BUFFER_START
|
2800 (dispatch_flags
& I915_DISPATCH_SECURE
?
2801 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2802 (dispatch_flags
& I915_DISPATCH_RS
?
2803 MI_BATCH_RESOURCE_STREAMER
: 0));
2804 /* bit0-7 is the length on GEN6+ */
2805 intel_ring_emit(engine
, offset
);
2806 intel_ring_advance(engine
);
2812 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2813 u64 offset
, u32 len
,
2814 unsigned dispatch_flags
)
2816 struct intel_engine_cs
*engine
= req
->engine
;
2819 ret
= intel_ring_begin(req
, 2);
2823 intel_ring_emit(engine
,
2824 MI_BATCH_BUFFER_START
|
2825 (dispatch_flags
& I915_DISPATCH_SECURE
?
2826 0 : MI_BATCH_NON_SECURE_I965
));
2827 /* bit0-7 is the length on GEN6+ */
2828 intel_ring_emit(engine
, offset
);
2829 intel_ring_advance(engine
);
2834 /* Blitter support (SandyBridge+) */
2836 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2837 u32 invalidate
, u32 flush
)
2839 struct intel_engine_cs
*engine
= req
->engine
;
2843 ret
= intel_ring_begin(req
, 4);
2848 if (INTEL_GEN(req
->i915
) >= 8)
2851 /* We always require a command barrier so that subsequent
2852 * commands, such as breadcrumb interrupts, are strictly ordered
2853 * wrt the contents of the write cache being flushed to memory
2854 * (and thus being coherent from the CPU).
2856 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2859 * Bspec vol 1c.3 - blitter engine command streamer:
2860 * "If ENABLED, all TLBs will be invalidated once the flush
2861 * operation is complete. This bit is only valid when the
2862 * Post-Sync Operation field is a value of 1h or 3h."
2864 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2865 cmd
|= MI_INVALIDATE_TLB
;
2866 intel_ring_emit(engine
, cmd
);
2867 intel_ring_emit(engine
,
2868 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2869 if (INTEL_GEN(req
->i915
) >= 8) {
2870 intel_ring_emit(engine
, 0); /* upper addr */
2871 intel_ring_emit(engine
, 0); /* value */
2873 intel_ring_emit(engine
, 0);
2874 intel_ring_emit(engine
, MI_NOOP
);
2876 intel_ring_advance(engine
);
2881 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2884 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2885 struct drm_i915_gem_object
*obj
;
2888 engine
->name
= "render ring";
2890 engine
->exec_id
= I915_EXEC_RENDER
;
2892 engine
->mmio_base
= RENDER_RING_BASE
;
2894 if (INTEL_GEN(dev_priv
) >= 8) {
2895 if (i915_semaphore_is_enabled(dev_priv
)) {
2896 obj
= i915_gem_object_create(dev
, 4096);
2898 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2899 i915
.semaphores
= 0;
2901 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2902 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2904 drm_gem_object_unreference(&obj
->base
);
2905 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2906 i915
.semaphores
= 0;
2908 dev_priv
->semaphore_obj
= obj
;
2912 engine
->init_context
= intel_rcs_ctx_init
;
2913 engine
->add_request
= gen8_render_add_request
;
2914 engine
->flush
= gen8_render_ring_flush
;
2915 engine
->irq_get
= gen8_ring_get_irq
;
2916 engine
->irq_put
= gen8_ring_put_irq
;
2917 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2918 engine
->get_seqno
= ring_get_seqno
;
2919 engine
->set_seqno
= ring_set_seqno
;
2920 if (i915_semaphore_is_enabled(dev_priv
)) {
2921 WARN_ON(!dev_priv
->semaphore_obj
);
2922 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2923 engine
->semaphore
.signal
= gen8_rcs_signal
;
2924 GEN8_RING_SEMAPHORE_INIT(engine
);
2926 } else if (INTEL_GEN(dev_priv
) >= 6) {
2927 engine
->init_context
= intel_rcs_ctx_init
;
2928 engine
->add_request
= gen6_add_request
;
2929 engine
->flush
= gen7_render_ring_flush
;
2930 if (IS_GEN6(dev_priv
))
2931 engine
->flush
= gen6_render_ring_flush
;
2932 engine
->irq_get
= gen6_ring_get_irq
;
2933 engine
->irq_put
= gen6_ring_put_irq
;
2934 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2935 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2936 engine
->get_seqno
= ring_get_seqno
;
2937 engine
->set_seqno
= ring_set_seqno
;
2938 if (i915_semaphore_is_enabled(dev_priv
)) {
2939 engine
->semaphore
.sync_to
= gen6_ring_sync
;
2940 engine
->semaphore
.signal
= gen6_signal
;
2942 * The current semaphore is only applied on pre-gen8
2943 * platform. And there is no VCS2 ring on the pre-gen8
2944 * platform. So the semaphore between RCS and VCS2 is
2945 * initialized as INVALID. Gen8 will initialize the
2946 * sema between VCS2 and RCS later.
2948 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2949 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2950 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2951 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2952 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2953 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2954 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2955 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2956 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2957 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2959 } else if (IS_GEN5(dev_priv
)) {
2960 engine
->add_request
= pc_render_add_request
;
2961 engine
->flush
= gen4_render_ring_flush
;
2962 engine
->get_seqno
= pc_render_get_seqno
;
2963 engine
->set_seqno
= pc_render_set_seqno
;
2964 engine
->irq_get
= gen5_ring_get_irq
;
2965 engine
->irq_put
= gen5_ring_put_irq
;
2966 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2967 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2969 engine
->add_request
= i9xx_add_request
;
2970 if (INTEL_GEN(dev_priv
) < 4)
2971 engine
->flush
= gen2_render_ring_flush
;
2973 engine
->flush
= gen4_render_ring_flush
;
2974 engine
->get_seqno
= ring_get_seqno
;
2975 engine
->set_seqno
= ring_set_seqno
;
2976 if (IS_GEN2(dev_priv
)) {
2977 engine
->irq_get
= i8xx_ring_get_irq
;
2978 engine
->irq_put
= i8xx_ring_put_irq
;
2980 engine
->irq_get
= i9xx_ring_get_irq
;
2981 engine
->irq_put
= i9xx_ring_put_irq
;
2983 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2985 engine
->write_tail
= ring_write_tail
;
2987 if (IS_HASWELL(dev_priv
))
2988 engine
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2989 else if (IS_GEN8(dev_priv
))
2990 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2991 else if (INTEL_GEN(dev_priv
) >= 6)
2992 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2993 else if (INTEL_GEN(dev_priv
) >= 4)
2994 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2995 else if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
2996 engine
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2998 engine
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2999 engine
->init_hw
= init_render_ring
;
3000 engine
->cleanup
= render_ring_cleanup
;
3002 /* Workaround batchbuffer to combat CS tlb bug. */
3003 if (HAS_BROKEN_CS_TLB(dev_priv
)) {
3004 obj
= i915_gem_object_create(dev
, I830_WA_SIZE
);
3006 DRM_ERROR("Failed to allocate batch bo\n");
3007 return PTR_ERR(obj
);
3010 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
3012 drm_gem_object_unreference(&obj
->base
);
3013 DRM_ERROR("Failed to ping batch bo\n");
3017 engine
->scratch
.obj
= obj
;
3018 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
3021 ret
= intel_init_ring_buffer(dev
, engine
);
3025 if (INTEL_GEN(dev_priv
) >= 5) {
3026 ret
= intel_init_pipe_control(engine
);
3034 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3037 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
3039 engine
->name
= "bsd ring";
3041 engine
->exec_id
= I915_EXEC_BSD
;
3044 engine
->write_tail
= ring_write_tail
;
3045 if (INTEL_GEN(dev_priv
) >= 6) {
3046 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
3047 /* gen6 bsd needs a special wa for tail updates */
3048 if (IS_GEN6(dev_priv
))
3049 engine
->write_tail
= gen6_bsd_ring_write_tail
;
3050 engine
->flush
= gen6_bsd_ring_flush
;
3051 engine
->add_request
= gen6_add_request
;
3052 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3053 engine
->get_seqno
= ring_get_seqno
;
3054 engine
->set_seqno
= ring_set_seqno
;
3055 if (INTEL_GEN(dev_priv
) >= 8) {
3056 engine
->irq_enable_mask
=
3057 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
3058 engine
->irq_get
= gen8_ring_get_irq
;
3059 engine
->irq_put
= gen8_ring_put_irq
;
3060 engine
->dispatch_execbuffer
=
3061 gen8_ring_dispatch_execbuffer
;
3062 if (i915_semaphore_is_enabled(dev_priv
)) {
3063 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3064 engine
->semaphore
.signal
= gen8_xcs_signal
;
3065 GEN8_RING_SEMAPHORE_INIT(engine
);
3068 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
3069 engine
->irq_get
= gen6_ring_get_irq
;
3070 engine
->irq_put
= gen6_ring_put_irq
;
3071 engine
->dispatch_execbuffer
=
3072 gen6_ring_dispatch_execbuffer
;
3073 if (i915_semaphore_is_enabled(dev_priv
)) {
3074 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3075 engine
->semaphore
.signal
= gen6_signal
;
3076 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
3077 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
3078 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
3079 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
3080 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3081 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
3082 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
3083 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
3084 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
3085 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3089 engine
->mmio_base
= BSD_RING_BASE
;
3090 engine
->flush
= bsd_ring_flush
;
3091 engine
->add_request
= i9xx_add_request
;
3092 engine
->get_seqno
= ring_get_seqno
;
3093 engine
->set_seqno
= ring_set_seqno
;
3094 if (IS_GEN5(dev_priv
)) {
3095 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
3096 engine
->irq_get
= gen5_ring_get_irq
;
3097 engine
->irq_put
= gen5_ring_put_irq
;
3099 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
3100 engine
->irq_get
= i9xx_ring_get_irq
;
3101 engine
->irq_put
= i9xx_ring_put_irq
;
3103 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
3105 engine
->init_hw
= init_ring_common
;
3107 return intel_init_ring_buffer(dev
, engine
);
3111 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3113 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
3115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3116 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
3118 engine
->name
= "bsd2 ring";
3120 engine
->exec_id
= I915_EXEC_BSD
;
3123 engine
->write_tail
= ring_write_tail
;
3124 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
3125 engine
->flush
= gen6_bsd_ring_flush
;
3126 engine
->add_request
= gen6_add_request
;
3127 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3128 engine
->get_seqno
= ring_get_seqno
;
3129 engine
->set_seqno
= ring_set_seqno
;
3130 engine
->irq_enable_mask
=
3131 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
3132 engine
->irq_get
= gen8_ring_get_irq
;
3133 engine
->irq_put
= gen8_ring_put_irq
;
3134 engine
->dispatch_execbuffer
=
3135 gen8_ring_dispatch_execbuffer
;
3136 if (i915_semaphore_is_enabled(dev_priv
)) {
3137 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3138 engine
->semaphore
.signal
= gen8_xcs_signal
;
3139 GEN8_RING_SEMAPHORE_INIT(engine
);
3141 engine
->init_hw
= init_ring_common
;
3143 return intel_init_ring_buffer(dev
, engine
);
3146 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
3148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3149 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
3151 engine
->name
= "blitter ring";
3153 engine
->exec_id
= I915_EXEC_BLT
;
3156 engine
->mmio_base
= BLT_RING_BASE
;
3157 engine
->write_tail
= ring_write_tail
;
3158 engine
->flush
= gen6_ring_flush
;
3159 engine
->add_request
= gen6_add_request
;
3160 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3161 engine
->get_seqno
= ring_get_seqno
;
3162 engine
->set_seqno
= ring_set_seqno
;
3163 if (INTEL_GEN(dev_priv
) >= 8) {
3164 engine
->irq_enable_mask
=
3165 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
3166 engine
->irq_get
= gen8_ring_get_irq
;
3167 engine
->irq_put
= gen8_ring_put_irq
;
3168 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3169 if (i915_semaphore_is_enabled(dev_priv
)) {
3170 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3171 engine
->semaphore
.signal
= gen8_xcs_signal
;
3172 GEN8_RING_SEMAPHORE_INIT(engine
);
3175 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
3176 engine
->irq_get
= gen6_ring_get_irq
;
3177 engine
->irq_put
= gen6_ring_put_irq
;
3178 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3179 if (i915_semaphore_is_enabled(dev_priv
)) {
3180 engine
->semaphore
.signal
= gen6_signal
;
3181 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3183 * The current semaphore is only applied on pre-gen8
3184 * platform. And there is no VCS2 ring on the pre-gen8
3185 * platform. So the semaphore between BCS and VCS2 is
3186 * initialized as INVALID. Gen8 will initialize the
3187 * sema between BCS and VCS2 later.
3189 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
3190 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
3191 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
3192 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
3193 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3194 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
3195 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
3196 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
3197 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
3198 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3201 engine
->init_hw
= init_ring_common
;
3203 return intel_init_ring_buffer(dev
, engine
);
3206 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
3208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3209 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
3211 engine
->name
= "video enhancement ring";
3213 engine
->exec_id
= I915_EXEC_VEBOX
;
3216 engine
->mmio_base
= VEBOX_RING_BASE
;
3217 engine
->write_tail
= ring_write_tail
;
3218 engine
->flush
= gen6_ring_flush
;
3219 engine
->add_request
= gen6_add_request
;
3220 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3221 engine
->get_seqno
= ring_get_seqno
;
3222 engine
->set_seqno
= ring_set_seqno
;
3224 if (INTEL_GEN(dev_priv
) >= 8) {
3225 engine
->irq_enable_mask
=
3226 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3227 engine
->irq_get
= gen8_ring_get_irq
;
3228 engine
->irq_put
= gen8_ring_put_irq
;
3229 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3230 if (i915_semaphore_is_enabled(dev_priv
)) {
3231 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3232 engine
->semaphore
.signal
= gen8_xcs_signal
;
3233 GEN8_RING_SEMAPHORE_INIT(engine
);
3236 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3237 engine
->irq_get
= hsw_vebox_get_irq
;
3238 engine
->irq_put
= hsw_vebox_put_irq
;
3239 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3240 if (i915_semaphore_is_enabled(dev_priv
)) {
3241 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3242 engine
->semaphore
.signal
= gen6_signal
;
3243 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
3244 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
3245 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
3246 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
3247 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3248 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
3249 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
3250 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
3251 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
3252 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3255 engine
->init_hw
= init_ring_common
;
3257 return intel_init_ring_buffer(dev
, engine
);
3261 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3263 struct intel_engine_cs
*engine
= req
->engine
;
3266 if (!engine
->gpu_caches_dirty
)
3269 ret
= engine
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3273 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3275 engine
->gpu_caches_dirty
= false;
3280 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3282 struct intel_engine_cs
*engine
= req
->engine
;
3283 uint32_t flush_domains
;
3287 if (engine
->gpu_caches_dirty
)
3288 flush_domains
= I915_GEM_GPU_DOMAINS
;
3290 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3294 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3296 engine
->gpu_caches_dirty
= false;
3301 intel_stop_engine(struct intel_engine_cs
*engine
)
3305 if (!intel_engine_initialized(engine
))
3308 ret
= intel_engine_idle(engine
);
3310 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",