2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- (tail
+ I915_RING_FREE_SPACE
);
61 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
63 return __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
64 ringbuf
->tail
, ringbuf
->size
);
67 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
69 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
70 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
73 void __intel_ring_advance(struct intel_engine_cs
*ring
)
75 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
76 ringbuf
->tail
&= ringbuf
->size
- 1;
77 if (intel_ring_stopped(ring
))
79 ring
->write_tail(ring
, ringbuf
->tail
);
83 gen2_render_ring_flush(struct intel_engine_cs
*ring
,
84 u32 invalidate_domains
,
91 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
92 cmd
|= MI_NO_WRITE_FLUSH
;
94 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
97 ret
= intel_ring_begin(ring
, 2);
101 intel_ring_emit(ring
, cmd
);
102 intel_ring_emit(ring
, MI_NOOP
);
103 intel_ring_advance(ring
);
109 gen4_render_ring_flush(struct intel_engine_cs
*ring
,
110 u32 invalidate_domains
,
113 struct drm_device
*dev
= ring
->dev
;
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
129 * I915_GEM_DOMAIN_COMMAND may not exist?
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
145 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
146 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
147 cmd
&= ~MI_NO_WRITE_FLUSH
;
148 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
151 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
152 (IS_G4X(dev
) || IS_GEN5(dev
)))
153 cmd
|= MI_INVALIDATE_ISP
;
155 ret
= intel_ring_begin(ring
, 2);
159 intel_ring_emit(ring
, cmd
);
160 intel_ring_emit(ring
, MI_NOOP
);
161 intel_ring_advance(ring
);
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
179 * And the workaround for these two requires this workaround first:
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs
*ring
)
206 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
210 ret
= intel_ring_begin(ring
, 6);
214 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
216 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
217 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
218 intel_ring_emit(ring
, 0); /* low dword */
219 intel_ring_emit(ring
, 0); /* high dword */
220 intel_ring_emit(ring
, MI_NOOP
);
221 intel_ring_advance(ring
);
223 ret
= intel_ring_begin(ring
, 6);
227 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
229 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
230 intel_ring_emit(ring
, 0);
231 intel_ring_emit(ring
, 0);
232 intel_ring_emit(ring
, MI_NOOP
);
233 intel_ring_advance(ring
);
239 gen6_render_ring_flush(struct intel_engine_cs
*ring
,
240 u32 invalidate_domains
, u32 flush_domains
)
243 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret
= intel_emit_post_sync_nonzero_flush(ring
);
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
256 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
257 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
262 flags
|= PIPE_CONTROL_CS_STALL
;
264 if (invalidate_domains
) {
265 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
266 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
267 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
268 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
269 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
270 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
272 * TLB invalidate requires a post-sync write.
274 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
277 ret
= intel_ring_begin(ring
, 4);
281 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring
, flags
);
283 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
284 intel_ring_emit(ring
, 0);
285 intel_ring_advance(ring
);
291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs
*ring
)
295 ret
= intel_ring_begin(ring
, 4);
299 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
301 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
302 intel_ring_emit(ring
, 0);
303 intel_ring_emit(ring
, 0);
304 intel_ring_advance(ring
);
309 static int gen7_ring_fbc_flush(struct intel_engine_cs
*ring
, u32 value
)
313 if (!ring
->fbc_dirty
)
316 ret
= intel_ring_begin(ring
, 6);
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
322 intel_ring_emit(ring
, value
);
323 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
324 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
325 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
326 intel_ring_advance(ring
);
328 ring
->fbc_dirty
= false;
333 gen7_render_ring_flush(struct intel_engine_cs
*ring
,
334 u32 invalidate_domains
, u32 flush_domains
)
337 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
348 flags
|= PIPE_CONTROL_CS_STALL
;
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
355 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
356 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
358 if (invalidate_domains
) {
359 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
360 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
361 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
362 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
363 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
364 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
366 * TLB invalidate requires a post-sync write.
368 flags
|= PIPE_CONTROL_QW_WRITE
;
369 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring
);
377 ret
= intel_ring_begin(ring
, 4);
381 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring
, flags
);
383 intel_ring_emit(ring
, scratch_addr
);
384 intel_ring_emit(ring
, 0);
385 intel_ring_advance(ring
);
387 if (!invalidate_domains
&& flush_domains
)
388 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
394 gen8_emit_pipe_control(struct intel_engine_cs
*ring
,
395 u32 flags
, u32 scratch_addr
)
399 ret
= intel_ring_begin(ring
, 6);
403 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring
, flags
);
405 intel_ring_emit(ring
, scratch_addr
);
406 intel_ring_emit(ring
, 0);
407 intel_ring_emit(ring
, 0);
408 intel_ring_emit(ring
, 0);
409 intel_ring_advance(ring
);
415 gen8_render_ring_flush(struct intel_engine_cs
*ring
,
416 u32 invalidate_domains
, u32 flush_domains
)
419 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
422 flags
|= PIPE_CONTROL_CS_STALL
;
425 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
426 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
428 if (invalidate_domains
) {
429 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
430 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
431 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
432 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
433 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
434 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
435 flags
|= PIPE_CONTROL_QW_WRITE
;
436 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret
= gen8_emit_pipe_control(ring
,
440 PIPE_CONTROL_CS_STALL
|
441 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
447 ret
= gen8_emit_pipe_control(ring
, flags
, scratch_addr
);
451 if (!invalidate_domains
&& flush_domains
)
452 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
457 static void ring_write_tail(struct intel_engine_cs
*ring
,
460 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
461 I915_WRITE_TAIL(ring
, value
);
464 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
466 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
469 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
470 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
471 RING_ACTHD_UDW(ring
->mmio_base
));
472 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
473 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
475 acthd
= I915_READ(ACTHD
);
480 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
482 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
485 addr
= dev_priv
->status_page_dmah
->busaddr
;
486 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
487 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
488 I915_WRITE(HWS_PGA
, addr
);
491 static bool stop_ring(struct intel_engine_cs
*ring
)
493 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
495 if (!IS_GEN2(ring
->dev
)) {
496 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
497 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
503 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
508 I915_WRITE_CTL(ring
, 0);
509 I915_WRITE_HEAD(ring
, 0);
510 ring
->write_tail(ring
, 0);
512 if (!IS_GEN2(ring
->dev
)) {
513 (void)I915_READ_CTL(ring
);
514 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
517 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
520 static int init_ring_common(struct intel_engine_cs
*ring
)
522 struct drm_device
*dev
= ring
->dev
;
523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
524 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
525 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
528 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
530 if (!stop_ring(ring
)) {
531 /* G45 ring initialization often fails to reset head to zero */
532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
536 I915_READ_HEAD(ring
),
537 I915_READ_TAIL(ring
),
538 I915_READ_START(ring
));
540 if (!stop_ring(ring
)) {
541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
545 I915_READ_HEAD(ring
),
546 I915_READ_TAIL(ring
),
547 I915_READ_START(ring
));
553 if (I915_NEED_GFX_HWS(dev
))
554 intel_ring_setup_status_page(ring
);
556 ring_setup_phys_status_page(ring
);
558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring
);
561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
565 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring
))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring
->name
, I915_READ_HEAD(ring
));
571 I915_WRITE_HEAD(ring
, 0);
572 (void)I915_READ_HEAD(ring
);
575 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
578 /* If the head is still not zero, the ring is dead */
579 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
580 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
581 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
582 DRM_ERROR("%s initialization failed "
583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
585 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
586 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
587 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
592 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
593 i915_kernel_lost_context(ring
->dev
);
595 ringbuf
->head
= I915_READ_HEAD(ring
);
596 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
597 ringbuf
->space
= intel_ring_space(ringbuf
);
598 ringbuf
->last_retired_head
= -1;
601 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
604 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
610 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
612 struct drm_device
*dev
= ring
->dev
;
614 if (ring
->scratch
.obj
== NULL
)
617 if (INTEL_INFO(dev
)->gen
>= 5) {
618 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
619 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
622 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
623 ring
->scratch
.obj
= NULL
;
627 intel_init_pipe_control(struct intel_engine_cs
*ring
)
631 if (ring
->scratch
.obj
)
634 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
635 if (ring
->scratch
.obj
== NULL
) {
636 DRM_ERROR("Failed to allocate seqno page\n");
641 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
645 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
649 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
650 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
651 if (ring
->scratch
.cpu_page
== NULL
) {
656 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
657 ring
->name
, ring
->scratch
.gtt_offset
);
661 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
663 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
668 static int intel_ring_workarounds_emit(struct intel_engine_cs
*ring
)
671 struct drm_device
*dev
= ring
->dev
;
672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
673 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
675 if (WARN_ON(w
->count
== 0))
678 ring
->gpu_caches_dirty
= true;
679 ret
= intel_ring_flush_all_caches(ring
);
683 ret
= intel_ring_begin(ring
, (w
->count
* 2 + 2));
687 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
688 for (i
= 0; i
< w
->count
; i
++) {
689 intel_ring_emit(ring
, w
->reg
[i
].addr
);
690 intel_ring_emit(ring
, w
->reg
[i
].value
);
692 intel_ring_emit(ring
, MI_NOOP
);
694 intel_ring_advance(ring
);
696 ring
->gpu_caches_dirty
= true;
697 ret
= intel_ring_flush_all_caches(ring
);
701 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
706 static int wa_add(struct drm_i915_private
*dev_priv
,
707 const u32 addr
, const u32 val
, const u32 mask
)
709 const u32 idx
= dev_priv
->workarounds
.count
;
711 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
714 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
715 dev_priv
->workarounds
.reg
[idx
].value
= val
;
716 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
718 dev_priv
->workarounds
.count
++;
723 #define WA_REG(addr, val, mask) { \
724 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
729 #define WA_SET_BIT_MASKED(addr, mask) \
730 WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
732 #define WA_CLR_BIT_MASKED(addr, mask) \
733 WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
735 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
736 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
738 #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
740 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
742 struct drm_device
*dev
= ring
->dev
;
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
745 /* WaDisablePartialInstShootdown:bdw */
746 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
747 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
748 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
749 STALL_DOP_GATING_DISABLE
);
751 /* WaDisableDopClockGating:bdw */
752 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
753 DOP_CLOCK_GATING_DISABLE
);
755 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
756 GEN8_SAMPLER_POWER_BYPASS_DIS
);
758 /* Use Force Non-Coherent whenever executing a 3D context. This is a
759 * workaround for for a possible hang in the unlikely event a TLB
760 * invalidation occurs during a PSD flush.
762 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
763 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
764 HDC_FORCE_NON_COHERENT
|
765 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
767 /* Wa4x4STCOptimizationDisable:bdw */
768 WA_SET_BIT_MASKED(CACHE_MODE_1
,
769 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
772 * BSpec recommends 8x4 when MSAA is used,
773 * however in practice 16x4 seems fastest.
775 * Note that PS/WM thread counts depend on the WIZ hashing
776 * disable bit, which we don't touch here, but it's good
777 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
779 WA_SET_BIT_MASKED(GEN7_GT_MODE
,
780 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
785 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
787 struct drm_device
*dev
= ring
->dev
;
788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
790 /* WaDisablePartialInstShootdown:chv */
791 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
792 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
794 /* WaDisableThreadStallDopClockGating:chv */
795 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
796 STALL_DOP_GATING_DISABLE
);
798 /* WaDisableDopClockGating:chv (pre-production hw) */
799 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
800 DOP_CLOCK_GATING_DISABLE
);
802 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
803 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
804 GEN8_SAMPLER_POWER_BYPASS_DIS
);
809 static int init_workarounds_ring(struct intel_engine_cs
*ring
)
811 struct drm_device
*dev
= ring
->dev
;
812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 WARN_ON(ring
->id
!= RCS
);
816 dev_priv
->workarounds
.count
= 0;
818 if (IS_BROADWELL(dev
))
819 return bdw_init_workarounds(ring
);
821 if (IS_CHERRYVIEW(dev
))
822 return chv_init_workarounds(ring
);
827 static int init_render_ring(struct intel_engine_cs
*ring
)
829 struct drm_device
*dev
= ring
->dev
;
830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
831 int ret
= init_ring_common(ring
);
835 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
836 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
837 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
839 /* We need to disable the AsyncFlip performance optimisations in order
840 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
841 * programmed to '1' on all products.
843 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
845 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 9)
846 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
848 /* Required for the hardware to program scanline values for waiting */
849 /* WaEnableFlushTlbInvalidationMode:snb */
850 if (INTEL_INFO(dev
)->gen
== 6)
852 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
854 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
856 I915_WRITE(GFX_MODE_GEN7
,
857 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
858 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
860 if (INTEL_INFO(dev
)->gen
>= 5) {
861 ret
= intel_init_pipe_control(ring
);
867 /* From the Sandybridge PRM, volume 1 part 3, page 24:
868 * "If this bit is set, STCunit will have LRA as replacement
869 * policy. [...] This bit must be reset. LRA replacement
870 * policy is not supported."
872 I915_WRITE(CACHE_MODE_0
,
873 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
876 if (INTEL_INFO(dev
)->gen
>= 6)
877 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
880 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
882 return init_workarounds_ring(ring
);
885 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
887 struct drm_device
*dev
= ring
->dev
;
888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
890 if (dev_priv
->semaphore_obj
) {
891 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
892 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
893 dev_priv
->semaphore_obj
= NULL
;
896 intel_fini_pipe_control(ring
);
899 static int gen8_rcs_signal(struct intel_engine_cs
*signaller
,
900 unsigned int num_dwords
)
902 #define MBOX_UPDATE_DWORDS 8
903 struct drm_device
*dev
= signaller
->dev
;
904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
905 struct intel_engine_cs
*waiter
;
906 int i
, ret
, num_rings
;
908 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
909 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
910 #undef MBOX_UPDATE_DWORDS
912 ret
= intel_ring_begin(signaller
, num_dwords
);
916 for_each_ring(waiter
, dev_priv
, i
) {
917 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
918 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
921 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
922 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
923 PIPE_CONTROL_QW_WRITE
|
924 PIPE_CONTROL_FLUSH_ENABLE
);
925 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
926 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
927 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
928 intel_ring_emit(signaller
, 0);
929 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
930 MI_SEMAPHORE_TARGET(waiter
->id
));
931 intel_ring_emit(signaller
, 0);
937 static int gen8_xcs_signal(struct intel_engine_cs
*signaller
,
938 unsigned int num_dwords
)
940 #define MBOX_UPDATE_DWORDS 6
941 struct drm_device
*dev
= signaller
->dev
;
942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
943 struct intel_engine_cs
*waiter
;
944 int i
, ret
, num_rings
;
946 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
947 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
948 #undef MBOX_UPDATE_DWORDS
950 ret
= intel_ring_begin(signaller
, num_dwords
);
954 for_each_ring(waiter
, dev_priv
, i
) {
955 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
956 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
959 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
960 MI_FLUSH_DW_OP_STOREDW
);
961 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
962 MI_FLUSH_DW_USE_GTT
);
963 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
964 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
965 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
966 MI_SEMAPHORE_TARGET(waiter
->id
));
967 intel_ring_emit(signaller
, 0);
973 static int gen6_signal(struct intel_engine_cs
*signaller
,
974 unsigned int num_dwords
)
976 struct drm_device
*dev
= signaller
->dev
;
977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
978 struct intel_engine_cs
*useless
;
979 int i
, ret
, num_rings
;
981 #define MBOX_UPDATE_DWORDS 3
982 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
983 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
984 #undef MBOX_UPDATE_DWORDS
986 ret
= intel_ring_begin(signaller
, num_dwords
);
990 for_each_ring(useless
, dev_priv
, i
) {
991 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
992 if (mbox_reg
!= GEN6_NOSYNC
) {
993 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
994 intel_ring_emit(signaller
, mbox_reg
);
995 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
999 /* If num_dwords was rounded, make sure the tail pointer is correct */
1000 if (num_rings
% 2 == 0)
1001 intel_ring_emit(signaller
, MI_NOOP
);
1007 * gen6_add_request - Update the semaphore mailbox registers
1009 * @ring - ring that is adding a request
1010 * @seqno - return seqno stuck into the ring
1012 * Update the mailbox registers in the *other* rings with the current seqno.
1013 * This acts like a signal in the canonical semaphore.
1016 gen6_add_request(struct intel_engine_cs
*ring
)
1020 if (ring
->semaphore
.signal
)
1021 ret
= ring
->semaphore
.signal(ring
, 4);
1023 ret
= intel_ring_begin(ring
, 4);
1028 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1029 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1030 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1031 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1032 __intel_ring_advance(ring
);
1037 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 return dev_priv
->last_seqno
< seqno
;
1045 * intel_ring_sync - sync the waiter to the signaller on seqno
1047 * @waiter - ring that is waiting
1048 * @signaller - ring which has, or will signal
1049 * @seqno - seqno which the waiter will block on
1053 gen8_ring_sync(struct intel_engine_cs
*waiter
,
1054 struct intel_engine_cs
*signaller
,
1057 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1060 ret
= intel_ring_begin(waiter
, 4);
1064 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1065 MI_SEMAPHORE_GLOBAL_GTT
|
1067 MI_SEMAPHORE_SAD_GTE_SDD
);
1068 intel_ring_emit(waiter
, seqno
);
1069 intel_ring_emit(waiter
,
1070 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1071 intel_ring_emit(waiter
,
1072 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1073 intel_ring_advance(waiter
);
1078 gen6_ring_sync(struct intel_engine_cs
*waiter
,
1079 struct intel_engine_cs
*signaller
,
1082 u32 dw1
= MI_SEMAPHORE_MBOX
|
1083 MI_SEMAPHORE_COMPARE
|
1084 MI_SEMAPHORE_REGISTER
;
1085 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1088 /* Throughout all of the GEM code, seqno passed implies our current
1089 * seqno is >= the last seqno executed. However for hardware the
1090 * comparison is strictly greater than.
1094 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1096 ret
= intel_ring_begin(waiter
, 4);
1100 /* If seqno wrap happened, omit the wait with no-ops */
1101 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1102 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1103 intel_ring_emit(waiter
, seqno
);
1104 intel_ring_emit(waiter
, 0);
1105 intel_ring_emit(waiter
, MI_NOOP
);
1107 intel_ring_emit(waiter
, MI_NOOP
);
1108 intel_ring_emit(waiter
, MI_NOOP
);
1109 intel_ring_emit(waiter
, MI_NOOP
);
1110 intel_ring_emit(waiter
, MI_NOOP
);
1112 intel_ring_advance(waiter
);
1117 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1119 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1120 PIPE_CONTROL_DEPTH_STALL); \
1121 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1122 intel_ring_emit(ring__, 0); \
1123 intel_ring_emit(ring__, 0); \
1127 pc_render_add_request(struct intel_engine_cs
*ring
)
1129 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1132 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1133 * incoherent with writes to memory, i.e. completely fubar,
1134 * so we need to use PIPE_NOTIFY instead.
1136 * However, we also need to workaround the qword write
1137 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1138 * memory before requesting an interrupt.
1140 ret
= intel_ring_begin(ring
, 32);
1144 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1145 PIPE_CONTROL_WRITE_FLUSH
|
1146 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1147 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1148 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1149 intel_ring_emit(ring
, 0);
1150 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1151 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1152 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1153 scratch_addr
+= 2 * CACHELINE_BYTES
;
1154 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1155 scratch_addr
+= 2 * CACHELINE_BYTES
;
1156 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1157 scratch_addr
+= 2 * CACHELINE_BYTES
;
1158 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1159 scratch_addr
+= 2 * CACHELINE_BYTES
;
1160 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1162 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1163 PIPE_CONTROL_WRITE_FLUSH
|
1164 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1165 PIPE_CONTROL_NOTIFY
);
1166 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1167 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1168 intel_ring_emit(ring
, 0);
1169 __intel_ring_advance(ring
);
1175 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1177 /* Workaround to force correct ordering between irq and seqno writes on
1178 * ivb (and maybe also on snb) by reading from a CS register (like
1179 * ACTHD) before reading the status page. */
1180 if (!lazy_coherency
) {
1181 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1182 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1185 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1189 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1191 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1195 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1197 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1201 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1203 return ring
->scratch
.cpu_page
[0];
1207 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1209 ring
->scratch
.cpu_page
[0] = seqno
;
1213 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1215 struct drm_device
*dev
= ring
->dev
;
1216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1217 unsigned long flags
;
1219 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1222 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1223 if (ring
->irq_refcount
++ == 0)
1224 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1225 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1231 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1233 struct drm_device
*dev
= ring
->dev
;
1234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1235 unsigned long flags
;
1237 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1238 if (--ring
->irq_refcount
== 0)
1239 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1240 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1244 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1246 struct drm_device
*dev
= ring
->dev
;
1247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1248 unsigned long flags
;
1250 if (!intel_irqs_enabled(dev_priv
))
1253 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1254 if (ring
->irq_refcount
++ == 0) {
1255 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1256 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1259 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1265 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1267 struct drm_device
*dev
= ring
->dev
;
1268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1269 unsigned long flags
;
1271 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1272 if (--ring
->irq_refcount
== 0) {
1273 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1274 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1277 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1281 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1283 struct drm_device
*dev
= ring
->dev
;
1284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1285 unsigned long flags
;
1287 if (!intel_irqs_enabled(dev_priv
))
1290 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1291 if (ring
->irq_refcount
++ == 0) {
1292 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1293 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1294 POSTING_READ16(IMR
);
1296 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1302 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1304 struct drm_device
*dev
= ring
->dev
;
1305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1306 unsigned long flags
;
1308 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1309 if (--ring
->irq_refcount
== 0) {
1310 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1311 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1312 POSTING_READ16(IMR
);
1314 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1317 void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
1319 struct drm_device
*dev
= ring
->dev
;
1320 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1323 /* The ring status page addresses are no longer next to the rest of
1324 * the ring registers as of gen7.
1329 mmio
= RENDER_HWS_PGA_GEN7
;
1332 mmio
= BLT_HWS_PGA_GEN7
;
1335 * VCS2 actually doesn't exist on Gen7. Only shut up
1336 * gcc switch check warning
1340 mmio
= BSD_HWS_PGA_GEN7
;
1343 mmio
= VEBOX_HWS_PGA_GEN7
;
1346 } else if (IS_GEN6(ring
->dev
)) {
1347 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
1349 /* XXX: gen8 returns to sanity */
1350 mmio
= RING_HWS_PGA(ring
->mmio_base
);
1353 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
1357 * Flush the TLB for this page
1359 * FIXME: These two bits have disappeared on gen8, so a question
1360 * arises: do we still need this and if so how should we go about
1361 * invalidating the TLB?
1363 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
1364 u32 reg
= RING_INSTPM(ring
->mmio_base
);
1366 /* ring should be idle before issuing a sync flush*/
1367 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1370 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
1371 INSTPM_SYNC_FLUSH
));
1372 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
1374 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1380 bsd_ring_flush(struct intel_engine_cs
*ring
,
1381 u32 invalidate_domains
,
1386 ret
= intel_ring_begin(ring
, 2);
1390 intel_ring_emit(ring
, MI_FLUSH
);
1391 intel_ring_emit(ring
, MI_NOOP
);
1392 intel_ring_advance(ring
);
1397 i9xx_add_request(struct intel_engine_cs
*ring
)
1401 ret
= intel_ring_begin(ring
, 4);
1405 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1406 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1407 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1408 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1409 __intel_ring_advance(ring
);
1415 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1417 struct drm_device
*dev
= ring
->dev
;
1418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1419 unsigned long flags
;
1421 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1424 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1425 if (ring
->irq_refcount
++ == 0) {
1426 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1427 I915_WRITE_IMR(ring
,
1428 ~(ring
->irq_enable_mask
|
1429 GT_PARITY_ERROR(dev
)));
1431 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1432 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1434 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1440 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1442 struct drm_device
*dev
= ring
->dev
;
1443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 unsigned long flags
;
1446 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1447 if (--ring
->irq_refcount
== 0) {
1448 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1449 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1451 I915_WRITE_IMR(ring
, ~0);
1452 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1454 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1458 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1460 struct drm_device
*dev
= ring
->dev
;
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1462 unsigned long flags
;
1464 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1467 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1468 if (ring
->irq_refcount
++ == 0) {
1469 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1470 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1472 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1478 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1480 struct drm_device
*dev
= ring
->dev
;
1481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1482 unsigned long flags
;
1484 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1485 if (--ring
->irq_refcount
== 0) {
1486 I915_WRITE_IMR(ring
, ~0);
1487 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1489 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1493 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1495 struct drm_device
*dev
= ring
->dev
;
1496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1497 unsigned long flags
;
1499 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1502 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1503 if (ring
->irq_refcount
++ == 0) {
1504 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1505 I915_WRITE_IMR(ring
,
1506 ~(ring
->irq_enable_mask
|
1507 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1509 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1511 POSTING_READ(RING_IMR(ring
->mmio_base
));
1513 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1519 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1521 struct drm_device
*dev
= ring
->dev
;
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 unsigned long flags
;
1525 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1526 if (--ring
->irq_refcount
== 0) {
1527 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1528 I915_WRITE_IMR(ring
,
1529 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1531 I915_WRITE_IMR(ring
, ~0);
1533 POSTING_READ(RING_IMR(ring
->mmio_base
));
1535 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1539 i965_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1540 u64 offset
, u32 length
,
1545 ret
= intel_ring_begin(ring
, 2);
1549 intel_ring_emit(ring
,
1550 MI_BATCH_BUFFER_START
|
1552 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1553 intel_ring_emit(ring
, offset
);
1554 intel_ring_advance(ring
);
1559 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1560 #define I830_BATCH_LIMIT (256*1024)
1561 #define I830_TLB_ENTRIES (2)
1562 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1564 i830_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1565 u64 offset
, u32 len
,
1568 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1571 ret
= intel_ring_begin(ring
, 6);
1575 /* Evict the invalid PTE TLBs */
1576 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1577 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1578 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1579 intel_ring_emit(ring
, cs_offset
);
1580 intel_ring_emit(ring
, 0xdeadbeef);
1581 intel_ring_emit(ring
, MI_NOOP
);
1582 intel_ring_advance(ring
);
1584 if ((flags
& I915_DISPATCH_PINNED
) == 0) {
1585 if (len
> I830_BATCH_LIMIT
)
1588 ret
= intel_ring_begin(ring
, 6 + 2);
1592 /* Blit the batch (which has now all relocs applied) to the
1593 * stable batch scratch bo area (so that the CS never
1594 * stumbles over its tlb invalidation bug) ...
1596 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1597 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1598 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1599 intel_ring_emit(ring
, cs_offset
);
1600 intel_ring_emit(ring
, 4096);
1601 intel_ring_emit(ring
, offset
);
1603 intel_ring_emit(ring
, MI_FLUSH
);
1604 intel_ring_emit(ring
, MI_NOOP
);
1605 intel_ring_advance(ring
);
1607 /* ... and execute it. */
1611 ret
= intel_ring_begin(ring
, 4);
1615 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1616 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1617 intel_ring_emit(ring
, offset
+ len
- 8);
1618 intel_ring_emit(ring
, MI_NOOP
);
1619 intel_ring_advance(ring
);
1625 i915_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1626 u64 offset
, u32 len
,
1631 ret
= intel_ring_begin(ring
, 2);
1635 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1636 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1637 intel_ring_advance(ring
);
1642 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1644 struct drm_i915_gem_object
*obj
;
1646 obj
= ring
->status_page
.obj
;
1650 kunmap(sg_page(obj
->pages
->sgl
));
1651 i915_gem_object_ggtt_unpin(obj
);
1652 drm_gem_object_unreference(&obj
->base
);
1653 ring
->status_page
.obj
= NULL
;
1656 static int init_status_page(struct intel_engine_cs
*ring
)
1658 struct drm_i915_gem_object
*obj
;
1660 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1664 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1666 DRM_ERROR("Failed to allocate status page\n");
1670 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1675 if (!HAS_LLC(ring
->dev
))
1676 /* On g33, we cannot place HWS above 256MiB, so
1677 * restrict its pinning to the low mappable arena.
1678 * Though this restriction is not documented for
1679 * gen4, gen5, or byt, they also behave similarly
1680 * and hang if the HWS is placed at the top of the
1681 * GTT. To generalise, it appears that all !llc
1682 * platforms have issues with us placing the HWS
1683 * above the mappable region (even though we never
1686 flags
|= PIN_MAPPABLE
;
1687 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1690 drm_gem_object_unreference(&obj
->base
);
1694 ring
->status_page
.obj
= obj
;
1697 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1698 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1699 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1701 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1702 ring
->name
, ring
->status_page
.gfx_addr
);
1707 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1709 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1711 if (!dev_priv
->status_page_dmah
) {
1712 dev_priv
->status_page_dmah
=
1713 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1714 if (!dev_priv
->status_page_dmah
)
1718 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1719 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1724 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1729 iounmap(ringbuf
->virtual_start
);
1730 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1731 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1732 ringbuf
->obj
= NULL
;
1735 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1736 struct intel_ringbuffer
*ringbuf
)
1738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1739 struct drm_i915_gem_object
*obj
;
1747 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
1749 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
1753 /* mark ring buffers as read-only from GPU side by default */
1756 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1760 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1764 ringbuf
->virtual_start
=
1765 ioremap_wc(dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
),
1767 if (ringbuf
->virtual_start
== NULL
) {
1776 i915_gem_object_ggtt_unpin(obj
);
1778 drm_gem_object_unreference(&obj
->base
);
1782 static int intel_init_ring_buffer(struct drm_device
*dev
,
1783 struct intel_engine_cs
*ring
)
1785 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1788 if (ringbuf
== NULL
) {
1789 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1792 ring
->buffer
= ringbuf
;
1796 INIT_LIST_HEAD(&ring
->active_list
);
1797 INIT_LIST_HEAD(&ring
->request_list
);
1798 INIT_LIST_HEAD(&ring
->execlist_queue
);
1799 ringbuf
->size
= 32 * PAGE_SIZE
;
1800 ringbuf
->ring
= ring
;
1801 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
1803 init_waitqueue_head(&ring
->irq_queue
);
1805 if (I915_NEED_GFX_HWS(dev
)) {
1806 ret
= init_status_page(ring
);
1810 BUG_ON(ring
->id
!= RCS
);
1811 ret
= init_phys_status_page(ring
);
1816 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1818 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring
->name
, ret
);
1822 /* Workaround an erratum on the i830 which causes a hang if
1823 * the TAIL pointer points to within the last 2 cachelines
1826 ringbuf
->effective_size
= ringbuf
->size
;
1827 if (IS_I830(dev
) || IS_845G(dev
))
1828 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
1830 ret
= i915_cmd_parser_init_ring(ring
);
1834 ret
= ring
->init(ring
);
1842 ring
->buffer
= NULL
;
1846 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
1848 struct drm_i915_private
*dev_priv
;
1849 struct intel_ringbuffer
*ringbuf
;
1851 if (!intel_ring_initialized(ring
))
1854 dev_priv
= to_i915(ring
->dev
);
1855 ringbuf
= ring
->buffer
;
1857 intel_stop_ring_buffer(ring
);
1858 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1860 intel_destroy_ringbuffer_obj(ringbuf
);
1861 ring
->preallocated_lazy_request
= NULL
;
1862 ring
->outstanding_lazy_seqno
= 0;
1865 ring
->cleanup(ring
);
1867 cleanup_status_page(ring
);
1869 i915_cmd_parser_fini_ring(ring
);
1872 ring
->buffer
= NULL
;
1875 static int intel_ring_wait_request(struct intel_engine_cs
*ring
, int n
)
1877 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1878 struct drm_i915_gem_request
*request
;
1882 if (ringbuf
->last_retired_head
!= -1) {
1883 ringbuf
->head
= ringbuf
->last_retired_head
;
1884 ringbuf
->last_retired_head
= -1;
1886 ringbuf
->space
= intel_ring_space(ringbuf
);
1887 if (ringbuf
->space
>= n
)
1891 list_for_each_entry(request
, &ring
->request_list
, list
) {
1892 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
1893 ringbuf
->size
) >= n
) {
1894 seqno
= request
->seqno
;
1902 ret
= i915_wait_seqno(ring
, seqno
);
1906 i915_gem_retire_requests_ring(ring
);
1907 ringbuf
->head
= ringbuf
->last_retired_head
;
1908 ringbuf
->last_retired_head
= -1;
1910 ringbuf
->space
= intel_ring_space(ringbuf
);
1914 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
1916 struct drm_device
*dev
= ring
->dev
;
1917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1918 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1922 ret
= intel_ring_wait_request(ring
, n
);
1926 /* force the tail write in case we have been skipping them */
1927 __intel_ring_advance(ring
);
1929 /* With GEM the hangcheck timer should kick us out of the loop,
1930 * leaving it early runs the risk of corrupting GEM state (due
1931 * to running on almost untested codepaths). But on resume
1932 * timers don't work yet, so prevent a complete hang in that
1933 * case by choosing an insanely large timeout. */
1934 end
= jiffies
+ 60 * HZ
;
1936 trace_i915_ring_wait_begin(ring
);
1938 ringbuf
->head
= I915_READ_HEAD(ring
);
1939 ringbuf
->space
= intel_ring_space(ringbuf
);
1940 if (ringbuf
->space
>= n
) {
1945 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) &&
1946 dev
->primary
->master
) {
1947 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1948 if (master_priv
->sarea_priv
)
1949 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1954 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
1959 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1960 dev_priv
->mm
.interruptible
);
1964 if (time_after(jiffies
, end
)) {
1969 trace_i915_ring_wait_end(ring
);
1973 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
1975 uint32_t __iomem
*virt
;
1976 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1977 int rem
= ringbuf
->size
- ringbuf
->tail
;
1979 if (ringbuf
->space
< rem
) {
1980 int ret
= ring_wait_for_space(ring
, rem
);
1985 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
1988 iowrite32(MI_NOOP
, virt
++);
1991 ringbuf
->space
= intel_ring_space(ringbuf
);
1996 int intel_ring_idle(struct intel_engine_cs
*ring
)
2001 /* We need to add any requests required to flush the objects and ring */
2002 if (ring
->outstanding_lazy_seqno
) {
2003 ret
= i915_add_request(ring
, NULL
);
2008 /* Wait upon the last request to be completed */
2009 if (list_empty(&ring
->request_list
))
2012 seqno
= list_entry(ring
->request_list
.prev
,
2013 struct drm_i915_gem_request
,
2016 return i915_wait_seqno(ring
, seqno
);
2020 intel_ring_alloc_seqno(struct intel_engine_cs
*ring
)
2022 if (ring
->outstanding_lazy_seqno
)
2025 if (ring
->preallocated_lazy_request
== NULL
) {
2026 struct drm_i915_gem_request
*request
;
2028 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2029 if (request
== NULL
)
2032 ring
->preallocated_lazy_request
= request
;
2035 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
2038 static int __intel_ring_prepare(struct intel_engine_cs
*ring
,
2041 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2044 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2045 ret
= intel_wrap_ring_buffer(ring
);
2050 if (unlikely(ringbuf
->space
< bytes
)) {
2051 ret
= ring_wait_for_space(ring
, bytes
);
2059 int intel_ring_begin(struct intel_engine_cs
*ring
,
2062 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2065 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2066 dev_priv
->mm
.interruptible
);
2070 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2074 /* Preallocate the olr before touching the ring */
2075 ret
= intel_ring_alloc_seqno(ring
);
2079 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2083 /* Align the ring tail to a cacheline boundary */
2084 int intel_ring_cacheline_align(struct intel_engine_cs
*ring
)
2086 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2089 if (num_dwords
== 0)
2092 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2093 ret
= intel_ring_begin(ring
, num_dwords
);
2097 while (num_dwords
--)
2098 intel_ring_emit(ring
, MI_NOOP
);
2100 intel_ring_advance(ring
);
2105 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2107 struct drm_device
*dev
= ring
->dev
;
2108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2110 BUG_ON(ring
->outstanding_lazy_seqno
);
2112 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2113 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2114 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2116 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2119 ring
->set_seqno(ring
, seqno
);
2120 ring
->hangcheck
.seqno
= seqno
;
2123 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2126 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2128 /* Every tail move must follow the sequence below */
2130 /* Disable notification that the ring is IDLE. The GT
2131 * will then assume that it is busy and bring it out of rc6.
2133 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2134 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2136 /* Clear the context id. Here be magic! */
2137 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2139 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2140 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2141 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2143 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2145 /* Now that the ring is fully powered up, update the tail */
2146 I915_WRITE_TAIL(ring
, value
);
2147 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2149 /* Let the ring send IDLE messages to the GT again,
2150 * and so let it sleep to conserve power when idle.
2152 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2153 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2156 static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring
,
2157 u32 invalidate
, u32 flush
)
2162 ret
= intel_ring_begin(ring
, 4);
2167 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2170 * Bspec vol 1c.5 - video engine command streamer:
2171 * "If ENABLED, all TLBs will be invalidated once the flush
2172 * operation is complete. This bit is only valid when the
2173 * Post-Sync Operation field is a value of 1h or 3h."
2175 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2176 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
2177 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2178 intel_ring_emit(ring
, cmd
);
2179 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2180 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2181 intel_ring_emit(ring
, 0); /* upper addr */
2182 intel_ring_emit(ring
, 0); /* value */
2184 intel_ring_emit(ring
, 0);
2185 intel_ring_emit(ring
, MI_NOOP
);
2187 intel_ring_advance(ring
);
2192 gen8_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2193 u64 offset
, u32 len
,
2196 bool ppgtt
= USES_PPGTT(ring
->dev
) && !(flags
& I915_DISPATCH_SECURE
);
2199 ret
= intel_ring_begin(ring
, 4);
2203 /* FIXME(BDW): Address space and security selectors. */
2204 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2205 intel_ring_emit(ring
, lower_32_bits(offset
));
2206 intel_ring_emit(ring
, upper_32_bits(offset
));
2207 intel_ring_emit(ring
, MI_NOOP
);
2208 intel_ring_advance(ring
);
2214 hsw_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2215 u64 offset
, u32 len
,
2220 ret
= intel_ring_begin(ring
, 2);
2224 intel_ring_emit(ring
,
2225 MI_BATCH_BUFFER_START
|
2226 (flags
& I915_DISPATCH_SECURE
?
2227 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
));
2228 /* bit0-7 is the length on GEN6+ */
2229 intel_ring_emit(ring
, offset
);
2230 intel_ring_advance(ring
);
2236 gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2237 u64 offset
, u32 len
,
2242 ret
= intel_ring_begin(ring
, 2);
2246 intel_ring_emit(ring
,
2247 MI_BATCH_BUFFER_START
|
2248 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
2249 /* bit0-7 is the length on GEN6+ */
2250 intel_ring_emit(ring
, offset
);
2251 intel_ring_advance(ring
);
2256 /* Blitter support (SandyBridge+) */
2258 static int gen6_ring_flush(struct intel_engine_cs
*ring
,
2259 u32 invalidate
, u32 flush
)
2261 struct drm_device
*dev
= ring
->dev
;
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 ret
= intel_ring_begin(ring
, 4);
2271 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2274 * Bspec vol 1c.3 - blitter engine command streamer:
2275 * "If ENABLED, all TLBs will be invalidated once the flush
2276 * operation is complete. This bit is only valid when the
2277 * Post-Sync Operation field is a value of 1h or 3h."
2279 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2280 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
2281 MI_FLUSH_DW_OP_STOREDW
;
2282 intel_ring_emit(ring
, cmd
);
2283 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2284 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2285 intel_ring_emit(ring
, 0); /* upper addr */
2286 intel_ring_emit(ring
, 0); /* value */
2288 intel_ring_emit(ring
, 0);
2289 intel_ring_emit(ring
, MI_NOOP
);
2291 intel_ring_advance(ring
);
2293 if (!invalidate
&& flush
) {
2295 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
2296 else if (IS_BROADWELL(dev
))
2297 dev_priv
->fbc
.need_sw_cache_clean
= true;
2303 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2307 struct drm_i915_gem_object
*obj
;
2310 ring
->name
= "render ring";
2312 ring
->mmio_base
= RENDER_RING_BASE
;
2314 if (INTEL_INFO(dev
)->gen
>= 8) {
2315 if (i915_semaphore_is_enabled(dev
)) {
2316 obj
= i915_gem_alloc_object(dev
, 4096);
2318 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2319 i915
.semaphores
= 0;
2321 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2322 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2324 drm_gem_object_unreference(&obj
->base
);
2325 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2326 i915
.semaphores
= 0;
2328 dev_priv
->semaphore_obj
= obj
;
2332 ring
->init_context
= intel_ring_workarounds_emit
;
2333 ring
->add_request
= gen6_add_request
;
2334 ring
->flush
= gen8_render_ring_flush
;
2335 ring
->irq_get
= gen8_ring_get_irq
;
2336 ring
->irq_put
= gen8_ring_put_irq
;
2337 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2338 ring
->get_seqno
= gen6_ring_get_seqno
;
2339 ring
->set_seqno
= ring_set_seqno
;
2340 if (i915_semaphore_is_enabled(dev
)) {
2341 WARN_ON(!dev_priv
->semaphore_obj
);
2342 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2343 ring
->semaphore
.signal
= gen8_rcs_signal
;
2344 GEN8_RING_SEMAPHORE_INIT
;
2346 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2347 ring
->add_request
= gen6_add_request
;
2348 ring
->flush
= gen7_render_ring_flush
;
2349 if (INTEL_INFO(dev
)->gen
== 6)
2350 ring
->flush
= gen6_render_ring_flush
;
2351 ring
->irq_get
= gen6_ring_get_irq
;
2352 ring
->irq_put
= gen6_ring_put_irq
;
2353 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2354 ring
->get_seqno
= gen6_ring_get_seqno
;
2355 ring
->set_seqno
= ring_set_seqno
;
2356 if (i915_semaphore_is_enabled(dev
)) {
2357 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2358 ring
->semaphore
.signal
= gen6_signal
;
2360 * The current semaphore is only applied on pre-gen8
2361 * platform. And there is no VCS2 ring on the pre-gen8
2362 * platform. So the semaphore between RCS and VCS2 is
2363 * initialized as INVALID. Gen8 will initialize the
2364 * sema between VCS2 and RCS later.
2366 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2367 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2368 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2369 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2370 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2371 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2372 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2373 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2374 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2375 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2377 } else if (IS_GEN5(dev
)) {
2378 ring
->add_request
= pc_render_add_request
;
2379 ring
->flush
= gen4_render_ring_flush
;
2380 ring
->get_seqno
= pc_render_get_seqno
;
2381 ring
->set_seqno
= pc_render_set_seqno
;
2382 ring
->irq_get
= gen5_ring_get_irq
;
2383 ring
->irq_put
= gen5_ring_put_irq
;
2384 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2385 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2387 ring
->add_request
= i9xx_add_request
;
2388 if (INTEL_INFO(dev
)->gen
< 4)
2389 ring
->flush
= gen2_render_ring_flush
;
2391 ring
->flush
= gen4_render_ring_flush
;
2392 ring
->get_seqno
= ring_get_seqno
;
2393 ring
->set_seqno
= ring_set_seqno
;
2395 ring
->irq_get
= i8xx_ring_get_irq
;
2396 ring
->irq_put
= i8xx_ring_put_irq
;
2398 ring
->irq_get
= i9xx_ring_get_irq
;
2399 ring
->irq_put
= i9xx_ring_put_irq
;
2401 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2403 ring
->write_tail
= ring_write_tail
;
2405 if (IS_HASWELL(dev
))
2406 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2407 else if (IS_GEN8(dev
))
2408 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2409 else if (INTEL_INFO(dev
)->gen
>= 6)
2410 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2411 else if (INTEL_INFO(dev
)->gen
>= 4)
2412 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2413 else if (IS_I830(dev
) || IS_845G(dev
))
2414 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2416 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2417 ring
->init
= init_render_ring
;
2418 ring
->cleanup
= render_ring_cleanup
;
2420 /* Workaround batchbuffer to combat CS tlb bug. */
2421 if (HAS_BROKEN_CS_TLB(dev
)) {
2422 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2424 DRM_ERROR("Failed to allocate batch bo\n");
2428 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2430 drm_gem_object_unreference(&obj
->base
);
2431 DRM_ERROR("Failed to ping batch bo\n");
2435 ring
->scratch
.obj
= obj
;
2436 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2439 return intel_init_ring_buffer(dev
, ring
);
2442 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
2444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2445 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2446 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2449 if (ringbuf
== NULL
) {
2450 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2453 ring
->buffer
= ringbuf
;
2456 ring
->name
= "render ring";
2458 ring
->mmio_base
= RENDER_RING_BASE
;
2460 if (INTEL_INFO(dev
)->gen
>= 6) {
2461 /* non-kms not supported on gen6+ */
2466 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2467 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2468 * the special gen5 functions. */
2469 ring
->add_request
= i9xx_add_request
;
2470 if (INTEL_INFO(dev
)->gen
< 4)
2471 ring
->flush
= gen2_render_ring_flush
;
2473 ring
->flush
= gen4_render_ring_flush
;
2474 ring
->get_seqno
= ring_get_seqno
;
2475 ring
->set_seqno
= ring_set_seqno
;
2477 ring
->irq_get
= i8xx_ring_get_irq
;
2478 ring
->irq_put
= i8xx_ring_put_irq
;
2480 ring
->irq_get
= i9xx_ring_get_irq
;
2481 ring
->irq_put
= i9xx_ring_put_irq
;
2483 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2484 ring
->write_tail
= ring_write_tail
;
2485 if (INTEL_INFO(dev
)->gen
>= 4)
2486 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2487 else if (IS_I830(dev
) || IS_845G(dev
))
2488 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2490 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2491 ring
->init
= init_render_ring
;
2492 ring
->cleanup
= render_ring_cleanup
;
2495 INIT_LIST_HEAD(&ring
->active_list
);
2496 INIT_LIST_HEAD(&ring
->request_list
);
2498 ringbuf
->size
= size
;
2499 ringbuf
->effective_size
= ringbuf
->size
;
2500 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
2501 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
2503 ringbuf
->virtual_start
= ioremap_wc(start
, size
);
2504 if (ringbuf
->virtual_start
== NULL
) {
2505 DRM_ERROR("can not ioremap virtual address for"
2511 if (!I915_NEED_GFX_HWS(dev
)) {
2512 ret
= init_phys_status_page(ring
);
2520 iounmap(ringbuf
->virtual_start
);
2523 ring
->buffer
= NULL
;
2527 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2530 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2532 ring
->name
= "bsd ring";
2535 ring
->write_tail
= ring_write_tail
;
2536 if (INTEL_INFO(dev
)->gen
>= 6) {
2537 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2538 /* gen6 bsd needs a special wa for tail updates */
2540 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2541 ring
->flush
= gen6_bsd_ring_flush
;
2542 ring
->add_request
= gen6_add_request
;
2543 ring
->get_seqno
= gen6_ring_get_seqno
;
2544 ring
->set_seqno
= ring_set_seqno
;
2545 if (INTEL_INFO(dev
)->gen
>= 8) {
2546 ring
->irq_enable_mask
=
2547 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2548 ring
->irq_get
= gen8_ring_get_irq
;
2549 ring
->irq_put
= gen8_ring_put_irq
;
2550 ring
->dispatch_execbuffer
=
2551 gen8_ring_dispatch_execbuffer
;
2552 if (i915_semaphore_is_enabled(dev
)) {
2553 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2554 ring
->semaphore
.signal
= gen8_xcs_signal
;
2555 GEN8_RING_SEMAPHORE_INIT
;
2558 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2559 ring
->irq_get
= gen6_ring_get_irq
;
2560 ring
->irq_put
= gen6_ring_put_irq
;
2561 ring
->dispatch_execbuffer
=
2562 gen6_ring_dispatch_execbuffer
;
2563 if (i915_semaphore_is_enabled(dev
)) {
2564 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2565 ring
->semaphore
.signal
= gen6_signal
;
2566 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2567 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2568 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2569 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2570 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2571 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2572 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2573 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2574 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2575 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2579 ring
->mmio_base
= BSD_RING_BASE
;
2580 ring
->flush
= bsd_ring_flush
;
2581 ring
->add_request
= i9xx_add_request
;
2582 ring
->get_seqno
= ring_get_seqno
;
2583 ring
->set_seqno
= ring_set_seqno
;
2585 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2586 ring
->irq_get
= gen5_ring_get_irq
;
2587 ring
->irq_put
= gen5_ring_put_irq
;
2589 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2590 ring
->irq_get
= i9xx_ring_get_irq
;
2591 ring
->irq_put
= i9xx_ring_put_irq
;
2593 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2595 ring
->init
= init_ring_common
;
2597 return intel_init_ring_buffer(dev
, ring
);
2601 * Initialize the second BSD ring for Broadwell GT3.
2602 * It is noted that this only exists on Broadwell GT3.
2604 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2607 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2609 if ((INTEL_INFO(dev
)->gen
!= 8)) {
2610 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2614 ring
->name
= "bsd2 ring";
2617 ring
->write_tail
= ring_write_tail
;
2618 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2619 ring
->flush
= gen6_bsd_ring_flush
;
2620 ring
->add_request
= gen6_add_request
;
2621 ring
->get_seqno
= gen6_ring_get_seqno
;
2622 ring
->set_seqno
= ring_set_seqno
;
2623 ring
->irq_enable_mask
=
2624 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2625 ring
->irq_get
= gen8_ring_get_irq
;
2626 ring
->irq_put
= gen8_ring_put_irq
;
2627 ring
->dispatch_execbuffer
=
2628 gen8_ring_dispatch_execbuffer
;
2629 if (i915_semaphore_is_enabled(dev
)) {
2630 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2631 ring
->semaphore
.signal
= gen8_xcs_signal
;
2632 GEN8_RING_SEMAPHORE_INIT
;
2634 ring
->init
= init_ring_common
;
2636 return intel_init_ring_buffer(dev
, ring
);
2639 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2642 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2644 ring
->name
= "blitter ring";
2647 ring
->mmio_base
= BLT_RING_BASE
;
2648 ring
->write_tail
= ring_write_tail
;
2649 ring
->flush
= gen6_ring_flush
;
2650 ring
->add_request
= gen6_add_request
;
2651 ring
->get_seqno
= gen6_ring_get_seqno
;
2652 ring
->set_seqno
= ring_set_seqno
;
2653 if (INTEL_INFO(dev
)->gen
>= 8) {
2654 ring
->irq_enable_mask
=
2655 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2656 ring
->irq_get
= gen8_ring_get_irq
;
2657 ring
->irq_put
= gen8_ring_put_irq
;
2658 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2659 if (i915_semaphore_is_enabled(dev
)) {
2660 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2661 ring
->semaphore
.signal
= gen8_xcs_signal
;
2662 GEN8_RING_SEMAPHORE_INIT
;
2665 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2666 ring
->irq_get
= gen6_ring_get_irq
;
2667 ring
->irq_put
= gen6_ring_put_irq
;
2668 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2669 if (i915_semaphore_is_enabled(dev
)) {
2670 ring
->semaphore
.signal
= gen6_signal
;
2671 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2673 * The current semaphore is only applied on pre-gen8
2674 * platform. And there is no VCS2 ring on the pre-gen8
2675 * platform. So the semaphore between BCS and VCS2 is
2676 * initialized as INVALID. Gen8 will initialize the
2677 * sema between BCS and VCS2 later.
2679 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2680 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2681 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2682 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2683 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2684 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2685 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2686 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2687 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2688 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2691 ring
->init
= init_ring_common
;
2693 return intel_init_ring_buffer(dev
, ring
);
2696 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2699 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2701 ring
->name
= "video enhancement ring";
2704 ring
->mmio_base
= VEBOX_RING_BASE
;
2705 ring
->write_tail
= ring_write_tail
;
2706 ring
->flush
= gen6_ring_flush
;
2707 ring
->add_request
= gen6_add_request
;
2708 ring
->get_seqno
= gen6_ring_get_seqno
;
2709 ring
->set_seqno
= ring_set_seqno
;
2711 if (INTEL_INFO(dev
)->gen
>= 8) {
2712 ring
->irq_enable_mask
=
2713 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2714 ring
->irq_get
= gen8_ring_get_irq
;
2715 ring
->irq_put
= gen8_ring_put_irq
;
2716 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2717 if (i915_semaphore_is_enabled(dev
)) {
2718 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2719 ring
->semaphore
.signal
= gen8_xcs_signal
;
2720 GEN8_RING_SEMAPHORE_INIT
;
2723 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2724 ring
->irq_get
= hsw_vebox_get_irq
;
2725 ring
->irq_put
= hsw_vebox_put_irq
;
2726 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2727 if (i915_semaphore_is_enabled(dev
)) {
2728 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2729 ring
->semaphore
.signal
= gen6_signal
;
2730 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2731 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2732 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2733 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2734 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2735 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2736 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2737 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2738 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2739 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2742 ring
->init
= init_ring_common
;
2744 return intel_init_ring_buffer(dev
, ring
);
2748 intel_ring_flush_all_caches(struct intel_engine_cs
*ring
)
2752 if (!ring
->gpu_caches_dirty
)
2755 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2759 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2761 ring
->gpu_caches_dirty
= false;
2766 intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
)
2768 uint32_t flush_domains
;
2772 if (ring
->gpu_caches_dirty
)
2773 flush_domains
= I915_GEM_GPU_DOMAINS
;
2775 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2779 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2781 ring
->gpu_caches_dirty
= false;
2786 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2790 if (!intel_ring_initialized(ring
))
2793 ret
= intel_ring_idle(ring
);
2794 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2795 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",