2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- tail
;
58 return space
- I915_RING_FREE_SPACE
;
61 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
63 if (ringbuf
->last_retired_head
!= -1) {
64 ringbuf
->head
= ringbuf
->last_retired_head
;
65 ringbuf
->last_retired_head
= -1;
68 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
69 ringbuf
->tail
, ringbuf
->size
);
72 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
74 intel_ring_update_space(ringbuf
);
75 return ringbuf
->space
;
78 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
80 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
81 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
84 void __intel_ring_advance(struct intel_engine_cs
*ring
)
86 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
87 ringbuf
->tail
&= ringbuf
->size
- 1;
88 if (intel_ring_stopped(ring
))
90 ring
->write_tail(ring
, ringbuf
->tail
);
94 gen2_render_ring_flush(struct intel_engine_cs
*ring
,
95 u32 invalidate_domains
,
102 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
103 cmd
|= MI_NO_WRITE_FLUSH
;
105 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
106 cmd
|= MI_READ_FLUSH
;
108 ret
= intel_ring_begin(ring
, 2);
112 intel_ring_emit(ring
, cmd
);
113 intel_ring_emit(ring
, MI_NOOP
);
114 intel_ring_advance(ring
);
120 gen4_render_ring_flush(struct intel_engine_cs
*ring
,
121 u32 invalidate_domains
,
124 struct drm_device
*dev
= ring
->dev
;
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
140 * I915_GEM_DOMAIN_COMMAND may not exist?
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
156 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
157 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
158 cmd
&= ~MI_NO_WRITE_FLUSH
;
159 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
162 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
163 (IS_G4X(dev
) || IS_GEN5(dev
)))
164 cmd
|= MI_INVALIDATE_ISP
;
166 ret
= intel_ring_begin(ring
, 2);
170 intel_ring_emit(ring
, cmd
);
171 intel_ring_emit(ring
, MI_NOOP
);
172 intel_ring_advance(ring
);
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 * And the workaround for these two requires this workaround first:
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs
*ring
)
217 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
221 ret
= intel_ring_begin(ring
, 6);
225 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
227 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
228 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
229 intel_ring_emit(ring
, 0); /* low dword */
230 intel_ring_emit(ring
, 0); /* high dword */
231 intel_ring_emit(ring
, MI_NOOP
);
232 intel_ring_advance(ring
);
234 ret
= intel_ring_begin(ring
, 6);
238 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
240 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
241 intel_ring_emit(ring
, 0);
242 intel_ring_emit(ring
, 0);
243 intel_ring_emit(ring
, MI_NOOP
);
244 intel_ring_advance(ring
);
250 gen6_render_ring_flush(struct intel_engine_cs
*ring
,
251 u32 invalidate_domains
, u32 flush_domains
)
254 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret
= intel_emit_post_sync_nonzero_flush(ring
);
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
267 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
268 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
273 flags
|= PIPE_CONTROL_CS_STALL
;
275 if (invalidate_domains
) {
276 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
277 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
278 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
279 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
280 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
281 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
283 * TLB invalidate requires a post-sync write.
285 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
288 ret
= intel_ring_begin(ring
, 4);
292 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring
, flags
);
294 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
295 intel_ring_emit(ring
, 0);
296 intel_ring_advance(ring
);
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs
*ring
)
306 ret
= intel_ring_begin(ring
, 4);
310 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
312 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
313 intel_ring_emit(ring
, 0);
314 intel_ring_emit(ring
, 0);
315 intel_ring_advance(ring
);
321 gen7_render_ring_flush(struct intel_engine_cs
*ring
,
322 u32 invalidate_domains
, u32 flush_domains
)
325 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
336 flags
|= PIPE_CONTROL_CS_STALL
;
338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
343 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
344 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
346 if (invalidate_domains
) {
347 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
348 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
349 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
350 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
351 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
352 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
353 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
355 * TLB invalidate requires a post-sync write.
357 flags
|= PIPE_CONTROL_QW_WRITE
;
358 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
360 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring
);
368 ret
= intel_ring_begin(ring
, 4);
372 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring
, flags
);
374 intel_ring_emit(ring
, scratch_addr
);
375 intel_ring_emit(ring
, 0);
376 intel_ring_advance(ring
);
382 gen8_emit_pipe_control(struct intel_engine_cs
*ring
,
383 u32 flags
, u32 scratch_addr
)
387 ret
= intel_ring_begin(ring
, 6);
391 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring
, flags
);
393 intel_ring_emit(ring
, scratch_addr
);
394 intel_ring_emit(ring
, 0);
395 intel_ring_emit(ring
, 0);
396 intel_ring_emit(ring
, 0);
397 intel_ring_advance(ring
);
403 gen8_render_ring_flush(struct intel_engine_cs
*ring
,
404 u32 invalidate_domains
, u32 flush_domains
)
407 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
410 flags
|= PIPE_CONTROL_CS_STALL
;
413 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
414 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
416 if (invalidate_domains
) {
417 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
418 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
419 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
420 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
421 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
422 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
423 flags
|= PIPE_CONTROL_QW_WRITE
;
424 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret
= gen8_emit_pipe_control(ring
,
428 PIPE_CONTROL_CS_STALL
|
429 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
435 return gen8_emit_pipe_control(ring
, flags
, scratch_addr
);
438 static void ring_write_tail(struct intel_engine_cs
*ring
,
441 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
442 I915_WRITE_TAIL(ring
, value
);
445 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
447 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
450 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
451 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
452 RING_ACTHD_UDW(ring
->mmio_base
));
453 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
454 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
456 acthd
= I915_READ(ACTHD
);
461 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
463 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
466 addr
= dev_priv
->status_page_dmah
->busaddr
;
467 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
468 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
469 I915_WRITE(HWS_PGA
, addr
);
472 static void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
474 struct drm_device
*dev
= ring
->dev
;
475 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
484 mmio
= RENDER_HWS_PGA_GEN7
;
487 mmio
= BLT_HWS_PGA_GEN7
;
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
495 mmio
= BSD_HWS_PGA_GEN7
;
498 mmio
= VEBOX_HWS_PGA_GEN7
;
501 } else if (IS_GEN6(ring
->dev
)) {
502 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
504 /* XXX: gen8 returns to sanity */
505 mmio
= RING_HWS_PGA(ring
->mmio_base
);
508 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
512 * Flush the TLB for this page
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
518 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
519 u32 reg
= RING_INSTPM(ring
->mmio_base
);
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
527 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
534 static bool stop_ring(struct intel_engine_cs
*ring
)
536 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
538 if (!IS_GEN2(ring
->dev
)) {
539 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
540 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
546 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
551 I915_WRITE_CTL(ring
, 0);
552 I915_WRITE_HEAD(ring
, 0);
553 ring
->write_tail(ring
, 0);
555 if (!IS_GEN2(ring
->dev
)) {
556 (void)I915_READ_CTL(ring
);
557 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
560 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
563 static int init_ring_common(struct intel_engine_cs
*ring
)
565 struct drm_device
*dev
= ring
->dev
;
566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
567 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
568 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
571 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
573 if (!stop_ring(ring
)) {
574 /* G45 ring initialization often fails to reset head to zero */
575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
579 I915_READ_HEAD(ring
),
580 I915_READ_TAIL(ring
),
581 I915_READ_START(ring
));
583 if (!stop_ring(ring
)) {
584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
588 I915_READ_HEAD(ring
),
589 I915_READ_TAIL(ring
),
590 I915_READ_START(ring
));
596 if (I915_NEED_GFX_HWS(dev
))
597 intel_ring_setup_status_page(ring
);
599 ring_setup_phys_status_page(ring
);
601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring
);
604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
608 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring
))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring
->name
, I915_READ_HEAD(ring
));
614 I915_WRITE_HEAD(ring
, 0);
615 (void)I915_READ_HEAD(ring
);
618 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
621 /* If the head is still not zero, the ring is dead */
622 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
623 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
624 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
625 DRM_ERROR("%s initialization failed "
626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
628 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
629 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
630 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
635 ringbuf
->last_retired_head
= -1;
636 ringbuf
->head
= I915_READ_HEAD(ring
);
637 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
638 intel_ring_update_space(ringbuf
);
640 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
643 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
649 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
651 struct drm_device
*dev
= ring
->dev
;
653 if (ring
->scratch
.obj
== NULL
)
656 if (INTEL_INFO(dev
)->gen
>= 5) {
657 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
658 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
661 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
662 ring
->scratch
.obj
= NULL
;
666 intel_init_pipe_control(struct intel_engine_cs
*ring
)
670 WARN_ON(ring
->scratch
.obj
);
672 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
673 if (ring
->scratch
.obj
== NULL
) {
674 DRM_ERROR("Failed to allocate seqno page\n");
679 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
683 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
687 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
688 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
689 if (ring
->scratch
.cpu_page
== NULL
) {
694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
695 ring
->name
, ring
->scratch
.gtt_offset
);
699 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
701 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
706 static int intel_ring_workarounds_emit(struct intel_engine_cs
*ring
,
707 struct intel_context
*ctx
)
710 struct drm_device
*dev
= ring
->dev
;
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
714 if (WARN_ON_ONCE(w
->count
== 0))
717 ring
->gpu_caches_dirty
= true;
718 ret
= intel_ring_flush_all_caches(ring
);
722 ret
= intel_ring_begin(ring
, (w
->count
* 2 + 2));
726 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
727 for (i
= 0; i
< w
->count
; i
++) {
728 intel_ring_emit(ring
, w
->reg
[i
].addr
);
729 intel_ring_emit(ring
, w
->reg
[i
].value
);
731 intel_ring_emit(ring
, MI_NOOP
);
733 intel_ring_advance(ring
);
735 ring
->gpu_caches_dirty
= true;
736 ret
= intel_ring_flush_all_caches(ring
);
740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
745 static int intel_rcs_ctx_init(struct intel_engine_cs
*ring
,
746 struct intel_context
*ctx
)
750 ret
= intel_ring_workarounds_emit(ring
, ctx
);
754 ret
= i915_gem_render_state_init(ring
);
756 DRM_ERROR("init render state: %d\n", ret
);
761 static int wa_add(struct drm_i915_private
*dev_priv
,
762 const u32 addr
, const u32 mask
, const u32 val
)
764 const u32 idx
= dev_priv
->workarounds
.count
;
766 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
769 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
770 dev_priv
->workarounds
.reg
[idx
].value
= val
;
771 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
773 dev_priv
->workarounds
.count
++;
778 #define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
784 #define WA_SET_BIT_MASKED(addr, mask) \
785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
787 #define WA_CLR_BIT_MASKED(addr, mask) \
788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
798 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
800 struct drm_device
*dev
= ring
->dev
;
801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 /* WaDisablePartialInstShootdown:bdw */
804 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
805 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
806 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
807 STALL_DOP_GATING_DISABLE
);
809 /* WaDisableDopClockGating:bdw */
810 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
811 DOP_CLOCK_GATING_DISABLE
);
813 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
814 GEN8_SAMPLER_POWER_BYPASS_DIS
);
816 /* Use Force Non-Coherent whenever executing a 3D context. This is a
817 * workaround for for a possible hang in the unlikely event a TLB
818 * invalidation occurs during a PSD flush.
820 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
821 /* WaForceEnableNonCoherent:bdw */
822 HDC_FORCE_NON_COHERENT
|
823 /* WaForceContextSaveRestoreNonCoherent:bdw */
824 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
825 /* WaHdcDisableFetchWhenMasked:bdw */
826 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
827 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
828 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
830 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
831 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
832 * polygons in the same 8x4 pixel/sample area to be processed without
833 * stalling waiting for the earlier ones to write to Hierarchical Z
836 * This optimization is off by default for Broadwell; turn it on.
838 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
840 /* Wa4x4STCOptimizationDisable:bdw */
841 WA_SET_BIT_MASKED(CACHE_MODE_1
,
842 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
852 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
853 GEN6_WIZ_HASHING_MASK
,
854 GEN6_WIZ_HASHING_16x4
);
856 /* WaProgramL3SqcReg1Default:bdw */
857 WA_WRITE(GEN8_L3SQCREG1
, BDW_WA_L3SQCREG1_DEFAULT
);
862 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
864 struct drm_device
*dev
= ring
->dev
;
865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
867 /* WaDisablePartialInstShootdown:chv */
868 /* WaDisableThreadStallDopClockGating:chv */
869 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
870 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
871 STALL_DOP_GATING_DISABLE
);
873 /* Use Force Non-Coherent whenever executing a 3D context. This is a
874 * workaround for a possible hang in the unlikely event a TLB
875 * invalidation occurs during a PSD flush.
877 /* WaForceEnableNonCoherent:chv */
878 /* WaHdcDisableFetchWhenMasked:chv */
879 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
880 HDC_FORCE_NON_COHERENT
|
881 HDC_DONOT_FETCH_MEM_WHEN_MASKED
);
883 /* According to the CACHE_MODE_0 default value documentation, some
884 * CHV platforms disable this optimization by default. Turn it on.
886 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
888 /* Wa4x4STCOptimizationDisable:chv */
889 WA_SET_BIT_MASKED(CACHE_MODE_1
,
890 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
892 /* Improve HiZ throughput on CHV. */
893 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
896 * BSpec recommends 8x4 when MSAA is used,
897 * however in practice 16x4 seems fastest.
899 * Note that PS/WM thread counts depend on the WIZ hashing
900 * disable bit, which we don't touch here, but it's good
901 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
903 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
904 GEN6_WIZ_HASHING_MASK
,
905 GEN6_WIZ_HASHING_16x4
);
907 if (INTEL_REVID(dev
) == SKL_REVID_C0
||
908 INTEL_REVID(dev
) == SKL_REVID_D0
)
909 /* WaBarrierPerformanceFixDisable:skl */
910 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
911 HDC_FENCE_DEST_SLM_DISABLE
|
912 HDC_BARRIER_PERFORMANCE_DISABLE
);
917 static int gen9_init_workarounds(struct intel_engine_cs
*ring
)
919 struct drm_device
*dev
= ring
->dev
;
920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
922 /* WaDisablePartialInstShootdown:skl,bxt */
923 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
924 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
926 /* Syncing dependencies between camera and graphics:skl,bxt */
927 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
928 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
930 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) == SKL_REVID_A0
||
931 INTEL_REVID(dev
) == SKL_REVID_B0
)) ||
932 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
)) {
933 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
935 GEN9_DG_MIRROR_FIX_ENABLE
);
938 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
) ||
939 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
)) {
940 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
941 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
942 GEN9_RHWO_OPTIMIZATION_DISABLE
);
943 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0
,
944 DISABLE_PIXEL_MASK_CAMMING
);
947 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) >= SKL_REVID_C0
) ||
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
950 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
951 GEN9_ENABLE_YV12_BUGFIX
);
954 /* Wa4x4STCOptimizationDisable:skl,bxt */
955 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
957 /* WaDisablePartialResolveInVc:skl,bxt */
958 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
);
960 /* WaCcsTlbPrefetchDisable:skl,bxt */
961 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
962 GEN9_CCS_TLB_PREFETCH_ENABLE
);
964 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
965 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) == SKL_REVID_C0
) ||
966 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
))
967 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
968 PIXEL_MASK_CAMMING_DISABLE
);
973 static int skl_tune_iz_hashing(struct intel_engine_cs
*ring
)
975 struct drm_device
*dev
= ring
->dev
;
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
977 u8 vals
[3] = { 0, 0, 0 };
980 for (i
= 0; i
< 3; i
++) {
984 * Only consider slices where one, and only one, subslice has 7
987 if (hweight8(dev_priv
->info
.subslice_7eu
[i
]) != 1)
991 * subslice_7eu[i] != 0 (because of the check above) and
992 * ss_max == 4 (maximum number of subslices possible per slice)
996 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1000 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1003 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1004 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1005 GEN9_IZ_HASHING_MASK(2) |
1006 GEN9_IZ_HASHING_MASK(1) |
1007 GEN9_IZ_HASHING_MASK(0),
1008 GEN9_IZ_HASHING(2, vals
[2]) |
1009 GEN9_IZ_HASHING(1, vals
[1]) |
1010 GEN9_IZ_HASHING(0, vals
[0]));
1016 static int skl_init_workarounds(struct intel_engine_cs
*ring
)
1018 struct drm_device
*dev
= ring
->dev
;
1019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1021 gen9_init_workarounds(ring
);
1023 /* WaDisablePowerCompilerClockGating:skl */
1024 if (INTEL_REVID(dev
) == SKL_REVID_B0
)
1025 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1026 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1028 if (INTEL_REVID(dev
) <= SKL_REVID_D0
) {
1030 *Use Force Non-Coherent whenever executing a 3D context. This
1031 * is a workaround for a possible hang in the unlikely event
1032 * a TLB invalidation occurs during a PSD flush.
1034 /* WaForceEnableNonCoherent:skl */
1035 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1036 HDC_FORCE_NON_COHERENT
);
1039 return skl_tune_iz_hashing(ring
);
1042 static int bxt_init_workarounds(struct intel_engine_cs
*ring
)
1044 struct drm_device
*dev
= ring
->dev
;
1045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1047 gen9_init_workarounds(ring
);
1049 /* WaDisableThreadStallDopClockGating:bxt */
1050 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1051 STALL_DOP_GATING_DISABLE
);
1053 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1054 if (INTEL_REVID(dev
) <= BXT_REVID_B0
) {
1056 GEN7_HALF_SLICE_CHICKEN1
,
1057 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1060 /* WaForceContextSaveRestoreNonCoherent:bxt */
1061 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1062 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
);
1067 int init_workarounds_ring(struct intel_engine_cs
*ring
)
1069 struct drm_device
*dev
= ring
->dev
;
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 WARN_ON(ring
->id
!= RCS
);
1074 dev_priv
->workarounds
.count
= 0;
1076 if (IS_BROADWELL(dev
))
1077 return bdw_init_workarounds(ring
);
1079 if (IS_CHERRYVIEW(dev
))
1080 return chv_init_workarounds(ring
);
1082 if (IS_SKYLAKE(dev
))
1083 return skl_init_workarounds(ring
);
1085 if (IS_BROXTON(dev
))
1086 return bxt_init_workarounds(ring
);
1091 static int init_render_ring(struct intel_engine_cs
*ring
)
1093 struct drm_device
*dev
= ring
->dev
;
1094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1095 int ret
= init_ring_common(ring
);
1099 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1100 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1101 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1103 /* We need to disable the AsyncFlip performance optimisations in order
1104 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1105 * programmed to '1' on all products.
1107 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1109 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 9)
1110 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1112 /* Required for the hardware to program scanline values for waiting */
1113 /* WaEnableFlushTlbInvalidationMode:snb */
1114 if (INTEL_INFO(dev
)->gen
== 6)
1115 I915_WRITE(GFX_MODE
,
1116 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1118 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1120 I915_WRITE(GFX_MODE_GEN7
,
1121 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1122 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1125 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1126 * "If this bit is set, STCunit will have LRA as replacement
1127 * policy. [...] This bit must be reset. LRA replacement
1128 * policy is not supported."
1130 I915_WRITE(CACHE_MODE_0
,
1131 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1134 if (INTEL_INFO(dev
)->gen
>= 6)
1135 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1137 if (HAS_L3_DPF(dev
))
1138 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1140 return init_workarounds_ring(ring
);
1143 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
1145 struct drm_device
*dev
= ring
->dev
;
1146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1148 if (dev_priv
->semaphore_obj
) {
1149 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1150 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1151 dev_priv
->semaphore_obj
= NULL
;
1154 intel_fini_pipe_control(ring
);
1157 static int gen8_rcs_signal(struct intel_engine_cs
*signaller
,
1158 unsigned int num_dwords
)
1160 #define MBOX_UPDATE_DWORDS 8
1161 struct drm_device
*dev
= signaller
->dev
;
1162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1163 struct intel_engine_cs
*waiter
;
1164 int i
, ret
, num_rings
;
1166 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1167 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1168 #undef MBOX_UPDATE_DWORDS
1170 ret
= intel_ring_begin(signaller
, num_dwords
);
1174 for_each_ring(waiter
, dev_priv
, i
) {
1176 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1177 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1180 seqno
= i915_gem_request_get_seqno(
1181 signaller
->outstanding_lazy_request
);
1182 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1183 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1184 PIPE_CONTROL_QW_WRITE
|
1185 PIPE_CONTROL_FLUSH_ENABLE
);
1186 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1187 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1188 intel_ring_emit(signaller
, seqno
);
1189 intel_ring_emit(signaller
, 0);
1190 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1191 MI_SEMAPHORE_TARGET(waiter
->id
));
1192 intel_ring_emit(signaller
, 0);
1198 static int gen8_xcs_signal(struct intel_engine_cs
*signaller
,
1199 unsigned int num_dwords
)
1201 #define MBOX_UPDATE_DWORDS 6
1202 struct drm_device
*dev
= signaller
->dev
;
1203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1204 struct intel_engine_cs
*waiter
;
1205 int i
, ret
, num_rings
;
1207 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1208 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1209 #undef MBOX_UPDATE_DWORDS
1211 ret
= intel_ring_begin(signaller
, num_dwords
);
1215 for_each_ring(waiter
, dev_priv
, i
) {
1217 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1218 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1221 seqno
= i915_gem_request_get_seqno(
1222 signaller
->outstanding_lazy_request
);
1223 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1224 MI_FLUSH_DW_OP_STOREDW
);
1225 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1226 MI_FLUSH_DW_USE_GTT
);
1227 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1228 intel_ring_emit(signaller
, seqno
);
1229 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1230 MI_SEMAPHORE_TARGET(waiter
->id
));
1231 intel_ring_emit(signaller
, 0);
1237 static int gen6_signal(struct intel_engine_cs
*signaller
,
1238 unsigned int num_dwords
)
1240 struct drm_device
*dev
= signaller
->dev
;
1241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1242 struct intel_engine_cs
*useless
;
1243 int i
, ret
, num_rings
;
1245 #define MBOX_UPDATE_DWORDS 3
1246 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1247 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1248 #undef MBOX_UPDATE_DWORDS
1250 ret
= intel_ring_begin(signaller
, num_dwords
);
1254 for_each_ring(useless
, dev_priv
, i
) {
1255 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1256 if (mbox_reg
!= GEN6_NOSYNC
) {
1257 u32 seqno
= i915_gem_request_get_seqno(
1258 signaller
->outstanding_lazy_request
);
1259 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1260 intel_ring_emit(signaller
, mbox_reg
);
1261 intel_ring_emit(signaller
, seqno
);
1265 /* If num_dwords was rounded, make sure the tail pointer is correct */
1266 if (num_rings
% 2 == 0)
1267 intel_ring_emit(signaller
, MI_NOOP
);
1273 * gen6_add_request - Update the semaphore mailbox registers
1275 * @ring - ring that is adding a request
1276 * @seqno - return seqno stuck into the ring
1278 * Update the mailbox registers in the *other* rings with the current seqno.
1279 * This acts like a signal in the canonical semaphore.
1282 gen6_add_request(struct intel_engine_cs
*ring
)
1286 if (ring
->semaphore
.signal
)
1287 ret
= ring
->semaphore
.signal(ring
, 4);
1289 ret
= intel_ring_begin(ring
, 4);
1294 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1295 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1296 intel_ring_emit(ring
,
1297 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1298 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1299 __intel_ring_advance(ring
);
1304 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1308 return dev_priv
->last_seqno
< seqno
;
1312 * intel_ring_sync - sync the waiter to the signaller on seqno
1314 * @waiter - ring that is waiting
1315 * @signaller - ring which has, or will signal
1316 * @seqno - seqno which the waiter will block on
1320 gen8_ring_sync(struct intel_engine_cs
*waiter
,
1321 struct intel_engine_cs
*signaller
,
1324 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1327 ret
= intel_ring_begin(waiter
, 4);
1331 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1332 MI_SEMAPHORE_GLOBAL_GTT
|
1334 MI_SEMAPHORE_SAD_GTE_SDD
);
1335 intel_ring_emit(waiter
, seqno
);
1336 intel_ring_emit(waiter
,
1337 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1338 intel_ring_emit(waiter
,
1339 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1340 intel_ring_advance(waiter
);
1345 gen6_ring_sync(struct intel_engine_cs
*waiter
,
1346 struct intel_engine_cs
*signaller
,
1349 u32 dw1
= MI_SEMAPHORE_MBOX
|
1350 MI_SEMAPHORE_COMPARE
|
1351 MI_SEMAPHORE_REGISTER
;
1352 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1355 /* Throughout all of the GEM code, seqno passed implies our current
1356 * seqno is >= the last seqno executed. However for hardware the
1357 * comparison is strictly greater than.
1361 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1363 ret
= intel_ring_begin(waiter
, 4);
1367 /* If seqno wrap happened, omit the wait with no-ops */
1368 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1369 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1370 intel_ring_emit(waiter
, seqno
);
1371 intel_ring_emit(waiter
, 0);
1372 intel_ring_emit(waiter
, MI_NOOP
);
1374 intel_ring_emit(waiter
, MI_NOOP
);
1375 intel_ring_emit(waiter
, MI_NOOP
);
1376 intel_ring_emit(waiter
, MI_NOOP
);
1377 intel_ring_emit(waiter
, MI_NOOP
);
1379 intel_ring_advance(waiter
);
1384 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1386 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1387 PIPE_CONTROL_DEPTH_STALL); \
1388 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1389 intel_ring_emit(ring__, 0); \
1390 intel_ring_emit(ring__, 0); \
1394 pc_render_add_request(struct intel_engine_cs
*ring
)
1396 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1399 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1400 * incoherent with writes to memory, i.e. completely fubar,
1401 * so we need to use PIPE_NOTIFY instead.
1403 * However, we also need to workaround the qword write
1404 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1405 * memory before requesting an interrupt.
1407 ret
= intel_ring_begin(ring
, 32);
1411 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1412 PIPE_CONTROL_WRITE_FLUSH
|
1413 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1414 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1415 intel_ring_emit(ring
,
1416 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1417 intel_ring_emit(ring
, 0);
1418 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1419 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1420 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1421 scratch_addr
+= 2 * CACHELINE_BYTES
;
1422 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1423 scratch_addr
+= 2 * CACHELINE_BYTES
;
1424 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1425 scratch_addr
+= 2 * CACHELINE_BYTES
;
1426 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1427 scratch_addr
+= 2 * CACHELINE_BYTES
;
1428 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1430 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1431 PIPE_CONTROL_WRITE_FLUSH
|
1432 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1433 PIPE_CONTROL_NOTIFY
);
1434 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1435 intel_ring_emit(ring
,
1436 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1437 intel_ring_emit(ring
, 0);
1438 __intel_ring_advance(ring
);
1444 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1446 /* Workaround to force correct ordering between irq and seqno writes on
1447 * ivb (and maybe also on snb) by reading from a CS register (like
1448 * ACTHD) before reading the status page. */
1449 if (!lazy_coherency
) {
1450 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1451 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1454 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1458 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1460 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1464 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1466 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1470 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1472 return ring
->scratch
.cpu_page
[0];
1476 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1478 ring
->scratch
.cpu_page
[0] = seqno
;
1482 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1484 struct drm_device
*dev
= ring
->dev
;
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 unsigned long flags
;
1488 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1491 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1492 if (ring
->irq_refcount
++ == 0)
1493 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1494 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1500 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1502 struct drm_device
*dev
= ring
->dev
;
1503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1504 unsigned long flags
;
1506 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1507 if (--ring
->irq_refcount
== 0)
1508 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1509 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1513 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1515 struct drm_device
*dev
= ring
->dev
;
1516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 unsigned long flags
;
1519 if (!intel_irqs_enabled(dev_priv
))
1522 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1523 if (ring
->irq_refcount
++ == 0) {
1524 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1525 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1528 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1534 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1536 struct drm_device
*dev
= ring
->dev
;
1537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1538 unsigned long flags
;
1540 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1541 if (--ring
->irq_refcount
== 0) {
1542 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1543 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1546 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1550 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1552 struct drm_device
*dev
= ring
->dev
;
1553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1554 unsigned long flags
;
1556 if (!intel_irqs_enabled(dev_priv
))
1559 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1560 if (ring
->irq_refcount
++ == 0) {
1561 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1562 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1563 POSTING_READ16(IMR
);
1565 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1571 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1573 struct drm_device
*dev
= ring
->dev
;
1574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1575 unsigned long flags
;
1577 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1578 if (--ring
->irq_refcount
== 0) {
1579 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1580 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1581 POSTING_READ16(IMR
);
1583 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1587 bsd_ring_flush(struct intel_engine_cs
*ring
,
1588 u32 invalidate_domains
,
1593 ret
= intel_ring_begin(ring
, 2);
1597 intel_ring_emit(ring
, MI_FLUSH
);
1598 intel_ring_emit(ring
, MI_NOOP
);
1599 intel_ring_advance(ring
);
1604 i9xx_add_request(struct intel_engine_cs
*ring
)
1608 ret
= intel_ring_begin(ring
, 4);
1612 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1613 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1614 intel_ring_emit(ring
,
1615 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1616 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1617 __intel_ring_advance(ring
);
1623 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1625 struct drm_device
*dev
= ring
->dev
;
1626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1627 unsigned long flags
;
1629 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1632 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1633 if (ring
->irq_refcount
++ == 0) {
1634 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1635 I915_WRITE_IMR(ring
,
1636 ~(ring
->irq_enable_mask
|
1637 GT_PARITY_ERROR(dev
)));
1639 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1640 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1642 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1648 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1650 struct drm_device
*dev
= ring
->dev
;
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1652 unsigned long flags
;
1654 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1655 if (--ring
->irq_refcount
== 0) {
1656 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1657 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1659 I915_WRITE_IMR(ring
, ~0);
1660 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1662 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1666 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1668 struct drm_device
*dev
= ring
->dev
;
1669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1670 unsigned long flags
;
1672 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1675 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1676 if (ring
->irq_refcount
++ == 0) {
1677 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1678 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1680 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1686 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1688 struct drm_device
*dev
= ring
->dev
;
1689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 unsigned long flags
;
1692 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1693 if (--ring
->irq_refcount
== 0) {
1694 I915_WRITE_IMR(ring
, ~0);
1695 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1697 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1701 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1703 struct drm_device
*dev
= ring
->dev
;
1704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1705 unsigned long flags
;
1707 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1710 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1711 if (ring
->irq_refcount
++ == 0) {
1712 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1713 I915_WRITE_IMR(ring
,
1714 ~(ring
->irq_enable_mask
|
1715 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1717 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1719 POSTING_READ(RING_IMR(ring
->mmio_base
));
1721 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1727 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1729 struct drm_device
*dev
= ring
->dev
;
1730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1731 unsigned long flags
;
1733 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1734 if (--ring
->irq_refcount
== 0) {
1735 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1736 I915_WRITE_IMR(ring
,
1737 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1739 I915_WRITE_IMR(ring
, ~0);
1741 POSTING_READ(RING_IMR(ring
->mmio_base
));
1743 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1747 i965_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1748 u64 offset
, u32 length
,
1749 unsigned dispatch_flags
)
1753 ret
= intel_ring_begin(ring
, 2);
1757 intel_ring_emit(ring
,
1758 MI_BATCH_BUFFER_START
|
1760 (dispatch_flags
& I915_DISPATCH_SECURE
?
1761 0 : MI_BATCH_NON_SECURE_I965
));
1762 intel_ring_emit(ring
, offset
);
1763 intel_ring_advance(ring
);
1768 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1769 #define I830_BATCH_LIMIT (256*1024)
1770 #define I830_TLB_ENTRIES (2)
1771 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1773 i830_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1774 u64 offset
, u32 len
,
1775 unsigned dispatch_flags
)
1777 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1780 ret
= intel_ring_begin(ring
, 6);
1784 /* Evict the invalid PTE TLBs */
1785 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1786 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1787 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1788 intel_ring_emit(ring
, cs_offset
);
1789 intel_ring_emit(ring
, 0xdeadbeef);
1790 intel_ring_emit(ring
, MI_NOOP
);
1791 intel_ring_advance(ring
);
1793 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1794 if (len
> I830_BATCH_LIMIT
)
1797 ret
= intel_ring_begin(ring
, 6 + 2);
1801 /* Blit the batch (which has now all relocs applied) to the
1802 * stable batch scratch bo area (so that the CS never
1803 * stumbles over its tlb invalidation bug) ...
1805 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1806 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1807 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1808 intel_ring_emit(ring
, cs_offset
);
1809 intel_ring_emit(ring
, 4096);
1810 intel_ring_emit(ring
, offset
);
1812 intel_ring_emit(ring
, MI_FLUSH
);
1813 intel_ring_emit(ring
, MI_NOOP
);
1814 intel_ring_advance(ring
);
1816 /* ... and execute it. */
1820 ret
= intel_ring_begin(ring
, 4);
1824 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1825 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1826 0 : MI_BATCH_NON_SECURE
));
1827 intel_ring_emit(ring
, offset
+ len
- 8);
1828 intel_ring_emit(ring
, MI_NOOP
);
1829 intel_ring_advance(ring
);
1835 i915_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1836 u64 offset
, u32 len
,
1837 unsigned dispatch_flags
)
1841 ret
= intel_ring_begin(ring
, 2);
1845 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1846 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1847 0 : MI_BATCH_NON_SECURE
));
1848 intel_ring_advance(ring
);
1853 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1855 struct drm_i915_gem_object
*obj
;
1857 obj
= ring
->status_page
.obj
;
1861 kunmap(sg_page(obj
->pages
->sgl
));
1862 i915_gem_object_ggtt_unpin(obj
);
1863 drm_gem_object_unreference(&obj
->base
);
1864 ring
->status_page
.obj
= NULL
;
1867 static int init_status_page(struct intel_engine_cs
*ring
)
1869 struct drm_i915_gem_object
*obj
;
1871 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1875 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1877 DRM_ERROR("Failed to allocate status page\n");
1881 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1886 if (!HAS_LLC(ring
->dev
))
1887 /* On g33, we cannot place HWS above 256MiB, so
1888 * restrict its pinning to the low mappable arena.
1889 * Though this restriction is not documented for
1890 * gen4, gen5, or byt, they also behave similarly
1891 * and hang if the HWS is placed at the top of the
1892 * GTT. To generalise, it appears that all !llc
1893 * platforms have issues with us placing the HWS
1894 * above the mappable region (even though we never
1897 flags
|= PIN_MAPPABLE
;
1898 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1901 drm_gem_object_unreference(&obj
->base
);
1905 ring
->status_page
.obj
= obj
;
1908 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1909 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1910 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1912 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1913 ring
->name
, ring
->status_page
.gfx_addr
);
1918 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1920 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1922 if (!dev_priv
->status_page_dmah
) {
1923 dev_priv
->status_page_dmah
=
1924 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1925 if (!dev_priv
->status_page_dmah
)
1929 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1930 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1935 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1937 iounmap(ringbuf
->virtual_start
);
1938 ringbuf
->virtual_start
= NULL
;
1939 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1942 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
1943 struct intel_ringbuffer
*ringbuf
)
1945 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1946 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
1949 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1953 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1955 i915_gem_object_ggtt_unpin(obj
);
1959 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
1960 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
1961 if (ringbuf
->virtual_start
== NULL
) {
1962 i915_gem_object_ggtt_unpin(obj
);
1969 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1971 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1972 ringbuf
->obj
= NULL
;
1975 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1976 struct intel_ringbuffer
*ringbuf
)
1978 struct drm_i915_gem_object
*obj
;
1982 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
1984 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
1988 /* mark ring buffers as read-only from GPU side by default */
1996 static int intel_init_ring_buffer(struct drm_device
*dev
,
1997 struct intel_engine_cs
*ring
)
1999 struct intel_ringbuffer
*ringbuf
;
2002 WARN_ON(ring
->buffer
);
2004 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2007 ring
->buffer
= ringbuf
;
2010 INIT_LIST_HEAD(&ring
->active_list
);
2011 INIT_LIST_HEAD(&ring
->request_list
);
2012 INIT_LIST_HEAD(&ring
->execlist_queue
);
2013 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2014 ringbuf
->size
= 32 * PAGE_SIZE
;
2015 ringbuf
->ring
= ring
;
2016 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
2018 init_waitqueue_head(&ring
->irq_queue
);
2020 if (I915_NEED_GFX_HWS(dev
)) {
2021 ret
= init_status_page(ring
);
2025 BUG_ON(ring
->id
!= RCS
);
2026 ret
= init_phys_status_page(ring
);
2031 WARN_ON(ringbuf
->obj
);
2033 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2035 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2040 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2042 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2044 intel_destroy_ringbuffer_obj(ringbuf
);
2048 /* Workaround an erratum on the i830 which causes a hang if
2049 * the TAIL pointer points to within the last 2 cachelines
2052 ringbuf
->effective_size
= ringbuf
->size
;
2053 if (IS_I830(dev
) || IS_845G(dev
))
2054 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
2056 ret
= i915_cmd_parser_init_ring(ring
);
2064 ring
->buffer
= NULL
;
2068 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
2070 struct drm_i915_private
*dev_priv
;
2071 struct intel_ringbuffer
*ringbuf
;
2073 if (!intel_ring_initialized(ring
))
2076 dev_priv
= to_i915(ring
->dev
);
2077 ringbuf
= ring
->buffer
;
2079 intel_stop_ring_buffer(ring
);
2080 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
2082 intel_unpin_ringbuffer_obj(ringbuf
);
2083 intel_destroy_ringbuffer_obj(ringbuf
);
2084 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2087 ring
->cleanup(ring
);
2089 cleanup_status_page(ring
);
2091 i915_cmd_parser_fini_ring(ring
);
2092 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2095 ring
->buffer
= NULL
;
2098 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
2100 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2101 struct drm_i915_gem_request
*request
;
2104 if (intel_ring_space(ringbuf
) >= n
)
2107 list_for_each_entry(request
, &ring
->request_list
, list
) {
2108 new_space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
2114 if (WARN_ON(&request
->list
== &ring
->request_list
))
2117 ret
= i915_wait_request(request
);
2121 i915_gem_retire_requests_ring(ring
);
2123 WARN_ON(intel_ring_space(ringbuf
) < new_space
);
2128 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
2130 uint32_t __iomem
*virt
;
2131 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2132 int rem
= ringbuf
->size
- ringbuf
->tail
;
2134 if (ringbuf
->space
< rem
) {
2135 int ret
= ring_wait_for_space(ring
, rem
);
2140 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2143 iowrite32(MI_NOOP
, virt
++);
2146 intel_ring_update_space(ringbuf
);
2151 int intel_ring_idle(struct intel_engine_cs
*ring
)
2153 struct drm_i915_gem_request
*req
;
2156 /* We need to add any requests required to flush the objects and ring */
2157 if (ring
->outstanding_lazy_request
) {
2158 ret
= i915_add_request(ring
);
2163 /* Wait upon the last request to be completed */
2164 if (list_empty(&ring
->request_list
))
2167 req
= list_entry(ring
->request_list
.prev
,
2168 struct drm_i915_gem_request
,
2171 return i915_wait_request(req
);
2174 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2176 request
->ringbuf
= request
->ring
->buffer
;
2180 static int __intel_ring_prepare(struct intel_engine_cs
*ring
,
2183 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2186 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2187 ret
= intel_wrap_ring_buffer(ring
);
2192 if (unlikely(ringbuf
->space
< bytes
)) {
2193 ret
= ring_wait_for_space(ring
, bytes
);
2201 int intel_ring_begin(struct intel_engine_cs
*ring
,
2204 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2207 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2208 dev_priv
->mm
.interruptible
);
2212 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2216 /* Preallocate the olr before touching the ring */
2217 ret
= i915_gem_request_alloc(ring
, ring
->default_context
);
2221 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2225 /* Align the ring tail to a cacheline boundary */
2226 int intel_ring_cacheline_align(struct intel_engine_cs
*ring
)
2228 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2231 if (num_dwords
== 0)
2234 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2235 ret
= intel_ring_begin(ring
, num_dwords
);
2239 while (num_dwords
--)
2240 intel_ring_emit(ring
, MI_NOOP
);
2242 intel_ring_advance(ring
);
2247 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2249 struct drm_device
*dev
= ring
->dev
;
2250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2252 BUG_ON(ring
->outstanding_lazy_request
);
2254 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2255 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2256 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2258 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2261 ring
->set_seqno(ring
, seqno
);
2262 ring
->hangcheck
.seqno
= seqno
;
2265 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2268 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2270 /* Every tail move must follow the sequence below */
2272 /* Disable notification that the ring is IDLE. The GT
2273 * will then assume that it is busy and bring it out of rc6.
2275 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2276 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2278 /* Clear the context id. Here be magic! */
2279 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2281 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2282 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2283 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2285 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2287 /* Now that the ring is fully powered up, update the tail */
2288 I915_WRITE_TAIL(ring
, value
);
2289 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2291 /* Let the ring send IDLE messages to the GT again,
2292 * and so let it sleep to conserve power when idle.
2294 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2295 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2298 static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring
,
2299 u32 invalidate
, u32 flush
)
2304 ret
= intel_ring_begin(ring
, 4);
2309 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2312 /* We always require a command barrier so that subsequent
2313 * commands, such as breadcrumb interrupts, are strictly ordered
2314 * wrt the contents of the write cache being flushed to memory
2315 * (and thus being coherent from the CPU).
2317 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2320 * Bspec vol 1c.5 - video engine command streamer:
2321 * "If ENABLED, all TLBs will be invalidated once the flush
2322 * operation is complete. This bit is only valid when the
2323 * Post-Sync Operation field is a value of 1h or 3h."
2325 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2326 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2328 intel_ring_emit(ring
, cmd
);
2329 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2330 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2331 intel_ring_emit(ring
, 0); /* upper addr */
2332 intel_ring_emit(ring
, 0); /* value */
2334 intel_ring_emit(ring
, 0);
2335 intel_ring_emit(ring
, MI_NOOP
);
2337 intel_ring_advance(ring
);
2342 gen8_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2343 u64 offset
, u32 len
,
2344 unsigned dispatch_flags
)
2346 bool ppgtt
= USES_PPGTT(ring
->dev
) &&
2347 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2350 ret
= intel_ring_begin(ring
, 4);
2354 /* FIXME(BDW): Address space and security selectors. */
2355 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2356 intel_ring_emit(ring
, lower_32_bits(offset
));
2357 intel_ring_emit(ring
, upper_32_bits(offset
));
2358 intel_ring_emit(ring
, MI_NOOP
);
2359 intel_ring_advance(ring
);
2365 hsw_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2366 u64 offset
, u32 len
,
2367 unsigned dispatch_flags
)
2371 ret
= intel_ring_begin(ring
, 2);
2375 intel_ring_emit(ring
,
2376 MI_BATCH_BUFFER_START
|
2377 (dispatch_flags
& I915_DISPATCH_SECURE
?
2378 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
));
2379 /* bit0-7 is the length on GEN6+ */
2380 intel_ring_emit(ring
, offset
);
2381 intel_ring_advance(ring
);
2387 gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2388 u64 offset
, u32 len
,
2389 unsigned dispatch_flags
)
2393 ret
= intel_ring_begin(ring
, 2);
2397 intel_ring_emit(ring
,
2398 MI_BATCH_BUFFER_START
|
2399 (dispatch_flags
& I915_DISPATCH_SECURE
?
2400 0 : MI_BATCH_NON_SECURE_I965
));
2401 /* bit0-7 is the length on GEN6+ */
2402 intel_ring_emit(ring
, offset
);
2403 intel_ring_advance(ring
);
2408 /* Blitter support (SandyBridge+) */
2410 static int gen6_ring_flush(struct intel_engine_cs
*ring
,
2411 u32 invalidate
, u32 flush
)
2413 struct drm_device
*dev
= ring
->dev
;
2417 ret
= intel_ring_begin(ring
, 4);
2422 if (INTEL_INFO(dev
)->gen
>= 8)
2425 /* We always require a command barrier so that subsequent
2426 * commands, such as breadcrumb interrupts, are strictly ordered
2427 * wrt the contents of the write cache being flushed to memory
2428 * (and thus being coherent from the CPU).
2430 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2433 * Bspec vol 1c.3 - blitter engine command streamer:
2434 * "If ENABLED, all TLBs will be invalidated once the flush
2435 * operation is complete. This bit is only valid when the
2436 * Post-Sync Operation field is a value of 1h or 3h."
2438 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2439 cmd
|= MI_INVALIDATE_TLB
;
2440 intel_ring_emit(ring
, cmd
);
2441 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2442 if (INTEL_INFO(dev
)->gen
>= 8) {
2443 intel_ring_emit(ring
, 0); /* upper addr */
2444 intel_ring_emit(ring
, 0); /* value */
2446 intel_ring_emit(ring
, 0);
2447 intel_ring_emit(ring
, MI_NOOP
);
2449 intel_ring_advance(ring
);
2454 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2458 struct drm_i915_gem_object
*obj
;
2461 ring
->name
= "render ring";
2463 ring
->mmio_base
= RENDER_RING_BASE
;
2465 if (INTEL_INFO(dev
)->gen
>= 8) {
2466 if (i915_semaphore_is_enabled(dev
)) {
2467 obj
= i915_gem_alloc_object(dev
, 4096);
2469 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2470 i915
.semaphores
= 0;
2472 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2473 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2475 drm_gem_object_unreference(&obj
->base
);
2476 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2477 i915
.semaphores
= 0;
2479 dev_priv
->semaphore_obj
= obj
;
2483 ring
->init_context
= intel_rcs_ctx_init
;
2484 ring
->add_request
= gen6_add_request
;
2485 ring
->flush
= gen8_render_ring_flush
;
2486 ring
->irq_get
= gen8_ring_get_irq
;
2487 ring
->irq_put
= gen8_ring_put_irq
;
2488 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2489 ring
->get_seqno
= gen6_ring_get_seqno
;
2490 ring
->set_seqno
= ring_set_seqno
;
2491 if (i915_semaphore_is_enabled(dev
)) {
2492 WARN_ON(!dev_priv
->semaphore_obj
);
2493 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2494 ring
->semaphore
.signal
= gen8_rcs_signal
;
2495 GEN8_RING_SEMAPHORE_INIT
;
2497 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2498 ring
->add_request
= gen6_add_request
;
2499 ring
->flush
= gen7_render_ring_flush
;
2500 if (INTEL_INFO(dev
)->gen
== 6)
2501 ring
->flush
= gen6_render_ring_flush
;
2502 ring
->irq_get
= gen6_ring_get_irq
;
2503 ring
->irq_put
= gen6_ring_put_irq
;
2504 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2505 ring
->get_seqno
= gen6_ring_get_seqno
;
2506 ring
->set_seqno
= ring_set_seqno
;
2507 if (i915_semaphore_is_enabled(dev
)) {
2508 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2509 ring
->semaphore
.signal
= gen6_signal
;
2511 * The current semaphore is only applied on pre-gen8
2512 * platform. And there is no VCS2 ring on the pre-gen8
2513 * platform. So the semaphore between RCS and VCS2 is
2514 * initialized as INVALID. Gen8 will initialize the
2515 * sema between VCS2 and RCS later.
2517 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2518 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2519 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2520 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2521 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2522 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2523 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2524 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2525 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2526 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2528 } else if (IS_GEN5(dev
)) {
2529 ring
->add_request
= pc_render_add_request
;
2530 ring
->flush
= gen4_render_ring_flush
;
2531 ring
->get_seqno
= pc_render_get_seqno
;
2532 ring
->set_seqno
= pc_render_set_seqno
;
2533 ring
->irq_get
= gen5_ring_get_irq
;
2534 ring
->irq_put
= gen5_ring_put_irq
;
2535 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2536 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2538 ring
->add_request
= i9xx_add_request
;
2539 if (INTEL_INFO(dev
)->gen
< 4)
2540 ring
->flush
= gen2_render_ring_flush
;
2542 ring
->flush
= gen4_render_ring_flush
;
2543 ring
->get_seqno
= ring_get_seqno
;
2544 ring
->set_seqno
= ring_set_seqno
;
2546 ring
->irq_get
= i8xx_ring_get_irq
;
2547 ring
->irq_put
= i8xx_ring_put_irq
;
2549 ring
->irq_get
= i9xx_ring_get_irq
;
2550 ring
->irq_put
= i9xx_ring_put_irq
;
2552 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2554 ring
->write_tail
= ring_write_tail
;
2556 if (IS_HASWELL(dev
))
2557 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2558 else if (IS_GEN8(dev
))
2559 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2560 else if (INTEL_INFO(dev
)->gen
>= 6)
2561 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2562 else if (INTEL_INFO(dev
)->gen
>= 4)
2563 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2564 else if (IS_I830(dev
) || IS_845G(dev
))
2565 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2567 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2568 ring
->init_hw
= init_render_ring
;
2569 ring
->cleanup
= render_ring_cleanup
;
2571 /* Workaround batchbuffer to combat CS tlb bug. */
2572 if (HAS_BROKEN_CS_TLB(dev
)) {
2573 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2575 DRM_ERROR("Failed to allocate batch bo\n");
2579 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2581 drm_gem_object_unreference(&obj
->base
);
2582 DRM_ERROR("Failed to ping batch bo\n");
2586 ring
->scratch
.obj
= obj
;
2587 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2590 ret
= intel_init_ring_buffer(dev
, ring
);
2594 if (INTEL_INFO(dev
)->gen
>= 5) {
2595 ret
= intel_init_pipe_control(ring
);
2603 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2606 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2608 ring
->name
= "bsd ring";
2611 ring
->write_tail
= ring_write_tail
;
2612 if (INTEL_INFO(dev
)->gen
>= 6) {
2613 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2614 /* gen6 bsd needs a special wa for tail updates */
2616 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2617 ring
->flush
= gen6_bsd_ring_flush
;
2618 ring
->add_request
= gen6_add_request
;
2619 ring
->get_seqno
= gen6_ring_get_seqno
;
2620 ring
->set_seqno
= ring_set_seqno
;
2621 if (INTEL_INFO(dev
)->gen
>= 8) {
2622 ring
->irq_enable_mask
=
2623 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2624 ring
->irq_get
= gen8_ring_get_irq
;
2625 ring
->irq_put
= gen8_ring_put_irq
;
2626 ring
->dispatch_execbuffer
=
2627 gen8_ring_dispatch_execbuffer
;
2628 if (i915_semaphore_is_enabled(dev
)) {
2629 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2630 ring
->semaphore
.signal
= gen8_xcs_signal
;
2631 GEN8_RING_SEMAPHORE_INIT
;
2634 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2635 ring
->irq_get
= gen6_ring_get_irq
;
2636 ring
->irq_put
= gen6_ring_put_irq
;
2637 ring
->dispatch_execbuffer
=
2638 gen6_ring_dispatch_execbuffer
;
2639 if (i915_semaphore_is_enabled(dev
)) {
2640 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2641 ring
->semaphore
.signal
= gen6_signal
;
2642 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2643 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2644 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2645 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2646 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2647 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2648 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2649 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2650 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2651 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2655 ring
->mmio_base
= BSD_RING_BASE
;
2656 ring
->flush
= bsd_ring_flush
;
2657 ring
->add_request
= i9xx_add_request
;
2658 ring
->get_seqno
= ring_get_seqno
;
2659 ring
->set_seqno
= ring_set_seqno
;
2661 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2662 ring
->irq_get
= gen5_ring_get_irq
;
2663 ring
->irq_put
= gen5_ring_put_irq
;
2665 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2666 ring
->irq_get
= i9xx_ring_get_irq
;
2667 ring
->irq_put
= i9xx_ring_put_irq
;
2669 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2671 ring
->init_hw
= init_ring_common
;
2673 return intel_init_ring_buffer(dev
, ring
);
2677 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2679 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2682 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2684 ring
->name
= "bsd2 ring";
2687 ring
->write_tail
= ring_write_tail
;
2688 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2689 ring
->flush
= gen6_bsd_ring_flush
;
2690 ring
->add_request
= gen6_add_request
;
2691 ring
->get_seqno
= gen6_ring_get_seqno
;
2692 ring
->set_seqno
= ring_set_seqno
;
2693 ring
->irq_enable_mask
=
2694 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2695 ring
->irq_get
= gen8_ring_get_irq
;
2696 ring
->irq_put
= gen8_ring_put_irq
;
2697 ring
->dispatch_execbuffer
=
2698 gen8_ring_dispatch_execbuffer
;
2699 if (i915_semaphore_is_enabled(dev
)) {
2700 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2701 ring
->semaphore
.signal
= gen8_xcs_signal
;
2702 GEN8_RING_SEMAPHORE_INIT
;
2704 ring
->init_hw
= init_ring_common
;
2706 return intel_init_ring_buffer(dev
, ring
);
2709 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2712 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2714 ring
->name
= "blitter ring";
2717 ring
->mmio_base
= BLT_RING_BASE
;
2718 ring
->write_tail
= ring_write_tail
;
2719 ring
->flush
= gen6_ring_flush
;
2720 ring
->add_request
= gen6_add_request
;
2721 ring
->get_seqno
= gen6_ring_get_seqno
;
2722 ring
->set_seqno
= ring_set_seqno
;
2723 if (INTEL_INFO(dev
)->gen
>= 8) {
2724 ring
->irq_enable_mask
=
2725 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2726 ring
->irq_get
= gen8_ring_get_irq
;
2727 ring
->irq_put
= gen8_ring_put_irq
;
2728 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2729 if (i915_semaphore_is_enabled(dev
)) {
2730 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2731 ring
->semaphore
.signal
= gen8_xcs_signal
;
2732 GEN8_RING_SEMAPHORE_INIT
;
2735 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2736 ring
->irq_get
= gen6_ring_get_irq
;
2737 ring
->irq_put
= gen6_ring_put_irq
;
2738 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2739 if (i915_semaphore_is_enabled(dev
)) {
2740 ring
->semaphore
.signal
= gen6_signal
;
2741 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2743 * The current semaphore is only applied on pre-gen8
2744 * platform. And there is no VCS2 ring on the pre-gen8
2745 * platform. So the semaphore between BCS and VCS2 is
2746 * initialized as INVALID. Gen8 will initialize the
2747 * sema between BCS and VCS2 later.
2749 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2750 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2751 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2752 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2753 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2754 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2755 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2756 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2757 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2758 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2761 ring
->init_hw
= init_ring_common
;
2763 return intel_init_ring_buffer(dev
, ring
);
2766 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2769 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2771 ring
->name
= "video enhancement ring";
2774 ring
->mmio_base
= VEBOX_RING_BASE
;
2775 ring
->write_tail
= ring_write_tail
;
2776 ring
->flush
= gen6_ring_flush
;
2777 ring
->add_request
= gen6_add_request
;
2778 ring
->get_seqno
= gen6_ring_get_seqno
;
2779 ring
->set_seqno
= ring_set_seqno
;
2781 if (INTEL_INFO(dev
)->gen
>= 8) {
2782 ring
->irq_enable_mask
=
2783 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2784 ring
->irq_get
= gen8_ring_get_irq
;
2785 ring
->irq_put
= gen8_ring_put_irq
;
2786 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2787 if (i915_semaphore_is_enabled(dev
)) {
2788 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2789 ring
->semaphore
.signal
= gen8_xcs_signal
;
2790 GEN8_RING_SEMAPHORE_INIT
;
2793 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2794 ring
->irq_get
= hsw_vebox_get_irq
;
2795 ring
->irq_put
= hsw_vebox_put_irq
;
2796 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2797 if (i915_semaphore_is_enabled(dev
)) {
2798 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2799 ring
->semaphore
.signal
= gen6_signal
;
2800 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2801 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2802 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2803 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2804 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2805 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2806 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2807 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2808 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2809 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2812 ring
->init_hw
= init_ring_common
;
2814 return intel_init_ring_buffer(dev
, ring
);
2818 intel_ring_flush_all_caches(struct intel_engine_cs
*ring
)
2822 if (!ring
->gpu_caches_dirty
)
2825 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2829 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2831 ring
->gpu_caches_dirty
= false;
2836 intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
)
2838 uint32_t flush_domains
;
2842 if (ring
->gpu_caches_dirty
)
2843 flush_domains
= I915_GEM_GPU_DOMAINS
;
2845 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2849 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2851 ring
->gpu_caches_dirty
= false;
2856 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2860 if (!intel_ring_initialized(ring
))
2863 ret
= intel_ring_idle(ring
);
2864 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2865 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",