2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head
, int tail
, int size
)
44 int space
= head
- tail
;
47 return space
- I915_RING_FREE_SPACE
;
50 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
52 if (ringbuf
->last_retired_head
!= -1) {
53 ringbuf
->head
= ringbuf
->last_retired_head
;
54 ringbuf
->last_retired_head
= -1;
57 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
58 ringbuf
->tail
, ringbuf
->size
);
61 bool intel_engine_stopped(struct intel_engine_cs
*engine
)
63 struct drm_i915_private
*dev_priv
= engine
->i915
;
64 return dev_priv
->gpu_error
.stop_rings
& intel_engine_flag(engine
);
67 static void __intel_ring_advance(struct intel_engine_cs
*engine
)
69 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
70 ringbuf
->tail
&= ringbuf
->size
- 1;
71 if (intel_engine_stopped(engine
))
73 engine
->write_tail(engine
, ringbuf
->tail
);
77 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
78 u32 invalidate_domains
,
81 struct intel_engine_cs
*engine
= req
->engine
;
86 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
87 cmd
|= MI_NO_WRITE_FLUSH
;
89 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
92 ret
= intel_ring_begin(req
, 2);
96 intel_ring_emit(engine
, cmd
);
97 intel_ring_emit(engine
, MI_NOOP
);
98 intel_ring_advance(engine
);
104 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
105 u32 invalidate_domains
,
108 struct intel_engine_cs
*engine
= req
->engine
;
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
124 * I915_GEM_DOMAIN_COMMAND may not exist?
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
140 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
141 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
142 cmd
&= ~MI_NO_WRITE_FLUSH
;
143 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
146 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
147 (IS_G4X(req
->i915
) || IS_GEN5(req
->i915
)))
148 cmd
|= MI_INVALIDATE_ISP
;
150 ret
= intel_ring_begin(req
, 2);
154 intel_ring_emit(engine
, cmd
);
155 intel_ring_emit(engine
, MI_NOOP
);
156 intel_ring_advance(engine
);
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
174 * And the workaround for these two requires this workaround first:
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
201 struct intel_engine_cs
*engine
= req
->engine
;
202 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
205 ret
= intel_ring_begin(req
, 6);
209 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
211 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
212 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
213 intel_ring_emit(engine
, 0); /* low dword */
214 intel_ring_emit(engine
, 0); /* high dword */
215 intel_ring_emit(engine
, MI_NOOP
);
216 intel_ring_advance(engine
);
218 ret
= intel_ring_begin(req
, 6);
222 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine
, PIPE_CONTROL_QW_WRITE
);
224 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
225 intel_ring_emit(engine
, 0);
226 intel_ring_emit(engine
, 0);
227 intel_ring_emit(engine
, MI_NOOP
);
228 intel_ring_advance(engine
);
234 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
235 u32 invalidate_domains
, u32 flush_domains
)
237 struct intel_engine_cs
*engine
= req
->engine
;
239 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
242 /* Force SNB workarounds for PIPE_CONTROL flushes */
243 ret
= intel_emit_post_sync_nonzero_flush(req
);
247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
252 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
253 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
258 flags
|= PIPE_CONTROL_CS_STALL
;
260 if (invalidate_domains
) {
261 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
262 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
263 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
264 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
265 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
266 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
268 * TLB invalidate requires a post-sync write.
270 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
273 ret
= intel_ring_begin(req
, 4);
277 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine
, flags
);
279 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
280 intel_ring_emit(engine
, 0);
281 intel_ring_advance(engine
);
287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
289 struct intel_engine_cs
*engine
= req
->engine
;
292 ret
= intel_ring_begin(req
, 4);
296 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
298 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
299 intel_ring_emit(engine
, 0);
300 intel_ring_emit(engine
, 0);
301 intel_ring_advance(engine
);
307 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
308 u32 invalidate_domains
, u32 flush_domains
)
310 struct intel_engine_cs
*engine
= req
->engine
;
312 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
323 flags
|= PIPE_CONTROL_CS_STALL
;
325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
330 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
331 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
332 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
333 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
335 if (invalidate_domains
) {
336 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
337 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
338 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
339 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
340 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
341 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
342 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
344 * TLB invalidate requires a post-sync write.
346 flags
|= PIPE_CONTROL_QW_WRITE
;
347 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
349 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
354 gen7_render_ring_cs_stall_wa(req
);
357 ret
= intel_ring_begin(req
, 4);
361 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine
, flags
);
363 intel_ring_emit(engine
, scratch_addr
);
364 intel_ring_emit(engine
, 0);
365 intel_ring_advance(engine
);
371 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
372 u32 flags
, u32 scratch_addr
)
374 struct intel_engine_cs
*engine
= req
->engine
;
377 ret
= intel_ring_begin(req
, 6);
381 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine
, flags
);
383 intel_ring_emit(engine
, scratch_addr
);
384 intel_ring_emit(engine
, 0);
385 intel_ring_emit(engine
, 0);
386 intel_ring_emit(engine
, 0);
387 intel_ring_advance(engine
);
393 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
394 u32 invalidate_domains
, u32 flush_domains
)
397 u32 scratch_addr
= req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
400 flags
|= PIPE_CONTROL_CS_STALL
;
403 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
404 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
405 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
406 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
408 if (invalidate_domains
) {
409 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
410 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
411 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
412 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
413 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
414 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
415 flags
|= PIPE_CONTROL_QW_WRITE
;
416 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
419 ret
= gen8_emit_pipe_control(req
,
420 PIPE_CONTROL_CS_STALL
|
421 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
427 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
430 static void ring_write_tail(struct intel_engine_cs
*engine
,
433 struct drm_i915_private
*dev_priv
= engine
->i915
;
434 I915_WRITE_TAIL(engine
, value
);
437 u64
intel_ring_get_active_head(struct intel_engine_cs
*engine
)
439 struct drm_i915_private
*dev_priv
= engine
->i915
;
442 if (INTEL_GEN(dev_priv
) >= 8)
443 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
444 RING_ACTHD_UDW(engine
->mmio_base
));
445 else if (INTEL_GEN(dev_priv
) >= 4)
446 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
448 acthd
= I915_READ(ACTHD
);
453 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
455 struct drm_i915_private
*dev_priv
= engine
->i915
;
458 addr
= dev_priv
->status_page_dmah
->busaddr
;
459 if (INTEL_GEN(dev_priv
) >= 4)
460 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
461 I915_WRITE(HWS_PGA
, addr
);
464 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
466 struct drm_i915_private
*dev_priv
= engine
->i915
;
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
472 if (IS_GEN7(dev_priv
)) {
473 switch (engine
->id
) {
475 mmio
= RENDER_HWS_PGA_GEN7
;
478 mmio
= BLT_HWS_PGA_GEN7
;
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
486 mmio
= BSD_HWS_PGA_GEN7
;
489 mmio
= VEBOX_HWS_PGA_GEN7
;
492 } else if (IS_GEN6(dev_priv
)) {
493 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
495 /* XXX: gen8 returns to sanity */
496 mmio
= RING_HWS_PGA(engine
->mmio_base
);
499 I915_WRITE(mmio
, (u32
)engine
->status_page
.gfx_addr
);
503 * Flush the TLB for this page
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
509 if (IS_GEN(dev_priv
, 6, 7)) {
510 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
512 /* ring should be idle before issuing a sync flush*/
513 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
518 if (intel_wait_for_register(dev_priv
,
519 reg
, INSTPM_SYNC_FLUSH
, 0,
521 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
526 static bool stop_ring(struct intel_engine_cs
*engine
)
528 struct drm_i915_private
*dev_priv
= engine
->i915
;
530 if (!IS_GEN2(dev_priv
)) {
531 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
532 if (intel_wait_for_register(dev_priv
,
533 RING_MI_MODE(engine
->mmio_base
),
537 DRM_ERROR("%s : timed out trying to stop ring\n",
539 /* Sometimes we observe that the idle flag is not
540 * set even though the ring is empty. So double
541 * check before giving up.
543 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
548 I915_WRITE_CTL(engine
, 0);
549 I915_WRITE_HEAD(engine
, 0);
550 engine
->write_tail(engine
, 0);
552 if (!IS_GEN2(dev_priv
)) {
553 (void)I915_READ_CTL(engine
);
554 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
557 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
560 void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
)
562 memset(&engine
->hangcheck
, 0, sizeof(engine
->hangcheck
));
565 static int init_ring_common(struct intel_engine_cs
*engine
)
567 struct drm_i915_private
*dev_priv
= engine
->i915
;
568 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
569 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
572 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
574 if (!stop_ring(engine
)) {
575 /* G45 ring initialization often fails to reset head to zero */
576 DRM_DEBUG_KMS("%s head not reset to zero "
577 "ctl %08x head %08x tail %08x start %08x\n",
579 I915_READ_CTL(engine
),
580 I915_READ_HEAD(engine
),
581 I915_READ_TAIL(engine
),
582 I915_READ_START(engine
));
584 if (!stop_ring(engine
)) {
585 DRM_ERROR("failed to set %s head to zero "
586 "ctl %08x head %08x tail %08x start %08x\n",
588 I915_READ_CTL(engine
),
589 I915_READ_HEAD(engine
),
590 I915_READ_TAIL(engine
),
591 I915_READ_START(engine
));
597 if (I915_NEED_GFX_HWS(dev_priv
))
598 intel_ring_setup_status_page(engine
);
600 ring_setup_phys_status_page(engine
);
602 /* Enforce ordering by reading HEAD register back */
603 I915_READ_HEAD(engine
);
605 /* Initialize the ring. This must happen _after_ we've cleared the ring
606 * registers with the above sequence (the readback of the HEAD registers
607 * also enforces ordering), otherwise the hw might lose the new ring
608 * register values. */
609 I915_WRITE_START(engine
, i915_gem_obj_ggtt_offset(obj
));
611 /* WaClearRingBufHeadRegAtInit:ctg,elk */
612 if (I915_READ_HEAD(engine
))
613 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
614 engine
->name
, I915_READ_HEAD(engine
));
615 I915_WRITE_HEAD(engine
, 0);
616 (void)I915_READ_HEAD(engine
);
618 I915_WRITE_CTL(engine
,
619 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
622 /* If the head is still not zero, the ring is dead */
623 if (wait_for((I915_READ_CTL(engine
) & RING_VALID
) != 0 &&
624 I915_READ_START(engine
) == i915_gem_obj_ggtt_offset(obj
) &&
625 (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0, 50)) {
626 DRM_ERROR("%s initialization failed "
627 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
629 I915_READ_CTL(engine
),
630 I915_READ_CTL(engine
) & RING_VALID
,
631 I915_READ_HEAD(engine
), I915_READ_TAIL(engine
),
632 I915_READ_START(engine
),
633 (unsigned long)i915_gem_obj_ggtt_offset(obj
));
638 ringbuf
->last_retired_head
= -1;
639 ringbuf
->head
= I915_READ_HEAD(engine
);
640 ringbuf
->tail
= I915_READ_TAIL(engine
) & TAIL_ADDR
;
641 intel_ring_update_space(ringbuf
);
643 intel_engine_init_hangcheck(engine
);
646 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
651 void intel_fini_pipe_control(struct intel_engine_cs
*engine
)
653 if (engine
->scratch
.obj
== NULL
)
656 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
657 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
658 engine
->scratch
.obj
= NULL
;
661 int intel_init_pipe_control(struct intel_engine_cs
*engine
, int size
)
663 struct drm_i915_gem_object
*obj
;
666 WARN_ON(engine
->scratch
.obj
);
668 obj
= i915_gem_object_create_stolen(engine
->i915
->dev
, size
);
670 obj
= i915_gem_object_create(engine
->i915
->dev
, size
);
672 DRM_ERROR("Failed to allocate scratch page\n");
677 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, PIN_HIGH
);
681 engine
->scratch
.obj
= obj
;
682 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
683 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
684 engine
->name
, engine
->scratch
.gtt_offset
);
688 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
693 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
695 struct intel_engine_cs
*engine
= req
->engine
;
696 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
702 engine
->gpu_caches_dirty
= true;
703 ret
= intel_ring_flush_all_caches(req
);
707 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
711 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(w
->count
));
712 for (i
= 0; i
< w
->count
; i
++) {
713 intel_ring_emit_reg(engine
, w
->reg
[i
].addr
);
714 intel_ring_emit(engine
, w
->reg
[i
].value
);
716 intel_ring_emit(engine
, MI_NOOP
);
718 intel_ring_advance(engine
);
720 engine
->gpu_caches_dirty
= true;
721 ret
= intel_ring_flush_all_caches(req
);
725 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
730 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
734 ret
= intel_ring_workarounds_emit(req
);
738 ret
= i915_gem_render_state_init(req
);
745 static int wa_add(struct drm_i915_private
*dev_priv
,
747 const u32 mask
, const u32 val
)
749 const u32 idx
= dev_priv
->workarounds
.count
;
751 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
754 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
755 dev_priv
->workarounds
.reg
[idx
].value
= val
;
756 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
758 dev_priv
->workarounds
.count
++;
763 #define WA_REG(addr, mask, val) do { \
764 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
769 #define WA_SET_BIT_MASKED(addr, mask) \
770 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
772 #define WA_CLR_BIT_MASKED(addr, mask) \
773 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
775 #define WA_SET_FIELD_MASKED(addr, mask, value) \
776 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
778 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
779 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
781 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
783 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
786 struct drm_i915_private
*dev_priv
= engine
->i915
;
787 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
788 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
790 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
793 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
794 i915_mmio_reg_offset(reg
));
795 wa
->hw_whitelist_count
[engine
->id
]++;
800 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
802 struct drm_i915_private
*dev_priv
= engine
->i915
;
804 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
806 /* WaDisableAsyncFlipPerfMode:bdw,chv */
807 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
809 /* WaDisablePartialInstShootdown:bdw,chv */
810 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
811 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
813 /* Use Force Non-Coherent whenever executing a 3D context. This is a
814 * workaround for for a possible hang in the unlikely event a TLB
815 * invalidation occurs during a PSD flush.
817 /* WaForceEnableNonCoherent:bdw,chv */
818 /* WaHdcDisableFetchWhenMasked:bdw,chv */
819 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
820 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
821 HDC_FORCE_NON_COHERENT
);
823 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
824 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
825 * polygons in the same 8x4 pixel/sample area to be processed without
826 * stalling waiting for the earlier ones to write to Hierarchical Z
829 * This optimization is off by default for BDW and CHV; turn it on.
831 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
833 /* Wa4x4STCOptimizationDisable:bdw,chv */
834 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
837 * BSpec recommends 8x4 when MSAA is used,
838 * however in practice 16x4 seems fastest.
840 * Note that PS/WM thread counts depend on the WIZ hashing
841 * disable bit, which we don't touch here, but it's good
842 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
844 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
845 GEN6_WIZ_HASHING_MASK
,
846 GEN6_WIZ_HASHING_16x4
);
851 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
853 struct drm_i915_private
*dev_priv
= engine
->i915
;
856 ret
= gen8_init_workarounds(engine
);
860 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
861 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
863 /* WaDisableDopClockGating:bdw */
864 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
865 DOP_CLOCK_GATING_DISABLE
);
867 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
868 GEN8_SAMPLER_POWER_BYPASS_DIS
);
870 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
871 /* WaForceContextSaveRestoreNonCoherent:bdw */
872 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
873 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
874 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
879 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
881 struct drm_i915_private
*dev_priv
= engine
->i915
;
884 ret
= gen8_init_workarounds(engine
);
888 /* WaDisableThreadStallDopClockGating:chv */
889 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
891 /* Improve HiZ throughput on CHV. */
892 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
897 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
899 struct drm_i915_private
*dev_priv
= engine
->i915
;
902 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
903 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
905 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
906 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
907 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
909 /* WaDisableKillLogic:bxt,skl,kbl */
910 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
913 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
914 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
915 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
916 FLOW_CONTROL_ENABLE
|
917 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
919 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
920 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
921 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
923 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
924 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
925 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
926 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
927 GEN9_DG_MIRROR_FIX_ENABLE
);
929 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
930 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
931 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
932 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
933 GEN9_RHWO_OPTIMIZATION_DISABLE
);
935 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
936 * but we do that in per ctx batchbuffer as there is an issue
937 * with this register not getting restored on ctx restore
941 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
942 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
943 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
944 GEN9_ENABLE_YV12_BUGFIX
|
945 GEN9_ENABLE_GPGPU_PREEMPTION
);
947 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
948 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
949 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
950 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
952 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
953 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
954 GEN9_CCS_TLB_PREFETCH_ENABLE
);
956 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
957 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_C0
) ||
958 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
959 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
960 PIXEL_MASK_CAMMING_DISABLE
);
962 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
963 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
964 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
965 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
967 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
968 * both tied to WaForceContextSaveRestoreNonCoherent
969 * in some hsds for skl. We keep the tie for all gen9. The
970 * documentation is a bit hazy and so we want to get common behaviour,
971 * even though there is no clear evidence we would need both on kbl/bxt.
972 * This area has been source of system hangs so we play it safe
973 * and mimic the skl regardless of what bspec says.
975 * Use Force Non-Coherent whenever executing a 3D context. This
976 * is a workaround for a possible hang in the unlikely event
977 * a TLB invalidation occurs during a PSD flush.
980 /* WaForceEnableNonCoherent:skl,bxt,kbl */
981 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
982 HDC_FORCE_NON_COHERENT
);
984 /* WaDisableHDCInvalidation:skl,bxt,kbl */
985 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
986 BDW_DISABLE_HDC_INVALIDATION
);
988 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
989 if (IS_SKYLAKE(dev_priv
) ||
990 IS_KABYLAKE(dev_priv
) ||
991 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
992 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
993 GEN8_SAMPLER_POWER_BYPASS_DIS
);
995 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
996 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
998 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
999 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
1000 GEN8_LQSC_FLUSH_COHERENT_LINES
));
1002 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1003 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
1007 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1008 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
1012 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1013 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
1020 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
1022 struct drm_i915_private
*dev_priv
= engine
->i915
;
1023 u8 vals
[3] = { 0, 0, 0 };
1026 for (i
= 0; i
< 3; i
++) {
1030 * Only consider slices where one, and only one, subslice has 7
1033 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1037 * subslice_7eu[i] != 0 (because of the check above) and
1038 * ss_max == 4 (maximum number of subslices possible per slice)
1042 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1046 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1049 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1050 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1051 GEN9_IZ_HASHING_MASK(2) |
1052 GEN9_IZ_HASHING_MASK(1) |
1053 GEN9_IZ_HASHING_MASK(0),
1054 GEN9_IZ_HASHING(2, vals
[2]) |
1055 GEN9_IZ_HASHING(1, vals
[1]) |
1056 GEN9_IZ_HASHING(0, vals
[0]));
1061 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
1063 struct drm_i915_private
*dev_priv
= engine
->i915
;
1066 ret
= gen9_init_workarounds(engine
);
1071 * Actual WA is to disable percontext preemption granularity control
1072 * until D0 which is the default case so this is equivalent to
1073 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1075 if (IS_SKL_REVID(dev_priv
, SKL_REVID_E0
, REVID_FOREVER
)) {
1076 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
1077 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
1080 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
)) {
1081 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1082 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1083 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1086 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1087 * involving this register should also be added to WA batch as required.
1089 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
))
1090 /* WaDisableLSQCROPERFforOCL:skl */
1091 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1092 GEN8_LQSC_RO_PERF_DIS
);
1094 /* WaEnableGapsTsvCreditFix:skl */
1095 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, REVID_FOREVER
)) {
1096 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1097 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1100 /* WaDisablePowerCompilerClockGating:skl */
1101 if (IS_SKL_REVID(dev_priv
, SKL_REVID_B0
, SKL_REVID_B0
))
1102 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1103 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1105 /* WaBarrierPerformanceFixDisable:skl */
1106 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_D0
))
1107 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1108 HDC_FENCE_DEST_SLM_DISABLE
|
1109 HDC_BARRIER_PERFORMANCE_DISABLE
);
1111 /* WaDisableSbeCacheDispatchPortSharing:skl */
1112 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
))
1114 GEN7_HALF_SLICE_CHICKEN1
,
1115 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1117 /* WaDisableGafsUnitClkGating:skl */
1118 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1120 /* WaDisableLSQCROPERFforOCL:skl */
1121 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1125 return skl_tune_iz_hashing(engine
);
1128 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1130 struct drm_i915_private
*dev_priv
= engine
->i915
;
1133 ret
= gen9_init_workarounds(engine
);
1137 /* WaStoreMultiplePTEenable:bxt */
1138 /* This is a requirement according to Hardware specification */
1139 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1140 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1142 /* WaSetClckGatingDisableMedia:bxt */
1143 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1144 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1145 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1148 /* WaDisableThreadStallDopClockGating:bxt */
1149 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1150 STALL_DOP_GATING_DISABLE
);
1152 /* WaDisablePooledEuLoadBalancingFix:bxt */
1153 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1154 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2
,
1155 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
);
1158 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1159 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1161 GEN7_HALF_SLICE_CHICKEN1
,
1162 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1165 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1166 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1167 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1168 /* WaDisableLSQCROPERFforOCL:bxt */
1169 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1170 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1174 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1179 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1180 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
1181 I915_WRITE(GEN8_L3SQCREG1
, L3_GENERAL_PRIO_CREDITS(62) |
1182 L3_HIGH_PRIO_CREDITS(2));
1184 /* WaInsertDummyPushConstPs:bxt */
1185 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1186 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1187 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1192 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1194 struct drm_i915_private
*dev_priv
= engine
->i915
;
1197 ret
= gen9_init_workarounds(engine
);
1201 /* WaEnableGapsTsvCreditFix:kbl */
1202 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1203 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1205 /* WaDisableDynamicCreditSharing:kbl */
1206 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1207 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1208 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1210 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1211 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1212 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1213 HDC_FENCE_DEST_SLM_DISABLE
);
1215 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1216 * involving this register should also be added to WA batch as required.
1218 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1219 /* WaDisableLSQCROPERFforOCL:kbl */
1220 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1221 GEN8_LQSC_RO_PERF_DIS
);
1223 /* WaInsertDummyPushConstPs:kbl */
1224 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1225 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1226 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1228 /* WaDisableGafsUnitClkGating:kbl */
1229 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1231 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1233 GEN7_HALF_SLICE_CHICKEN1
,
1234 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1236 /* WaDisableLSQCROPERFforOCL:kbl */
1237 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1244 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1246 struct drm_i915_private
*dev_priv
= engine
->i915
;
1248 WARN_ON(engine
->id
!= RCS
);
1250 dev_priv
->workarounds
.count
= 0;
1251 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1253 if (IS_BROADWELL(dev_priv
))
1254 return bdw_init_workarounds(engine
);
1256 if (IS_CHERRYVIEW(dev_priv
))
1257 return chv_init_workarounds(engine
);
1259 if (IS_SKYLAKE(dev_priv
))
1260 return skl_init_workarounds(engine
);
1262 if (IS_BROXTON(dev_priv
))
1263 return bxt_init_workarounds(engine
);
1265 if (IS_KABYLAKE(dev_priv
))
1266 return kbl_init_workarounds(engine
);
1271 static int init_render_ring(struct intel_engine_cs
*engine
)
1273 struct drm_i915_private
*dev_priv
= engine
->i915
;
1274 int ret
= init_ring_common(engine
);
1278 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1279 if (IS_GEN(dev_priv
, 4, 6))
1280 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1282 /* We need to disable the AsyncFlip performance optimisations in order
1283 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1284 * programmed to '1' on all products.
1286 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1288 if (IS_GEN(dev_priv
, 6, 7))
1289 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1291 /* Required for the hardware to program scanline values for waiting */
1292 /* WaEnableFlushTlbInvalidationMode:snb */
1293 if (IS_GEN6(dev_priv
))
1294 I915_WRITE(GFX_MODE
,
1295 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1297 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1298 if (IS_GEN7(dev_priv
))
1299 I915_WRITE(GFX_MODE_GEN7
,
1300 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1301 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1303 if (IS_GEN6(dev_priv
)) {
1304 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1305 * "If this bit is set, STCunit will have LRA as replacement
1306 * policy. [...] This bit must be reset. LRA replacement
1307 * policy is not supported."
1309 I915_WRITE(CACHE_MODE_0
,
1310 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1313 if (IS_GEN(dev_priv
, 6, 7))
1314 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1316 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1318 return init_workarounds_ring(engine
);
1321 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1323 struct drm_i915_private
*dev_priv
= engine
->i915
;
1325 if (dev_priv
->semaphore_obj
) {
1326 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1327 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1328 dev_priv
->semaphore_obj
= NULL
;
1331 intel_fini_pipe_control(engine
);
1334 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1335 unsigned int num_dwords
)
1337 #define MBOX_UPDATE_DWORDS 8
1338 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1339 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1340 struct intel_engine_cs
*waiter
;
1341 enum intel_engine_id id
;
1344 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1345 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1346 #undef MBOX_UPDATE_DWORDS
1348 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1352 for_each_engine_id(waiter
, dev_priv
, id
) {
1353 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1354 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1357 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1358 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1359 PIPE_CONTROL_QW_WRITE
|
1360 PIPE_CONTROL_CS_STALL
);
1361 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1362 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1363 intel_ring_emit(signaller
, signaller_req
->seqno
);
1364 intel_ring_emit(signaller
, 0);
1365 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1366 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1367 intel_ring_emit(signaller
, 0);
1373 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1374 unsigned int num_dwords
)
1376 #define MBOX_UPDATE_DWORDS 6
1377 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1378 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1379 struct intel_engine_cs
*waiter
;
1380 enum intel_engine_id id
;
1383 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1384 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1385 #undef MBOX_UPDATE_DWORDS
1387 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1391 for_each_engine_id(waiter
, dev_priv
, id
) {
1392 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1393 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1396 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1397 MI_FLUSH_DW_OP_STOREDW
);
1398 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1399 MI_FLUSH_DW_USE_GTT
);
1400 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1401 intel_ring_emit(signaller
, signaller_req
->seqno
);
1402 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1403 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1404 intel_ring_emit(signaller
, 0);
1410 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1411 unsigned int num_dwords
)
1413 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1414 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1415 struct intel_engine_cs
*useless
;
1416 enum intel_engine_id id
;
1419 #define MBOX_UPDATE_DWORDS 3
1420 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1421 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1422 #undef MBOX_UPDATE_DWORDS
1424 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1428 for_each_engine_id(useless
, dev_priv
, id
) {
1429 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[id
];
1431 if (i915_mmio_reg_valid(mbox_reg
)) {
1432 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1433 intel_ring_emit_reg(signaller
, mbox_reg
);
1434 intel_ring_emit(signaller
, signaller_req
->seqno
);
1438 /* If num_dwords was rounded, make sure the tail pointer is correct */
1439 if (num_rings
% 2 == 0)
1440 intel_ring_emit(signaller
, MI_NOOP
);
1446 * gen6_add_request - Update the semaphore mailbox registers
1448 * @request - request to write to the ring
1450 * Update the mailbox registers in the *other* rings with the current seqno.
1451 * This acts like a signal in the canonical semaphore.
1454 gen6_add_request(struct drm_i915_gem_request
*req
)
1456 struct intel_engine_cs
*engine
= req
->engine
;
1459 if (engine
->semaphore
.signal
)
1460 ret
= engine
->semaphore
.signal(req
, 4);
1462 ret
= intel_ring_begin(req
, 4);
1467 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1468 intel_ring_emit(engine
,
1469 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1470 intel_ring_emit(engine
, req
->seqno
);
1471 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1472 __intel_ring_advance(engine
);
1478 gen8_render_add_request(struct drm_i915_gem_request
*req
)
1480 struct intel_engine_cs
*engine
= req
->engine
;
1483 if (engine
->semaphore
.signal
)
1484 ret
= engine
->semaphore
.signal(req
, 8);
1486 ret
= intel_ring_begin(req
, 8);
1490 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
1491 intel_ring_emit(engine
, (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1492 PIPE_CONTROL_CS_STALL
|
1493 PIPE_CONTROL_QW_WRITE
));
1494 intel_ring_emit(engine
, intel_hws_seqno_address(req
->engine
));
1495 intel_ring_emit(engine
, 0);
1496 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1497 /* We're thrashing one dword of HWS. */
1498 intel_ring_emit(engine
, 0);
1499 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1500 intel_ring_emit(engine
, MI_NOOP
);
1501 __intel_ring_advance(engine
);
1506 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private
*dev_priv
,
1509 return dev_priv
->last_seqno
< seqno
;
1513 * intel_ring_sync - sync the waiter to the signaller on seqno
1515 * @waiter - ring that is waiting
1516 * @signaller - ring which has, or will signal
1517 * @seqno - seqno which the waiter will block on
1521 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1522 struct intel_engine_cs
*signaller
,
1525 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1526 struct drm_i915_private
*dev_priv
= waiter_req
->i915
;
1527 u64 offset
= GEN8_WAIT_OFFSET(waiter
, signaller
->id
);
1528 struct i915_hw_ppgtt
*ppgtt
;
1531 ret
= intel_ring_begin(waiter_req
, 4);
1535 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1536 MI_SEMAPHORE_GLOBAL_GTT
|
1537 MI_SEMAPHORE_SAD_GTE_SDD
);
1538 intel_ring_emit(waiter
, seqno
);
1539 intel_ring_emit(waiter
, lower_32_bits(offset
));
1540 intel_ring_emit(waiter
, upper_32_bits(offset
));
1541 intel_ring_advance(waiter
);
1543 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1544 * pagetables and we must reload them before executing the batch.
1545 * We do this on the i915_switch_context() following the wait and
1546 * before the dispatch.
1548 ppgtt
= waiter_req
->ctx
->ppgtt
;
1549 if (ppgtt
&& waiter_req
->engine
->id
!= RCS
)
1550 ppgtt
->pd_dirty_rings
|= intel_engine_flag(waiter_req
->engine
);
1555 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1556 struct intel_engine_cs
*signaller
,
1559 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1560 u32 dw1
= MI_SEMAPHORE_MBOX
|
1561 MI_SEMAPHORE_COMPARE
|
1562 MI_SEMAPHORE_REGISTER
;
1563 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1566 /* Throughout all of the GEM code, seqno passed implies our current
1567 * seqno is >= the last seqno executed. However for hardware the
1568 * comparison is strictly greater than.
1572 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1574 ret
= intel_ring_begin(waiter_req
, 4);
1578 /* If seqno wrap happened, omit the wait with no-ops */
1579 if (likely(!i915_gem_has_seqno_wrapped(waiter_req
->i915
, seqno
))) {
1580 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1581 intel_ring_emit(waiter
, seqno
);
1582 intel_ring_emit(waiter
, 0);
1583 intel_ring_emit(waiter
, MI_NOOP
);
1585 intel_ring_emit(waiter
, MI_NOOP
);
1586 intel_ring_emit(waiter
, MI_NOOP
);
1587 intel_ring_emit(waiter
, MI_NOOP
);
1588 intel_ring_emit(waiter
, MI_NOOP
);
1590 intel_ring_advance(waiter
);
1596 gen5_seqno_barrier(struct intel_engine_cs
*ring
)
1598 /* MI_STORE are internally buffered by the GPU and not flushed
1599 * either by MI_FLUSH or SyncFlush or any other combination of
1602 * "Only the submission of the store operation is guaranteed.
1603 * The write result will be complete (coherent) some time later
1604 * (this is practically a finite period but there is no guaranteed
1607 * Empirically, we observe that we need a delay of at least 75us to
1608 * be sure that the seqno write is visible by the CPU.
1610 usleep_range(125, 250);
1614 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1616 struct drm_i915_private
*dev_priv
= engine
->i915
;
1618 /* Workaround to force correct ordering between irq and seqno writes on
1619 * ivb (and maybe also on snb) by reading from a CS register (like
1620 * ACTHD) before reading the status page.
1622 * Note that this effectively stalls the read by the time it takes to
1623 * do a memory transaction, which more or less ensures that the write
1624 * from the GPU has sufficient time to invalidate the CPU cacheline.
1625 * Alternatively we could delay the interrupt from the CS ring to give
1626 * the write time to land, but that would incur a delay after every
1627 * batch i.e. much more frequent than a delay when waiting for the
1628 * interrupt (with the same net latency).
1630 * Also note that to prevent whole machine hangs on gen7, we have to
1631 * take the spinlock to guard against concurrent cacheline access.
1633 spin_lock_irq(&dev_priv
->uncore
.lock
);
1634 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1635 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1639 gen5_irq_enable(struct intel_engine_cs
*engine
)
1641 gen5_enable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1645 gen5_irq_disable(struct intel_engine_cs
*engine
)
1647 gen5_disable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1651 i9xx_irq_enable(struct intel_engine_cs
*engine
)
1653 struct drm_i915_private
*dev_priv
= engine
->i915
;
1655 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1656 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1657 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1661 i9xx_irq_disable(struct intel_engine_cs
*engine
)
1663 struct drm_i915_private
*dev_priv
= engine
->i915
;
1665 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1666 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1670 i8xx_irq_enable(struct intel_engine_cs
*engine
)
1672 struct drm_i915_private
*dev_priv
= engine
->i915
;
1674 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1675 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1676 POSTING_READ16(RING_IMR(engine
->mmio_base
));
1680 i8xx_irq_disable(struct intel_engine_cs
*engine
)
1682 struct drm_i915_private
*dev_priv
= engine
->i915
;
1684 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1685 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1689 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1690 u32 invalidate_domains
,
1693 struct intel_engine_cs
*engine
= req
->engine
;
1696 ret
= intel_ring_begin(req
, 2);
1700 intel_ring_emit(engine
, MI_FLUSH
);
1701 intel_ring_emit(engine
, MI_NOOP
);
1702 intel_ring_advance(engine
);
1707 i9xx_add_request(struct drm_i915_gem_request
*req
)
1709 struct intel_engine_cs
*engine
= req
->engine
;
1712 ret
= intel_ring_begin(req
, 4);
1716 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1717 intel_ring_emit(engine
,
1718 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1719 intel_ring_emit(engine
, req
->seqno
);
1720 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1721 __intel_ring_advance(engine
);
1727 gen6_irq_enable(struct intel_engine_cs
*engine
)
1729 struct drm_i915_private
*dev_priv
= engine
->i915
;
1731 I915_WRITE_IMR(engine
,
1732 ~(engine
->irq_enable_mask
|
1733 engine
->irq_keep_mask
));
1734 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1738 gen6_irq_disable(struct intel_engine_cs
*engine
)
1740 struct drm_i915_private
*dev_priv
= engine
->i915
;
1742 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1743 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1747 hsw_vebox_irq_enable(struct intel_engine_cs
*engine
)
1749 struct drm_i915_private
*dev_priv
= engine
->i915
;
1751 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1752 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1756 hsw_vebox_irq_disable(struct intel_engine_cs
*engine
)
1758 struct drm_i915_private
*dev_priv
= engine
->i915
;
1760 I915_WRITE_IMR(engine
, ~0);
1761 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1765 gen8_irq_enable(struct intel_engine_cs
*engine
)
1767 struct drm_i915_private
*dev_priv
= engine
->i915
;
1769 I915_WRITE_IMR(engine
,
1770 ~(engine
->irq_enable_mask
|
1771 engine
->irq_keep_mask
));
1772 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1776 gen8_irq_disable(struct intel_engine_cs
*engine
)
1778 struct drm_i915_private
*dev_priv
= engine
->i915
;
1780 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1784 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1785 u64 offset
, u32 length
,
1786 unsigned dispatch_flags
)
1788 struct intel_engine_cs
*engine
= req
->engine
;
1791 ret
= intel_ring_begin(req
, 2);
1795 intel_ring_emit(engine
,
1796 MI_BATCH_BUFFER_START
|
1798 (dispatch_flags
& I915_DISPATCH_SECURE
?
1799 0 : MI_BATCH_NON_SECURE_I965
));
1800 intel_ring_emit(engine
, offset
);
1801 intel_ring_advance(engine
);
1806 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1807 #define I830_BATCH_LIMIT (256*1024)
1808 #define I830_TLB_ENTRIES (2)
1809 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1811 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1812 u64 offset
, u32 len
,
1813 unsigned dispatch_flags
)
1815 struct intel_engine_cs
*engine
= req
->engine
;
1816 u32 cs_offset
= engine
->scratch
.gtt_offset
;
1819 ret
= intel_ring_begin(req
, 6);
1823 /* Evict the invalid PTE TLBs */
1824 intel_ring_emit(engine
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1825 intel_ring_emit(engine
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1826 intel_ring_emit(engine
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1827 intel_ring_emit(engine
, cs_offset
);
1828 intel_ring_emit(engine
, 0xdeadbeef);
1829 intel_ring_emit(engine
, MI_NOOP
);
1830 intel_ring_advance(engine
);
1832 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1833 if (len
> I830_BATCH_LIMIT
)
1836 ret
= intel_ring_begin(req
, 6 + 2);
1840 /* Blit the batch (which has now all relocs applied) to the
1841 * stable batch scratch bo area (so that the CS never
1842 * stumbles over its tlb invalidation bug) ...
1844 intel_ring_emit(engine
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1845 intel_ring_emit(engine
,
1846 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1847 intel_ring_emit(engine
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1848 intel_ring_emit(engine
, cs_offset
);
1849 intel_ring_emit(engine
, 4096);
1850 intel_ring_emit(engine
, offset
);
1852 intel_ring_emit(engine
, MI_FLUSH
);
1853 intel_ring_emit(engine
, MI_NOOP
);
1854 intel_ring_advance(engine
);
1856 /* ... and execute it. */
1860 ret
= intel_ring_begin(req
, 2);
1864 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1865 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1866 0 : MI_BATCH_NON_SECURE
));
1867 intel_ring_advance(engine
);
1873 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1874 u64 offset
, u32 len
,
1875 unsigned dispatch_flags
)
1877 struct intel_engine_cs
*engine
= req
->engine
;
1880 ret
= intel_ring_begin(req
, 2);
1884 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1885 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1886 0 : MI_BATCH_NON_SECURE
));
1887 intel_ring_advance(engine
);
1892 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
1894 struct drm_i915_private
*dev_priv
= engine
->i915
;
1896 if (!dev_priv
->status_page_dmah
)
1899 drm_pci_free(dev_priv
->dev
, dev_priv
->status_page_dmah
);
1900 engine
->status_page
.page_addr
= NULL
;
1903 static void cleanup_status_page(struct intel_engine_cs
*engine
)
1905 struct drm_i915_gem_object
*obj
;
1907 obj
= engine
->status_page
.obj
;
1911 kunmap(sg_page(obj
->pages
->sgl
));
1912 i915_gem_object_ggtt_unpin(obj
);
1913 drm_gem_object_unreference(&obj
->base
);
1914 engine
->status_page
.obj
= NULL
;
1917 static int init_status_page(struct intel_engine_cs
*engine
)
1919 struct drm_i915_gem_object
*obj
= engine
->status_page
.obj
;
1925 obj
= i915_gem_object_create(engine
->i915
->dev
, 4096);
1927 DRM_ERROR("Failed to allocate status page\n");
1928 return PTR_ERR(obj
);
1931 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1936 if (!HAS_LLC(engine
->i915
))
1937 /* On g33, we cannot place HWS above 256MiB, so
1938 * restrict its pinning to the low mappable arena.
1939 * Though this restriction is not documented for
1940 * gen4, gen5, or byt, they also behave similarly
1941 * and hang if the HWS is placed at the top of the
1942 * GTT. To generalise, it appears that all !llc
1943 * platforms have issues with us placing the HWS
1944 * above the mappable region (even though we never
1947 flags
|= PIN_MAPPABLE
;
1948 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1951 drm_gem_object_unreference(&obj
->base
);
1955 engine
->status_page
.obj
= obj
;
1958 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1959 engine
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1960 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
1962 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1963 engine
->name
, engine
->status_page
.gfx_addr
);
1968 static int init_phys_status_page(struct intel_engine_cs
*engine
)
1970 struct drm_i915_private
*dev_priv
= engine
->i915
;
1972 if (!dev_priv
->status_page_dmah
) {
1973 dev_priv
->status_page_dmah
=
1974 drm_pci_alloc(dev_priv
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1975 if (!dev_priv
->status_page_dmah
)
1979 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1980 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
1985 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1987 GEM_BUG_ON(ringbuf
->vma
== NULL
);
1988 GEM_BUG_ON(ringbuf
->virtual_start
== NULL
);
1990 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
1991 i915_gem_object_unpin_map(ringbuf
->obj
);
1993 i915_vma_unpin_iomap(ringbuf
->vma
);
1994 ringbuf
->virtual_start
= NULL
;
1996 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1997 ringbuf
->vma
= NULL
;
2000 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private
*dev_priv
,
2001 struct intel_ringbuffer
*ringbuf
)
2003 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2004 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2005 unsigned flags
= PIN_OFFSET_BIAS
| 4096;
2009 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2010 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, flags
);
2014 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2018 addr
= i915_gem_object_pin_map(obj
);
2020 ret
= PTR_ERR(addr
);
2024 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
2025 flags
| PIN_MAPPABLE
);
2029 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2033 /* Access through the GTT requires the device to be awake. */
2034 assert_rpm_wakelock_held(dev_priv
);
2036 addr
= i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj
));
2038 ret
= PTR_ERR(addr
);
2043 ringbuf
->virtual_start
= addr
;
2044 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2048 i915_gem_object_ggtt_unpin(obj
);
2052 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2054 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2055 ringbuf
->obj
= NULL
;
2058 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2059 struct intel_ringbuffer
*ringbuf
)
2061 struct drm_i915_gem_object
*obj
;
2065 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2067 obj
= i915_gem_object_create(dev
, ringbuf
->size
);
2069 return PTR_ERR(obj
);
2071 /* mark ring buffers as read-only from GPU side by default */
2079 struct intel_ringbuffer
*
2080 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2082 struct intel_ringbuffer
*ring
;
2085 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2087 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2089 return ERR_PTR(-ENOMEM
);
2092 ring
->engine
= engine
;
2093 list_add(&ring
->link
, &engine
->buffers
);
2096 /* Workaround an erratum on the i830 which causes a hang if
2097 * the TAIL pointer points to within the last 2 cachelines
2100 ring
->effective_size
= size
;
2101 if (IS_I830(engine
->i915
) || IS_845G(engine
->i915
))
2102 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2104 ring
->last_retired_head
= -1;
2105 intel_ring_update_space(ring
);
2107 ret
= intel_alloc_ringbuffer_obj(engine
->i915
->dev
, ring
);
2109 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2111 list_del(&ring
->link
);
2113 return ERR_PTR(ret
);
2120 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2122 intel_destroy_ringbuffer_obj(ring
);
2123 list_del(&ring
->link
);
2127 static int intel_ring_context_pin(struct i915_gem_context
*ctx
,
2128 struct intel_engine_cs
*engine
)
2130 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2133 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
2135 if (ce
->pin_count
++)
2139 ret
= i915_gem_obj_ggtt_pin(ce
->state
, ctx
->ggtt_alignment
, 0);
2144 /* The kernel context is only used as a placeholder for flushing the
2145 * active context. It is never used for submitting user rendering and
2146 * as such never requires the golden render context, and so we can skip
2147 * emitting it when we switch to the kernel context. This is required
2148 * as during eviction we cannot allocate and pin the renderstate in
2149 * order to initialise the context.
2151 if (ctx
== ctx
->i915
->kernel_context
)
2152 ce
->initialised
= true;
2154 i915_gem_context_reference(ctx
);
2162 static void intel_ring_context_unpin(struct i915_gem_context
*ctx
,
2163 struct intel_engine_cs
*engine
)
2165 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2167 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
2169 if (--ce
->pin_count
)
2173 i915_gem_object_ggtt_unpin(ce
->state
);
2175 i915_gem_context_unreference(ctx
);
2178 static int intel_init_ring_buffer(struct drm_device
*dev
,
2179 struct intel_engine_cs
*engine
)
2181 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2182 struct intel_ringbuffer
*ringbuf
;
2185 WARN_ON(engine
->buffer
);
2187 engine
->i915
= dev_priv
;
2188 INIT_LIST_HEAD(&engine
->active_list
);
2189 INIT_LIST_HEAD(&engine
->request_list
);
2190 INIT_LIST_HEAD(&engine
->execlist_queue
);
2191 INIT_LIST_HEAD(&engine
->buffers
);
2192 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2193 memset(engine
->semaphore
.sync_seqno
, 0,
2194 sizeof(engine
->semaphore
.sync_seqno
));
2196 ret
= intel_engine_init_breadcrumbs(engine
);
2200 /* We may need to do things with the shrinker which
2201 * require us to immediately switch back to the default
2202 * context. This can cause a problem as pinning the
2203 * default context also requires GTT space which may not
2204 * be available. To avoid this we always pin the default
2207 ret
= intel_ring_context_pin(dev_priv
->kernel_context
, engine
);
2211 ringbuf
= intel_engine_create_ringbuffer(engine
, 32 * PAGE_SIZE
);
2212 if (IS_ERR(ringbuf
)) {
2213 ret
= PTR_ERR(ringbuf
);
2216 engine
->buffer
= ringbuf
;
2218 if (I915_NEED_GFX_HWS(dev_priv
)) {
2219 ret
= init_status_page(engine
);
2223 WARN_ON(engine
->id
!= RCS
);
2224 ret
= init_phys_status_page(engine
);
2229 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ringbuf
);
2231 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2233 intel_destroy_ringbuffer_obj(ringbuf
);
2237 ret
= i915_cmd_parser_init_ring(engine
);
2244 intel_cleanup_engine(engine
);
2248 void intel_cleanup_engine(struct intel_engine_cs
*engine
)
2250 struct drm_i915_private
*dev_priv
;
2252 if (!intel_engine_initialized(engine
))
2255 dev_priv
= engine
->i915
;
2257 if (engine
->buffer
) {
2258 intel_stop_engine(engine
);
2259 WARN_ON(!IS_GEN2(dev_priv
) && (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2261 intel_unpin_ringbuffer_obj(engine
->buffer
);
2262 intel_ringbuffer_free(engine
->buffer
);
2263 engine
->buffer
= NULL
;
2266 if (engine
->cleanup
)
2267 engine
->cleanup(engine
);
2269 if (I915_NEED_GFX_HWS(dev_priv
)) {
2270 cleanup_status_page(engine
);
2272 WARN_ON(engine
->id
!= RCS
);
2273 cleanup_phys_status_page(engine
);
2276 i915_cmd_parser_fini_ring(engine
);
2277 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2278 intel_engine_fini_breadcrumbs(engine
);
2280 intel_ring_context_unpin(dev_priv
->kernel_context
, engine
);
2282 engine
->i915
= NULL
;
2285 int intel_engine_idle(struct intel_engine_cs
*engine
)
2287 struct drm_i915_gem_request
*req
;
2289 /* Wait upon the last request to be completed */
2290 if (list_empty(&engine
->request_list
))
2293 req
= list_entry(engine
->request_list
.prev
,
2294 struct drm_i915_gem_request
,
2297 /* Make sure we do not trigger any retires */
2298 return __i915_wait_request(req
,
2299 req
->i915
->mm
.interruptible
,
2303 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2307 /* Flush enough space to reduce the likelihood of waiting after
2308 * we start building the request - in which case we will just
2309 * have to repeat work.
2311 request
->reserved_space
+= LEGACY_REQUEST_SIZE
;
2313 request
->ringbuf
= request
->engine
->buffer
;
2315 ret
= intel_ring_begin(request
, 0);
2319 request
->reserved_space
-= LEGACY_REQUEST_SIZE
;
2323 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2325 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2326 struct intel_engine_cs
*engine
= req
->engine
;
2327 struct drm_i915_gem_request
*target
;
2329 intel_ring_update_space(ringbuf
);
2330 if (ringbuf
->space
>= bytes
)
2334 * Space is reserved in the ringbuffer for finalising the request,
2335 * as that cannot be allowed to fail. During request finalisation,
2336 * reserved_space is set to 0 to stop the overallocation and the
2337 * assumption is that then we never need to wait (which has the
2338 * risk of failing with EINTR).
2340 * See also i915_gem_request_alloc() and i915_add_request().
2342 GEM_BUG_ON(!req
->reserved_space
);
2344 list_for_each_entry(target
, &engine
->request_list
, list
) {
2348 * The request queue is per-engine, so can contain requests
2349 * from multiple ringbuffers. Here, we must ignore any that
2350 * aren't from the ringbuffer we're considering.
2352 if (target
->ringbuf
!= ringbuf
)
2355 /* Would completion of this request free enough space? */
2356 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
2362 if (WARN_ON(&target
->list
== &engine
->request_list
))
2365 return i915_wait_request(target
);
2368 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2370 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2371 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2372 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2373 int bytes
= num_dwords
* sizeof(u32
);
2374 int total_bytes
, wait_bytes
;
2375 bool need_wrap
= false;
2377 total_bytes
= bytes
+ req
->reserved_space
;
2379 if (unlikely(bytes
> remain_usable
)) {
2381 * Not enough space for the basic request. So need to flush
2382 * out the remainder and then wait for base + reserved.
2384 wait_bytes
= remain_actual
+ total_bytes
;
2386 } else if (unlikely(total_bytes
> remain_usable
)) {
2388 * The base request will fit but the reserved space
2389 * falls off the end. So we don't need an immediate wrap
2390 * and only need to effectively wait for the reserved
2391 * size space from the start of ringbuffer.
2393 wait_bytes
= remain_actual
+ req
->reserved_space
;
2395 /* No wrapping required, just waiting. */
2396 wait_bytes
= total_bytes
;
2399 if (wait_bytes
> ringbuf
->space
) {
2400 int ret
= wait_for_space(req
, wait_bytes
);
2404 intel_ring_update_space(ringbuf
);
2405 if (unlikely(ringbuf
->space
< wait_bytes
))
2409 if (unlikely(need_wrap
)) {
2410 GEM_BUG_ON(remain_actual
> ringbuf
->space
);
2411 GEM_BUG_ON(ringbuf
->tail
+ remain_actual
> ringbuf
->size
);
2413 /* Fill the tail with MI_NOOP */
2414 memset(ringbuf
->virtual_start
+ ringbuf
->tail
,
2417 ringbuf
->space
-= remain_actual
;
2420 ringbuf
->space
-= bytes
;
2421 GEM_BUG_ON(ringbuf
->space
< 0);
2425 /* Align the ring tail to a cacheline boundary */
2426 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2428 struct intel_engine_cs
*engine
= req
->engine
;
2429 int num_dwords
= (engine
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2432 if (num_dwords
== 0)
2435 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2436 ret
= intel_ring_begin(req
, num_dwords
);
2440 while (num_dwords
--)
2441 intel_ring_emit(engine
, MI_NOOP
);
2443 intel_ring_advance(engine
);
2448 void intel_ring_init_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
2450 struct drm_i915_private
*dev_priv
= engine
->i915
;
2452 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2453 * so long as the semaphore value in the register/page is greater
2454 * than the sync value), so whenever we reset the seqno,
2455 * so long as we reset the tracking semaphore value to 0, it will
2456 * always be before the next request's seqno. If we don't reset
2457 * the semaphore value, then when the seqno moves backwards all
2458 * future waits will complete instantly (causing rendering corruption).
2460 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
2461 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
2462 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
2463 if (HAS_VEBOX(dev_priv
))
2464 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
2466 if (dev_priv
->semaphore_obj
) {
2467 struct drm_i915_gem_object
*obj
= dev_priv
->semaphore_obj
;
2468 struct page
*page
= i915_gem_object_get_dirty_page(obj
, 0);
2469 void *semaphores
= kmap(page
);
2470 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
2471 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
2474 memset(engine
->semaphore
.sync_seqno
, 0,
2475 sizeof(engine
->semaphore
.sync_seqno
));
2477 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
2478 if (engine
->irq_seqno_barrier
)
2479 engine
->irq_seqno_barrier(engine
);
2480 engine
->last_submitted_seqno
= seqno
;
2482 engine
->hangcheck
.seqno
= seqno
;
2484 /* After manually advancing the seqno, fake the interrupt in case
2485 * there are any waiters for that seqno.
2488 intel_engine_wakeup(engine
);
2492 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*engine
,
2495 struct drm_i915_private
*dev_priv
= engine
->i915
;
2497 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
2499 /* Every tail move must follow the sequence below */
2501 /* Disable notification that the ring is IDLE. The GT
2502 * will then assume that it is busy and bring it out of rc6.
2504 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2505 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2507 /* Clear the context id. Here be magic! */
2508 I915_WRITE64_FW(GEN6_BSD_RNCID
, 0x0);
2510 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2511 if (intel_wait_for_register_fw(dev_priv
,
2512 GEN6_BSD_SLEEP_PSMI_CONTROL
,
2513 GEN6_BSD_SLEEP_INDICATOR
,
2516 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2518 /* Now that the ring is fully powered up, update the tail */
2519 I915_WRITE_FW(RING_TAIL(engine
->mmio_base
), value
);
2520 POSTING_READ_FW(RING_TAIL(engine
->mmio_base
));
2522 /* Let the ring send IDLE messages to the GT again,
2523 * and so let it sleep to conserve power when idle.
2525 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2526 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2528 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
2531 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2532 u32 invalidate
, u32 flush
)
2534 struct intel_engine_cs
*engine
= req
->engine
;
2538 ret
= intel_ring_begin(req
, 4);
2543 if (INTEL_GEN(req
->i915
) >= 8)
2546 /* We always require a command barrier so that subsequent
2547 * commands, such as breadcrumb interrupts, are strictly ordered
2548 * wrt the contents of the write cache being flushed to memory
2549 * (and thus being coherent from the CPU).
2551 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2554 * Bspec vol 1c.5 - video engine command streamer:
2555 * "If ENABLED, all TLBs will be invalidated once the flush
2556 * operation is complete. This bit is only valid when the
2557 * Post-Sync Operation field is a value of 1h or 3h."
2559 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2560 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2562 intel_ring_emit(engine
, cmd
);
2563 intel_ring_emit(engine
,
2564 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2565 if (INTEL_GEN(req
->i915
) >= 8) {
2566 intel_ring_emit(engine
, 0); /* upper addr */
2567 intel_ring_emit(engine
, 0); /* value */
2569 intel_ring_emit(engine
, 0);
2570 intel_ring_emit(engine
, MI_NOOP
);
2572 intel_ring_advance(engine
);
2577 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2578 u64 offset
, u32 len
,
2579 unsigned dispatch_flags
)
2581 struct intel_engine_cs
*engine
= req
->engine
;
2582 bool ppgtt
= USES_PPGTT(engine
->dev
) &&
2583 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2586 ret
= intel_ring_begin(req
, 4);
2590 /* FIXME(BDW): Address space and security selectors. */
2591 intel_ring_emit(engine
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2592 (dispatch_flags
& I915_DISPATCH_RS
?
2593 MI_BATCH_RESOURCE_STREAMER
: 0));
2594 intel_ring_emit(engine
, lower_32_bits(offset
));
2595 intel_ring_emit(engine
, upper_32_bits(offset
));
2596 intel_ring_emit(engine
, MI_NOOP
);
2597 intel_ring_advance(engine
);
2603 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2604 u64 offset
, u32 len
,
2605 unsigned dispatch_flags
)
2607 struct intel_engine_cs
*engine
= req
->engine
;
2610 ret
= intel_ring_begin(req
, 2);
2614 intel_ring_emit(engine
,
2615 MI_BATCH_BUFFER_START
|
2616 (dispatch_flags
& I915_DISPATCH_SECURE
?
2617 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2618 (dispatch_flags
& I915_DISPATCH_RS
?
2619 MI_BATCH_RESOURCE_STREAMER
: 0));
2620 /* bit0-7 is the length on GEN6+ */
2621 intel_ring_emit(engine
, offset
);
2622 intel_ring_advance(engine
);
2628 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2629 u64 offset
, u32 len
,
2630 unsigned dispatch_flags
)
2632 struct intel_engine_cs
*engine
= req
->engine
;
2635 ret
= intel_ring_begin(req
, 2);
2639 intel_ring_emit(engine
,
2640 MI_BATCH_BUFFER_START
|
2641 (dispatch_flags
& I915_DISPATCH_SECURE
?
2642 0 : MI_BATCH_NON_SECURE_I965
));
2643 /* bit0-7 is the length on GEN6+ */
2644 intel_ring_emit(engine
, offset
);
2645 intel_ring_advance(engine
);
2650 /* Blitter support (SandyBridge+) */
2652 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2653 u32 invalidate
, u32 flush
)
2655 struct intel_engine_cs
*engine
= req
->engine
;
2659 ret
= intel_ring_begin(req
, 4);
2664 if (INTEL_GEN(req
->i915
) >= 8)
2667 /* We always require a command barrier so that subsequent
2668 * commands, such as breadcrumb interrupts, are strictly ordered
2669 * wrt the contents of the write cache being flushed to memory
2670 * (and thus being coherent from the CPU).
2672 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2675 * Bspec vol 1c.3 - blitter engine command streamer:
2676 * "If ENABLED, all TLBs will be invalidated once the flush
2677 * operation is complete. This bit is only valid when the
2678 * Post-Sync Operation field is a value of 1h or 3h."
2680 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2681 cmd
|= MI_INVALIDATE_TLB
;
2682 intel_ring_emit(engine
, cmd
);
2683 intel_ring_emit(engine
,
2684 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2685 if (INTEL_GEN(req
->i915
) >= 8) {
2686 intel_ring_emit(engine
, 0); /* upper addr */
2687 intel_ring_emit(engine
, 0); /* value */
2689 intel_ring_emit(engine
, 0);
2690 intel_ring_emit(engine
, MI_NOOP
);
2692 intel_ring_advance(engine
);
2697 static void intel_ring_init_semaphores(struct drm_i915_private
*dev_priv
,
2698 struct intel_engine_cs
*engine
)
2700 struct drm_i915_gem_object
*obj
;
2703 if (!i915_semaphore_is_enabled(dev_priv
))
2706 if (INTEL_GEN(dev_priv
) >= 8 && !dev_priv
->semaphore_obj
) {
2707 obj
= i915_gem_object_create(dev_priv
->dev
, 4096);
2709 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2710 i915
.semaphores
= 0;
2712 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2713 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2715 drm_gem_object_unreference(&obj
->base
);
2716 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2717 i915
.semaphores
= 0;
2719 dev_priv
->semaphore_obj
= obj
;
2724 if (!i915_semaphore_is_enabled(dev_priv
))
2727 if (INTEL_GEN(dev_priv
) >= 8) {
2728 u64 offset
= i915_gem_obj_ggtt_offset(dev_priv
->semaphore_obj
);
2730 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2731 engine
->semaphore
.signal
= gen8_xcs_signal
;
2733 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2736 if (i
!= engine
->id
)
2737 ring_offset
= offset
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, i
);
2739 ring_offset
= MI_SEMAPHORE_SYNC_INVALID
;
2741 engine
->semaphore
.signal_ggtt
[i
] = ring_offset
;
2743 } else if (INTEL_GEN(dev_priv
) >= 6) {
2744 engine
->semaphore
.sync_to
= gen6_ring_sync
;
2745 engine
->semaphore
.signal
= gen6_signal
;
2748 * The current semaphore is only applied on pre-gen8
2749 * platform. And there is no VCS2 ring on the pre-gen8
2750 * platform. So the semaphore between RCS and VCS2 is
2751 * initialized as INVALID. Gen8 will initialize the
2752 * sema between VCS2 and RCS later.
2754 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2755 static const struct {
2757 i915_reg_t mbox_reg
;
2758 } sem_data
[I915_NUM_ENGINES
][I915_NUM_ENGINES
] = {
2760 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RV
, .mbox_reg
= GEN6_VRSYNC
},
2761 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RB
, .mbox_reg
= GEN6_BRSYNC
},
2762 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RVE
, .mbox_reg
= GEN6_VERSYNC
},
2765 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VR
, .mbox_reg
= GEN6_RVSYNC
},
2766 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VB
, .mbox_reg
= GEN6_BVSYNC
},
2767 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VVE
, .mbox_reg
= GEN6_VEVSYNC
},
2770 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BR
, .mbox_reg
= GEN6_RBSYNC
},
2771 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BV
, .mbox_reg
= GEN6_VBSYNC
},
2772 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BVE
, .mbox_reg
= GEN6_VEBSYNC
},
2775 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VER
, .mbox_reg
= GEN6_RVESYNC
},
2776 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEV
, .mbox_reg
= GEN6_VVESYNC
},
2777 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEB
, .mbox_reg
= GEN6_BVESYNC
},
2781 i915_reg_t mbox_reg
;
2783 if (i
== engine
->id
|| i
== VCS2
) {
2784 wait_mbox
= MI_SEMAPHORE_SYNC_INVALID
;
2785 mbox_reg
= GEN6_NOSYNC
;
2787 wait_mbox
= sem_data
[engine
->id
][i
].wait_mbox
;
2788 mbox_reg
= sem_data
[engine
->id
][i
].mbox_reg
;
2791 engine
->semaphore
.mbox
.wait
[i
] = wait_mbox
;
2792 engine
->semaphore
.mbox
.signal
[i
] = mbox_reg
;
2797 static void intel_ring_init_irq(struct drm_i915_private
*dev_priv
,
2798 struct intel_engine_cs
*engine
)
2800 if (INTEL_GEN(dev_priv
) >= 8) {
2801 engine
->irq_enable
= gen8_irq_enable
;
2802 engine
->irq_disable
= gen8_irq_disable
;
2803 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2804 } else if (INTEL_GEN(dev_priv
) >= 6) {
2805 engine
->irq_enable
= gen6_irq_enable
;
2806 engine
->irq_disable
= gen6_irq_disable
;
2807 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2808 } else if (INTEL_GEN(dev_priv
) >= 5) {
2809 engine
->irq_enable
= gen5_irq_enable
;
2810 engine
->irq_disable
= gen5_irq_disable
;
2811 engine
->irq_seqno_barrier
= gen5_seqno_barrier
;
2812 } else if (INTEL_GEN(dev_priv
) >= 3) {
2813 engine
->irq_enable
= i9xx_irq_enable
;
2814 engine
->irq_disable
= i9xx_irq_disable
;
2816 engine
->irq_enable
= i8xx_irq_enable
;
2817 engine
->irq_disable
= i8xx_irq_disable
;
2821 static void intel_ring_default_vfuncs(struct drm_i915_private
*dev_priv
,
2822 struct intel_engine_cs
*engine
)
2824 engine
->init_hw
= init_ring_common
;
2825 engine
->write_tail
= ring_write_tail
;
2827 engine
->add_request
= i9xx_add_request
;
2828 if (INTEL_GEN(dev_priv
) >= 6)
2829 engine
->add_request
= gen6_add_request
;
2831 if (INTEL_GEN(dev_priv
) >= 8)
2832 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2833 else if (INTEL_GEN(dev_priv
) >= 6)
2834 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2835 else if (INTEL_GEN(dev_priv
) >= 4)
2836 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2837 else if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
2838 engine
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2840 engine
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2842 intel_ring_init_irq(dev_priv
, engine
);
2843 intel_ring_init_semaphores(dev_priv
, engine
);
2846 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2849 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2852 engine
->name
= "render ring";
2854 engine
->exec_id
= I915_EXEC_RENDER
;
2856 engine
->mmio_base
= RENDER_RING_BASE
;
2858 intel_ring_default_vfuncs(dev_priv
, engine
);
2860 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2861 if (HAS_L3_DPF(dev_priv
))
2862 engine
->irq_keep_mask
= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2864 if (INTEL_GEN(dev_priv
) >= 8) {
2865 engine
->init_context
= intel_rcs_ctx_init
;
2866 engine
->add_request
= gen8_render_add_request
;
2867 engine
->flush
= gen8_render_ring_flush
;
2868 if (i915_semaphore_is_enabled(dev_priv
))
2869 engine
->semaphore
.signal
= gen8_rcs_signal
;
2870 } else if (INTEL_GEN(dev_priv
) >= 6) {
2871 engine
->init_context
= intel_rcs_ctx_init
;
2872 engine
->flush
= gen7_render_ring_flush
;
2873 if (IS_GEN6(dev_priv
))
2874 engine
->flush
= gen6_render_ring_flush
;
2875 } else if (IS_GEN5(dev_priv
)) {
2876 engine
->flush
= gen4_render_ring_flush
;
2878 if (INTEL_GEN(dev_priv
) < 4)
2879 engine
->flush
= gen2_render_ring_flush
;
2881 engine
->flush
= gen4_render_ring_flush
;
2882 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2885 if (IS_HASWELL(dev_priv
))
2886 engine
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2888 engine
->init_hw
= init_render_ring
;
2889 engine
->cleanup
= render_ring_cleanup
;
2891 ret
= intel_init_ring_buffer(dev
, engine
);
2895 if (INTEL_GEN(dev_priv
) >= 6) {
2896 ret
= intel_init_pipe_control(engine
, 4096);
2899 } else if (HAS_BROKEN_CS_TLB(dev_priv
)) {
2900 ret
= intel_init_pipe_control(engine
, I830_WA_SIZE
);
2908 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2911 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2913 engine
->name
= "bsd ring";
2915 engine
->exec_id
= I915_EXEC_BSD
;
2918 intel_ring_default_vfuncs(dev_priv
, engine
);
2920 if (INTEL_GEN(dev_priv
) >= 6) {
2921 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2922 /* gen6 bsd needs a special wa for tail updates */
2923 if (IS_GEN6(dev_priv
))
2924 engine
->write_tail
= gen6_bsd_ring_write_tail
;
2925 engine
->flush
= gen6_bsd_ring_flush
;
2926 if (INTEL_GEN(dev_priv
) >= 8)
2927 engine
->irq_enable_mask
=
2928 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2930 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2932 engine
->mmio_base
= BSD_RING_BASE
;
2933 engine
->flush
= bsd_ring_flush
;
2934 if (IS_GEN5(dev_priv
))
2935 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2937 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2940 return intel_init_ring_buffer(dev
, engine
);
2944 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2946 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2949 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2951 engine
->name
= "bsd2 ring";
2953 engine
->exec_id
= I915_EXEC_BSD
;
2955 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2957 intel_ring_default_vfuncs(dev_priv
, engine
);
2959 engine
->flush
= gen6_bsd_ring_flush
;
2960 engine
->irq_enable_mask
=
2961 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2963 return intel_init_ring_buffer(dev
, engine
);
2966 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2969 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2971 engine
->name
= "blitter ring";
2973 engine
->exec_id
= I915_EXEC_BLT
;
2975 engine
->mmio_base
= BLT_RING_BASE
;
2977 intel_ring_default_vfuncs(dev_priv
, engine
);
2979 engine
->flush
= gen6_ring_flush
;
2980 if (INTEL_GEN(dev_priv
) >= 8)
2981 engine
->irq_enable_mask
=
2982 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2984 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2986 return intel_init_ring_buffer(dev
, engine
);
2989 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2992 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
2994 engine
->name
= "video enhancement ring";
2996 engine
->exec_id
= I915_EXEC_VEBOX
;
2998 engine
->mmio_base
= VEBOX_RING_BASE
;
3000 intel_ring_default_vfuncs(dev_priv
, engine
);
3002 engine
->flush
= gen6_ring_flush
;
3004 if (INTEL_GEN(dev_priv
) >= 8) {
3005 engine
->irq_enable_mask
=
3006 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3008 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3009 engine
->irq_enable
= hsw_vebox_irq_enable
;
3010 engine
->irq_disable
= hsw_vebox_irq_disable
;
3013 return intel_init_ring_buffer(dev
, engine
);
3017 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3019 struct intel_engine_cs
*engine
= req
->engine
;
3022 if (!engine
->gpu_caches_dirty
)
3025 ret
= engine
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3029 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3031 engine
->gpu_caches_dirty
= false;
3036 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3038 struct intel_engine_cs
*engine
= req
->engine
;
3039 uint32_t flush_domains
;
3043 if (engine
->gpu_caches_dirty
)
3044 flush_domains
= I915_GEM_GPU_DOMAINS
;
3046 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3050 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3052 engine
->gpu_caches_dirty
= false;
3057 intel_stop_engine(struct intel_engine_cs
*engine
)
3061 if (!intel_engine_initialized(engine
))
3064 ret
= intel_engine_idle(engine
);
3066 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",