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drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <linux/log2.h>
31 #include <drm/drmP.h>
32 #include "i915_drv.h"
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
39 */
40 #define LEGACY_REQUEST_SIZE 200
41
42 int __intel_ring_space(int head, int tail, int size)
43 {
44 int space = head - tail;
45 if (space <= 0)
46 space += size;
47 return space - I915_RING_FREE_SPACE;
48 }
49
50 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
51 {
52 if (ringbuf->last_retired_head != -1) {
53 ringbuf->head = ringbuf->last_retired_head;
54 ringbuf->last_retired_head = -1;
55 }
56
57 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
58 ringbuf->tail, ringbuf->size);
59 }
60
61 bool intel_engine_stopped(struct intel_engine_cs *engine)
62 {
63 struct drm_i915_private *dev_priv = engine->i915;
64 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
65 }
66
67 static void __intel_ring_advance(struct intel_engine_cs *engine)
68 {
69 struct intel_ringbuffer *ringbuf = engine->buffer;
70 ringbuf->tail &= ringbuf->size - 1;
71 if (intel_engine_stopped(engine))
72 return;
73 engine->write_tail(engine, ringbuf->tail);
74 }
75
76 static int
77 gen2_render_ring_flush(struct drm_i915_gem_request *req,
78 u32 invalidate_domains,
79 u32 flush_domains)
80 {
81 struct intel_engine_cs *engine = req->engine;
82 u32 cmd;
83 int ret;
84
85 cmd = MI_FLUSH;
86 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
87 cmd |= MI_NO_WRITE_FLUSH;
88
89 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
90 cmd |= MI_READ_FLUSH;
91
92 ret = intel_ring_begin(req, 2);
93 if (ret)
94 return ret;
95
96 intel_ring_emit(engine, cmd);
97 intel_ring_emit(engine, MI_NOOP);
98 intel_ring_advance(engine);
99
100 return 0;
101 }
102
103 static int
104 gen4_render_ring_flush(struct drm_i915_gem_request *req,
105 u32 invalidate_domains,
106 u32 flush_domains)
107 {
108 struct intel_engine_cs *engine = req->engine;
109 u32 cmd;
110 int ret;
111
112 /*
113 * read/write caches:
114 *
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
118 *
119 * read-only caches:
120 *
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
123 *
124 * I915_GEM_DOMAIN_COMMAND may not exist?
125 *
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
128 *
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
131 *
132 * TLBs:
133 *
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
138 */
139
140 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
141 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
142 cmd &= ~MI_NO_WRITE_FLUSH;
143 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
144 cmd |= MI_EXE_FLUSH;
145
146 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
147 (IS_G4X(req->i915) || IS_GEN5(req->i915)))
148 cmd |= MI_INVALIDATE_ISP;
149
150 ret = intel_ring_begin(req, 2);
151 if (ret)
152 return ret;
153
154 intel_ring_emit(engine, cmd);
155 intel_ring_emit(engine, MI_NOOP);
156 intel_ring_advance(engine);
157
158 return 0;
159 }
160
161 /**
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
165 *
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
169 * 0.
170 *
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
173 *
174 * And the workaround for these two requires this workaround first:
175 *
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
178 * flushes.
179 *
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
182 * volume 2 part 1:
183 *
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
191 *
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
197 */
198 static int
199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
200 {
201 struct intel_engine_cs *engine = req->engine;
202 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
203 int ret;
204
205 ret = intel_ring_begin(req, 6);
206 if (ret)
207 return ret;
208
209 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
211 PIPE_CONTROL_STALL_AT_SCOREBOARD);
212 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(engine, 0); /* low dword */
214 intel_ring_emit(engine, 0); /* high dword */
215 intel_ring_emit(engine, MI_NOOP);
216 intel_ring_advance(engine);
217
218 ret = intel_ring_begin(req, 6);
219 if (ret)
220 return ret;
221
222 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
224 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
225 intel_ring_emit(engine, 0);
226 intel_ring_emit(engine, 0);
227 intel_ring_emit(engine, MI_NOOP);
228 intel_ring_advance(engine);
229
230 return 0;
231 }
232
233 static int
234 gen6_render_ring_flush(struct drm_i915_gem_request *req,
235 u32 invalidate_domains, u32 flush_domains)
236 {
237 struct intel_engine_cs *engine = req->engine;
238 u32 flags = 0;
239 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
240 int ret;
241
242 /* Force SNB workarounds for PIPE_CONTROL flushes */
243 ret = intel_emit_post_sync_nonzero_flush(req);
244 if (ret)
245 return ret;
246
247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
249 * impact.
250 */
251 if (flush_domains) {
252 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
253 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
254 /*
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
257 */
258 flags |= PIPE_CONTROL_CS_STALL;
259 }
260 if (invalidate_domains) {
261 flags |= PIPE_CONTROL_TLB_INVALIDATE;
262 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
263 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
264 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
267 /*
268 * TLB invalidate requires a post-sync write.
269 */
270 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
271 }
272
273 ret = intel_ring_begin(req, 4);
274 if (ret)
275 return ret;
276
277 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine, flags);
279 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
280 intel_ring_emit(engine, 0);
281 intel_ring_advance(engine);
282
283 return 0;
284 }
285
286 static int
287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
288 {
289 struct intel_engine_cs *engine = req->engine;
290 int ret;
291
292 ret = intel_ring_begin(req, 4);
293 if (ret)
294 return ret;
295
296 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
298 PIPE_CONTROL_STALL_AT_SCOREBOARD);
299 intel_ring_emit(engine, 0);
300 intel_ring_emit(engine, 0);
301 intel_ring_advance(engine);
302
303 return 0;
304 }
305
306 static int
307 gen7_render_ring_flush(struct drm_i915_gem_request *req,
308 u32 invalidate_domains, u32 flush_domains)
309 {
310 struct intel_engine_cs *engine = req->engine;
311 u32 flags = 0;
312 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
313 int ret;
314
315 /*
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
318 *
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
322 */
323 flags |= PIPE_CONTROL_CS_STALL;
324
325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
327 * impact.
328 */
329 if (flush_domains) {
330 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
331 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
332 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
333 flags |= PIPE_CONTROL_FLUSH_ENABLE;
334 }
335 if (invalidate_domains) {
336 flags |= PIPE_CONTROL_TLB_INVALIDATE;
337 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
338 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
339 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
343 /*
344 * TLB invalidate requires a post-sync write.
345 */
346 flags |= PIPE_CONTROL_QW_WRITE;
347 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
348
349 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
350
351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
354 gen7_render_ring_cs_stall_wa(req);
355 }
356
357 ret = intel_ring_begin(req, 4);
358 if (ret)
359 return ret;
360
361 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine, flags);
363 intel_ring_emit(engine, scratch_addr);
364 intel_ring_emit(engine, 0);
365 intel_ring_advance(engine);
366
367 return 0;
368 }
369
370 static int
371 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
372 u32 flags, u32 scratch_addr)
373 {
374 struct intel_engine_cs *engine = req->engine;
375 int ret;
376
377 ret = intel_ring_begin(req, 6);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine, flags);
383 intel_ring_emit(engine, scratch_addr);
384 intel_ring_emit(engine, 0);
385 intel_ring_emit(engine, 0);
386 intel_ring_emit(engine, 0);
387 intel_ring_advance(engine);
388
389 return 0;
390 }
391
392 static int
393 gen8_render_ring_flush(struct drm_i915_gem_request *req,
394 u32 invalidate_domains, u32 flush_domains)
395 {
396 u32 flags = 0;
397 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
398 int ret;
399
400 flags |= PIPE_CONTROL_CS_STALL;
401
402 if (flush_domains) {
403 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
404 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
405 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
406 flags |= PIPE_CONTROL_FLUSH_ENABLE;
407 }
408 if (invalidate_domains) {
409 flags |= PIPE_CONTROL_TLB_INVALIDATE;
410 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
412 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_QW_WRITE;
416 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
417
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
419 ret = gen8_emit_pipe_control(req,
420 PIPE_CONTROL_CS_STALL |
421 PIPE_CONTROL_STALL_AT_SCOREBOARD,
422 0);
423 if (ret)
424 return ret;
425 }
426
427 return gen8_emit_pipe_control(req, flags, scratch_addr);
428 }
429
430 static void ring_write_tail(struct intel_engine_cs *engine,
431 u32 value)
432 {
433 struct drm_i915_private *dev_priv = engine->i915;
434 I915_WRITE_TAIL(engine, value);
435 }
436
437 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
438 {
439 struct drm_i915_private *dev_priv = engine->i915;
440 u64 acthd;
441
442 if (INTEL_GEN(dev_priv) >= 8)
443 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
444 RING_ACTHD_UDW(engine->mmio_base));
445 else if (INTEL_GEN(dev_priv) >= 4)
446 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
447 else
448 acthd = I915_READ(ACTHD);
449
450 return acthd;
451 }
452
453 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
454 {
455 struct drm_i915_private *dev_priv = engine->i915;
456 u32 addr;
457
458 addr = dev_priv->status_page_dmah->busaddr;
459 if (INTEL_GEN(dev_priv) >= 4)
460 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
461 I915_WRITE(HWS_PGA, addr);
462 }
463
464 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
465 {
466 struct drm_i915_private *dev_priv = engine->i915;
467 i915_reg_t mmio;
468
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
471 */
472 if (IS_GEN7(dev_priv)) {
473 switch (engine->id) {
474 case RCS:
475 mmio = RENDER_HWS_PGA_GEN7;
476 break;
477 case BCS:
478 mmio = BLT_HWS_PGA_GEN7;
479 break;
480 /*
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
483 */
484 case VCS2:
485 case VCS:
486 mmio = BSD_HWS_PGA_GEN7;
487 break;
488 case VECS:
489 mmio = VEBOX_HWS_PGA_GEN7;
490 break;
491 }
492 } else if (IS_GEN6(dev_priv)) {
493 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
494 } else {
495 /* XXX: gen8 returns to sanity */
496 mmio = RING_HWS_PGA(engine->mmio_base);
497 }
498
499 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
500 POSTING_READ(mmio);
501
502 /*
503 * Flush the TLB for this page
504 *
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
508 */
509 if (IS_GEN(dev_priv, 6, 7)) {
510 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
511
512 /* ring should be idle before issuing a sync flush*/
513 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
514
515 I915_WRITE(reg,
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
517 INSTPM_SYNC_FLUSH));
518 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
519 1000))
520 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
521 engine->name);
522 }
523 }
524
525 static bool stop_ring(struct intel_engine_cs *engine)
526 {
527 struct drm_i915_private *dev_priv = engine->i915;
528
529 if (!IS_GEN2(dev_priv)) {
530 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
531 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
532 DRM_ERROR("%s : timed out trying to stop ring\n",
533 engine->name);
534 /* Sometimes we observe that the idle flag is not
535 * set even though the ring is empty. So double
536 * check before giving up.
537 */
538 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
539 return false;
540 }
541 }
542
543 I915_WRITE_CTL(engine, 0);
544 I915_WRITE_HEAD(engine, 0);
545 engine->write_tail(engine, 0);
546
547 if (!IS_GEN2(dev_priv)) {
548 (void)I915_READ_CTL(engine);
549 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
550 }
551
552 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
553 }
554
555 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
556 {
557 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
558 }
559
560 static int init_ring_common(struct intel_engine_cs *engine)
561 {
562 struct drm_i915_private *dev_priv = engine->i915;
563 struct intel_ringbuffer *ringbuf = engine->buffer;
564 struct drm_i915_gem_object *obj = ringbuf->obj;
565 int ret = 0;
566
567 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
568
569 if (!stop_ring(engine)) {
570 /* G45 ring initialization often fails to reset head to zero */
571 DRM_DEBUG_KMS("%s head not reset to zero "
572 "ctl %08x head %08x tail %08x start %08x\n",
573 engine->name,
574 I915_READ_CTL(engine),
575 I915_READ_HEAD(engine),
576 I915_READ_TAIL(engine),
577 I915_READ_START(engine));
578
579 if (!stop_ring(engine)) {
580 DRM_ERROR("failed to set %s head to zero "
581 "ctl %08x head %08x tail %08x start %08x\n",
582 engine->name,
583 I915_READ_CTL(engine),
584 I915_READ_HEAD(engine),
585 I915_READ_TAIL(engine),
586 I915_READ_START(engine));
587 ret = -EIO;
588 goto out;
589 }
590 }
591
592 if (I915_NEED_GFX_HWS(dev_priv))
593 intel_ring_setup_status_page(engine);
594 else
595 ring_setup_phys_status_page(engine);
596
597 /* Enforce ordering by reading HEAD register back */
598 I915_READ_HEAD(engine);
599
600 /* Initialize the ring. This must happen _after_ we've cleared the ring
601 * registers with the above sequence (the readback of the HEAD registers
602 * also enforces ordering), otherwise the hw might lose the new ring
603 * register values. */
604 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
605
606 /* WaClearRingBufHeadRegAtInit:ctg,elk */
607 if (I915_READ_HEAD(engine))
608 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
609 engine->name, I915_READ_HEAD(engine));
610 I915_WRITE_HEAD(engine, 0);
611 (void)I915_READ_HEAD(engine);
612
613 I915_WRITE_CTL(engine,
614 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
615 | RING_VALID);
616
617 /* If the head is still not zero, the ring is dead */
618 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
619 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
620 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
621 DRM_ERROR("%s initialization failed "
622 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
623 engine->name,
624 I915_READ_CTL(engine),
625 I915_READ_CTL(engine) & RING_VALID,
626 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
627 I915_READ_START(engine),
628 (unsigned long)i915_gem_obj_ggtt_offset(obj));
629 ret = -EIO;
630 goto out;
631 }
632
633 ringbuf->last_retired_head = -1;
634 ringbuf->head = I915_READ_HEAD(engine);
635 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
636 intel_ring_update_space(ringbuf);
637
638 intel_engine_init_hangcheck(engine);
639
640 out:
641 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
642
643 return ret;
644 }
645
646 void
647 intel_fini_pipe_control(struct intel_engine_cs *engine)
648 {
649 if (engine->scratch.obj == NULL)
650 return;
651
652 if (INTEL_GEN(engine->i915) >= 5) {
653 kunmap(sg_page(engine->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(engine->scratch.obj);
655 }
656
657 drm_gem_object_unreference(&engine->scratch.obj->base);
658 engine->scratch.obj = NULL;
659 }
660
661 int
662 intel_init_pipe_control(struct intel_engine_cs *engine)
663 {
664 int ret;
665
666 WARN_ON(engine->scratch.obj);
667
668 engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
669 if (IS_ERR(engine->scratch.obj)) {
670 DRM_ERROR("Failed to allocate seqno page\n");
671 ret = PTR_ERR(engine->scratch.obj);
672 engine->scratch.obj = NULL;
673 goto err;
674 }
675
676 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
677 I915_CACHE_LLC);
678 if (ret)
679 goto err_unref;
680
681 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
682 if (ret)
683 goto err_unref;
684
685 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
686 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
687 if (engine->scratch.cpu_page == NULL) {
688 ret = -ENOMEM;
689 goto err_unpin;
690 }
691
692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
693 engine->name, engine->scratch.gtt_offset);
694 return 0;
695
696 err_unpin:
697 i915_gem_object_ggtt_unpin(engine->scratch.obj);
698 err_unref:
699 drm_gem_object_unreference(&engine->scratch.obj->base);
700 err:
701 return ret;
702 }
703
704 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
705 {
706 struct intel_engine_cs *engine = req->engine;
707 struct i915_workarounds *w = &req->i915->workarounds;
708 int ret, i;
709
710 if (w->count == 0)
711 return 0;
712
713 engine->gpu_caches_dirty = true;
714 ret = intel_ring_flush_all_caches(req);
715 if (ret)
716 return ret;
717
718 ret = intel_ring_begin(req, (w->count * 2 + 2));
719 if (ret)
720 return ret;
721
722 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
723 for (i = 0; i < w->count; i++) {
724 intel_ring_emit_reg(engine, w->reg[i].addr);
725 intel_ring_emit(engine, w->reg[i].value);
726 }
727 intel_ring_emit(engine, MI_NOOP);
728
729 intel_ring_advance(engine);
730
731 engine->gpu_caches_dirty = true;
732 ret = intel_ring_flush_all_caches(req);
733 if (ret)
734 return ret;
735
736 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
737
738 return 0;
739 }
740
741 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
742 {
743 int ret;
744
745 ret = intel_ring_workarounds_emit(req);
746 if (ret != 0)
747 return ret;
748
749 ret = i915_gem_render_state_init(req);
750 if (ret)
751 return ret;
752
753 return 0;
754 }
755
756 static int wa_add(struct drm_i915_private *dev_priv,
757 i915_reg_t addr,
758 const u32 mask, const u32 val)
759 {
760 const u32 idx = dev_priv->workarounds.count;
761
762 if (WARN_ON(idx >= I915_MAX_WA_REGS))
763 return -ENOSPC;
764
765 dev_priv->workarounds.reg[idx].addr = addr;
766 dev_priv->workarounds.reg[idx].value = val;
767 dev_priv->workarounds.reg[idx].mask = mask;
768
769 dev_priv->workarounds.count++;
770
771 return 0;
772 }
773
774 #define WA_REG(addr, mask, val) do { \
775 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
776 if (r) \
777 return r; \
778 } while (0)
779
780 #define WA_SET_BIT_MASKED(addr, mask) \
781 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
782
783 #define WA_CLR_BIT_MASKED(addr, mask) \
784 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
785
786 #define WA_SET_FIELD_MASKED(addr, mask, value) \
787 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
788
789 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
790 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
791
792 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
793
794 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
795 i915_reg_t reg)
796 {
797 struct drm_i915_private *dev_priv = engine->i915;
798 struct i915_workarounds *wa = &dev_priv->workarounds;
799 const uint32_t index = wa->hw_whitelist_count[engine->id];
800
801 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
802 return -EINVAL;
803
804 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
805 i915_mmio_reg_offset(reg));
806 wa->hw_whitelist_count[engine->id]++;
807
808 return 0;
809 }
810
811 static int gen8_init_workarounds(struct intel_engine_cs *engine)
812 {
813 struct drm_i915_private *dev_priv = engine->i915;
814
815 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
816
817 /* WaDisableAsyncFlipPerfMode:bdw,chv */
818 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
819
820 /* WaDisablePartialInstShootdown:bdw,chv */
821 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
822 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
823
824 /* Use Force Non-Coherent whenever executing a 3D context. This is a
825 * workaround for for a possible hang in the unlikely event a TLB
826 * invalidation occurs during a PSD flush.
827 */
828 /* WaForceEnableNonCoherent:bdw,chv */
829 /* WaHdcDisableFetchWhenMasked:bdw,chv */
830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
831 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
832 HDC_FORCE_NON_COHERENT);
833
834 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
835 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
836 * polygons in the same 8x4 pixel/sample area to be processed without
837 * stalling waiting for the earlier ones to write to Hierarchical Z
838 * buffer."
839 *
840 * This optimization is off by default for BDW and CHV; turn it on.
841 */
842 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
843
844 /* Wa4x4STCOptimizationDisable:bdw,chv */
845 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
846
847 /*
848 * BSpec recommends 8x4 when MSAA is used,
849 * however in practice 16x4 seems fastest.
850 *
851 * Note that PS/WM thread counts depend on the WIZ hashing
852 * disable bit, which we don't touch here, but it's good
853 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
854 */
855 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
856 GEN6_WIZ_HASHING_MASK,
857 GEN6_WIZ_HASHING_16x4);
858
859 return 0;
860 }
861
862 static int bdw_init_workarounds(struct intel_engine_cs *engine)
863 {
864 struct drm_i915_private *dev_priv = engine->i915;
865 int ret;
866
867 ret = gen8_init_workarounds(engine);
868 if (ret)
869 return ret;
870
871 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
872 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
873
874 /* WaDisableDopClockGating:bdw */
875 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
876 DOP_CLOCK_GATING_DISABLE);
877
878 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
879 GEN8_SAMPLER_POWER_BYPASS_DIS);
880
881 WA_SET_BIT_MASKED(HDC_CHICKEN0,
882 /* WaForceContextSaveRestoreNonCoherent:bdw */
883 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
884 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
885 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
886
887 return 0;
888 }
889
890 static int chv_init_workarounds(struct intel_engine_cs *engine)
891 {
892 struct drm_i915_private *dev_priv = engine->i915;
893 int ret;
894
895 ret = gen8_init_workarounds(engine);
896 if (ret)
897 return ret;
898
899 /* WaDisableThreadStallDopClockGating:chv */
900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
901
902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
904
905 return 0;
906 }
907
908 static int gen9_init_workarounds(struct intel_engine_cs *engine)
909 {
910 struct drm_i915_private *dev_priv = engine->i915;
911 int ret;
912
913 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
914 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
915 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
916
917 /* WaDisableKillLogic:bxt,skl,kbl */
918 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
919 ECOCHK_DIS_TLB);
920
921 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
922 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
923 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
924 FLOW_CONTROL_ENABLE |
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
926
927 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
930
931 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
932 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
933 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
935 GEN9_DG_MIRROR_FIX_ENABLE);
936
937 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
938 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
939 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
940 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
941 GEN9_RHWO_OPTIMIZATION_DISABLE);
942 /*
943 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
944 * but we do that in per ctx batchbuffer as there is an issue
945 * with this register not getting restored on ctx restore
946 */
947 }
948
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
950 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
952 GEN9_ENABLE_YV12_BUGFIX |
953 GEN9_ENABLE_GPGPU_PREEMPTION);
954
955 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
956 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
957 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
958 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
959
960 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
961 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
962 GEN9_CCS_TLB_PREFETCH_ENABLE);
963
964 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
965 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
966 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
967 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
968 PIXEL_MASK_CAMMING_DISABLE);
969
970 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
971 WA_SET_BIT_MASKED(HDC_CHICKEN0,
972 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
973 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
974
975 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
976 * both tied to WaForceContextSaveRestoreNonCoherent
977 * in some hsds for skl. We keep the tie for all gen9. The
978 * documentation is a bit hazy and so we want to get common behaviour,
979 * even though there is no clear evidence we would need both on kbl/bxt.
980 * This area has been source of system hangs so we play it safe
981 * and mimic the skl regardless of what bspec says.
982 *
983 * Use Force Non-Coherent whenever executing a 3D context. This
984 * is a workaround for a possible hang in the unlikely event
985 * a TLB invalidation occurs during a PSD flush.
986 */
987
988 /* WaForceEnableNonCoherent:skl,bxt,kbl */
989 WA_SET_BIT_MASKED(HDC_CHICKEN0,
990 HDC_FORCE_NON_COHERENT);
991
992 /* WaDisableHDCInvalidation:skl,bxt,kbl */
993 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
994 BDW_DISABLE_HDC_INVALIDATION);
995
996 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
997 if (IS_SKYLAKE(dev_priv) ||
998 IS_KABYLAKE(dev_priv) ||
999 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1000 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1001 GEN8_SAMPLER_POWER_BYPASS_DIS);
1002
1003 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1004 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1005
1006 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1007 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1008 GEN8_LQSC_FLUSH_COHERENT_LINES));
1009
1010 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1011 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1012 if (ret)
1013 return ret;
1014
1015 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1016 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1017 if (ret)
1018 return ret;
1019
1020 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1021 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1022 if (ret)
1023 return ret;
1024
1025 return 0;
1026 }
1027
1028 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1029 {
1030 struct drm_i915_private *dev_priv = engine->i915;
1031 u8 vals[3] = { 0, 0, 0 };
1032 unsigned int i;
1033
1034 for (i = 0; i < 3; i++) {
1035 u8 ss;
1036
1037 /*
1038 * Only consider slices where one, and only one, subslice has 7
1039 * EUs
1040 */
1041 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1042 continue;
1043
1044 /*
1045 * subslice_7eu[i] != 0 (because of the check above) and
1046 * ss_max == 4 (maximum number of subslices possible per slice)
1047 *
1048 * -> 0 <= ss <= 3;
1049 */
1050 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1051 vals[i] = 3 - ss;
1052 }
1053
1054 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1055 return 0;
1056
1057 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1058 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1059 GEN9_IZ_HASHING_MASK(2) |
1060 GEN9_IZ_HASHING_MASK(1) |
1061 GEN9_IZ_HASHING_MASK(0),
1062 GEN9_IZ_HASHING(2, vals[2]) |
1063 GEN9_IZ_HASHING(1, vals[1]) |
1064 GEN9_IZ_HASHING(0, vals[0]));
1065
1066 return 0;
1067 }
1068
1069 static int skl_init_workarounds(struct intel_engine_cs *engine)
1070 {
1071 struct drm_i915_private *dev_priv = engine->i915;
1072 int ret;
1073
1074 ret = gen9_init_workarounds(engine);
1075 if (ret)
1076 return ret;
1077
1078 /*
1079 * Actual WA is to disable percontext preemption granularity control
1080 * until D0 which is the default case so this is equivalent to
1081 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1082 */
1083 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
1084 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1085 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1086 }
1087
1088 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
1089 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1090 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1091 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1092 }
1093
1094 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1095 * involving this register should also be added to WA batch as required.
1096 */
1097 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1098 /* WaDisableLSQCROPERFforOCL:skl */
1099 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1100 GEN8_LQSC_RO_PERF_DIS);
1101
1102 /* WaEnableGapsTsvCreditFix:skl */
1103 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1104 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1105 GEN9_GAPS_TSV_CREDIT_DISABLE));
1106 }
1107
1108 /* WaDisablePowerCompilerClockGating:skl */
1109 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1110 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1111 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1112
1113 /* WaBarrierPerformanceFixDisable:skl */
1114 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1115 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1116 HDC_FENCE_DEST_SLM_DISABLE |
1117 HDC_BARRIER_PERFORMANCE_DISABLE);
1118
1119 /* WaDisableSbeCacheDispatchPortSharing:skl */
1120 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1121 WA_SET_BIT_MASKED(
1122 GEN7_HALF_SLICE_CHICKEN1,
1123 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1124
1125 /* WaDisableGafsUnitClkGating:skl */
1126 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1127
1128 /* WaDisableLSQCROPERFforOCL:skl */
1129 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1130 if (ret)
1131 return ret;
1132
1133 return skl_tune_iz_hashing(engine);
1134 }
1135
1136 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1137 {
1138 struct drm_i915_private *dev_priv = engine->i915;
1139 int ret;
1140
1141 ret = gen9_init_workarounds(engine);
1142 if (ret)
1143 return ret;
1144
1145 /* WaStoreMultiplePTEenable:bxt */
1146 /* This is a requirement according to Hardware specification */
1147 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1148 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1149
1150 /* WaSetClckGatingDisableMedia:bxt */
1151 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1152 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1153 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1154 }
1155
1156 /* WaDisableThreadStallDopClockGating:bxt */
1157 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1158 STALL_DOP_GATING_DISABLE);
1159
1160 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1161 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1162 WA_SET_BIT_MASKED(
1163 GEN7_HALF_SLICE_CHICKEN1,
1164 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1165 }
1166
1167 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1168 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1169 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1170 /* WaDisableLSQCROPERFforOCL:bxt */
1171 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1172 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1173 if (ret)
1174 return ret;
1175
1176 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1177 if (ret)
1178 return ret;
1179 }
1180
1181 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1182 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1183 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1184 L3_HIGH_PRIO_CREDITS(2));
1185
1186 return 0;
1187 }
1188
1189 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1190 {
1191 struct drm_i915_private *dev_priv = engine->i915;
1192 int ret;
1193
1194 ret = gen9_init_workarounds(engine);
1195 if (ret)
1196 return ret;
1197
1198 /* WaEnableGapsTsvCreditFix:kbl */
1199 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1200 GEN9_GAPS_TSV_CREDIT_DISABLE));
1201
1202 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1203 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1204 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1205 HDC_FENCE_DEST_SLM_DISABLE);
1206
1207 return 0;
1208 }
1209
1210 int init_workarounds_ring(struct intel_engine_cs *engine)
1211 {
1212 struct drm_i915_private *dev_priv = engine->i915;
1213
1214 WARN_ON(engine->id != RCS);
1215
1216 dev_priv->workarounds.count = 0;
1217 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1218
1219 if (IS_BROADWELL(dev_priv))
1220 return bdw_init_workarounds(engine);
1221
1222 if (IS_CHERRYVIEW(dev_priv))
1223 return chv_init_workarounds(engine);
1224
1225 if (IS_SKYLAKE(dev_priv))
1226 return skl_init_workarounds(engine);
1227
1228 if (IS_BROXTON(dev_priv))
1229 return bxt_init_workarounds(engine);
1230
1231 if (IS_KABYLAKE(dev_priv))
1232 return kbl_init_workarounds(engine);
1233
1234 return 0;
1235 }
1236
1237 static int init_render_ring(struct intel_engine_cs *engine)
1238 {
1239 struct drm_i915_private *dev_priv = engine->i915;
1240 int ret = init_ring_common(engine);
1241 if (ret)
1242 return ret;
1243
1244 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1245 if (IS_GEN(dev_priv, 4, 6))
1246 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1247
1248 /* We need to disable the AsyncFlip performance optimisations in order
1249 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1250 * programmed to '1' on all products.
1251 *
1252 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1253 */
1254 if (IS_GEN(dev_priv, 6, 7))
1255 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1256
1257 /* Required for the hardware to program scanline values for waiting */
1258 /* WaEnableFlushTlbInvalidationMode:snb */
1259 if (IS_GEN6(dev_priv))
1260 I915_WRITE(GFX_MODE,
1261 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1262
1263 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1264 if (IS_GEN7(dev_priv))
1265 I915_WRITE(GFX_MODE_GEN7,
1266 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1267 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1268
1269 if (IS_GEN6(dev_priv)) {
1270 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1271 * "If this bit is set, STCunit will have LRA as replacement
1272 * policy. [...] This bit must be reset. LRA replacement
1273 * policy is not supported."
1274 */
1275 I915_WRITE(CACHE_MODE_0,
1276 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1277 }
1278
1279 if (IS_GEN(dev_priv, 6, 7))
1280 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1281
1282 if (HAS_L3_DPF(dev_priv))
1283 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1284
1285 return init_workarounds_ring(engine);
1286 }
1287
1288 static void render_ring_cleanup(struct intel_engine_cs *engine)
1289 {
1290 struct drm_i915_private *dev_priv = engine->i915;
1291
1292 if (dev_priv->semaphore_obj) {
1293 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1294 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1295 dev_priv->semaphore_obj = NULL;
1296 }
1297
1298 intel_fini_pipe_control(engine);
1299 }
1300
1301 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1302 unsigned int num_dwords)
1303 {
1304 #define MBOX_UPDATE_DWORDS 8
1305 struct intel_engine_cs *signaller = signaller_req->engine;
1306 struct drm_i915_private *dev_priv = signaller_req->i915;
1307 struct intel_engine_cs *waiter;
1308 enum intel_engine_id id;
1309 int ret, num_rings;
1310
1311 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1312 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1313 #undef MBOX_UPDATE_DWORDS
1314
1315 ret = intel_ring_begin(signaller_req, num_dwords);
1316 if (ret)
1317 return ret;
1318
1319 for_each_engine_id(waiter, dev_priv, id) {
1320 u32 seqno;
1321 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1322 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1323 continue;
1324
1325 seqno = i915_gem_request_get_seqno(signaller_req);
1326 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1327 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1328 PIPE_CONTROL_QW_WRITE |
1329 PIPE_CONTROL_CS_STALL);
1330 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1331 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1332 intel_ring_emit(signaller, seqno);
1333 intel_ring_emit(signaller, 0);
1334 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1335 MI_SEMAPHORE_TARGET(waiter->hw_id));
1336 intel_ring_emit(signaller, 0);
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1343 unsigned int num_dwords)
1344 {
1345 #define MBOX_UPDATE_DWORDS 6
1346 struct intel_engine_cs *signaller = signaller_req->engine;
1347 struct drm_i915_private *dev_priv = signaller_req->i915;
1348 struct intel_engine_cs *waiter;
1349 enum intel_engine_id id;
1350 int ret, num_rings;
1351
1352 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1353 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1354 #undef MBOX_UPDATE_DWORDS
1355
1356 ret = intel_ring_begin(signaller_req, num_dwords);
1357 if (ret)
1358 return ret;
1359
1360 for_each_engine_id(waiter, dev_priv, id) {
1361 u32 seqno;
1362 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1363 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1364 continue;
1365
1366 seqno = i915_gem_request_get_seqno(signaller_req);
1367 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1368 MI_FLUSH_DW_OP_STOREDW);
1369 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1370 MI_FLUSH_DW_USE_GTT);
1371 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1372 intel_ring_emit(signaller, seqno);
1373 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1374 MI_SEMAPHORE_TARGET(waiter->hw_id));
1375 intel_ring_emit(signaller, 0);
1376 }
1377
1378 return 0;
1379 }
1380
1381 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1382 unsigned int num_dwords)
1383 {
1384 struct intel_engine_cs *signaller = signaller_req->engine;
1385 struct drm_i915_private *dev_priv = signaller_req->i915;
1386 struct intel_engine_cs *useless;
1387 enum intel_engine_id id;
1388 int ret, num_rings;
1389
1390 #define MBOX_UPDATE_DWORDS 3
1391 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1392 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1393 #undef MBOX_UPDATE_DWORDS
1394
1395 ret = intel_ring_begin(signaller_req, num_dwords);
1396 if (ret)
1397 return ret;
1398
1399 for_each_engine_id(useless, dev_priv, id) {
1400 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1401
1402 if (i915_mmio_reg_valid(mbox_reg)) {
1403 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1404
1405 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1406 intel_ring_emit_reg(signaller, mbox_reg);
1407 intel_ring_emit(signaller, seqno);
1408 }
1409 }
1410
1411 /* If num_dwords was rounded, make sure the tail pointer is correct */
1412 if (num_rings % 2 == 0)
1413 intel_ring_emit(signaller, MI_NOOP);
1414
1415 return 0;
1416 }
1417
1418 /**
1419 * gen6_add_request - Update the semaphore mailbox registers
1420 *
1421 * @request - request to write to the ring
1422 *
1423 * Update the mailbox registers in the *other* rings with the current seqno.
1424 * This acts like a signal in the canonical semaphore.
1425 */
1426 static int
1427 gen6_add_request(struct drm_i915_gem_request *req)
1428 {
1429 struct intel_engine_cs *engine = req->engine;
1430 int ret;
1431
1432 if (engine->semaphore.signal)
1433 ret = engine->semaphore.signal(req, 4);
1434 else
1435 ret = intel_ring_begin(req, 4);
1436
1437 if (ret)
1438 return ret;
1439
1440 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1441 intel_ring_emit(engine,
1442 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1443 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1444 intel_ring_emit(engine, MI_USER_INTERRUPT);
1445 __intel_ring_advance(engine);
1446
1447 return 0;
1448 }
1449
1450 static int
1451 gen8_render_add_request(struct drm_i915_gem_request *req)
1452 {
1453 struct intel_engine_cs *engine = req->engine;
1454 int ret;
1455
1456 if (engine->semaphore.signal)
1457 ret = engine->semaphore.signal(req, 8);
1458 else
1459 ret = intel_ring_begin(req, 8);
1460 if (ret)
1461 return ret;
1462
1463 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1464 intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1465 PIPE_CONTROL_CS_STALL |
1466 PIPE_CONTROL_QW_WRITE));
1467 intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1468 intel_ring_emit(engine, 0);
1469 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1470 /* We're thrashing one dword of HWS. */
1471 intel_ring_emit(engine, 0);
1472 intel_ring_emit(engine, MI_USER_INTERRUPT);
1473 intel_ring_emit(engine, MI_NOOP);
1474 __intel_ring_advance(engine);
1475
1476 return 0;
1477 }
1478
1479 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
1480 u32 seqno)
1481 {
1482 return dev_priv->last_seqno < seqno;
1483 }
1484
1485 /**
1486 * intel_ring_sync - sync the waiter to the signaller on seqno
1487 *
1488 * @waiter - ring that is waiting
1489 * @signaller - ring which has, or will signal
1490 * @seqno - seqno which the waiter will block on
1491 */
1492
1493 static int
1494 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1495 struct intel_engine_cs *signaller,
1496 u32 seqno)
1497 {
1498 struct intel_engine_cs *waiter = waiter_req->engine;
1499 struct drm_i915_private *dev_priv = waiter_req->i915;
1500 struct i915_hw_ppgtt *ppgtt;
1501 int ret;
1502
1503 ret = intel_ring_begin(waiter_req, 4);
1504 if (ret)
1505 return ret;
1506
1507 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1508 MI_SEMAPHORE_GLOBAL_GTT |
1509 MI_SEMAPHORE_SAD_GTE_SDD);
1510 intel_ring_emit(waiter, seqno);
1511 intel_ring_emit(waiter,
1512 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1513 intel_ring_emit(waiter,
1514 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1515 intel_ring_advance(waiter);
1516
1517 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1518 * pagetables and we must reload them before executing the batch.
1519 * We do this on the i915_switch_context() following the wait and
1520 * before the dispatch.
1521 */
1522 ppgtt = waiter_req->ctx->ppgtt;
1523 if (ppgtt && waiter_req->engine->id != RCS)
1524 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
1525 return 0;
1526 }
1527
1528 static int
1529 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1530 struct intel_engine_cs *signaller,
1531 u32 seqno)
1532 {
1533 struct intel_engine_cs *waiter = waiter_req->engine;
1534 u32 dw1 = MI_SEMAPHORE_MBOX |
1535 MI_SEMAPHORE_COMPARE |
1536 MI_SEMAPHORE_REGISTER;
1537 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1538 int ret;
1539
1540 /* Throughout all of the GEM code, seqno passed implies our current
1541 * seqno is >= the last seqno executed. However for hardware the
1542 * comparison is strictly greater than.
1543 */
1544 seqno -= 1;
1545
1546 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1547
1548 ret = intel_ring_begin(waiter_req, 4);
1549 if (ret)
1550 return ret;
1551
1552 /* If seqno wrap happened, omit the wait with no-ops */
1553 if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
1554 intel_ring_emit(waiter, dw1 | wait_mbox);
1555 intel_ring_emit(waiter, seqno);
1556 intel_ring_emit(waiter, 0);
1557 intel_ring_emit(waiter, MI_NOOP);
1558 } else {
1559 intel_ring_emit(waiter, MI_NOOP);
1560 intel_ring_emit(waiter, MI_NOOP);
1561 intel_ring_emit(waiter, MI_NOOP);
1562 intel_ring_emit(waiter, MI_NOOP);
1563 }
1564 intel_ring_advance(waiter);
1565
1566 return 0;
1567 }
1568
1569 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1570 do { \
1571 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1572 PIPE_CONTROL_DEPTH_STALL); \
1573 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1574 intel_ring_emit(ring__, 0); \
1575 intel_ring_emit(ring__, 0); \
1576 } while (0)
1577
1578 static int
1579 pc_render_add_request(struct drm_i915_gem_request *req)
1580 {
1581 struct intel_engine_cs *engine = req->engine;
1582 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1583 int ret;
1584
1585 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1586 * incoherent with writes to memory, i.e. completely fubar,
1587 * so we need to use PIPE_NOTIFY instead.
1588 *
1589 * However, we also need to workaround the qword write
1590 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1591 * memory before requesting an interrupt.
1592 */
1593 ret = intel_ring_begin(req, 32);
1594 if (ret)
1595 return ret;
1596
1597 intel_ring_emit(engine,
1598 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1599 PIPE_CONTROL_WRITE_FLUSH |
1600 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1601 intel_ring_emit(engine,
1602 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1603 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1604 intel_ring_emit(engine, 0);
1605 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1606 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1607 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1608 scratch_addr += 2 * CACHELINE_BYTES;
1609 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1610 scratch_addr += 2 * CACHELINE_BYTES;
1611 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1612 scratch_addr += 2 * CACHELINE_BYTES;
1613 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1614 scratch_addr += 2 * CACHELINE_BYTES;
1615 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1616
1617 intel_ring_emit(engine,
1618 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1619 PIPE_CONTROL_WRITE_FLUSH |
1620 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1621 PIPE_CONTROL_NOTIFY);
1622 intel_ring_emit(engine,
1623 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1624 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1625 intel_ring_emit(engine, 0);
1626 __intel_ring_advance(engine);
1627
1628 return 0;
1629 }
1630
1631 static void
1632 gen6_seqno_barrier(struct intel_engine_cs *engine)
1633 {
1634 struct drm_i915_private *dev_priv = engine->i915;
1635
1636 /* Workaround to force correct ordering between irq and seqno writes on
1637 * ivb (and maybe also on snb) by reading from a CS register (like
1638 * ACTHD) before reading the status page.
1639 *
1640 * Note that this effectively stalls the read by the time it takes to
1641 * do a memory transaction, which more or less ensures that the write
1642 * from the GPU has sufficient time to invalidate the CPU cacheline.
1643 * Alternatively we could delay the interrupt from the CS ring to give
1644 * the write time to land, but that would incur a delay after every
1645 * batch i.e. much more frequent than a delay when waiting for the
1646 * interrupt (with the same net latency).
1647 *
1648 * Also note that to prevent whole machine hangs on gen7, we have to
1649 * take the spinlock to guard against concurrent cacheline access.
1650 */
1651 spin_lock_irq(&dev_priv->uncore.lock);
1652 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1653 spin_unlock_irq(&dev_priv->uncore.lock);
1654 }
1655
1656 static u32
1657 ring_get_seqno(struct intel_engine_cs *engine)
1658 {
1659 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1660 }
1661
1662 static void
1663 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1664 {
1665 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1666 }
1667
1668 static u32
1669 pc_render_get_seqno(struct intel_engine_cs *engine)
1670 {
1671 return engine->scratch.cpu_page[0];
1672 }
1673
1674 static void
1675 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1676 {
1677 engine->scratch.cpu_page[0] = seqno;
1678 }
1679
1680 static bool
1681 gen5_ring_get_irq(struct intel_engine_cs *engine)
1682 {
1683 struct drm_i915_private *dev_priv = engine->i915;
1684 unsigned long flags;
1685
1686 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1687 return false;
1688
1689 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1690 if (engine->irq_refcount++ == 0)
1691 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1692 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1693
1694 return true;
1695 }
1696
1697 static void
1698 gen5_ring_put_irq(struct intel_engine_cs *engine)
1699 {
1700 struct drm_i915_private *dev_priv = engine->i915;
1701 unsigned long flags;
1702
1703 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1704 if (--engine->irq_refcount == 0)
1705 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1706 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1707 }
1708
1709 static bool
1710 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1711 {
1712 struct drm_i915_private *dev_priv = engine->i915;
1713 unsigned long flags;
1714
1715 if (!intel_irqs_enabled(dev_priv))
1716 return false;
1717
1718 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1719 if (engine->irq_refcount++ == 0) {
1720 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1721 I915_WRITE(IMR, dev_priv->irq_mask);
1722 POSTING_READ(IMR);
1723 }
1724 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1725
1726 return true;
1727 }
1728
1729 static void
1730 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1731 {
1732 struct drm_i915_private *dev_priv = engine->i915;
1733 unsigned long flags;
1734
1735 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1736 if (--engine->irq_refcount == 0) {
1737 dev_priv->irq_mask |= engine->irq_enable_mask;
1738 I915_WRITE(IMR, dev_priv->irq_mask);
1739 POSTING_READ(IMR);
1740 }
1741 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1742 }
1743
1744 static bool
1745 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1746 {
1747 struct drm_i915_private *dev_priv = engine->i915;
1748 unsigned long flags;
1749
1750 if (!intel_irqs_enabled(dev_priv))
1751 return false;
1752
1753 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1754 if (engine->irq_refcount++ == 0) {
1755 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1756 I915_WRITE16(IMR, dev_priv->irq_mask);
1757 POSTING_READ16(IMR);
1758 }
1759 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1760
1761 return true;
1762 }
1763
1764 static void
1765 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1766 {
1767 struct drm_i915_private *dev_priv = engine->i915;
1768 unsigned long flags;
1769
1770 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1771 if (--engine->irq_refcount == 0) {
1772 dev_priv->irq_mask |= engine->irq_enable_mask;
1773 I915_WRITE16(IMR, dev_priv->irq_mask);
1774 POSTING_READ16(IMR);
1775 }
1776 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1777 }
1778
1779 static int
1780 bsd_ring_flush(struct drm_i915_gem_request *req,
1781 u32 invalidate_domains,
1782 u32 flush_domains)
1783 {
1784 struct intel_engine_cs *engine = req->engine;
1785 int ret;
1786
1787 ret = intel_ring_begin(req, 2);
1788 if (ret)
1789 return ret;
1790
1791 intel_ring_emit(engine, MI_FLUSH);
1792 intel_ring_emit(engine, MI_NOOP);
1793 intel_ring_advance(engine);
1794 return 0;
1795 }
1796
1797 static int
1798 i9xx_add_request(struct drm_i915_gem_request *req)
1799 {
1800 struct intel_engine_cs *engine = req->engine;
1801 int ret;
1802
1803 ret = intel_ring_begin(req, 4);
1804 if (ret)
1805 return ret;
1806
1807 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1808 intel_ring_emit(engine,
1809 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1810 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1811 intel_ring_emit(engine, MI_USER_INTERRUPT);
1812 __intel_ring_advance(engine);
1813
1814 return 0;
1815 }
1816
1817 static bool
1818 gen6_ring_get_irq(struct intel_engine_cs *engine)
1819 {
1820 struct drm_i915_private *dev_priv = engine->i915;
1821 unsigned long flags;
1822
1823 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1824 return false;
1825
1826 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1827 if (engine->irq_refcount++ == 0) {
1828 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1829 I915_WRITE_IMR(engine,
1830 ~(engine->irq_enable_mask |
1831 GT_PARITY_ERROR(dev_priv)));
1832 else
1833 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1834 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1835 }
1836 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1837
1838 return true;
1839 }
1840
1841 static void
1842 gen6_ring_put_irq(struct intel_engine_cs *engine)
1843 {
1844 struct drm_i915_private *dev_priv = engine->i915;
1845 unsigned long flags;
1846
1847 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1848 if (--engine->irq_refcount == 0) {
1849 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1850 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1851 else
1852 I915_WRITE_IMR(engine, ~0);
1853 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1854 }
1855 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1856 }
1857
1858 static bool
1859 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1860 {
1861 struct drm_i915_private *dev_priv = engine->i915;
1862 unsigned long flags;
1863
1864 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1865 return false;
1866
1867 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1868 if (engine->irq_refcount++ == 0) {
1869 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1870 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1871 }
1872 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1873
1874 return true;
1875 }
1876
1877 static void
1878 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1879 {
1880 struct drm_i915_private *dev_priv = engine->i915;
1881 unsigned long flags;
1882
1883 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1884 if (--engine->irq_refcount == 0) {
1885 I915_WRITE_IMR(engine, ~0);
1886 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1887 }
1888 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1889 }
1890
1891 static bool
1892 gen8_ring_get_irq(struct intel_engine_cs *engine)
1893 {
1894 struct drm_i915_private *dev_priv = engine->i915;
1895 unsigned long flags;
1896
1897 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1898 return false;
1899
1900 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1901 if (engine->irq_refcount++ == 0) {
1902 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1903 I915_WRITE_IMR(engine,
1904 ~(engine->irq_enable_mask |
1905 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1906 } else {
1907 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1908 }
1909 POSTING_READ(RING_IMR(engine->mmio_base));
1910 }
1911 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1912
1913 return true;
1914 }
1915
1916 static void
1917 gen8_ring_put_irq(struct intel_engine_cs *engine)
1918 {
1919 struct drm_i915_private *dev_priv = engine->i915;
1920 unsigned long flags;
1921
1922 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1923 if (--engine->irq_refcount == 0) {
1924 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1925 I915_WRITE_IMR(engine,
1926 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1927 } else {
1928 I915_WRITE_IMR(engine, ~0);
1929 }
1930 POSTING_READ(RING_IMR(engine->mmio_base));
1931 }
1932 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1933 }
1934
1935 static int
1936 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1937 u64 offset, u32 length,
1938 unsigned dispatch_flags)
1939 {
1940 struct intel_engine_cs *engine = req->engine;
1941 int ret;
1942
1943 ret = intel_ring_begin(req, 2);
1944 if (ret)
1945 return ret;
1946
1947 intel_ring_emit(engine,
1948 MI_BATCH_BUFFER_START |
1949 MI_BATCH_GTT |
1950 (dispatch_flags & I915_DISPATCH_SECURE ?
1951 0 : MI_BATCH_NON_SECURE_I965));
1952 intel_ring_emit(engine, offset);
1953 intel_ring_advance(engine);
1954
1955 return 0;
1956 }
1957
1958 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1959 #define I830_BATCH_LIMIT (256*1024)
1960 #define I830_TLB_ENTRIES (2)
1961 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1962 static int
1963 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1964 u64 offset, u32 len,
1965 unsigned dispatch_flags)
1966 {
1967 struct intel_engine_cs *engine = req->engine;
1968 u32 cs_offset = engine->scratch.gtt_offset;
1969 int ret;
1970
1971 ret = intel_ring_begin(req, 6);
1972 if (ret)
1973 return ret;
1974
1975 /* Evict the invalid PTE TLBs */
1976 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1977 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1978 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1979 intel_ring_emit(engine, cs_offset);
1980 intel_ring_emit(engine, 0xdeadbeef);
1981 intel_ring_emit(engine, MI_NOOP);
1982 intel_ring_advance(engine);
1983
1984 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1985 if (len > I830_BATCH_LIMIT)
1986 return -ENOSPC;
1987
1988 ret = intel_ring_begin(req, 6 + 2);
1989 if (ret)
1990 return ret;
1991
1992 /* Blit the batch (which has now all relocs applied) to the
1993 * stable batch scratch bo area (so that the CS never
1994 * stumbles over its tlb invalidation bug) ...
1995 */
1996 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1997 intel_ring_emit(engine,
1998 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1999 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2000 intel_ring_emit(engine, cs_offset);
2001 intel_ring_emit(engine, 4096);
2002 intel_ring_emit(engine, offset);
2003
2004 intel_ring_emit(engine, MI_FLUSH);
2005 intel_ring_emit(engine, MI_NOOP);
2006 intel_ring_advance(engine);
2007
2008 /* ... and execute it. */
2009 offset = cs_offset;
2010 }
2011
2012 ret = intel_ring_begin(req, 2);
2013 if (ret)
2014 return ret;
2015
2016 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2017 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2018 0 : MI_BATCH_NON_SECURE));
2019 intel_ring_advance(engine);
2020
2021 return 0;
2022 }
2023
2024 static int
2025 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
2026 u64 offset, u32 len,
2027 unsigned dispatch_flags)
2028 {
2029 struct intel_engine_cs *engine = req->engine;
2030 int ret;
2031
2032 ret = intel_ring_begin(req, 2);
2033 if (ret)
2034 return ret;
2035
2036 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2037 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2038 0 : MI_BATCH_NON_SECURE));
2039 intel_ring_advance(engine);
2040
2041 return 0;
2042 }
2043
2044 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2045 {
2046 struct drm_i915_private *dev_priv = engine->i915;
2047
2048 if (!dev_priv->status_page_dmah)
2049 return;
2050
2051 drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
2052 engine->status_page.page_addr = NULL;
2053 }
2054
2055 static void cleanup_status_page(struct intel_engine_cs *engine)
2056 {
2057 struct drm_i915_gem_object *obj;
2058
2059 obj = engine->status_page.obj;
2060 if (obj == NULL)
2061 return;
2062
2063 kunmap(sg_page(obj->pages->sgl));
2064 i915_gem_object_ggtt_unpin(obj);
2065 drm_gem_object_unreference(&obj->base);
2066 engine->status_page.obj = NULL;
2067 }
2068
2069 static int init_status_page(struct intel_engine_cs *engine)
2070 {
2071 struct drm_i915_gem_object *obj = engine->status_page.obj;
2072
2073 if (obj == NULL) {
2074 unsigned flags;
2075 int ret;
2076
2077 obj = i915_gem_object_create(engine->i915->dev, 4096);
2078 if (IS_ERR(obj)) {
2079 DRM_ERROR("Failed to allocate status page\n");
2080 return PTR_ERR(obj);
2081 }
2082
2083 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2084 if (ret)
2085 goto err_unref;
2086
2087 flags = 0;
2088 if (!HAS_LLC(engine->i915))
2089 /* On g33, we cannot place HWS above 256MiB, so
2090 * restrict its pinning to the low mappable arena.
2091 * Though this restriction is not documented for
2092 * gen4, gen5, or byt, they also behave similarly
2093 * and hang if the HWS is placed at the top of the
2094 * GTT. To generalise, it appears that all !llc
2095 * platforms have issues with us placing the HWS
2096 * above the mappable region (even though we never
2097 * actualy map it).
2098 */
2099 flags |= PIN_MAPPABLE;
2100 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2101 if (ret) {
2102 err_unref:
2103 drm_gem_object_unreference(&obj->base);
2104 return ret;
2105 }
2106
2107 engine->status_page.obj = obj;
2108 }
2109
2110 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2111 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2112 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2113
2114 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2115 engine->name, engine->status_page.gfx_addr);
2116
2117 return 0;
2118 }
2119
2120 static int init_phys_status_page(struct intel_engine_cs *engine)
2121 {
2122 struct drm_i915_private *dev_priv = engine->i915;
2123
2124 if (!dev_priv->status_page_dmah) {
2125 dev_priv->status_page_dmah =
2126 drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
2127 if (!dev_priv->status_page_dmah)
2128 return -ENOMEM;
2129 }
2130
2131 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2132 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2133
2134 return 0;
2135 }
2136
2137 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2138 {
2139 GEM_BUG_ON(ringbuf->vma == NULL);
2140 GEM_BUG_ON(ringbuf->virtual_start == NULL);
2141
2142 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2143 i915_gem_object_unpin_map(ringbuf->obj);
2144 else
2145 i915_vma_unpin_iomap(ringbuf->vma);
2146 ringbuf->virtual_start = NULL;
2147
2148 i915_gem_object_ggtt_unpin(ringbuf->obj);
2149 ringbuf->vma = NULL;
2150 }
2151
2152 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
2153 struct intel_ringbuffer *ringbuf)
2154 {
2155 struct drm_i915_gem_object *obj = ringbuf->obj;
2156 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2157 unsigned flags = PIN_OFFSET_BIAS | 4096;
2158 void *addr;
2159 int ret;
2160
2161 if (HAS_LLC(dev_priv) && !obj->stolen) {
2162 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2163 if (ret)
2164 return ret;
2165
2166 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2167 if (ret)
2168 goto err_unpin;
2169
2170 addr = i915_gem_object_pin_map(obj);
2171 if (IS_ERR(addr)) {
2172 ret = PTR_ERR(addr);
2173 goto err_unpin;
2174 }
2175 } else {
2176 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2177 flags | PIN_MAPPABLE);
2178 if (ret)
2179 return ret;
2180
2181 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2182 if (ret)
2183 goto err_unpin;
2184
2185 /* Access through the GTT requires the device to be awake. */
2186 assert_rpm_wakelock_held(dev_priv);
2187
2188 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2189 if (IS_ERR(addr)) {
2190 ret = PTR_ERR(addr);
2191 goto err_unpin;
2192 }
2193 }
2194
2195 ringbuf->virtual_start = addr;
2196 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2197 return 0;
2198
2199 err_unpin:
2200 i915_gem_object_ggtt_unpin(obj);
2201 return ret;
2202 }
2203
2204 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2205 {
2206 drm_gem_object_unreference(&ringbuf->obj->base);
2207 ringbuf->obj = NULL;
2208 }
2209
2210 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2211 struct intel_ringbuffer *ringbuf)
2212 {
2213 struct drm_i915_gem_object *obj;
2214
2215 obj = NULL;
2216 if (!HAS_LLC(dev))
2217 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2218 if (obj == NULL)
2219 obj = i915_gem_object_create(dev, ringbuf->size);
2220 if (IS_ERR(obj))
2221 return PTR_ERR(obj);
2222
2223 /* mark ring buffers as read-only from GPU side by default */
2224 obj->gt_ro = 1;
2225
2226 ringbuf->obj = obj;
2227
2228 return 0;
2229 }
2230
2231 struct intel_ringbuffer *
2232 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2233 {
2234 struct intel_ringbuffer *ring;
2235 int ret;
2236
2237 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2238 if (ring == NULL) {
2239 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2240 engine->name);
2241 return ERR_PTR(-ENOMEM);
2242 }
2243
2244 ring->engine = engine;
2245 list_add(&ring->link, &engine->buffers);
2246
2247 ring->size = size;
2248 /* Workaround an erratum on the i830 which causes a hang if
2249 * the TAIL pointer points to within the last 2 cachelines
2250 * of the buffer.
2251 */
2252 ring->effective_size = size;
2253 if (IS_I830(engine->i915) || IS_845G(engine->i915))
2254 ring->effective_size -= 2 * CACHELINE_BYTES;
2255
2256 ring->last_retired_head = -1;
2257 intel_ring_update_space(ring);
2258
2259 ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
2260 if (ret) {
2261 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2262 engine->name, ret);
2263 list_del(&ring->link);
2264 kfree(ring);
2265 return ERR_PTR(ret);
2266 }
2267
2268 return ring;
2269 }
2270
2271 void
2272 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2273 {
2274 intel_destroy_ringbuffer_obj(ring);
2275 list_del(&ring->link);
2276 kfree(ring);
2277 }
2278
2279 static int intel_init_ring_buffer(struct drm_device *dev,
2280 struct intel_engine_cs *engine)
2281 {
2282 struct drm_i915_private *dev_priv = to_i915(dev);
2283 struct intel_ringbuffer *ringbuf;
2284 int ret;
2285
2286 WARN_ON(engine->buffer);
2287
2288 engine->i915 = dev_priv;
2289 INIT_LIST_HEAD(&engine->active_list);
2290 INIT_LIST_HEAD(&engine->request_list);
2291 INIT_LIST_HEAD(&engine->execlist_queue);
2292 INIT_LIST_HEAD(&engine->buffers);
2293 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2294 memset(engine->semaphore.sync_seqno, 0,
2295 sizeof(engine->semaphore.sync_seqno));
2296
2297 init_waitqueue_head(&engine->irq_queue);
2298
2299 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2300 if (IS_ERR(ringbuf)) {
2301 ret = PTR_ERR(ringbuf);
2302 goto error;
2303 }
2304 engine->buffer = ringbuf;
2305
2306 if (I915_NEED_GFX_HWS(dev_priv)) {
2307 ret = init_status_page(engine);
2308 if (ret)
2309 goto error;
2310 } else {
2311 WARN_ON(engine->id != RCS);
2312 ret = init_phys_status_page(engine);
2313 if (ret)
2314 goto error;
2315 }
2316
2317 ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
2318 if (ret) {
2319 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2320 engine->name, ret);
2321 intel_destroy_ringbuffer_obj(ringbuf);
2322 goto error;
2323 }
2324
2325 ret = i915_cmd_parser_init_ring(engine);
2326 if (ret)
2327 goto error;
2328
2329 return 0;
2330
2331 error:
2332 intel_cleanup_engine(engine);
2333 return ret;
2334 }
2335
2336 void intel_cleanup_engine(struct intel_engine_cs *engine)
2337 {
2338 struct drm_i915_private *dev_priv;
2339
2340 if (!intel_engine_initialized(engine))
2341 return;
2342
2343 dev_priv = engine->i915;
2344
2345 if (engine->buffer) {
2346 intel_stop_engine(engine);
2347 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2348
2349 intel_unpin_ringbuffer_obj(engine->buffer);
2350 intel_ringbuffer_free(engine->buffer);
2351 engine->buffer = NULL;
2352 }
2353
2354 if (engine->cleanup)
2355 engine->cleanup(engine);
2356
2357 if (I915_NEED_GFX_HWS(dev_priv)) {
2358 cleanup_status_page(engine);
2359 } else {
2360 WARN_ON(engine->id != RCS);
2361 cleanup_phys_status_page(engine);
2362 }
2363
2364 i915_cmd_parser_fini_ring(engine);
2365 i915_gem_batch_pool_fini(&engine->batch_pool);
2366 engine->i915 = NULL;
2367 }
2368
2369 int intel_engine_idle(struct intel_engine_cs *engine)
2370 {
2371 struct drm_i915_gem_request *req;
2372
2373 /* Wait upon the last request to be completed */
2374 if (list_empty(&engine->request_list))
2375 return 0;
2376
2377 req = list_entry(engine->request_list.prev,
2378 struct drm_i915_gem_request,
2379 list);
2380
2381 /* Make sure we do not trigger any retires */
2382 return __i915_wait_request(req,
2383 req->i915->mm.interruptible,
2384 NULL, NULL);
2385 }
2386
2387 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2388 {
2389 int ret;
2390
2391 /* Flush enough space to reduce the likelihood of waiting after
2392 * we start building the request - in which case we will just
2393 * have to repeat work.
2394 */
2395 request->reserved_space += LEGACY_REQUEST_SIZE;
2396
2397 request->ringbuf = request->engine->buffer;
2398
2399 ret = intel_ring_begin(request, 0);
2400 if (ret)
2401 return ret;
2402
2403 request->reserved_space -= LEGACY_REQUEST_SIZE;
2404 return 0;
2405 }
2406
2407 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2408 {
2409 struct intel_ringbuffer *ringbuf = req->ringbuf;
2410 struct intel_engine_cs *engine = req->engine;
2411 struct drm_i915_gem_request *target;
2412
2413 intel_ring_update_space(ringbuf);
2414 if (ringbuf->space >= bytes)
2415 return 0;
2416
2417 /*
2418 * Space is reserved in the ringbuffer for finalising the request,
2419 * as that cannot be allowed to fail. During request finalisation,
2420 * reserved_space is set to 0 to stop the overallocation and the
2421 * assumption is that then we never need to wait (which has the
2422 * risk of failing with EINTR).
2423 *
2424 * See also i915_gem_request_alloc() and i915_add_request().
2425 */
2426 GEM_BUG_ON(!req->reserved_space);
2427
2428 list_for_each_entry(target, &engine->request_list, list) {
2429 unsigned space;
2430
2431 /*
2432 * The request queue is per-engine, so can contain requests
2433 * from multiple ringbuffers. Here, we must ignore any that
2434 * aren't from the ringbuffer we're considering.
2435 */
2436 if (target->ringbuf != ringbuf)
2437 continue;
2438
2439 /* Would completion of this request free enough space? */
2440 space = __intel_ring_space(target->postfix, ringbuf->tail,
2441 ringbuf->size);
2442 if (space >= bytes)
2443 break;
2444 }
2445
2446 if (WARN_ON(&target->list == &engine->request_list))
2447 return -ENOSPC;
2448
2449 return i915_wait_request(target);
2450 }
2451
2452 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2453 {
2454 struct intel_ringbuffer *ringbuf = req->ringbuf;
2455 int remain_actual = ringbuf->size - ringbuf->tail;
2456 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2457 int bytes = num_dwords * sizeof(u32);
2458 int total_bytes, wait_bytes;
2459 bool need_wrap = false;
2460
2461 total_bytes = bytes + req->reserved_space;
2462
2463 if (unlikely(bytes > remain_usable)) {
2464 /*
2465 * Not enough space for the basic request. So need to flush
2466 * out the remainder and then wait for base + reserved.
2467 */
2468 wait_bytes = remain_actual + total_bytes;
2469 need_wrap = true;
2470 } else if (unlikely(total_bytes > remain_usable)) {
2471 /*
2472 * The base request will fit but the reserved space
2473 * falls off the end. So we don't need an immediate wrap
2474 * and only need to effectively wait for the reserved
2475 * size space from the start of ringbuffer.
2476 */
2477 wait_bytes = remain_actual + req->reserved_space;
2478 } else {
2479 /* No wrapping required, just waiting. */
2480 wait_bytes = total_bytes;
2481 }
2482
2483 if (wait_bytes > ringbuf->space) {
2484 int ret = wait_for_space(req, wait_bytes);
2485 if (unlikely(ret))
2486 return ret;
2487
2488 intel_ring_update_space(ringbuf);
2489 if (unlikely(ringbuf->space < wait_bytes))
2490 return -EAGAIN;
2491 }
2492
2493 if (unlikely(need_wrap)) {
2494 GEM_BUG_ON(remain_actual > ringbuf->space);
2495 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2496
2497 /* Fill the tail with MI_NOOP */
2498 memset(ringbuf->virtual_start + ringbuf->tail,
2499 0, remain_actual);
2500 ringbuf->tail = 0;
2501 ringbuf->space -= remain_actual;
2502 }
2503
2504 ringbuf->space -= bytes;
2505 GEM_BUG_ON(ringbuf->space < 0);
2506 return 0;
2507 }
2508
2509 /* Align the ring tail to a cacheline boundary */
2510 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2511 {
2512 struct intel_engine_cs *engine = req->engine;
2513 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2514 int ret;
2515
2516 if (num_dwords == 0)
2517 return 0;
2518
2519 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2520 ret = intel_ring_begin(req, num_dwords);
2521 if (ret)
2522 return ret;
2523
2524 while (num_dwords--)
2525 intel_ring_emit(engine, MI_NOOP);
2526
2527 intel_ring_advance(engine);
2528
2529 return 0;
2530 }
2531
2532 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2533 {
2534 struct drm_i915_private *dev_priv = engine->i915;
2535
2536 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2537 * so long as the semaphore value in the register/page is greater
2538 * than the sync value), so whenever we reset the seqno,
2539 * so long as we reset the tracking semaphore value to 0, it will
2540 * always be before the next request's seqno. If we don't reset
2541 * the semaphore value, then when the seqno moves backwards all
2542 * future waits will complete instantly (causing rendering corruption).
2543 */
2544 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
2545 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2546 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2547 if (HAS_VEBOX(dev_priv))
2548 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2549 }
2550 if (dev_priv->semaphore_obj) {
2551 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2552 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2553 void *semaphores = kmap(page);
2554 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2555 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2556 kunmap(page);
2557 }
2558 memset(engine->semaphore.sync_seqno, 0,
2559 sizeof(engine->semaphore.sync_seqno));
2560
2561 engine->set_seqno(engine, seqno);
2562 engine->last_submitted_seqno = seqno;
2563
2564 engine->hangcheck.seqno = seqno;
2565 }
2566
2567 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2568 u32 value)
2569 {
2570 struct drm_i915_private *dev_priv = engine->i915;
2571
2572 /* Every tail move must follow the sequence below */
2573
2574 /* Disable notification that the ring is IDLE. The GT
2575 * will then assume that it is busy and bring it out of rc6.
2576 */
2577 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2578 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2579
2580 /* Clear the context id. Here be magic! */
2581 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2582
2583 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2584 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2585 GEN6_BSD_SLEEP_INDICATOR) == 0,
2586 50))
2587 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2588
2589 /* Now that the ring is fully powered up, update the tail */
2590 I915_WRITE_TAIL(engine, value);
2591 POSTING_READ(RING_TAIL(engine->mmio_base));
2592
2593 /* Let the ring send IDLE messages to the GT again,
2594 * and so let it sleep to conserve power when idle.
2595 */
2596 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2597 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2598 }
2599
2600 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2601 u32 invalidate, u32 flush)
2602 {
2603 struct intel_engine_cs *engine = req->engine;
2604 uint32_t cmd;
2605 int ret;
2606
2607 ret = intel_ring_begin(req, 4);
2608 if (ret)
2609 return ret;
2610
2611 cmd = MI_FLUSH_DW;
2612 if (INTEL_GEN(req->i915) >= 8)
2613 cmd += 1;
2614
2615 /* We always require a command barrier so that subsequent
2616 * commands, such as breadcrumb interrupts, are strictly ordered
2617 * wrt the contents of the write cache being flushed to memory
2618 * (and thus being coherent from the CPU).
2619 */
2620 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2621
2622 /*
2623 * Bspec vol 1c.5 - video engine command streamer:
2624 * "If ENABLED, all TLBs will be invalidated once the flush
2625 * operation is complete. This bit is only valid when the
2626 * Post-Sync Operation field is a value of 1h or 3h."
2627 */
2628 if (invalidate & I915_GEM_GPU_DOMAINS)
2629 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2630
2631 intel_ring_emit(engine, cmd);
2632 intel_ring_emit(engine,
2633 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2634 if (INTEL_GEN(req->i915) >= 8) {
2635 intel_ring_emit(engine, 0); /* upper addr */
2636 intel_ring_emit(engine, 0); /* value */
2637 } else {
2638 intel_ring_emit(engine, 0);
2639 intel_ring_emit(engine, MI_NOOP);
2640 }
2641 intel_ring_advance(engine);
2642 return 0;
2643 }
2644
2645 static int
2646 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2647 u64 offset, u32 len,
2648 unsigned dispatch_flags)
2649 {
2650 struct intel_engine_cs *engine = req->engine;
2651 bool ppgtt = USES_PPGTT(engine->dev) &&
2652 !(dispatch_flags & I915_DISPATCH_SECURE);
2653 int ret;
2654
2655 ret = intel_ring_begin(req, 4);
2656 if (ret)
2657 return ret;
2658
2659 /* FIXME(BDW): Address space and security selectors. */
2660 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2661 (dispatch_flags & I915_DISPATCH_RS ?
2662 MI_BATCH_RESOURCE_STREAMER : 0));
2663 intel_ring_emit(engine, lower_32_bits(offset));
2664 intel_ring_emit(engine, upper_32_bits(offset));
2665 intel_ring_emit(engine, MI_NOOP);
2666 intel_ring_advance(engine);
2667
2668 return 0;
2669 }
2670
2671 static int
2672 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2673 u64 offset, u32 len,
2674 unsigned dispatch_flags)
2675 {
2676 struct intel_engine_cs *engine = req->engine;
2677 int ret;
2678
2679 ret = intel_ring_begin(req, 2);
2680 if (ret)
2681 return ret;
2682
2683 intel_ring_emit(engine,
2684 MI_BATCH_BUFFER_START |
2685 (dispatch_flags & I915_DISPATCH_SECURE ?
2686 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2687 (dispatch_flags & I915_DISPATCH_RS ?
2688 MI_BATCH_RESOURCE_STREAMER : 0));
2689 /* bit0-7 is the length on GEN6+ */
2690 intel_ring_emit(engine, offset);
2691 intel_ring_advance(engine);
2692
2693 return 0;
2694 }
2695
2696 static int
2697 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2698 u64 offset, u32 len,
2699 unsigned dispatch_flags)
2700 {
2701 struct intel_engine_cs *engine = req->engine;
2702 int ret;
2703
2704 ret = intel_ring_begin(req, 2);
2705 if (ret)
2706 return ret;
2707
2708 intel_ring_emit(engine,
2709 MI_BATCH_BUFFER_START |
2710 (dispatch_flags & I915_DISPATCH_SECURE ?
2711 0 : MI_BATCH_NON_SECURE_I965));
2712 /* bit0-7 is the length on GEN6+ */
2713 intel_ring_emit(engine, offset);
2714 intel_ring_advance(engine);
2715
2716 return 0;
2717 }
2718
2719 /* Blitter support (SandyBridge+) */
2720
2721 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2722 u32 invalidate, u32 flush)
2723 {
2724 struct intel_engine_cs *engine = req->engine;
2725 uint32_t cmd;
2726 int ret;
2727
2728 ret = intel_ring_begin(req, 4);
2729 if (ret)
2730 return ret;
2731
2732 cmd = MI_FLUSH_DW;
2733 if (INTEL_GEN(req->i915) >= 8)
2734 cmd += 1;
2735
2736 /* We always require a command barrier so that subsequent
2737 * commands, such as breadcrumb interrupts, are strictly ordered
2738 * wrt the contents of the write cache being flushed to memory
2739 * (and thus being coherent from the CPU).
2740 */
2741 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2742
2743 /*
2744 * Bspec vol 1c.3 - blitter engine command streamer:
2745 * "If ENABLED, all TLBs will be invalidated once the flush
2746 * operation is complete. This bit is only valid when the
2747 * Post-Sync Operation field is a value of 1h or 3h."
2748 */
2749 if (invalidate & I915_GEM_DOMAIN_RENDER)
2750 cmd |= MI_INVALIDATE_TLB;
2751 intel_ring_emit(engine, cmd);
2752 intel_ring_emit(engine,
2753 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2754 if (INTEL_GEN(req->i915) >= 8) {
2755 intel_ring_emit(engine, 0); /* upper addr */
2756 intel_ring_emit(engine, 0); /* value */
2757 } else {
2758 intel_ring_emit(engine, 0);
2759 intel_ring_emit(engine, MI_NOOP);
2760 }
2761 intel_ring_advance(engine);
2762
2763 return 0;
2764 }
2765
2766 int intel_init_render_ring_buffer(struct drm_device *dev)
2767 {
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2770 struct drm_i915_gem_object *obj;
2771 int ret;
2772
2773 engine->name = "render ring";
2774 engine->id = RCS;
2775 engine->exec_id = I915_EXEC_RENDER;
2776 engine->hw_id = 0;
2777 engine->mmio_base = RENDER_RING_BASE;
2778
2779 if (INTEL_GEN(dev_priv) >= 8) {
2780 if (i915_semaphore_is_enabled(dev_priv)) {
2781 obj = i915_gem_object_create(dev, 4096);
2782 if (IS_ERR(obj)) {
2783 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2784 i915.semaphores = 0;
2785 } else {
2786 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2787 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2788 if (ret != 0) {
2789 drm_gem_object_unreference(&obj->base);
2790 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2791 i915.semaphores = 0;
2792 } else
2793 dev_priv->semaphore_obj = obj;
2794 }
2795 }
2796
2797 engine->init_context = intel_rcs_ctx_init;
2798 engine->add_request = gen8_render_add_request;
2799 engine->flush = gen8_render_ring_flush;
2800 engine->irq_get = gen8_ring_get_irq;
2801 engine->irq_put = gen8_ring_put_irq;
2802 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2803 engine->get_seqno = ring_get_seqno;
2804 engine->set_seqno = ring_set_seqno;
2805 if (i915_semaphore_is_enabled(dev_priv)) {
2806 WARN_ON(!dev_priv->semaphore_obj);
2807 engine->semaphore.sync_to = gen8_ring_sync;
2808 engine->semaphore.signal = gen8_rcs_signal;
2809 GEN8_RING_SEMAPHORE_INIT(engine);
2810 }
2811 } else if (INTEL_GEN(dev_priv) >= 6) {
2812 engine->init_context = intel_rcs_ctx_init;
2813 engine->add_request = gen6_add_request;
2814 engine->flush = gen7_render_ring_flush;
2815 if (IS_GEN6(dev_priv))
2816 engine->flush = gen6_render_ring_flush;
2817 engine->irq_get = gen6_ring_get_irq;
2818 engine->irq_put = gen6_ring_put_irq;
2819 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2820 engine->irq_seqno_barrier = gen6_seqno_barrier;
2821 engine->get_seqno = ring_get_seqno;
2822 engine->set_seqno = ring_set_seqno;
2823 if (i915_semaphore_is_enabled(dev_priv)) {
2824 engine->semaphore.sync_to = gen6_ring_sync;
2825 engine->semaphore.signal = gen6_signal;
2826 /*
2827 * The current semaphore is only applied on pre-gen8
2828 * platform. And there is no VCS2 ring on the pre-gen8
2829 * platform. So the semaphore between RCS and VCS2 is
2830 * initialized as INVALID. Gen8 will initialize the
2831 * sema between VCS2 and RCS later.
2832 */
2833 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2834 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2835 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2836 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2837 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2838 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2839 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2840 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2841 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2842 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2843 }
2844 } else if (IS_GEN5(dev_priv)) {
2845 engine->add_request = pc_render_add_request;
2846 engine->flush = gen4_render_ring_flush;
2847 engine->get_seqno = pc_render_get_seqno;
2848 engine->set_seqno = pc_render_set_seqno;
2849 engine->irq_get = gen5_ring_get_irq;
2850 engine->irq_put = gen5_ring_put_irq;
2851 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2852 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2853 } else {
2854 engine->add_request = i9xx_add_request;
2855 if (INTEL_GEN(dev_priv) < 4)
2856 engine->flush = gen2_render_ring_flush;
2857 else
2858 engine->flush = gen4_render_ring_flush;
2859 engine->get_seqno = ring_get_seqno;
2860 engine->set_seqno = ring_set_seqno;
2861 if (IS_GEN2(dev_priv)) {
2862 engine->irq_get = i8xx_ring_get_irq;
2863 engine->irq_put = i8xx_ring_put_irq;
2864 } else {
2865 engine->irq_get = i9xx_ring_get_irq;
2866 engine->irq_put = i9xx_ring_put_irq;
2867 }
2868 engine->irq_enable_mask = I915_USER_INTERRUPT;
2869 }
2870 engine->write_tail = ring_write_tail;
2871
2872 if (IS_HASWELL(dev_priv))
2873 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2874 else if (IS_GEN8(dev_priv))
2875 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2876 else if (INTEL_GEN(dev_priv) >= 6)
2877 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2878 else if (INTEL_GEN(dev_priv) >= 4)
2879 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2880 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2881 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2882 else
2883 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2884 engine->init_hw = init_render_ring;
2885 engine->cleanup = render_ring_cleanup;
2886
2887 /* Workaround batchbuffer to combat CS tlb bug. */
2888 if (HAS_BROKEN_CS_TLB(dev_priv)) {
2889 obj = i915_gem_object_create(dev, I830_WA_SIZE);
2890 if (IS_ERR(obj)) {
2891 DRM_ERROR("Failed to allocate batch bo\n");
2892 return PTR_ERR(obj);
2893 }
2894
2895 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2896 if (ret != 0) {
2897 drm_gem_object_unreference(&obj->base);
2898 DRM_ERROR("Failed to ping batch bo\n");
2899 return ret;
2900 }
2901
2902 engine->scratch.obj = obj;
2903 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2904 }
2905
2906 ret = intel_init_ring_buffer(dev, engine);
2907 if (ret)
2908 return ret;
2909
2910 if (INTEL_GEN(dev_priv) >= 5) {
2911 ret = intel_init_pipe_control(engine);
2912 if (ret)
2913 return ret;
2914 }
2915
2916 return 0;
2917 }
2918
2919 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2920 {
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2923
2924 engine->name = "bsd ring";
2925 engine->id = VCS;
2926 engine->exec_id = I915_EXEC_BSD;
2927 engine->hw_id = 1;
2928
2929 engine->write_tail = ring_write_tail;
2930 if (INTEL_GEN(dev_priv) >= 6) {
2931 engine->mmio_base = GEN6_BSD_RING_BASE;
2932 /* gen6 bsd needs a special wa for tail updates */
2933 if (IS_GEN6(dev_priv))
2934 engine->write_tail = gen6_bsd_ring_write_tail;
2935 engine->flush = gen6_bsd_ring_flush;
2936 engine->add_request = gen6_add_request;
2937 engine->irq_seqno_barrier = gen6_seqno_barrier;
2938 engine->get_seqno = ring_get_seqno;
2939 engine->set_seqno = ring_set_seqno;
2940 if (INTEL_GEN(dev_priv) >= 8) {
2941 engine->irq_enable_mask =
2942 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2943 engine->irq_get = gen8_ring_get_irq;
2944 engine->irq_put = gen8_ring_put_irq;
2945 engine->dispatch_execbuffer =
2946 gen8_ring_dispatch_execbuffer;
2947 if (i915_semaphore_is_enabled(dev_priv)) {
2948 engine->semaphore.sync_to = gen8_ring_sync;
2949 engine->semaphore.signal = gen8_xcs_signal;
2950 GEN8_RING_SEMAPHORE_INIT(engine);
2951 }
2952 } else {
2953 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2954 engine->irq_get = gen6_ring_get_irq;
2955 engine->irq_put = gen6_ring_put_irq;
2956 engine->dispatch_execbuffer =
2957 gen6_ring_dispatch_execbuffer;
2958 if (i915_semaphore_is_enabled(dev_priv)) {
2959 engine->semaphore.sync_to = gen6_ring_sync;
2960 engine->semaphore.signal = gen6_signal;
2961 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2962 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2963 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2964 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2965 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2966 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2967 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2968 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2969 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2970 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2971 }
2972 }
2973 } else {
2974 engine->mmio_base = BSD_RING_BASE;
2975 engine->flush = bsd_ring_flush;
2976 engine->add_request = i9xx_add_request;
2977 engine->get_seqno = ring_get_seqno;
2978 engine->set_seqno = ring_set_seqno;
2979 if (IS_GEN5(dev_priv)) {
2980 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2981 engine->irq_get = gen5_ring_get_irq;
2982 engine->irq_put = gen5_ring_put_irq;
2983 } else {
2984 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2985 engine->irq_get = i9xx_ring_get_irq;
2986 engine->irq_put = i9xx_ring_put_irq;
2987 }
2988 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2989 }
2990 engine->init_hw = init_ring_common;
2991
2992 return intel_init_ring_buffer(dev, engine);
2993 }
2994
2995 /**
2996 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2997 */
2998 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2999 {
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3002
3003 engine->name = "bsd2 ring";
3004 engine->id = VCS2;
3005 engine->exec_id = I915_EXEC_BSD;
3006 engine->hw_id = 4;
3007
3008 engine->write_tail = ring_write_tail;
3009 engine->mmio_base = GEN8_BSD2_RING_BASE;
3010 engine->flush = gen6_bsd_ring_flush;
3011 engine->add_request = gen6_add_request;
3012 engine->irq_seqno_barrier = gen6_seqno_barrier;
3013 engine->get_seqno = ring_get_seqno;
3014 engine->set_seqno = ring_set_seqno;
3015 engine->irq_enable_mask =
3016 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3017 engine->irq_get = gen8_ring_get_irq;
3018 engine->irq_put = gen8_ring_put_irq;
3019 engine->dispatch_execbuffer =
3020 gen8_ring_dispatch_execbuffer;
3021 if (i915_semaphore_is_enabled(dev_priv)) {
3022 engine->semaphore.sync_to = gen8_ring_sync;
3023 engine->semaphore.signal = gen8_xcs_signal;
3024 GEN8_RING_SEMAPHORE_INIT(engine);
3025 }
3026 engine->init_hw = init_ring_common;
3027
3028 return intel_init_ring_buffer(dev, engine);
3029 }
3030
3031 int intel_init_blt_ring_buffer(struct drm_device *dev)
3032 {
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3035
3036 engine->name = "blitter ring";
3037 engine->id = BCS;
3038 engine->exec_id = I915_EXEC_BLT;
3039 engine->hw_id = 2;
3040
3041 engine->mmio_base = BLT_RING_BASE;
3042 engine->write_tail = ring_write_tail;
3043 engine->flush = gen6_ring_flush;
3044 engine->add_request = gen6_add_request;
3045 engine->irq_seqno_barrier = gen6_seqno_barrier;
3046 engine->get_seqno = ring_get_seqno;
3047 engine->set_seqno = ring_set_seqno;
3048 if (INTEL_GEN(dev_priv) >= 8) {
3049 engine->irq_enable_mask =
3050 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3051 engine->irq_get = gen8_ring_get_irq;
3052 engine->irq_put = gen8_ring_put_irq;
3053 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3054 if (i915_semaphore_is_enabled(dev_priv)) {
3055 engine->semaphore.sync_to = gen8_ring_sync;
3056 engine->semaphore.signal = gen8_xcs_signal;
3057 GEN8_RING_SEMAPHORE_INIT(engine);
3058 }
3059 } else {
3060 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3061 engine->irq_get = gen6_ring_get_irq;
3062 engine->irq_put = gen6_ring_put_irq;
3063 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3064 if (i915_semaphore_is_enabled(dev_priv)) {
3065 engine->semaphore.signal = gen6_signal;
3066 engine->semaphore.sync_to = gen6_ring_sync;
3067 /*
3068 * The current semaphore is only applied on pre-gen8
3069 * platform. And there is no VCS2 ring on the pre-gen8
3070 * platform. So the semaphore between BCS and VCS2 is
3071 * initialized as INVALID. Gen8 will initialize the
3072 * sema between BCS and VCS2 later.
3073 */
3074 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3075 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3076 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3077 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3078 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3079 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3080 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3081 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3082 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3083 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3084 }
3085 }
3086 engine->init_hw = init_ring_common;
3087
3088 return intel_init_ring_buffer(dev, engine);
3089 }
3090
3091 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3092 {
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3095
3096 engine->name = "video enhancement ring";
3097 engine->id = VECS;
3098 engine->exec_id = I915_EXEC_VEBOX;
3099 engine->hw_id = 3;
3100
3101 engine->mmio_base = VEBOX_RING_BASE;
3102 engine->write_tail = ring_write_tail;
3103 engine->flush = gen6_ring_flush;
3104 engine->add_request = gen6_add_request;
3105 engine->irq_seqno_barrier = gen6_seqno_barrier;
3106 engine->get_seqno = ring_get_seqno;
3107 engine->set_seqno = ring_set_seqno;
3108
3109 if (INTEL_GEN(dev_priv) >= 8) {
3110 engine->irq_enable_mask =
3111 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3112 engine->irq_get = gen8_ring_get_irq;
3113 engine->irq_put = gen8_ring_put_irq;
3114 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3115 if (i915_semaphore_is_enabled(dev_priv)) {
3116 engine->semaphore.sync_to = gen8_ring_sync;
3117 engine->semaphore.signal = gen8_xcs_signal;
3118 GEN8_RING_SEMAPHORE_INIT(engine);
3119 }
3120 } else {
3121 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3122 engine->irq_get = hsw_vebox_get_irq;
3123 engine->irq_put = hsw_vebox_put_irq;
3124 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3125 if (i915_semaphore_is_enabled(dev_priv)) {
3126 engine->semaphore.sync_to = gen6_ring_sync;
3127 engine->semaphore.signal = gen6_signal;
3128 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3129 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3130 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3131 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3132 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3133 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3134 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3135 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3136 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3137 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3138 }
3139 }
3140 engine->init_hw = init_ring_common;
3141
3142 return intel_init_ring_buffer(dev, engine);
3143 }
3144
3145 int
3146 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3147 {
3148 struct intel_engine_cs *engine = req->engine;
3149 int ret;
3150
3151 if (!engine->gpu_caches_dirty)
3152 return 0;
3153
3154 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3155 if (ret)
3156 return ret;
3157
3158 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3159
3160 engine->gpu_caches_dirty = false;
3161 return 0;
3162 }
3163
3164 int
3165 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3166 {
3167 struct intel_engine_cs *engine = req->engine;
3168 uint32_t flush_domains;
3169 int ret;
3170
3171 flush_domains = 0;
3172 if (engine->gpu_caches_dirty)
3173 flush_domains = I915_GEM_GPU_DOMAINS;
3174
3175 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3176 if (ret)
3177 return ret;
3178
3179 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3180
3181 engine->gpu_caches_dirty = false;
3182 return 0;
3183 }
3184
3185 void
3186 intel_stop_engine(struct intel_engine_cs *engine)
3187 {
3188 int ret;
3189
3190 if (!intel_engine_initialized(engine))
3191 return;
3192
3193 ret = intel_engine_idle(engine);
3194 if (ret)
3195 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3196 engine->name, ret);
3197
3198 stop_ring(engine);
3199 }
Linux kernel - Deliverables
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