2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head
, int tail
, int size
)
44 int space
= head
- tail
;
47 return space
- I915_RING_FREE_SPACE
;
50 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
52 if (ringbuf
->last_retired_head
!= -1) {
53 ringbuf
->head
= ringbuf
->last_retired_head
;
54 ringbuf
->last_retired_head
= -1;
57 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
58 ringbuf
->tail
, ringbuf
->size
);
61 static void __intel_ring_advance(struct intel_engine_cs
*engine
)
63 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
64 ringbuf
->tail
&= ringbuf
->size
- 1;
65 engine
->write_tail(engine
, ringbuf
->tail
);
69 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
70 u32 invalidate_domains
,
73 struct intel_engine_cs
*engine
= req
->engine
;
78 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
79 cmd
|= MI_NO_WRITE_FLUSH
;
81 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
84 ret
= intel_ring_begin(req
, 2);
88 intel_ring_emit(engine
, cmd
);
89 intel_ring_emit(engine
, MI_NOOP
);
90 intel_ring_advance(engine
);
96 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
97 u32 invalidate_domains
,
100 struct intel_engine_cs
*engine
= req
->engine
;
107 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
108 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
109 * also flushed at 2d versus 3d pipeline switches.
113 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
114 * MI_READ_FLUSH is set, and is always flushed on 965.
116 * I915_GEM_DOMAIN_COMMAND may not exist?
118 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
119 * invalidated when MI_EXE_FLUSH is set.
121 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
122 * invalidated with every MI_FLUSH.
126 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
127 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
128 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
129 * are flushed at any MI_FLUSH.
132 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
133 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
134 cmd
&= ~MI_NO_WRITE_FLUSH
;
135 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
138 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
139 (IS_G4X(req
->i915
) || IS_GEN5(req
->i915
)))
140 cmd
|= MI_INVALIDATE_ISP
;
142 ret
= intel_ring_begin(req
, 2);
146 intel_ring_emit(engine
, cmd
);
147 intel_ring_emit(engine
, MI_NOOP
);
148 intel_ring_advance(engine
);
154 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
155 * implementing two workarounds on gen6. From section 1.4.7.1
156 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
158 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
159 * produced by non-pipelined state commands), software needs to first
160 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
163 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
164 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
166 * And the workaround for these two requires this workaround first:
168 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
169 * BEFORE the pipe-control with a post-sync op and no write-cache
172 * And this last workaround is tricky because of the requirements on
173 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
176 * "1 of the following must also be set:
177 * - Render Target Cache Flush Enable ([12] of DW1)
178 * - Depth Cache Flush Enable ([0] of DW1)
179 * - Stall at Pixel Scoreboard ([1] of DW1)
180 * - Depth Stall ([13] of DW1)
181 * - Post-Sync Operation ([13] of DW1)
182 * - Notify Enable ([8] of DW1)"
184 * The cache flushes require the workaround flush that triggered this
185 * one, so we can't use it. Depth stall would trigger the same.
186 * Post-sync nonzero is what triggered this second workaround, so we
187 * can't use that one either. Notify enable is IRQs, which aren't
188 * really our business. That leaves only stall at scoreboard.
191 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
193 struct intel_engine_cs
*engine
= req
->engine
;
194 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
197 ret
= intel_ring_begin(req
, 6);
201 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
203 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
204 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
205 intel_ring_emit(engine
, 0); /* low dword */
206 intel_ring_emit(engine
, 0); /* high dword */
207 intel_ring_emit(engine
, MI_NOOP
);
208 intel_ring_advance(engine
);
210 ret
= intel_ring_begin(req
, 6);
214 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(engine
, PIPE_CONTROL_QW_WRITE
);
216 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
217 intel_ring_emit(engine
, 0);
218 intel_ring_emit(engine
, 0);
219 intel_ring_emit(engine
, MI_NOOP
);
220 intel_ring_advance(engine
);
226 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
227 u32 invalidate_domains
, u32 flush_domains
)
229 struct intel_engine_cs
*engine
= req
->engine
;
231 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
234 /* Force SNB workarounds for PIPE_CONTROL flushes */
235 ret
= intel_emit_post_sync_nonzero_flush(req
);
239 /* Just flush everything. Experiments have shown that reducing the
240 * number of bits based on the write domains has little performance
244 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
245 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
247 * Ensure that any following seqno writes only happen
248 * when the render cache is indeed flushed.
250 flags
|= PIPE_CONTROL_CS_STALL
;
252 if (invalidate_domains
) {
253 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
254 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
255 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
256 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
257 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
258 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
260 * TLB invalidate requires a post-sync write.
262 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
265 ret
= intel_ring_begin(req
, 4);
269 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
270 intel_ring_emit(engine
, flags
);
271 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
272 intel_ring_emit(engine
, 0);
273 intel_ring_advance(engine
);
279 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
281 struct intel_engine_cs
*engine
= req
->engine
;
284 ret
= intel_ring_begin(req
, 4);
288 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
289 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
290 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
291 intel_ring_emit(engine
, 0);
292 intel_ring_emit(engine
, 0);
293 intel_ring_advance(engine
);
299 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
300 u32 invalidate_domains
, u32 flush_domains
)
302 struct intel_engine_cs
*engine
= req
->engine
;
304 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
308 * Ensure that any following seqno writes only happen when the render
309 * cache is indeed flushed.
311 * Workaround: 4th PIPE_CONTROL command (except the ones with only
312 * read-cache invalidate bits set) must have the CS_STALL bit set. We
313 * don't try to be clever and just set it unconditionally.
315 flags
|= PIPE_CONTROL_CS_STALL
;
317 /* Just flush everything. Experiments have shown that reducing the
318 * number of bits based on the write domains has little performance
322 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
323 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
324 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
325 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
327 if (invalidate_domains
) {
328 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
329 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
330 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
331 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
332 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
333 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
334 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
336 * TLB invalidate requires a post-sync write.
338 flags
|= PIPE_CONTROL_QW_WRITE
;
339 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
341 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(req
);
349 ret
= intel_ring_begin(req
, 4);
353 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(engine
, flags
);
355 intel_ring_emit(engine
, scratch_addr
);
356 intel_ring_emit(engine
, 0);
357 intel_ring_advance(engine
);
363 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
364 u32 flags
, u32 scratch_addr
)
366 struct intel_engine_cs
*engine
= req
->engine
;
369 ret
= intel_ring_begin(req
, 6);
373 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
374 intel_ring_emit(engine
, flags
);
375 intel_ring_emit(engine
, scratch_addr
);
376 intel_ring_emit(engine
, 0);
377 intel_ring_emit(engine
, 0);
378 intel_ring_emit(engine
, 0);
379 intel_ring_advance(engine
);
385 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
386 u32 invalidate_domains
, u32 flush_domains
)
389 u32 scratch_addr
= req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
392 flags
|= PIPE_CONTROL_CS_STALL
;
395 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
396 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
397 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
398 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
400 if (invalidate_domains
) {
401 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
402 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
403 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
404 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
405 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
406 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
407 flags
|= PIPE_CONTROL_QW_WRITE
;
408 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
410 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
411 ret
= gen8_emit_pipe_control(req
,
412 PIPE_CONTROL_CS_STALL
|
413 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
419 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
422 static void ring_write_tail(struct intel_engine_cs
*engine
,
425 struct drm_i915_private
*dev_priv
= engine
->i915
;
426 I915_WRITE_TAIL(engine
, value
);
429 u64
intel_ring_get_active_head(struct intel_engine_cs
*engine
)
431 struct drm_i915_private
*dev_priv
= engine
->i915
;
434 if (INTEL_GEN(dev_priv
) >= 8)
435 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
436 RING_ACTHD_UDW(engine
->mmio_base
));
437 else if (INTEL_GEN(dev_priv
) >= 4)
438 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
440 acthd
= I915_READ(ACTHD
);
445 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
447 struct drm_i915_private
*dev_priv
= engine
->i915
;
450 addr
= dev_priv
->status_page_dmah
->busaddr
;
451 if (INTEL_GEN(dev_priv
) >= 4)
452 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
453 I915_WRITE(HWS_PGA
, addr
);
456 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
458 struct drm_i915_private
*dev_priv
= engine
->i915
;
461 /* The ring status page addresses are no longer next to the rest of
462 * the ring registers as of gen7.
464 if (IS_GEN7(dev_priv
)) {
465 switch (engine
->id
) {
467 mmio
= RENDER_HWS_PGA_GEN7
;
470 mmio
= BLT_HWS_PGA_GEN7
;
473 * VCS2 actually doesn't exist on Gen7. Only shut up
474 * gcc switch check warning
478 mmio
= BSD_HWS_PGA_GEN7
;
481 mmio
= VEBOX_HWS_PGA_GEN7
;
484 } else if (IS_GEN6(dev_priv
)) {
485 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
487 /* XXX: gen8 returns to sanity */
488 mmio
= RING_HWS_PGA(engine
->mmio_base
);
491 I915_WRITE(mmio
, (u32
)engine
->status_page
.gfx_addr
);
495 * Flush the TLB for this page
497 * FIXME: These two bits have disappeared on gen8, so a question
498 * arises: do we still need this and if so how should we go about
499 * invalidating the TLB?
501 if (IS_GEN(dev_priv
, 6, 7)) {
502 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
504 /* ring should be idle before issuing a sync flush*/
505 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
508 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
510 if (intel_wait_for_register(dev_priv
,
511 reg
, INSTPM_SYNC_FLUSH
, 0,
513 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
518 static bool stop_ring(struct intel_engine_cs
*engine
)
520 struct drm_i915_private
*dev_priv
= engine
->i915
;
522 if (!IS_GEN2(dev_priv
)) {
523 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
524 if (intel_wait_for_register(dev_priv
,
525 RING_MI_MODE(engine
->mmio_base
),
529 DRM_ERROR("%s : timed out trying to stop ring\n",
531 /* Sometimes we observe that the idle flag is not
532 * set even though the ring is empty. So double
533 * check before giving up.
535 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
540 I915_WRITE_CTL(engine
, 0);
541 I915_WRITE_HEAD(engine
, 0);
542 engine
->write_tail(engine
, 0);
544 if (!IS_GEN2(dev_priv
)) {
545 (void)I915_READ_CTL(engine
);
546 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
549 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
552 void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
)
554 memset(&engine
->hangcheck
, 0, sizeof(engine
->hangcheck
));
557 static int init_ring_common(struct intel_engine_cs
*engine
)
559 struct drm_i915_private
*dev_priv
= engine
->i915
;
560 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
561 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
564 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
566 if (!stop_ring(engine
)) {
567 /* G45 ring initialization often fails to reset head to zero */
568 DRM_DEBUG_KMS("%s head not reset to zero "
569 "ctl %08x head %08x tail %08x start %08x\n",
571 I915_READ_CTL(engine
),
572 I915_READ_HEAD(engine
),
573 I915_READ_TAIL(engine
),
574 I915_READ_START(engine
));
576 if (!stop_ring(engine
)) {
577 DRM_ERROR("failed to set %s head to zero "
578 "ctl %08x head %08x tail %08x start %08x\n",
580 I915_READ_CTL(engine
),
581 I915_READ_HEAD(engine
),
582 I915_READ_TAIL(engine
),
583 I915_READ_START(engine
));
589 if (I915_NEED_GFX_HWS(dev_priv
))
590 intel_ring_setup_status_page(engine
);
592 ring_setup_phys_status_page(engine
);
594 /* Enforce ordering by reading HEAD register back */
595 I915_READ_HEAD(engine
);
597 /* Initialize the ring. This must happen _after_ we've cleared the ring
598 * registers with the above sequence (the readback of the HEAD registers
599 * also enforces ordering), otherwise the hw might lose the new ring
600 * register values. */
601 I915_WRITE_START(engine
, i915_gem_obj_ggtt_offset(obj
));
603 /* WaClearRingBufHeadRegAtInit:ctg,elk */
604 if (I915_READ_HEAD(engine
))
605 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
606 engine
->name
, I915_READ_HEAD(engine
));
607 I915_WRITE_HEAD(engine
, 0);
608 (void)I915_READ_HEAD(engine
);
610 I915_WRITE_CTL(engine
,
611 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
614 /* If the head is still not zero, the ring is dead */
615 if (wait_for((I915_READ_CTL(engine
) & RING_VALID
) != 0 &&
616 I915_READ_START(engine
) == i915_gem_obj_ggtt_offset(obj
) &&
617 (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0, 50)) {
618 DRM_ERROR("%s initialization failed "
619 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
621 I915_READ_CTL(engine
),
622 I915_READ_CTL(engine
) & RING_VALID
,
623 I915_READ_HEAD(engine
), I915_READ_TAIL(engine
),
624 I915_READ_START(engine
),
625 (unsigned long)i915_gem_obj_ggtt_offset(obj
));
630 ringbuf
->last_retired_head
= -1;
631 ringbuf
->head
= I915_READ_HEAD(engine
);
632 ringbuf
->tail
= I915_READ_TAIL(engine
) & TAIL_ADDR
;
633 intel_ring_update_space(ringbuf
);
635 intel_engine_init_hangcheck(engine
);
638 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
643 void intel_fini_pipe_control(struct intel_engine_cs
*engine
)
645 if (engine
->scratch
.obj
== NULL
)
648 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
649 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
650 engine
->scratch
.obj
= NULL
;
653 int intel_init_pipe_control(struct intel_engine_cs
*engine
, int size
)
655 struct drm_i915_gem_object
*obj
;
658 WARN_ON(engine
->scratch
.obj
);
660 obj
= i915_gem_object_create_stolen(&engine
->i915
->drm
, size
);
662 obj
= i915_gem_object_create(&engine
->i915
->drm
, size
);
664 DRM_ERROR("Failed to allocate scratch page\n");
669 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, PIN_HIGH
);
673 engine
->scratch
.obj
= obj
;
674 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
675 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
676 engine
->name
, engine
->scratch
.gtt_offset
);
680 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
685 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
687 struct intel_engine_cs
*engine
= req
->engine
;
688 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
694 engine
->gpu_caches_dirty
= true;
695 ret
= intel_ring_flush_all_caches(req
);
699 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
703 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(w
->count
));
704 for (i
= 0; i
< w
->count
; i
++) {
705 intel_ring_emit_reg(engine
, w
->reg
[i
].addr
);
706 intel_ring_emit(engine
, w
->reg
[i
].value
);
708 intel_ring_emit(engine
, MI_NOOP
);
710 intel_ring_advance(engine
);
712 engine
->gpu_caches_dirty
= true;
713 ret
= intel_ring_flush_all_caches(req
);
717 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
722 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
726 ret
= intel_ring_workarounds_emit(req
);
730 ret
= i915_gem_render_state_init(req
);
737 static int wa_add(struct drm_i915_private
*dev_priv
,
739 const u32 mask
, const u32 val
)
741 const u32 idx
= dev_priv
->workarounds
.count
;
743 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
746 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
747 dev_priv
->workarounds
.reg
[idx
].value
= val
;
748 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
750 dev_priv
->workarounds
.count
++;
755 #define WA_REG(addr, mask, val) do { \
756 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
761 #define WA_SET_BIT_MASKED(addr, mask) \
762 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
764 #define WA_CLR_BIT_MASKED(addr, mask) \
765 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
767 #define WA_SET_FIELD_MASKED(addr, mask, value) \
768 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
770 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
771 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
773 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
775 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
778 struct drm_i915_private
*dev_priv
= engine
->i915
;
779 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
780 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
782 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
785 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
786 i915_mmio_reg_offset(reg
));
787 wa
->hw_whitelist_count
[engine
->id
]++;
792 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
794 struct drm_i915_private
*dev_priv
= engine
->i915
;
796 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
798 /* WaDisableAsyncFlipPerfMode:bdw,chv */
799 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
801 /* WaDisablePartialInstShootdown:bdw,chv */
802 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
803 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
805 /* Use Force Non-Coherent whenever executing a 3D context. This is a
806 * workaround for for a possible hang in the unlikely event a TLB
807 * invalidation occurs during a PSD flush.
809 /* WaForceEnableNonCoherent:bdw,chv */
810 /* WaHdcDisableFetchWhenMasked:bdw,chv */
811 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
812 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
813 HDC_FORCE_NON_COHERENT
);
815 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
816 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
817 * polygons in the same 8x4 pixel/sample area to be processed without
818 * stalling waiting for the earlier ones to write to Hierarchical Z
821 * This optimization is off by default for BDW and CHV; turn it on.
823 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
825 /* Wa4x4STCOptimizationDisable:bdw,chv */
826 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
829 * BSpec recommends 8x4 when MSAA is used,
830 * however in practice 16x4 seems fastest.
832 * Note that PS/WM thread counts depend on the WIZ hashing
833 * disable bit, which we don't touch here, but it's good
834 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
836 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
837 GEN6_WIZ_HASHING_MASK
,
838 GEN6_WIZ_HASHING_16x4
);
843 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
845 struct drm_i915_private
*dev_priv
= engine
->i915
;
848 ret
= gen8_init_workarounds(engine
);
852 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
853 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
855 /* WaDisableDopClockGating:bdw */
856 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
857 DOP_CLOCK_GATING_DISABLE
);
859 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
860 GEN8_SAMPLER_POWER_BYPASS_DIS
);
862 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
863 /* WaForceContextSaveRestoreNonCoherent:bdw */
864 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
865 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
866 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
871 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
873 struct drm_i915_private
*dev_priv
= engine
->i915
;
876 ret
= gen8_init_workarounds(engine
);
880 /* WaDisableThreadStallDopClockGating:chv */
881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
883 /* Improve HiZ throughput on CHV. */
884 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
889 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
891 struct drm_i915_private
*dev_priv
= engine
->i915
;
894 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
895 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
897 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
898 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
899 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
901 /* WaDisableKillLogic:bxt,skl,kbl */
902 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
905 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
906 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
907 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
908 FLOW_CONTROL_ENABLE
|
909 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
911 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
912 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
913 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
915 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
916 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
917 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
918 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
919 GEN9_DG_MIRROR_FIX_ENABLE
);
921 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
922 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
923 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
924 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
925 GEN9_RHWO_OPTIMIZATION_DISABLE
);
927 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
928 * but we do that in per ctx batchbuffer as there is an issue
929 * with this register not getting restored on ctx restore
933 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
934 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
935 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
936 GEN9_ENABLE_YV12_BUGFIX
|
937 GEN9_ENABLE_GPGPU_PREEMPTION
);
939 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
940 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
941 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
942 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
944 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
945 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
946 GEN9_CCS_TLB_PREFETCH_ENABLE
);
948 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
949 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_C0
) ||
950 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
951 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
952 PIXEL_MASK_CAMMING_DISABLE
);
954 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
955 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
956 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
957 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
959 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
960 * both tied to WaForceContextSaveRestoreNonCoherent
961 * in some hsds for skl. We keep the tie for all gen9. The
962 * documentation is a bit hazy and so we want to get common behaviour,
963 * even though there is no clear evidence we would need both on kbl/bxt.
964 * This area has been source of system hangs so we play it safe
965 * and mimic the skl regardless of what bspec says.
967 * Use Force Non-Coherent whenever executing a 3D context. This
968 * is a workaround for a possible hang in the unlikely event
969 * a TLB invalidation occurs during a PSD flush.
972 /* WaForceEnableNonCoherent:skl,bxt,kbl */
973 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
974 HDC_FORCE_NON_COHERENT
);
976 /* WaDisableHDCInvalidation:skl,bxt,kbl */
977 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
978 BDW_DISABLE_HDC_INVALIDATION
);
980 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
981 if (IS_SKYLAKE(dev_priv
) ||
982 IS_KABYLAKE(dev_priv
) ||
983 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
984 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
985 GEN8_SAMPLER_POWER_BYPASS_DIS
);
987 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
988 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
990 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
991 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
992 GEN8_LQSC_FLUSH_COHERENT_LINES
));
994 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
995 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
999 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1000 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
1004 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1005 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
1012 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
1014 struct drm_i915_private
*dev_priv
= engine
->i915
;
1015 u8 vals
[3] = { 0, 0, 0 };
1018 for (i
= 0; i
< 3; i
++) {
1022 * Only consider slices where one, and only one, subslice has 7
1025 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1029 * subslice_7eu[i] != 0 (because of the check above) and
1030 * ss_max == 4 (maximum number of subslices possible per slice)
1034 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1038 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1041 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1042 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1043 GEN9_IZ_HASHING_MASK(2) |
1044 GEN9_IZ_HASHING_MASK(1) |
1045 GEN9_IZ_HASHING_MASK(0),
1046 GEN9_IZ_HASHING(2, vals
[2]) |
1047 GEN9_IZ_HASHING(1, vals
[1]) |
1048 GEN9_IZ_HASHING(0, vals
[0]));
1053 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
1055 struct drm_i915_private
*dev_priv
= engine
->i915
;
1058 ret
= gen9_init_workarounds(engine
);
1063 * Actual WA is to disable percontext preemption granularity control
1064 * until D0 which is the default case so this is equivalent to
1065 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1067 if (IS_SKL_REVID(dev_priv
, SKL_REVID_E0
, REVID_FOREVER
)) {
1068 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
1069 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
1072 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
)) {
1073 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1074 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1075 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1078 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1079 * involving this register should also be added to WA batch as required.
1081 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
))
1082 /* WaDisableLSQCROPERFforOCL:skl */
1083 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1084 GEN8_LQSC_RO_PERF_DIS
);
1086 /* WaEnableGapsTsvCreditFix:skl */
1087 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, REVID_FOREVER
)) {
1088 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1089 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1092 /* WaDisablePowerCompilerClockGating:skl */
1093 if (IS_SKL_REVID(dev_priv
, SKL_REVID_B0
, SKL_REVID_B0
))
1094 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1095 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1097 /* WaBarrierPerformanceFixDisable:skl */
1098 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_D0
))
1099 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1100 HDC_FENCE_DEST_SLM_DISABLE
|
1101 HDC_BARRIER_PERFORMANCE_DISABLE
);
1103 /* WaDisableSbeCacheDispatchPortSharing:skl */
1104 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
))
1106 GEN7_HALF_SLICE_CHICKEN1
,
1107 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1109 /* WaDisableGafsUnitClkGating:skl */
1110 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1112 /* WaInPlaceDecompressionHang:skl */
1113 if (IS_SKL_REVID(dev_priv
, SKL_REVID_H0
, REVID_FOREVER
))
1114 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1115 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1117 /* WaDisableLSQCROPERFforOCL:skl */
1118 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1122 return skl_tune_iz_hashing(engine
);
1125 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1127 struct drm_i915_private
*dev_priv
= engine
->i915
;
1130 ret
= gen9_init_workarounds(engine
);
1134 /* WaStoreMultiplePTEenable:bxt */
1135 /* This is a requirement according to Hardware specification */
1136 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1137 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1139 /* WaSetClckGatingDisableMedia:bxt */
1140 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1141 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1142 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1145 /* WaDisableThreadStallDopClockGating:bxt */
1146 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1147 STALL_DOP_GATING_DISABLE
);
1149 /* WaDisablePooledEuLoadBalancingFix:bxt */
1150 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1151 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2
,
1152 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
);
1155 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1156 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1158 GEN7_HALF_SLICE_CHICKEN1
,
1159 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1162 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1163 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1164 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1165 /* WaDisableLSQCROPERFforOCL:bxt */
1166 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1167 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1171 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1176 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1177 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
1178 I915_WRITE(GEN8_L3SQCREG1
, L3_GENERAL_PRIO_CREDITS(62) |
1179 L3_HIGH_PRIO_CREDITS(2));
1181 /* WaInsertDummyPushConstPs:bxt */
1182 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1183 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1184 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1186 /* WaInPlaceDecompressionHang:bxt */
1187 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1188 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1189 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1194 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1196 struct drm_i915_private
*dev_priv
= engine
->i915
;
1199 ret
= gen9_init_workarounds(engine
);
1203 /* WaEnableGapsTsvCreditFix:kbl */
1204 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1205 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1207 /* WaDisableDynamicCreditSharing:kbl */
1208 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1209 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1210 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1212 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1213 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1214 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1215 HDC_FENCE_DEST_SLM_DISABLE
);
1217 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1218 * involving this register should also be added to WA batch as required.
1220 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1221 /* WaDisableLSQCROPERFforOCL:kbl */
1222 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1223 GEN8_LQSC_RO_PERF_DIS
);
1225 /* WaInsertDummyPushConstPs:kbl */
1226 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1227 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1228 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1230 /* WaDisableGafsUnitClkGating:kbl */
1231 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1233 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1235 GEN7_HALF_SLICE_CHICKEN1
,
1236 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1238 /* WaInPlaceDecompressionHang:kbl */
1239 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1240 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1242 /* WaDisableLSQCROPERFforOCL:kbl */
1243 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1250 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1252 struct drm_i915_private
*dev_priv
= engine
->i915
;
1254 WARN_ON(engine
->id
!= RCS
);
1256 dev_priv
->workarounds
.count
= 0;
1257 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1259 if (IS_BROADWELL(dev_priv
))
1260 return bdw_init_workarounds(engine
);
1262 if (IS_CHERRYVIEW(dev_priv
))
1263 return chv_init_workarounds(engine
);
1265 if (IS_SKYLAKE(dev_priv
))
1266 return skl_init_workarounds(engine
);
1268 if (IS_BROXTON(dev_priv
))
1269 return bxt_init_workarounds(engine
);
1271 if (IS_KABYLAKE(dev_priv
))
1272 return kbl_init_workarounds(engine
);
1277 static int init_render_ring(struct intel_engine_cs
*engine
)
1279 struct drm_i915_private
*dev_priv
= engine
->i915
;
1280 int ret
= init_ring_common(engine
);
1284 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1285 if (IS_GEN(dev_priv
, 4, 6))
1286 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1288 /* We need to disable the AsyncFlip performance optimisations in order
1289 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1290 * programmed to '1' on all products.
1292 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1294 if (IS_GEN(dev_priv
, 6, 7))
1295 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1297 /* Required for the hardware to program scanline values for waiting */
1298 /* WaEnableFlushTlbInvalidationMode:snb */
1299 if (IS_GEN6(dev_priv
))
1300 I915_WRITE(GFX_MODE
,
1301 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1303 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1304 if (IS_GEN7(dev_priv
))
1305 I915_WRITE(GFX_MODE_GEN7
,
1306 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1307 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1309 if (IS_GEN6(dev_priv
)) {
1310 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1311 * "If this bit is set, STCunit will have LRA as replacement
1312 * policy. [...] This bit must be reset. LRA replacement
1313 * policy is not supported."
1315 I915_WRITE(CACHE_MODE_0
,
1316 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1319 if (IS_GEN(dev_priv
, 6, 7))
1320 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1322 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1323 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1325 return init_workarounds_ring(engine
);
1328 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1330 struct drm_i915_private
*dev_priv
= engine
->i915
;
1332 if (dev_priv
->semaphore_obj
) {
1333 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1334 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1335 dev_priv
->semaphore_obj
= NULL
;
1338 intel_fini_pipe_control(engine
);
1341 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1342 unsigned int num_dwords
)
1344 #define MBOX_UPDATE_DWORDS 8
1345 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1346 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1347 struct intel_engine_cs
*waiter
;
1348 enum intel_engine_id id
;
1351 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1352 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1353 #undef MBOX_UPDATE_DWORDS
1355 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1359 for_each_engine_id(waiter
, dev_priv
, id
) {
1360 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1361 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1364 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1365 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1366 PIPE_CONTROL_QW_WRITE
|
1367 PIPE_CONTROL_CS_STALL
);
1368 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1369 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1370 intel_ring_emit(signaller
, signaller_req
->seqno
);
1371 intel_ring_emit(signaller
, 0);
1372 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1373 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1374 intel_ring_emit(signaller
, 0);
1380 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1381 unsigned int num_dwords
)
1383 #define MBOX_UPDATE_DWORDS 6
1384 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1385 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1386 struct intel_engine_cs
*waiter
;
1387 enum intel_engine_id id
;
1390 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1391 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1392 #undef MBOX_UPDATE_DWORDS
1394 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1398 for_each_engine_id(waiter
, dev_priv
, id
) {
1399 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1400 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1403 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1404 MI_FLUSH_DW_OP_STOREDW
);
1405 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1406 MI_FLUSH_DW_USE_GTT
);
1407 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1408 intel_ring_emit(signaller
, signaller_req
->seqno
);
1409 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1410 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1411 intel_ring_emit(signaller
, 0);
1417 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1418 unsigned int num_dwords
)
1420 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1421 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1422 struct intel_engine_cs
*useless
;
1423 enum intel_engine_id id
;
1426 #define MBOX_UPDATE_DWORDS 3
1427 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1428 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1429 #undef MBOX_UPDATE_DWORDS
1431 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1435 for_each_engine_id(useless
, dev_priv
, id
) {
1436 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[id
];
1438 if (i915_mmio_reg_valid(mbox_reg
)) {
1439 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1440 intel_ring_emit_reg(signaller
, mbox_reg
);
1441 intel_ring_emit(signaller
, signaller_req
->seqno
);
1445 /* If num_dwords was rounded, make sure the tail pointer is correct */
1446 if (num_rings
% 2 == 0)
1447 intel_ring_emit(signaller
, MI_NOOP
);
1453 * gen6_add_request - Update the semaphore mailbox registers
1455 * @request - request to write to the ring
1457 * Update the mailbox registers in the *other* rings with the current seqno.
1458 * This acts like a signal in the canonical semaphore.
1461 gen6_add_request(struct drm_i915_gem_request
*req
)
1463 struct intel_engine_cs
*engine
= req
->engine
;
1466 if (engine
->semaphore
.signal
)
1467 ret
= engine
->semaphore
.signal(req
, 4);
1469 ret
= intel_ring_begin(req
, 4);
1474 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1475 intel_ring_emit(engine
,
1476 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1477 intel_ring_emit(engine
, req
->seqno
);
1478 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1479 __intel_ring_advance(engine
);
1485 gen8_render_add_request(struct drm_i915_gem_request
*req
)
1487 struct intel_engine_cs
*engine
= req
->engine
;
1490 if (engine
->semaphore
.signal
)
1491 ret
= engine
->semaphore
.signal(req
, 8);
1493 ret
= intel_ring_begin(req
, 8);
1497 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
1498 intel_ring_emit(engine
, (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1499 PIPE_CONTROL_CS_STALL
|
1500 PIPE_CONTROL_QW_WRITE
));
1501 intel_ring_emit(engine
, intel_hws_seqno_address(req
->engine
));
1502 intel_ring_emit(engine
, 0);
1503 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1504 /* We're thrashing one dword of HWS. */
1505 intel_ring_emit(engine
, 0);
1506 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1507 intel_ring_emit(engine
, MI_NOOP
);
1508 __intel_ring_advance(engine
);
1513 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private
*dev_priv
,
1516 return dev_priv
->last_seqno
< seqno
;
1520 * intel_ring_sync - sync the waiter to the signaller on seqno
1522 * @waiter - ring that is waiting
1523 * @signaller - ring which has, or will signal
1524 * @seqno - seqno which the waiter will block on
1528 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1529 struct intel_engine_cs
*signaller
,
1532 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1533 struct drm_i915_private
*dev_priv
= waiter_req
->i915
;
1534 u64 offset
= GEN8_WAIT_OFFSET(waiter
, signaller
->id
);
1535 struct i915_hw_ppgtt
*ppgtt
;
1538 ret
= intel_ring_begin(waiter_req
, 4);
1542 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1543 MI_SEMAPHORE_GLOBAL_GTT
|
1544 MI_SEMAPHORE_SAD_GTE_SDD
);
1545 intel_ring_emit(waiter
, seqno
);
1546 intel_ring_emit(waiter
, lower_32_bits(offset
));
1547 intel_ring_emit(waiter
, upper_32_bits(offset
));
1548 intel_ring_advance(waiter
);
1550 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1551 * pagetables and we must reload them before executing the batch.
1552 * We do this on the i915_switch_context() following the wait and
1553 * before the dispatch.
1555 ppgtt
= waiter_req
->ctx
->ppgtt
;
1556 if (ppgtt
&& waiter_req
->engine
->id
!= RCS
)
1557 ppgtt
->pd_dirty_rings
|= intel_engine_flag(waiter_req
->engine
);
1562 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1563 struct intel_engine_cs
*signaller
,
1566 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1567 u32 dw1
= MI_SEMAPHORE_MBOX
|
1568 MI_SEMAPHORE_COMPARE
|
1569 MI_SEMAPHORE_REGISTER
;
1570 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1573 /* Throughout all of the GEM code, seqno passed implies our current
1574 * seqno is >= the last seqno executed. However for hardware the
1575 * comparison is strictly greater than.
1579 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1581 ret
= intel_ring_begin(waiter_req
, 4);
1585 /* If seqno wrap happened, omit the wait with no-ops */
1586 if (likely(!i915_gem_has_seqno_wrapped(waiter_req
->i915
, seqno
))) {
1587 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1588 intel_ring_emit(waiter
, seqno
);
1589 intel_ring_emit(waiter
, 0);
1590 intel_ring_emit(waiter
, MI_NOOP
);
1592 intel_ring_emit(waiter
, MI_NOOP
);
1593 intel_ring_emit(waiter
, MI_NOOP
);
1594 intel_ring_emit(waiter
, MI_NOOP
);
1595 intel_ring_emit(waiter
, MI_NOOP
);
1597 intel_ring_advance(waiter
);
1603 gen5_seqno_barrier(struct intel_engine_cs
*ring
)
1605 /* MI_STORE are internally buffered by the GPU and not flushed
1606 * either by MI_FLUSH or SyncFlush or any other combination of
1609 * "Only the submission of the store operation is guaranteed.
1610 * The write result will be complete (coherent) some time later
1611 * (this is practically a finite period but there is no guaranteed
1614 * Empirically, we observe that we need a delay of at least 75us to
1615 * be sure that the seqno write is visible by the CPU.
1617 usleep_range(125, 250);
1621 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1623 struct drm_i915_private
*dev_priv
= engine
->i915
;
1625 /* Workaround to force correct ordering between irq and seqno writes on
1626 * ivb (and maybe also on snb) by reading from a CS register (like
1627 * ACTHD) before reading the status page.
1629 * Note that this effectively stalls the read by the time it takes to
1630 * do a memory transaction, which more or less ensures that the write
1631 * from the GPU has sufficient time to invalidate the CPU cacheline.
1632 * Alternatively we could delay the interrupt from the CS ring to give
1633 * the write time to land, but that would incur a delay after every
1634 * batch i.e. much more frequent than a delay when waiting for the
1635 * interrupt (with the same net latency).
1637 * Also note that to prevent whole machine hangs on gen7, we have to
1638 * take the spinlock to guard against concurrent cacheline access.
1640 spin_lock_irq(&dev_priv
->uncore
.lock
);
1641 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1642 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1646 gen5_irq_enable(struct intel_engine_cs
*engine
)
1648 gen5_enable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1652 gen5_irq_disable(struct intel_engine_cs
*engine
)
1654 gen5_disable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1658 i9xx_irq_enable(struct intel_engine_cs
*engine
)
1660 struct drm_i915_private
*dev_priv
= engine
->i915
;
1662 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1663 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1664 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1668 i9xx_irq_disable(struct intel_engine_cs
*engine
)
1670 struct drm_i915_private
*dev_priv
= engine
->i915
;
1672 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1673 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1677 i8xx_irq_enable(struct intel_engine_cs
*engine
)
1679 struct drm_i915_private
*dev_priv
= engine
->i915
;
1681 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1682 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1683 POSTING_READ16(RING_IMR(engine
->mmio_base
));
1687 i8xx_irq_disable(struct intel_engine_cs
*engine
)
1689 struct drm_i915_private
*dev_priv
= engine
->i915
;
1691 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1692 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1696 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1697 u32 invalidate_domains
,
1700 struct intel_engine_cs
*engine
= req
->engine
;
1703 ret
= intel_ring_begin(req
, 2);
1707 intel_ring_emit(engine
, MI_FLUSH
);
1708 intel_ring_emit(engine
, MI_NOOP
);
1709 intel_ring_advance(engine
);
1714 i9xx_add_request(struct drm_i915_gem_request
*req
)
1716 struct intel_engine_cs
*engine
= req
->engine
;
1719 ret
= intel_ring_begin(req
, 4);
1723 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1724 intel_ring_emit(engine
,
1725 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1726 intel_ring_emit(engine
, req
->seqno
);
1727 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1728 __intel_ring_advance(engine
);
1734 gen6_irq_enable(struct intel_engine_cs
*engine
)
1736 struct drm_i915_private
*dev_priv
= engine
->i915
;
1738 I915_WRITE_IMR(engine
,
1739 ~(engine
->irq_enable_mask
|
1740 engine
->irq_keep_mask
));
1741 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1745 gen6_irq_disable(struct intel_engine_cs
*engine
)
1747 struct drm_i915_private
*dev_priv
= engine
->i915
;
1749 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1750 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1754 hsw_vebox_irq_enable(struct intel_engine_cs
*engine
)
1756 struct drm_i915_private
*dev_priv
= engine
->i915
;
1758 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1759 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1763 hsw_vebox_irq_disable(struct intel_engine_cs
*engine
)
1765 struct drm_i915_private
*dev_priv
= engine
->i915
;
1767 I915_WRITE_IMR(engine
, ~0);
1768 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1772 gen8_irq_enable(struct intel_engine_cs
*engine
)
1774 struct drm_i915_private
*dev_priv
= engine
->i915
;
1776 I915_WRITE_IMR(engine
,
1777 ~(engine
->irq_enable_mask
|
1778 engine
->irq_keep_mask
));
1779 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1783 gen8_irq_disable(struct intel_engine_cs
*engine
)
1785 struct drm_i915_private
*dev_priv
= engine
->i915
;
1787 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1791 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1792 u64 offset
, u32 length
,
1793 unsigned dispatch_flags
)
1795 struct intel_engine_cs
*engine
= req
->engine
;
1798 ret
= intel_ring_begin(req
, 2);
1802 intel_ring_emit(engine
,
1803 MI_BATCH_BUFFER_START
|
1805 (dispatch_flags
& I915_DISPATCH_SECURE
?
1806 0 : MI_BATCH_NON_SECURE_I965
));
1807 intel_ring_emit(engine
, offset
);
1808 intel_ring_advance(engine
);
1813 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1814 #define I830_BATCH_LIMIT (256*1024)
1815 #define I830_TLB_ENTRIES (2)
1816 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1818 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1819 u64 offset
, u32 len
,
1820 unsigned dispatch_flags
)
1822 struct intel_engine_cs
*engine
= req
->engine
;
1823 u32 cs_offset
= engine
->scratch
.gtt_offset
;
1826 ret
= intel_ring_begin(req
, 6);
1830 /* Evict the invalid PTE TLBs */
1831 intel_ring_emit(engine
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1832 intel_ring_emit(engine
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1833 intel_ring_emit(engine
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1834 intel_ring_emit(engine
, cs_offset
);
1835 intel_ring_emit(engine
, 0xdeadbeef);
1836 intel_ring_emit(engine
, MI_NOOP
);
1837 intel_ring_advance(engine
);
1839 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1840 if (len
> I830_BATCH_LIMIT
)
1843 ret
= intel_ring_begin(req
, 6 + 2);
1847 /* Blit the batch (which has now all relocs applied) to the
1848 * stable batch scratch bo area (so that the CS never
1849 * stumbles over its tlb invalidation bug) ...
1851 intel_ring_emit(engine
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1852 intel_ring_emit(engine
,
1853 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1854 intel_ring_emit(engine
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1855 intel_ring_emit(engine
, cs_offset
);
1856 intel_ring_emit(engine
, 4096);
1857 intel_ring_emit(engine
, offset
);
1859 intel_ring_emit(engine
, MI_FLUSH
);
1860 intel_ring_emit(engine
, MI_NOOP
);
1861 intel_ring_advance(engine
);
1863 /* ... and execute it. */
1867 ret
= intel_ring_begin(req
, 2);
1871 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1872 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1873 0 : MI_BATCH_NON_SECURE
));
1874 intel_ring_advance(engine
);
1880 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1881 u64 offset
, u32 len
,
1882 unsigned dispatch_flags
)
1884 struct intel_engine_cs
*engine
= req
->engine
;
1887 ret
= intel_ring_begin(req
, 2);
1891 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1892 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1893 0 : MI_BATCH_NON_SECURE
));
1894 intel_ring_advance(engine
);
1899 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
1901 struct drm_i915_private
*dev_priv
= engine
->i915
;
1903 if (!dev_priv
->status_page_dmah
)
1906 drm_pci_free(&dev_priv
->drm
, dev_priv
->status_page_dmah
);
1907 engine
->status_page
.page_addr
= NULL
;
1910 static void cleanup_status_page(struct intel_engine_cs
*engine
)
1912 struct drm_i915_gem_object
*obj
;
1914 obj
= engine
->status_page
.obj
;
1918 kunmap(sg_page(obj
->pages
->sgl
));
1919 i915_gem_object_ggtt_unpin(obj
);
1920 drm_gem_object_unreference(&obj
->base
);
1921 engine
->status_page
.obj
= NULL
;
1924 static int init_status_page(struct intel_engine_cs
*engine
)
1926 struct drm_i915_gem_object
*obj
= engine
->status_page
.obj
;
1932 obj
= i915_gem_object_create(&engine
->i915
->drm
, 4096);
1934 DRM_ERROR("Failed to allocate status page\n");
1935 return PTR_ERR(obj
);
1938 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1943 if (!HAS_LLC(engine
->i915
))
1944 /* On g33, we cannot place HWS above 256MiB, so
1945 * restrict its pinning to the low mappable arena.
1946 * Though this restriction is not documented for
1947 * gen4, gen5, or byt, they also behave similarly
1948 * and hang if the HWS is placed at the top of the
1949 * GTT. To generalise, it appears that all !llc
1950 * platforms have issues with us placing the HWS
1951 * above the mappable region (even though we never
1954 flags
|= PIN_MAPPABLE
;
1955 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1958 drm_gem_object_unreference(&obj
->base
);
1962 engine
->status_page
.obj
= obj
;
1965 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1966 engine
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1967 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
1969 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1970 engine
->name
, engine
->status_page
.gfx_addr
);
1975 static int init_phys_status_page(struct intel_engine_cs
*engine
)
1977 struct drm_i915_private
*dev_priv
= engine
->i915
;
1979 if (!dev_priv
->status_page_dmah
) {
1980 dev_priv
->status_page_dmah
=
1981 drm_pci_alloc(&dev_priv
->drm
, PAGE_SIZE
, PAGE_SIZE
);
1982 if (!dev_priv
->status_page_dmah
)
1986 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1987 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
1992 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1994 GEM_BUG_ON(ringbuf
->vma
== NULL
);
1995 GEM_BUG_ON(ringbuf
->virtual_start
== NULL
);
1997 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
1998 i915_gem_object_unpin_map(ringbuf
->obj
);
2000 i915_vma_unpin_iomap(ringbuf
->vma
);
2001 ringbuf
->virtual_start
= NULL
;
2003 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2004 ringbuf
->vma
= NULL
;
2007 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private
*dev_priv
,
2008 struct intel_ringbuffer
*ringbuf
)
2010 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2011 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2012 unsigned flags
= PIN_OFFSET_BIAS
| 4096;
2016 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2017 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, flags
);
2021 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2025 addr
= i915_gem_object_pin_map(obj
);
2027 ret
= PTR_ERR(addr
);
2031 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
2032 flags
| PIN_MAPPABLE
);
2036 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2040 /* Access through the GTT requires the device to be awake. */
2041 assert_rpm_wakelock_held(dev_priv
);
2043 addr
= i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj
));
2045 ret
= PTR_ERR(addr
);
2050 ringbuf
->virtual_start
= addr
;
2051 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2055 i915_gem_object_ggtt_unpin(obj
);
2059 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2061 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2062 ringbuf
->obj
= NULL
;
2065 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2066 struct intel_ringbuffer
*ringbuf
)
2068 struct drm_i915_gem_object
*obj
;
2072 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2074 obj
= i915_gem_object_create(dev
, ringbuf
->size
);
2076 return PTR_ERR(obj
);
2078 /* mark ring buffers as read-only from GPU side by default */
2086 struct intel_ringbuffer
*
2087 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2089 struct intel_ringbuffer
*ring
;
2092 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2094 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2096 return ERR_PTR(-ENOMEM
);
2099 ring
->engine
= engine
;
2100 list_add(&ring
->link
, &engine
->buffers
);
2103 /* Workaround an erratum on the i830 which causes a hang if
2104 * the TAIL pointer points to within the last 2 cachelines
2107 ring
->effective_size
= size
;
2108 if (IS_I830(engine
->i915
) || IS_845G(engine
->i915
))
2109 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2111 ring
->last_retired_head
= -1;
2112 intel_ring_update_space(ring
);
2114 ret
= intel_alloc_ringbuffer_obj(&engine
->i915
->drm
, ring
);
2116 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2118 list_del(&ring
->link
);
2120 return ERR_PTR(ret
);
2127 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2129 intel_destroy_ringbuffer_obj(ring
);
2130 list_del(&ring
->link
);
2134 static int intel_ring_context_pin(struct i915_gem_context
*ctx
,
2135 struct intel_engine_cs
*engine
)
2137 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2140 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
2142 if (ce
->pin_count
++)
2146 ret
= i915_gem_obj_ggtt_pin(ce
->state
, ctx
->ggtt_alignment
, 0);
2151 /* The kernel context is only used as a placeholder for flushing the
2152 * active context. It is never used for submitting user rendering and
2153 * as such never requires the golden render context, and so we can skip
2154 * emitting it when we switch to the kernel context. This is required
2155 * as during eviction we cannot allocate and pin the renderstate in
2156 * order to initialise the context.
2158 if (ctx
== ctx
->i915
->kernel_context
)
2159 ce
->initialised
= true;
2161 i915_gem_context_reference(ctx
);
2169 static void intel_ring_context_unpin(struct i915_gem_context
*ctx
,
2170 struct intel_engine_cs
*engine
)
2172 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2174 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
2176 if (--ce
->pin_count
)
2180 i915_gem_object_ggtt_unpin(ce
->state
);
2182 i915_gem_context_unreference(ctx
);
2185 static int intel_init_ring_buffer(struct drm_device
*dev
,
2186 struct intel_engine_cs
*engine
)
2188 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2189 struct intel_ringbuffer
*ringbuf
;
2192 WARN_ON(engine
->buffer
);
2194 engine
->i915
= dev_priv
;
2195 INIT_LIST_HEAD(&engine
->active_list
);
2196 INIT_LIST_HEAD(&engine
->request_list
);
2197 INIT_LIST_HEAD(&engine
->execlist_queue
);
2198 INIT_LIST_HEAD(&engine
->buffers
);
2199 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2200 memset(engine
->semaphore
.sync_seqno
, 0,
2201 sizeof(engine
->semaphore
.sync_seqno
));
2203 ret
= intel_engine_init_breadcrumbs(engine
);
2207 /* We may need to do things with the shrinker which
2208 * require us to immediately switch back to the default
2209 * context. This can cause a problem as pinning the
2210 * default context also requires GTT space which may not
2211 * be available. To avoid this we always pin the default
2214 ret
= intel_ring_context_pin(dev_priv
->kernel_context
, engine
);
2218 ringbuf
= intel_engine_create_ringbuffer(engine
, 32 * PAGE_SIZE
);
2219 if (IS_ERR(ringbuf
)) {
2220 ret
= PTR_ERR(ringbuf
);
2223 engine
->buffer
= ringbuf
;
2225 if (I915_NEED_GFX_HWS(dev_priv
)) {
2226 ret
= init_status_page(engine
);
2230 WARN_ON(engine
->id
!= RCS
);
2231 ret
= init_phys_status_page(engine
);
2236 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ringbuf
);
2238 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2240 intel_destroy_ringbuffer_obj(ringbuf
);
2244 ret
= i915_cmd_parser_init_ring(engine
);
2251 intel_cleanup_engine(engine
);
2255 void intel_cleanup_engine(struct intel_engine_cs
*engine
)
2257 struct drm_i915_private
*dev_priv
;
2259 if (!intel_engine_initialized(engine
))
2262 dev_priv
= engine
->i915
;
2264 if (engine
->buffer
) {
2265 intel_stop_engine(engine
);
2266 WARN_ON(!IS_GEN2(dev_priv
) && (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2268 intel_unpin_ringbuffer_obj(engine
->buffer
);
2269 intel_ringbuffer_free(engine
->buffer
);
2270 engine
->buffer
= NULL
;
2273 if (engine
->cleanup
)
2274 engine
->cleanup(engine
);
2276 if (I915_NEED_GFX_HWS(dev_priv
)) {
2277 cleanup_status_page(engine
);
2279 WARN_ON(engine
->id
!= RCS
);
2280 cleanup_phys_status_page(engine
);
2283 i915_cmd_parser_fini_ring(engine
);
2284 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2285 intel_engine_fini_breadcrumbs(engine
);
2287 intel_ring_context_unpin(dev_priv
->kernel_context
, engine
);
2289 engine
->i915
= NULL
;
2292 int intel_engine_idle(struct intel_engine_cs
*engine
)
2294 struct drm_i915_gem_request
*req
;
2296 /* Wait upon the last request to be completed */
2297 if (list_empty(&engine
->request_list
))
2300 req
= list_entry(engine
->request_list
.prev
,
2301 struct drm_i915_gem_request
,
2304 /* Make sure we do not trigger any retires */
2305 return __i915_wait_request(req
,
2306 req
->i915
->mm
.interruptible
,
2310 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2314 /* Flush enough space to reduce the likelihood of waiting after
2315 * we start building the request - in which case we will just
2316 * have to repeat work.
2318 request
->reserved_space
+= LEGACY_REQUEST_SIZE
;
2320 request
->ringbuf
= request
->engine
->buffer
;
2322 ret
= intel_ring_begin(request
, 0);
2326 request
->reserved_space
-= LEGACY_REQUEST_SIZE
;
2330 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2332 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2333 struct intel_engine_cs
*engine
= req
->engine
;
2334 struct drm_i915_gem_request
*target
;
2336 intel_ring_update_space(ringbuf
);
2337 if (ringbuf
->space
>= bytes
)
2341 * Space is reserved in the ringbuffer for finalising the request,
2342 * as that cannot be allowed to fail. During request finalisation,
2343 * reserved_space is set to 0 to stop the overallocation and the
2344 * assumption is that then we never need to wait (which has the
2345 * risk of failing with EINTR).
2347 * See also i915_gem_request_alloc() and i915_add_request().
2349 GEM_BUG_ON(!req
->reserved_space
);
2351 list_for_each_entry(target
, &engine
->request_list
, list
) {
2355 * The request queue is per-engine, so can contain requests
2356 * from multiple ringbuffers. Here, we must ignore any that
2357 * aren't from the ringbuffer we're considering.
2359 if (target
->ringbuf
!= ringbuf
)
2362 /* Would completion of this request free enough space? */
2363 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
2369 if (WARN_ON(&target
->list
== &engine
->request_list
))
2372 return i915_wait_request(target
);
2375 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2377 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2378 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2379 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2380 int bytes
= num_dwords
* sizeof(u32
);
2381 int total_bytes
, wait_bytes
;
2382 bool need_wrap
= false;
2384 total_bytes
= bytes
+ req
->reserved_space
;
2386 if (unlikely(bytes
> remain_usable
)) {
2388 * Not enough space for the basic request. So need to flush
2389 * out the remainder and then wait for base + reserved.
2391 wait_bytes
= remain_actual
+ total_bytes
;
2393 } else if (unlikely(total_bytes
> remain_usable
)) {
2395 * The base request will fit but the reserved space
2396 * falls off the end. So we don't need an immediate wrap
2397 * and only need to effectively wait for the reserved
2398 * size space from the start of ringbuffer.
2400 wait_bytes
= remain_actual
+ req
->reserved_space
;
2402 /* No wrapping required, just waiting. */
2403 wait_bytes
= total_bytes
;
2406 if (wait_bytes
> ringbuf
->space
) {
2407 int ret
= wait_for_space(req
, wait_bytes
);
2411 intel_ring_update_space(ringbuf
);
2412 if (unlikely(ringbuf
->space
< wait_bytes
))
2416 if (unlikely(need_wrap
)) {
2417 GEM_BUG_ON(remain_actual
> ringbuf
->space
);
2418 GEM_BUG_ON(ringbuf
->tail
+ remain_actual
> ringbuf
->size
);
2420 /* Fill the tail with MI_NOOP */
2421 memset(ringbuf
->virtual_start
+ ringbuf
->tail
,
2424 ringbuf
->space
-= remain_actual
;
2427 ringbuf
->space
-= bytes
;
2428 GEM_BUG_ON(ringbuf
->space
< 0);
2432 /* Align the ring tail to a cacheline boundary */
2433 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2435 struct intel_engine_cs
*engine
= req
->engine
;
2436 int num_dwords
= (engine
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2439 if (num_dwords
== 0)
2442 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2443 ret
= intel_ring_begin(req
, num_dwords
);
2447 while (num_dwords
--)
2448 intel_ring_emit(engine
, MI_NOOP
);
2450 intel_ring_advance(engine
);
2455 void intel_ring_init_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
2457 struct drm_i915_private
*dev_priv
= engine
->i915
;
2459 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2460 * so long as the semaphore value in the register/page is greater
2461 * than the sync value), so whenever we reset the seqno,
2462 * so long as we reset the tracking semaphore value to 0, it will
2463 * always be before the next request's seqno. If we don't reset
2464 * the semaphore value, then when the seqno moves backwards all
2465 * future waits will complete instantly (causing rendering corruption).
2467 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
2468 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
2469 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
2470 if (HAS_VEBOX(dev_priv
))
2471 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
2473 if (dev_priv
->semaphore_obj
) {
2474 struct drm_i915_gem_object
*obj
= dev_priv
->semaphore_obj
;
2475 struct page
*page
= i915_gem_object_get_dirty_page(obj
, 0);
2476 void *semaphores
= kmap(page
);
2477 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
2478 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
2481 memset(engine
->semaphore
.sync_seqno
, 0,
2482 sizeof(engine
->semaphore
.sync_seqno
));
2484 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
2485 if (engine
->irq_seqno_barrier
)
2486 engine
->irq_seqno_barrier(engine
);
2487 engine
->last_submitted_seqno
= seqno
;
2489 engine
->hangcheck
.seqno
= seqno
;
2491 /* After manually advancing the seqno, fake the interrupt in case
2492 * there are any waiters for that seqno.
2495 intel_engine_wakeup(engine
);
2499 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*engine
,
2502 struct drm_i915_private
*dev_priv
= engine
->i915
;
2504 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
2506 /* Every tail move must follow the sequence below */
2508 /* Disable notification that the ring is IDLE. The GT
2509 * will then assume that it is busy and bring it out of rc6.
2511 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2512 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2514 /* Clear the context id. Here be magic! */
2515 I915_WRITE64_FW(GEN6_BSD_RNCID
, 0x0);
2517 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2518 if (intel_wait_for_register_fw(dev_priv
,
2519 GEN6_BSD_SLEEP_PSMI_CONTROL
,
2520 GEN6_BSD_SLEEP_INDICATOR
,
2523 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2525 /* Now that the ring is fully powered up, update the tail */
2526 I915_WRITE_FW(RING_TAIL(engine
->mmio_base
), value
);
2527 POSTING_READ_FW(RING_TAIL(engine
->mmio_base
));
2529 /* Let the ring send IDLE messages to the GT again,
2530 * and so let it sleep to conserve power when idle.
2532 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2533 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2535 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
2538 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2539 u32 invalidate
, u32 flush
)
2541 struct intel_engine_cs
*engine
= req
->engine
;
2545 ret
= intel_ring_begin(req
, 4);
2550 if (INTEL_GEN(req
->i915
) >= 8)
2553 /* We always require a command barrier so that subsequent
2554 * commands, such as breadcrumb interrupts, are strictly ordered
2555 * wrt the contents of the write cache being flushed to memory
2556 * (and thus being coherent from the CPU).
2558 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2561 * Bspec vol 1c.5 - video engine command streamer:
2562 * "If ENABLED, all TLBs will be invalidated once the flush
2563 * operation is complete. This bit is only valid when the
2564 * Post-Sync Operation field is a value of 1h or 3h."
2566 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2567 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2569 intel_ring_emit(engine
, cmd
);
2570 intel_ring_emit(engine
,
2571 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2572 if (INTEL_GEN(req
->i915
) >= 8) {
2573 intel_ring_emit(engine
, 0); /* upper addr */
2574 intel_ring_emit(engine
, 0); /* value */
2576 intel_ring_emit(engine
, 0);
2577 intel_ring_emit(engine
, MI_NOOP
);
2579 intel_ring_advance(engine
);
2584 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2585 u64 offset
, u32 len
,
2586 unsigned dispatch_flags
)
2588 struct intel_engine_cs
*engine
= req
->engine
;
2589 bool ppgtt
= USES_PPGTT(engine
->dev
) &&
2590 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2593 ret
= intel_ring_begin(req
, 4);
2597 /* FIXME(BDW): Address space and security selectors. */
2598 intel_ring_emit(engine
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2599 (dispatch_flags
& I915_DISPATCH_RS
?
2600 MI_BATCH_RESOURCE_STREAMER
: 0));
2601 intel_ring_emit(engine
, lower_32_bits(offset
));
2602 intel_ring_emit(engine
, upper_32_bits(offset
));
2603 intel_ring_emit(engine
, MI_NOOP
);
2604 intel_ring_advance(engine
);
2610 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2611 u64 offset
, u32 len
,
2612 unsigned dispatch_flags
)
2614 struct intel_engine_cs
*engine
= req
->engine
;
2617 ret
= intel_ring_begin(req
, 2);
2621 intel_ring_emit(engine
,
2622 MI_BATCH_BUFFER_START
|
2623 (dispatch_flags
& I915_DISPATCH_SECURE
?
2624 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2625 (dispatch_flags
& I915_DISPATCH_RS
?
2626 MI_BATCH_RESOURCE_STREAMER
: 0));
2627 /* bit0-7 is the length on GEN6+ */
2628 intel_ring_emit(engine
, offset
);
2629 intel_ring_advance(engine
);
2635 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2636 u64 offset
, u32 len
,
2637 unsigned dispatch_flags
)
2639 struct intel_engine_cs
*engine
= req
->engine
;
2642 ret
= intel_ring_begin(req
, 2);
2646 intel_ring_emit(engine
,
2647 MI_BATCH_BUFFER_START
|
2648 (dispatch_flags
& I915_DISPATCH_SECURE
?
2649 0 : MI_BATCH_NON_SECURE_I965
));
2650 /* bit0-7 is the length on GEN6+ */
2651 intel_ring_emit(engine
, offset
);
2652 intel_ring_advance(engine
);
2657 /* Blitter support (SandyBridge+) */
2659 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2660 u32 invalidate
, u32 flush
)
2662 struct intel_engine_cs
*engine
= req
->engine
;
2666 ret
= intel_ring_begin(req
, 4);
2671 if (INTEL_GEN(req
->i915
) >= 8)
2674 /* We always require a command barrier so that subsequent
2675 * commands, such as breadcrumb interrupts, are strictly ordered
2676 * wrt the contents of the write cache being flushed to memory
2677 * (and thus being coherent from the CPU).
2679 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2682 * Bspec vol 1c.3 - blitter engine command streamer:
2683 * "If ENABLED, all TLBs will be invalidated once the flush
2684 * operation is complete. This bit is only valid when the
2685 * Post-Sync Operation field is a value of 1h or 3h."
2687 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2688 cmd
|= MI_INVALIDATE_TLB
;
2689 intel_ring_emit(engine
, cmd
);
2690 intel_ring_emit(engine
,
2691 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2692 if (INTEL_GEN(req
->i915
) >= 8) {
2693 intel_ring_emit(engine
, 0); /* upper addr */
2694 intel_ring_emit(engine
, 0); /* value */
2696 intel_ring_emit(engine
, 0);
2697 intel_ring_emit(engine
, MI_NOOP
);
2699 intel_ring_advance(engine
);
2704 static void intel_ring_init_semaphores(struct drm_i915_private
*dev_priv
,
2705 struct intel_engine_cs
*engine
)
2707 struct drm_i915_gem_object
*obj
;
2710 if (!i915_semaphore_is_enabled(dev_priv
))
2713 if (INTEL_GEN(dev_priv
) >= 8 && !dev_priv
->semaphore_obj
) {
2714 obj
= i915_gem_object_create(&dev_priv
->drm
, 4096);
2716 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2717 i915
.semaphores
= 0;
2719 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2720 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2722 drm_gem_object_unreference(&obj
->base
);
2723 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2724 i915
.semaphores
= 0;
2726 dev_priv
->semaphore_obj
= obj
;
2731 if (!i915_semaphore_is_enabled(dev_priv
))
2734 if (INTEL_GEN(dev_priv
) >= 8) {
2735 u64 offset
= i915_gem_obj_ggtt_offset(dev_priv
->semaphore_obj
);
2737 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2738 engine
->semaphore
.signal
= gen8_xcs_signal
;
2740 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2743 if (i
!= engine
->id
)
2744 ring_offset
= offset
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, i
);
2746 ring_offset
= MI_SEMAPHORE_SYNC_INVALID
;
2748 engine
->semaphore
.signal_ggtt
[i
] = ring_offset
;
2750 } else if (INTEL_GEN(dev_priv
) >= 6) {
2751 engine
->semaphore
.sync_to
= gen6_ring_sync
;
2752 engine
->semaphore
.signal
= gen6_signal
;
2755 * The current semaphore is only applied on pre-gen8
2756 * platform. And there is no VCS2 ring on the pre-gen8
2757 * platform. So the semaphore between RCS and VCS2 is
2758 * initialized as INVALID. Gen8 will initialize the
2759 * sema between VCS2 and RCS later.
2761 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2762 static const struct {
2764 i915_reg_t mbox_reg
;
2765 } sem_data
[I915_NUM_ENGINES
][I915_NUM_ENGINES
] = {
2767 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RV
, .mbox_reg
= GEN6_VRSYNC
},
2768 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RB
, .mbox_reg
= GEN6_BRSYNC
},
2769 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RVE
, .mbox_reg
= GEN6_VERSYNC
},
2772 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VR
, .mbox_reg
= GEN6_RVSYNC
},
2773 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VB
, .mbox_reg
= GEN6_BVSYNC
},
2774 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VVE
, .mbox_reg
= GEN6_VEVSYNC
},
2777 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BR
, .mbox_reg
= GEN6_RBSYNC
},
2778 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BV
, .mbox_reg
= GEN6_VBSYNC
},
2779 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BVE
, .mbox_reg
= GEN6_VEBSYNC
},
2782 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VER
, .mbox_reg
= GEN6_RVESYNC
},
2783 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEV
, .mbox_reg
= GEN6_VVESYNC
},
2784 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEB
, .mbox_reg
= GEN6_BVESYNC
},
2788 i915_reg_t mbox_reg
;
2790 if (i
== engine
->id
|| i
== VCS2
) {
2791 wait_mbox
= MI_SEMAPHORE_SYNC_INVALID
;
2792 mbox_reg
= GEN6_NOSYNC
;
2794 wait_mbox
= sem_data
[engine
->id
][i
].wait_mbox
;
2795 mbox_reg
= sem_data
[engine
->id
][i
].mbox_reg
;
2798 engine
->semaphore
.mbox
.wait
[i
] = wait_mbox
;
2799 engine
->semaphore
.mbox
.signal
[i
] = mbox_reg
;
2804 static void intel_ring_init_irq(struct drm_i915_private
*dev_priv
,
2805 struct intel_engine_cs
*engine
)
2807 if (INTEL_GEN(dev_priv
) >= 8) {
2808 engine
->irq_enable
= gen8_irq_enable
;
2809 engine
->irq_disable
= gen8_irq_disable
;
2810 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2811 } else if (INTEL_GEN(dev_priv
) >= 6) {
2812 engine
->irq_enable
= gen6_irq_enable
;
2813 engine
->irq_disable
= gen6_irq_disable
;
2814 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2815 } else if (INTEL_GEN(dev_priv
) >= 5) {
2816 engine
->irq_enable
= gen5_irq_enable
;
2817 engine
->irq_disable
= gen5_irq_disable
;
2818 engine
->irq_seqno_barrier
= gen5_seqno_barrier
;
2819 } else if (INTEL_GEN(dev_priv
) >= 3) {
2820 engine
->irq_enable
= i9xx_irq_enable
;
2821 engine
->irq_disable
= i9xx_irq_disable
;
2823 engine
->irq_enable
= i8xx_irq_enable
;
2824 engine
->irq_disable
= i8xx_irq_disable
;
2828 static void intel_ring_default_vfuncs(struct drm_i915_private
*dev_priv
,
2829 struct intel_engine_cs
*engine
)
2831 engine
->init_hw
= init_ring_common
;
2832 engine
->write_tail
= ring_write_tail
;
2834 engine
->add_request
= i9xx_add_request
;
2835 if (INTEL_GEN(dev_priv
) >= 6)
2836 engine
->add_request
= gen6_add_request
;
2838 if (INTEL_GEN(dev_priv
) >= 8)
2839 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2840 else if (INTEL_GEN(dev_priv
) >= 6)
2841 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2842 else if (INTEL_GEN(dev_priv
) >= 4)
2843 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2844 else if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
2845 engine
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2847 engine
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2849 intel_ring_init_irq(dev_priv
, engine
);
2850 intel_ring_init_semaphores(dev_priv
, engine
);
2853 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2855 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2856 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2859 engine
->name
= "render ring";
2861 engine
->exec_id
= I915_EXEC_RENDER
;
2863 engine
->mmio_base
= RENDER_RING_BASE
;
2865 intel_ring_default_vfuncs(dev_priv
, engine
);
2867 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2868 if (HAS_L3_DPF(dev_priv
))
2869 engine
->irq_keep_mask
= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2871 if (INTEL_GEN(dev_priv
) >= 8) {
2872 engine
->init_context
= intel_rcs_ctx_init
;
2873 engine
->add_request
= gen8_render_add_request
;
2874 engine
->flush
= gen8_render_ring_flush
;
2875 if (i915_semaphore_is_enabled(dev_priv
))
2876 engine
->semaphore
.signal
= gen8_rcs_signal
;
2877 } else if (INTEL_GEN(dev_priv
) >= 6) {
2878 engine
->init_context
= intel_rcs_ctx_init
;
2879 engine
->flush
= gen7_render_ring_flush
;
2880 if (IS_GEN6(dev_priv
))
2881 engine
->flush
= gen6_render_ring_flush
;
2882 } else if (IS_GEN5(dev_priv
)) {
2883 engine
->flush
= gen4_render_ring_flush
;
2885 if (INTEL_GEN(dev_priv
) < 4)
2886 engine
->flush
= gen2_render_ring_flush
;
2888 engine
->flush
= gen4_render_ring_flush
;
2889 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2892 if (IS_HASWELL(dev_priv
))
2893 engine
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2895 engine
->init_hw
= init_render_ring
;
2896 engine
->cleanup
= render_ring_cleanup
;
2898 ret
= intel_init_ring_buffer(dev
, engine
);
2902 if (INTEL_GEN(dev_priv
) >= 6) {
2903 ret
= intel_init_pipe_control(engine
, 4096);
2906 } else if (HAS_BROKEN_CS_TLB(dev_priv
)) {
2907 ret
= intel_init_pipe_control(engine
, I830_WA_SIZE
);
2915 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2917 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2918 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2920 engine
->name
= "bsd ring";
2922 engine
->exec_id
= I915_EXEC_BSD
;
2925 intel_ring_default_vfuncs(dev_priv
, engine
);
2927 if (INTEL_GEN(dev_priv
) >= 6) {
2928 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2929 /* gen6 bsd needs a special wa for tail updates */
2930 if (IS_GEN6(dev_priv
))
2931 engine
->write_tail
= gen6_bsd_ring_write_tail
;
2932 engine
->flush
= gen6_bsd_ring_flush
;
2933 if (INTEL_GEN(dev_priv
) >= 8)
2934 engine
->irq_enable_mask
=
2935 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2937 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2939 engine
->mmio_base
= BSD_RING_BASE
;
2940 engine
->flush
= bsd_ring_flush
;
2941 if (IS_GEN5(dev_priv
))
2942 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2944 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2947 return intel_init_ring_buffer(dev
, engine
);
2951 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2953 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2955 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2956 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2958 engine
->name
= "bsd2 ring";
2960 engine
->exec_id
= I915_EXEC_BSD
;
2962 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2964 intel_ring_default_vfuncs(dev_priv
, engine
);
2966 engine
->flush
= gen6_bsd_ring_flush
;
2967 engine
->irq_enable_mask
=
2968 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2970 return intel_init_ring_buffer(dev
, engine
);
2973 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2975 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2976 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2978 engine
->name
= "blitter ring";
2980 engine
->exec_id
= I915_EXEC_BLT
;
2982 engine
->mmio_base
= BLT_RING_BASE
;
2984 intel_ring_default_vfuncs(dev_priv
, engine
);
2986 engine
->flush
= gen6_ring_flush
;
2987 if (INTEL_GEN(dev_priv
) >= 8)
2988 engine
->irq_enable_mask
=
2989 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2991 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2993 return intel_init_ring_buffer(dev
, engine
);
2996 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2998 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2999 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
3001 engine
->name
= "video enhancement ring";
3003 engine
->exec_id
= I915_EXEC_VEBOX
;
3005 engine
->mmio_base
= VEBOX_RING_BASE
;
3007 intel_ring_default_vfuncs(dev_priv
, engine
);
3009 engine
->flush
= gen6_ring_flush
;
3011 if (INTEL_GEN(dev_priv
) >= 8) {
3012 engine
->irq_enable_mask
=
3013 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3015 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3016 engine
->irq_enable
= hsw_vebox_irq_enable
;
3017 engine
->irq_disable
= hsw_vebox_irq_disable
;
3020 return intel_init_ring_buffer(dev
, engine
);
3024 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3026 struct intel_engine_cs
*engine
= req
->engine
;
3029 if (!engine
->gpu_caches_dirty
)
3032 ret
= engine
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3036 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3038 engine
->gpu_caches_dirty
= false;
3043 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3045 struct intel_engine_cs
*engine
= req
->engine
;
3046 uint32_t flush_domains
;
3050 if (engine
->gpu_caches_dirty
)
3051 flush_domains
= I915_GEM_GPU_DOMAINS
;
3053 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3057 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3059 engine
->gpu_caches_dirty
= false;
3064 intel_stop_engine(struct intel_engine_cs
*engine
)
3068 if (!intel_engine_initialized(engine
))
3071 ret
= intel_engine_idle(engine
);
3073 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",