2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head
, int tail
, int size
)
44 int space
= head
- tail
;
47 return space
- I915_RING_FREE_SPACE
;
50 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
52 if (ringbuf
->last_retired_head
!= -1) {
53 ringbuf
->head
= ringbuf
->last_retired_head
;
54 ringbuf
->last_retired_head
= -1;
57 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
58 ringbuf
->tail
, ringbuf
->size
);
61 bool intel_engine_stopped(struct intel_engine_cs
*engine
)
63 struct drm_i915_private
*dev_priv
= engine
->i915
;
64 return dev_priv
->gpu_error
.stop_rings
& intel_engine_flag(engine
);
67 static void __intel_ring_advance(struct intel_engine_cs
*engine
)
69 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
70 ringbuf
->tail
&= ringbuf
->size
- 1;
71 if (intel_engine_stopped(engine
))
73 engine
->write_tail(engine
, ringbuf
->tail
);
77 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
78 u32 invalidate_domains
,
81 struct intel_engine_cs
*engine
= req
->engine
;
86 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
87 cmd
|= MI_NO_WRITE_FLUSH
;
89 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
92 ret
= intel_ring_begin(req
, 2);
96 intel_ring_emit(engine
, cmd
);
97 intel_ring_emit(engine
, MI_NOOP
);
98 intel_ring_advance(engine
);
104 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
105 u32 invalidate_domains
,
108 struct intel_engine_cs
*engine
= req
->engine
;
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
124 * I915_GEM_DOMAIN_COMMAND may not exist?
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
140 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
141 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
142 cmd
&= ~MI_NO_WRITE_FLUSH
;
143 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
146 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
147 (IS_G4X(req
->i915
) || IS_GEN5(req
->i915
)))
148 cmd
|= MI_INVALIDATE_ISP
;
150 ret
= intel_ring_begin(req
, 2);
154 intel_ring_emit(engine
, cmd
);
155 intel_ring_emit(engine
, MI_NOOP
);
156 intel_ring_advance(engine
);
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
174 * And the workaround for these two requires this workaround first:
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
201 struct intel_engine_cs
*engine
= req
->engine
;
202 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
205 ret
= intel_ring_begin(req
, 6);
209 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
211 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
212 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
213 intel_ring_emit(engine
, 0); /* low dword */
214 intel_ring_emit(engine
, 0); /* high dword */
215 intel_ring_emit(engine
, MI_NOOP
);
216 intel_ring_advance(engine
);
218 ret
= intel_ring_begin(req
, 6);
222 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine
, PIPE_CONTROL_QW_WRITE
);
224 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
225 intel_ring_emit(engine
, 0);
226 intel_ring_emit(engine
, 0);
227 intel_ring_emit(engine
, MI_NOOP
);
228 intel_ring_advance(engine
);
234 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
235 u32 invalidate_domains
, u32 flush_domains
)
237 struct intel_engine_cs
*engine
= req
->engine
;
239 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
242 /* Force SNB workarounds for PIPE_CONTROL flushes */
243 ret
= intel_emit_post_sync_nonzero_flush(req
);
247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
252 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
253 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
258 flags
|= PIPE_CONTROL_CS_STALL
;
260 if (invalidate_domains
) {
261 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
262 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
263 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
264 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
265 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
266 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
268 * TLB invalidate requires a post-sync write.
270 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
273 ret
= intel_ring_begin(req
, 4);
277 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine
, flags
);
279 intel_ring_emit(engine
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
280 intel_ring_emit(engine
, 0);
281 intel_ring_advance(engine
);
287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
289 struct intel_engine_cs
*engine
= req
->engine
;
292 ret
= intel_ring_begin(req
, 4);
296 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine
, PIPE_CONTROL_CS_STALL
|
298 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
299 intel_ring_emit(engine
, 0);
300 intel_ring_emit(engine
, 0);
301 intel_ring_advance(engine
);
307 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
308 u32 invalidate_domains
, u32 flush_domains
)
310 struct intel_engine_cs
*engine
= req
->engine
;
312 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
323 flags
|= PIPE_CONTROL_CS_STALL
;
325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
330 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
331 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
332 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
333 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
335 if (invalidate_domains
) {
336 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
337 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
338 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
339 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
340 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
341 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
342 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
344 * TLB invalidate requires a post-sync write.
346 flags
|= PIPE_CONTROL_QW_WRITE
;
347 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
349 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
354 gen7_render_ring_cs_stall_wa(req
);
357 ret
= intel_ring_begin(req
, 4);
361 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine
, flags
);
363 intel_ring_emit(engine
, scratch_addr
);
364 intel_ring_emit(engine
, 0);
365 intel_ring_advance(engine
);
371 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
372 u32 flags
, u32 scratch_addr
)
374 struct intel_engine_cs
*engine
= req
->engine
;
377 ret
= intel_ring_begin(req
, 6);
381 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine
, flags
);
383 intel_ring_emit(engine
, scratch_addr
);
384 intel_ring_emit(engine
, 0);
385 intel_ring_emit(engine
, 0);
386 intel_ring_emit(engine
, 0);
387 intel_ring_advance(engine
);
393 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
394 u32 invalidate_domains
, u32 flush_domains
)
397 u32 scratch_addr
= req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
400 flags
|= PIPE_CONTROL_CS_STALL
;
403 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
404 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
405 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
406 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
408 if (invalidate_domains
) {
409 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
410 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
411 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
412 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
413 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
414 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
415 flags
|= PIPE_CONTROL_QW_WRITE
;
416 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
419 ret
= gen8_emit_pipe_control(req
,
420 PIPE_CONTROL_CS_STALL
|
421 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
427 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
430 static void ring_write_tail(struct intel_engine_cs
*engine
,
433 struct drm_i915_private
*dev_priv
= engine
->i915
;
434 I915_WRITE_TAIL(engine
, value
);
437 u64
intel_ring_get_active_head(struct intel_engine_cs
*engine
)
439 struct drm_i915_private
*dev_priv
= engine
->i915
;
442 if (INTEL_GEN(dev_priv
) >= 8)
443 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
444 RING_ACTHD_UDW(engine
->mmio_base
));
445 else if (INTEL_GEN(dev_priv
) >= 4)
446 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
448 acthd
= I915_READ(ACTHD
);
453 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
455 struct drm_i915_private
*dev_priv
= engine
->i915
;
458 addr
= dev_priv
->status_page_dmah
->busaddr
;
459 if (INTEL_GEN(dev_priv
) >= 4)
460 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
461 I915_WRITE(HWS_PGA
, addr
);
464 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
466 struct drm_i915_private
*dev_priv
= engine
->i915
;
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
472 if (IS_GEN7(dev_priv
)) {
473 switch (engine
->id
) {
475 mmio
= RENDER_HWS_PGA_GEN7
;
478 mmio
= BLT_HWS_PGA_GEN7
;
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
486 mmio
= BSD_HWS_PGA_GEN7
;
489 mmio
= VEBOX_HWS_PGA_GEN7
;
492 } else if (IS_GEN6(dev_priv
)) {
493 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
495 /* XXX: gen8 returns to sanity */
496 mmio
= RING_HWS_PGA(engine
->mmio_base
);
499 I915_WRITE(mmio
, (u32
)engine
->status_page
.gfx_addr
);
503 * Flush the TLB for this page
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
509 if (IS_GEN(dev_priv
, 6, 7)) {
510 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
512 /* ring should be idle before issuing a sync flush*/
513 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
518 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
520 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
525 static bool stop_ring(struct intel_engine_cs
*engine
)
527 struct drm_i915_private
*dev_priv
= engine
->i915
;
529 if (!IS_GEN2(dev_priv
)) {
530 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
531 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
532 DRM_ERROR("%s : timed out trying to stop ring\n",
534 /* Sometimes we observe that the idle flag is not
535 * set even though the ring is empty. So double
536 * check before giving up.
538 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
543 I915_WRITE_CTL(engine
, 0);
544 I915_WRITE_HEAD(engine
, 0);
545 engine
->write_tail(engine
, 0);
547 if (!IS_GEN2(dev_priv
)) {
548 (void)I915_READ_CTL(engine
);
549 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
552 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
555 void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
)
557 memset(&engine
->hangcheck
, 0, sizeof(engine
->hangcheck
));
560 static int init_ring_common(struct intel_engine_cs
*engine
)
562 struct drm_i915_private
*dev_priv
= engine
->i915
;
563 struct intel_ringbuffer
*ringbuf
= engine
->buffer
;
564 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
567 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
569 if (!stop_ring(engine
)) {
570 /* G45 ring initialization often fails to reset head to zero */
571 DRM_DEBUG_KMS("%s head not reset to zero "
572 "ctl %08x head %08x tail %08x start %08x\n",
574 I915_READ_CTL(engine
),
575 I915_READ_HEAD(engine
),
576 I915_READ_TAIL(engine
),
577 I915_READ_START(engine
));
579 if (!stop_ring(engine
)) {
580 DRM_ERROR("failed to set %s head to zero "
581 "ctl %08x head %08x tail %08x start %08x\n",
583 I915_READ_CTL(engine
),
584 I915_READ_HEAD(engine
),
585 I915_READ_TAIL(engine
),
586 I915_READ_START(engine
));
592 if (I915_NEED_GFX_HWS(dev_priv
))
593 intel_ring_setup_status_page(engine
);
595 ring_setup_phys_status_page(engine
);
597 /* Enforce ordering by reading HEAD register back */
598 I915_READ_HEAD(engine
);
600 /* Initialize the ring. This must happen _after_ we've cleared the ring
601 * registers with the above sequence (the readback of the HEAD registers
602 * also enforces ordering), otherwise the hw might lose the new ring
603 * register values. */
604 I915_WRITE_START(engine
, i915_gem_obj_ggtt_offset(obj
));
606 /* WaClearRingBufHeadRegAtInit:ctg,elk */
607 if (I915_READ_HEAD(engine
))
608 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
609 engine
->name
, I915_READ_HEAD(engine
));
610 I915_WRITE_HEAD(engine
, 0);
611 (void)I915_READ_HEAD(engine
);
613 I915_WRITE_CTL(engine
,
614 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
617 /* If the head is still not zero, the ring is dead */
618 if (wait_for((I915_READ_CTL(engine
) & RING_VALID
) != 0 &&
619 I915_READ_START(engine
) == i915_gem_obj_ggtt_offset(obj
) &&
620 (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0, 50)) {
621 DRM_ERROR("%s initialization failed "
622 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
624 I915_READ_CTL(engine
),
625 I915_READ_CTL(engine
) & RING_VALID
,
626 I915_READ_HEAD(engine
), I915_READ_TAIL(engine
),
627 I915_READ_START(engine
),
628 (unsigned long)i915_gem_obj_ggtt_offset(obj
));
633 ringbuf
->last_retired_head
= -1;
634 ringbuf
->head
= I915_READ_HEAD(engine
);
635 ringbuf
->tail
= I915_READ_TAIL(engine
) & TAIL_ADDR
;
636 intel_ring_update_space(ringbuf
);
638 intel_engine_init_hangcheck(engine
);
641 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
647 intel_fini_pipe_control(struct intel_engine_cs
*engine
)
649 if (engine
->scratch
.obj
== NULL
)
652 if (INTEL_GEN(engine
->i915
) >= 5) {
653 kunmap(sg_page(engine
->scratch
.obj
->pages
->sgl
));
654 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
657 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
658 engine
->scratch
.obj
= NULL
;
662 intel_init_pipe_control(struct intel_engine_cs
*engine
)
666 WARN_ON(engine
->scratch
.obj
);
668 engine
->scratch
.obj
= i915_gem_object_create(engine
->i915
->dev
, 4096);
669 if (IS_ERR(engine
->scratch
.obj
)) {
670 DRM_ERROR("Failed to allocate seqno page\n");
671 ret
= PTR_ERR(engine
->scratch
.obj
);
672 engine
->scratch
.obj
= NULL
;
676 ret
= i915_gem_object_set_cache_level(engine
->scratch
.obj
,
681 ret
= i915_gem_obj_ggtt_pin(engine
->scratch
.obj
, 4096, 0);
685 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(engine
->scratch
.obj
);
686 engine
->scratch
.cpu_page
= kmap(sg_page(engine
->scratch
.obj
->pages
->sgl
));
687 if (engine
->scratch
.cpu_page
== NULL
) {
692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
693 engine
->name
, engine
->scratch
.gtt_offset
);
697 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
699 drm_gem_object_unreference(&engine
->scratch
.obj
->base
);
704 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
706 struct intel_engine_cs
*engine
= req
->engine
;
707 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
713 engine
->gpu_caches_dirty
= true;
714 ret
= intel_ring_flush_all_caches(req
);
718 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
722 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(w
->count
));
723 for (i
= 0; i
< w
->count
; i
++) {
724 intel_ring_emit_reg(engine
, w
->reg
[i
].addr
);
725 intel_ring_emit(engine
, w
->reg
[i
].value
);
727 intel_ring_emit(engine
, MI_NOOP
);
729 intel_ring_advance(engine
);
731 engine
->gpu_caches_dirty
= true;
732 ret
= intel_ring_flush_all_caches(req
);
736 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
741 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
745 ret
= intel_ring_workarounds_emit(req
);
749 ret
= i915_gem_render_state_init(req
);
756 static int wa_add(struct drm_i915_private
*dev_priv
,
758 const u32 mask
, const u32 val
)
760 const u32 idx
= dev_priv
->workarounds
.count
;
762 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
765 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
766 dev_priv
->workarounds
.reg
[idx
].value
= val
;
767 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
769 dev_priv
->workarounds
.count
++;
774 #define WA_REG(addr, mask, val) do { \
775 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
780 #define WA_SET_BIT_MASKED(addr, mask) \
781 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
783 #define WA_CLR_BIT_MASKED(addr, mask) \
784 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
786 #define WA_SET_FIELD_MASKED(addr, mask, value) \
787 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
789 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
790 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
792 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
794 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
797 struct drm_i915_private
*dev_priv
= engine
->i915
;
798 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
799 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
801 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
804 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
805 i915_mmio_reg_offset(reg
));
806 wa
->hw_whitelist_count
[engine
->id
]++;
811 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
813 struct drm_i915_private
*dev_priv
= engine
->i915
;
815 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
817 /* WaDisableAsyncFlipPerfMode:bdw,chv */
818 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
820 /* WaDisablePartialInstShootdown:bdw,chv */
821 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
822 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
824 /* Use Force Non-Coherent whenever executing a 3D context. This is a
825 * workaround for for a possible hang in the unlikely event a TLB
826 * invalidation occurs during a PSD flush.
828 /* WaForceEnableNonCoherent:bdw,chv */
829 /* WaHdcDisableFetchWhenMasked:bdw,chv */
830 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
831 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
832 HDC_FORCE_NON_COHERENT
);
834 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
835 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
836 * polygons in the same 8x4 pixel/sample area to be processed without
837 * stalling waiting for the earlier ones to write to Hierarchical Z
840 * This optimization is off by default for BDW and CHV; turn it on.
842 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
844 /* Wa4x4STCOptimizationDisable:bdw,chv */
845 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
848 * BSpec recommends 8x4 when MSAA is used,
849 * however in practice 16x4 seems fastest.
851 * Note that PS/WM thread counts depend on the WIZ hashing
852 * disable bit, which we don't touch here, but it's good
853 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
855 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
856 GEN6_WIZ_HASHING_MASK
,
857 GEN6_WIZ_HASHING_16x4
);
862 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
864 struct drm_i915_private
*dev_priv
= engine
->i915
;
867 ret
= gen8_init_workarounds(engine
);
871 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
872 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
874 /* WaDisableDopClockGating:bdw */
875 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
876 DOP_CLOCK_GATING_DISABLE
);
878 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
879 GEN8_SAMPLER_POWER_BYPASS_DIS
);
881 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
882 /* WaForceContextSaveRestoreNonCoherent:bdw */
883 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
884 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
885 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
890 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
892 struct drm_i915_private
*dev_priv
= engine
->i915
;
895 ret
= gen8_init_workarounds(engine
);
899 /* WaDisableThreadStallDopClockGating:chv */
900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
908 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
910 struct drm_i915_private
*dev_priv
= engine
->i915
;
913 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
914 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
915 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
917 /* WaDisableKillLogic:bxt,skl,kbl */
918 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
921 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
922 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
923 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
924 FLOW_CONTROL_ENABLE
|
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
927 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
931 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
932 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
933 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
935 GEN9_DG_MIRROR_FIX_ENABLE
);
937 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
938 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
939 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
940 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
941 GEN9_RHWO_OPTIMIZATION_DISABLE
);
943 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
944 * but we do that in per ctx batchbuffer as there is an issue
945 * with this register not getting restored on ctx restore
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
950 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
952 GEN9_ENABLE_YV12_BUGFIX
|
953 GEN9_ENABLE_GPGPU_PREEMPTION
);
955 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
956 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
957 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
958 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
960 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
961 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
962 GEN9_CCS_TLB_PREFETCH_ENABLE
);
964 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
965 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_C0
) ||
966 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
967 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
968 PIXEL_MASK_CAMMING_DISABLE
);
970 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
971 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
972 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
973 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
975 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
976 * both tied to WaForceContextSaveRestoreNonCoherent
977 * in some hsds for skl. We keep the tie for all gen9. The
978 * documentation is a bit hazy and so we want to get common behaviour,
979 * even though there is no clear evidence we would need both on kbl/bxt.
980 * This area has been source of system hangs so we play it safe
981 * and mimic the skl regardless of what bspec says.
983 * Use Force Non-Coherent whenever executing a 3D context. This
984 * is a workaround for a possible hang in the unlikely event
985 * a TLB invalidation occurs during a PSD flush.
988 /* WaForceEnableNonCoherent:skl,bxt,kbl */
989 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
990 HDC_FORCE_NON_COHERENT
);
992 /* WaDisableHDCInvalidation:skl,bxt,kbl */
993 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
994 BDW_DISABLE_HDC_INVALIDATION
);
996 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
997 if (IS_SKYLAKE(dev_priv
) ||
998 IS_KABYLAKE(dev_priv
) ||
999 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
1000 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
1001 GEN8_SAMPLER_POWER_BYPASS_DIS
);
1003 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1004 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
1006 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1007 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
1008 GEN8_LQSC_FLUSH_COHERENT_LINES
));
1010 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1011 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
1015 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1016 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
1020 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1021 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
1028 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
1030 struct drm_i915_private
*dev_priv
= engine
->i915
;
1031 u8 vals
[3] = { 0, 0, 0 };
1034 for (i
= 0; i
< 3; i
++) {
1038 * Only consider slices where one, and only one, subslice has 7
1041 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1045 * subslice_7eu[i] != 0 (because of the check above) and
1046 * ss_max == 4 (maximum number of subslices possible per slice)
1050 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1054 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1057 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1058 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1059 GEN9_IZ_HASHING_MASK(2) |
1060 GEN9_IZ_HASHING_MASK(1) |
1061 GEN9_IZ_HASHING_MASK(0),
1062 GEN9_IZ_HASHING(2, vals
[2]) |
1063 GEN9_IZ_HASHING(1, vals
[1]) |
1064 GEN9_IZ_HASHING(0, vals
[0]));
1069 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
1071 struct drm_i915_private
*dev_priv
= engine
->i915
;
1074 ret
= gen9_init_workarounds(engine
);
1079 * Actual WA is to disable percontext preemption granularity control
1080 * until D0 which is the default case so this is equivalent to
1081 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1083 if (IS_SKL_REVID(dev_priv
, SKL_REVID_E0
, REVID_FOREVER
)) {
1084 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
1085 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
1088 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_D0
)) {
1089 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1090 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1091 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1094 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1095 * involving this register should also be added to WA batch as required.
1097 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
))
1098 /* WaDisableLSQCROPERFforOCL:skl */
1099 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1100 GEN8_LQSC_RO_PERF_DIS
);
1102 /* WaEnableGapsTsvCreditFix:skl */
1103 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, REVID_FOREVER
)) {
1104 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1105 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1108 /* WaDisablePowerCompilerClockGating:skl */
1109 if (IS_SKL_REVID(dev_priv
, SKL_REVID_B0
, SKL_REVID_B0
))
1110 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1111 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1113 /* WaBarrierPerformanceFixDisable:skl */
1114 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_D0
))
1115 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1116 HDC_FENCE_DEST_SLM_DISABLE
|
1117 HDC_BARRIER_PERFORMANCE_DISABLE
);
1119 /* WaDisableSbeCacheDispatchPortSharing:skl */
1120 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
))
1122 GEN7_HALF_SLICE_CHICKEN1
,
1123 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1125 /* WaDisableGafsUnitClkGating:skl */
1126 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1128 /* WaDisableLSQCROPERFforOCL:skl */
1129 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1133 return skl_tune_iz_hashing(engine
);
1136 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1138 struct drm_i915_private
*dev_priv
= engine
->i915
;
1141 ret
= gen9_init_workarounds(engine
);
1145 /* WaStoreMultiplePTEenable:bxt */
1146 /* This is a requirement according to Hardware specification */
1147 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1148 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1150 /* WaSetClckGatingDisableMedia:bxt */
1151 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1152 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1153 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1156 /* WaDisableThreadStallDopClockGating:bxt */
1157 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1158 STALL_DOP_GATING_DISABLE
);
1160 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1161 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1163 GEN7_HALF_SLICE_CHICKEN1
,
1164 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1167 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1168 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1169 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1170 /* WaDisableLSQCROPERFforOCL:bxt */
1171 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1172 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1176 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1181 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1182 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
1183 I915_WRITE(GEN8_L3SQCREG1
, L3_GENERAL_PRIO_CREDITS(62) |
1184 L3_HIGH_PRIO_CREDITS(2));
1189 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1191 struct drm_i915_private
*dev_priv
= engine
->i915
;
1194 ret
= gen9_init_workarounds(engine
);
1198 /* WaEnableGapsTsvCreditFix:kbl */
1199 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1200 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1202 /* WaDisableDynamicCreditSharing:kbl */
1203 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1204 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1205 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1207 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1208 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1209 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1210 HDC_FENCE_DEST_SLM_DISABLE
);
1212 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1213 * involving this register should also be added to WA batch as required.
1215 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1216 /* WaDisableLSQCROPERFforOCL:kbl */
1217 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1218 GEN8_LQSC_RO_PERF_DIS
);
1220 /* WaDisableLSQCROPERFforOCL:kbl */
1221 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1228 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1230 struct drm_i915_private
*dev_priv
= engine
->i915
;
1232 WARN_ON(engine
->id
!= RCS
);
1234 dev_priv
->workarounds
.count
= 0;
1235 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1237 if (IS_BROADWELL(dev_priv
))
1238 return bdw_init_workarounds(engine
);
1240 if (IS_CHERRYVIEW(dev_priv
))
1241 return chv_init_workarounds(engine
);
1243 if (IS_SKYLAKE(dev_priv
))
1244 return skl_init_workarounds(engine
);
1246 if (IS_BROXTON(dev_priv
))
1247 return bxt_init_workarounds(engine
);
1249 if (IS_KABYLAKE(dev_priv
))
1250 return kbl_init_workarounds(engine
);
1255 static int init_render_ring(struct intel_engine_cs
*engine
)
1257 struct drm_i915_private
*dev_priv
= engine
->i915
;
1258 int ret
= init_ring_common(engine
);
1262 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1263 if (IS_GEN(dev_priv
, 4, 6))
1264 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1266 /* We need to disable the AsyncFlip performance optimisations in order
1267 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1268 * programmed to '1' on all products.
1270 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1272 if (IS_GEN(dev_priv
, 6, 7))
1273 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1275 /* Required for the hardware to program scanline values for waiting */
1276 /* WaEnableFlushTlbInvalidationMode:snb */
1277 if (IS_GEN6(dev_priv
))
1278 I915_WRITE(GFX_MODE
,
1279 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1281 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1282 if (IS_GEN7(dev_priv
))
1283 I915_WRITE(GFX_MODE_GEN7
,
1284 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1285 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1287 if (IS_GEN6(dev_priv
)) {
1288 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1289 * "If this bit is set, STCunit will have LRA as replacement
1290 * policy. [...] This bit must be reset. LRA replacement
1291 * policy is not supported."
1293 I915_WRITE(CACHE_MODE_0
,
1294 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1297 if (IS_GEN(dev_priv
, 6, 7))
1298 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1300 if (HAS_L3_DPF(dev_priv
))
1301 I915_WRITE_IMR(engine
, ~GT_PARITY_ERROR(dev_priv
));
1303 return init_workarounds_ring(engine
);
1306 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1308 struct drm_i915_private
*dev_priv
= engine
->i915
;
1310 if (dev_priv
->semaphore_obj
) {
1311 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1312 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1313 dev_priv
->semaphore_obj
= NULL
;
1316 intel_fini_pipe_control(engine
);
1319 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1320 unsigned int num_dwords
)
1322 #define MBOX_UPDATE_DWORDS 8
1323 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1324 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1325 struct intel_engine_cs
*waiter
;
1326 enum intel_engine_id id
;
1329 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1330 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1331 #undef MBOX_UPDATE_DWORDS
1333 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1337 for_each_engine_id(waiter
, dev_priv
, id
) {
1339 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1340 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1343 seqno
= i915_gem_request_get_seqno(signaller_req
);
1344 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1345 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1346 PIPE_CONTROL_QW_WRITE
|
1347 PIPE_CONTROL_CS_STALL
);
1348 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1349 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1350 intel_ring_emit(signaller
, seqno
);
1351 intel_ring_emit(signaller
, 0);
1352 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1353 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1354 intel_ring_emit(signaller
, 0);
1360 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1361 unsigned int num_dwords
)
1363 #define MBOX_UPDATE_DWORDS 6
1364 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1365 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1366 struct intel_engine_cs
*waiter
;
1367 enum intel_engine_id id
;
1370 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1371 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1372 #undef MBOX_UPDATE_DWORDS
1374 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1378 for_each_engine_id(waiter
, dev_priv
, id
) {
1380 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[id
];
1381 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1384 seqno
= i915_gem_request_get_seqno(signaller_req
);
1385 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1386 MI_FLUSH_DW_OP_STOREDW
);
1387 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1388 MI_FLUSH_DW_USE_GTT
);
1389 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1390 intel_ring_emit(signaller
, seqno
);
1391 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1392 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1393 intel_ring_emit(signaller
, 0);
1399 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1400 unsigned int num_dwords
)
1402 struct intel_engine_cs
*signaller
= signaller_req
->engine
;
1403 struct drm_i915_private
*dev_priv
= signaller_req
->i915
;
1404 struct intel_engine_cs
*useless
;
1405 enum intel_engine_id id
;
1408 #define MBOX_UPDATE_DWORDS 3
1409 num_rings
= hweight32(INTEL_INFO(dev_priv
)->ring_mask
);
1410 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1411 #undef MBOX_UPDATE_DWORDS
1413 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1417 for_each_engine_id(useless
, dev_priv
, id
) {
1418 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[id
];
1420 if (i915_mmio_reg_valid(mbox_reg
)) {
1421 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1423 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1424 intel_ring_emit_reg(signaller
, mbox_reg
);
1425 intel_ring_emit(signaller
, seqno
);
1429 /* If num_dwords was rounded, make sure the tail pointer is correct */
1430 if (num_rings
% 2 == 0)
1431 intel_ring_emit(signaller
, MI_NOOP
);
1437 * gen6_add_request - Update the semaphore mailbox registers
1439 * @request - request to write to the ring
1441 * Update the mailbox registers in the *other* rings with the current seqno.
1442 * This acts like a signal in the canonical semaphore.
1445 gen6_add_request(struct drm_i915_gem_request
*req
)
1447 struct intel_engine_cs
*engine
= req
->engine
;
1450 if (engine
->semaphore
.signal
)
1451 ret
= engine
->semaphore
.signal(req
, 4);
1453 ret
= intel_ring_begin(req
, 4);
1458 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1459 intel_ring_emit(engine
,
1460 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1461 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1462 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1463 __intel_ring_advance(engine
);
1469 gen8_render_add_request(struct drm_i915_gem_request
*req
)
1471 struct intel_engine_cs
*engine
= req
->engine
;
1474 if (engine
->semaphore
.signal
)
1475 ret
= engine
->semaphore
.signal(req
, 8);
1477 ret
= intel_ring_begin(req
, 8);
1481 intel_ring_emit(engine
, GFX_OP_PIPE_CONTROL(6));
1482 intel_ring_emit(engine
, (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1483 PIPE_CONTROL_CS_STALL
|
1484 PIPE_CONTROL_QW_WRITE
));
1485 intel_ring_emit(engine
, intel_hws_seqno_address(req
->engine
));
1486 intel_ring_emit(engine
, 0);
1487 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1488 /* We're thrashing one dword of HWS. */
1489 intel_ring_emit(engine
, 0);
1490 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1491 intel_ring_emit(engine
, MI_NOOP
);
1492 __intel_ring_advance(engine
);
1497 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private
*dev_priv
,
1500 return dev_priv
->last_seqno
< seqno
;
1504 * intel_ring_sync - sync the waiter to the signaller on seqno
1506 * @waiter - ring that is waiting
1507 * @signaller - ring which has, or will signal
1508 * @seqno - seqno which the waiter will block on
1512 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1513 struct intel_engine_cs
*signaller
,
1516 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1517 struct drm_i915_private
*dev_priv
= waiter_req
->i915
;
1518 struct i915_hw_ppgtt
*ppgtt
;
1521 ret
= intel_ring_begin(waiter_req
, 4);
1525 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1526 MI_SEMAPHORE_GLOBAL_GTT
|
1527 MI_SEMAPHORE_SAD_GTE_SDD
);
1528 intel_ring_emit(waiter
, seqno
);
1529 intel_ring_emit(waiter
,
1530 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1531 intel_ring_emit(waiter
,
1532 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1533 intel_ring_advance(waiter
);
1535 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1536 * pagetables and we must reload them before executing the batch.
1537 * We do this on the i915_switch_context() following the wait and
1538 * before the dispatch.
1540 ppgtt
= waiter_req
->ctx
->ppgtt
;
1541 if (ppgtt
&& waiter_req
->engine
->id
!= RCS
)
1542 ppgtt
->pd_dirty_rings
|= intel_engine_flag(waiter_req
->engine
);
1547 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1548 struct intel_engine_cs
*signaller
,
1551 struct intel_engine_cs
*waiter
= waiter_req
->engine
;
1552 u32 dw1
= MI_SEMAPHORE_MBOX
|
1553 MI_SEMAPHORE_COMPARE
|
1554 MI_SEMAPHORE_REGISTER
;
1555 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1558 /* Throughout all of the GEM code, seqno passed implies our current
1559 * seqno is >= the last seqno executed. However for hardware the
1560 * comparison is strictly greater than.
1564 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1566 ret
= intel_ring_begin(waiter_req
, 4);
1570 /* If seqno wrap happened, omit the wait with no-ops */
1571 if (likely(!i915_gem_has_seqno_wrapped(waiter_req
->i915
, seqno
))) {
1572 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1573 intel_ring_emit(waiter
, seqno
);
1574 intel_ring_emit(waiter
, 0);
1575 intel_ring_emit(waiter
, MI_NOOP
);
1577 intel_ring_emit(waiter
, MI_NOOP
);
1578 intel_ring_emit(waiter
, MI_NOOP
);
1579 intel_ring_emit(waiter
, MI_NOOP
);
1580 intel_ring_emit(waiter
, MI_NOOP
);
1582 intel_ring_advance(waiter
);
1587 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1589 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1590 PIPE_CONTROL_DEPTH_STALL); \
1591 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1592 intel_ring_emit(ring__, 0); \
1593 intel_ring_emit(ring__, 0); \
1597 pc_render_add_request(struct drm_i915_gem_request
*req
)
1599 struct intel_engine_cs
*engine
= req
->engine
;
1600 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1603 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1604 * incoherent with writes to memory, i.e. completely fubar,
1605 * so we need to use PIPE_NOTIFY instead.
1607 * However, we also need to workaround the qword write
1608 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1609 * memory before requesting an interrupt.
1611 ret
= intel_ring_begin(req
, 32);
1615 intel_ring_emit(engine
,
1616 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1617 PIPE_CONTROL_WRITE_FLUSH
|
1618 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1619 intel_ring_emit(engine
,
1620 engine
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1621 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1622 intel_ring_emit(engine
, 0);
1623 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1624 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1625 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1626 scratch_addr
+= 2 * CACHELINE_BYTES
;
1627 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1628 scratch_addr
+= 2 * CACHELINE_BYTES
;
1629 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1630 scratch_addr
+= 2 * CACHELINE_BYTES
;
1631 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1632 scratch_addr
+= 2 * CACHELINE_BYTES
;
1633 PIPE_CONTROL_FLUSH(engine
, scratch_addr
);
1635 intel_ring_emit(engine
,
1636 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1637 PIPE_CONTROL_WRITE_FLUSH
|
1638 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1639 PIPE_CONTROL_NOTIFY
);
1640 intel_ring_emit(engine
,
1641 engine
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1642 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1643 intel_ring_emit(engine
, 0);
1644 __intel_ring_advance(engine
);
1650 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1652 struct drm_i915_private
*dev_priv
= engine
->i915
;
1654 /* Workaround to force correct ordering between irq and seqno writes on
1655 * ivb (and maybe also on snb) by reading from a CS register (like
1656 * ACTHD) before reading the status page.
1658 * Note that this effectively stalls the read by the time it takes to
1659 * do a memory transaction, which more or less ensures that the write
1660 * from the GPU has sufficient time to invalidate the CPU cacheline.
1661 * Alternatively we could delay the interrupt from the CS ring to give
1662 * the write time to land, but that would incur a delay after every
1663 * batch i.e. much more frequent than a delay when waiting for the
1664 * interrupt (with the same net latency).
1666 * Also note that to prevent whole machine hangs on gen7, we have to
1667 * take the spinlock to guard against concurrent cacheline access.
1669 spin_lock_irq(&dev_priv
->uncore
.lock
);
1670 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1671 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1675 ring_get_seqno(struct intel_engine_cs
*engine
)
1677 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1681 ring_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1683 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1687 pc_render_get_seqno(struct intel_engine_cs
*engine
)
1689 return engine
->scratch
.cpu_page
[0];
1693 pc_render_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1695 engine
->scratch
.cpu_page
[0] = seqno
;
1699 gen5_ring_get_irq(struct intel_engine_cs
*engine
)
1701 struct drm_i915_private
*dev_priv
= engine
->i915
;
1702 unsigned long flags
;
1704 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1707 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1708 if (engine
->irq_refcount
++ == 0)
1709 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1710 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1716 gen5_ring_put_irq(struct intel_engine_cs
*engine
)
1718 struct drm_i915_private
*dev_priv
= engine
->i915
;
1719 unsigned long flags
;
1721 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1722 if (--engine
->irq_refcount
== 0)
1723 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1724 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1728 i9xx_ring_get_irq(struct intel_engine_cs
*engine
)
1730 struct drm_i915_private
*dev_priv
= engine
->i915
;
1731 unsigned long flags
;
1733 if (!intel_irqs_enabled(dev_priv
))
1736 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1737 if (engine
->irq_refcount
++ == 0) {
1738 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1739 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1742 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1748 i9xx_ring_put_irq(struct intel_engine_cs
*engine
)
1750 struct drm_i915_private
*dev_priv
= engine
->i915
;
1751 unsigned long flags
;
1753 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1754 if (--engine
->irq_refcount
== 0) {
1755 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1756 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1759 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1763 i8xx_ring_get_irq(struct intel_engine_cs
*engine
)
1765 struct drm_i915_private
*dev_priv
= engine
->i915
;
1766 unsigned long flags
;
1768 if (!intel_irqs_enabled(dev_priv
))
1771 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1772 if (engine
->irq_refcount
++ == 0) {
1773 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1774 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1775 POSTING_READ16(IMR
);
1777 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1783 i8xx_ring_put_irq(struct intel_engine_cs
*engine
)
1785 struct drm_i915_private
*dev_priv
= engine
->i915
;
1786 unsigned long flags
;
1788 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1789 if (--engine
->irq_refcount
== 0) {
1790 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1791 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1792 POSTING_READ16(IMR
);
1794 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1798 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1799 u32 invalidate_domains
,
1802 struct intel_engine_cs
*engine
= req
->engine
;
1805 ret
= intel_ring_begin(req
, 2);
1809 intel_ring_emit(engine
, MI_FLUSH
);
1810 intel_ring_emit(engine
, MI_NOOP
);
1811 intel_ring_advance(engine
);
1816 i9xx_add_request(struct drm_i915_gem_request
*req
)
1818 struct intel_engine_cs
*engine
= req
->engine
;
1821 ret
= intel_ring_begin(req
, 4);
1825 intel_ring_emit(engine
, MI_STORE_DWORD_INDEX
);
1826 intel_ring_emit(engine
,
1827 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1828 intel_ring_emit(engine
, i915_gem_request_get_seqno(req
));
1829 intel_ring_emit(engine
, MI_USER_INTERRUPT
);
1830 __intel_ring_advance(engine
);
1836 gen6_ring_get_irq(struct intel_engine_cs
*engine
)
1838 struct drm_i915_private
*dev_priv
= engine
->i915
;
1839 unsigned long flags
;
1841 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1844 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1845 if (engine
->irq_refcount
++ == 0) {
1846 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
)
1847 I915_WRITE_IMR(engine
,
1848 ~(engine
->irq_enable_mask
|
1849 GT_PARITY_ERROR(dev_priv
)));
1851 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1852 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1854 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1860 gen6_ring_put_irq(struct intel_engine_cs
*engine
)
1862 struct drm_i915_private
*dev_priv
= engine
->i915
;
1863 unsigned long flags
;
1865 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1866 if (--engine
->irq_refcount
== 0) {
1867 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
)
1868 I915_WRITE_IMR(engine
, ~GT_PARITY_ERROR(dev_priv
));
1870 I915_WRITE_IMR(engine
, ~0);
1871 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1873 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1877 hsw_vebox_get_irq(struct intel_engine_cs
*engine
)
1879 struct drm_i915_private
*dev_priv
= engine
->i915
;
1880 unsigned long flags
;
1882 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1885 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1886 if (engine
->irq_refcount
++ == 0) {
1887 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1888 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1890 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1896 hsw_vebox_put_irq(struct intel_engine_cs
*engine
)
1898 struct drm_i915_private
*dev_priv
= engine
->i915
;
1899 unsigned long flags
;
1901 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1902 if (--engine
->irq_refcount
== 0) {
1903 I915_WRITE_IMR(engine
, ~0);
1904 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1906 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1910 gen8_ring_get_irq(struct intel_engine_cs
*engine
)
1912 struct drm_i915_private
*dev_priv
= engine
->i915
;
1913 unsigned long flags
;
1915 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1918 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1919 if (engine
->irq_refcount
++ == 0) {
1920 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
) {
1921 I915_WRITE_IMR(engine
,
1922 ~(engine
->irq_enable_mask
|
1923 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1925 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1927 POSTING_READ(RING_IMR(engine
->mmio_base
));
1929 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1935 gen8_ring_put_irq(struct intel_engine_cs
*engine
)
1937 struct drm_i915_private
*dev_priv
= engine
->i915
;
1938 unsigned long flags
;
1940 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1941 if (--engine
->irq_refcount
== 0) {
1942 if (HAS_L3_DPF(dev_priv
) && engine
->id
== RCS
) {
1943 I915_WRITE_IMR(engine
,
1944 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1946 I915_WRITE_IMR(engine
, ~0);
1948 POSTING_READ(RING_IMR(engine
->mmio_base
));
1950 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1954 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1955 u64 offset
, u32 length
,
1956 unsigned dispatch_flags
)
1958 struct intel_engine_cs
*engine
= req
->engine
;
1961 ret
= intel_ring_begin(req
, 2);
1965 intel_ring_emit(engine
,
1966 MI_BATCH_BUFFER_START
|
1968 (dispatch_flags
& I915_DISPATCH_SECURE
?
1969 0 : MI_BATCH_NON_SECURE_I965
));
1970 intel_ring_emit(engine
, offset
);
1971 intel_ring_advance(engine
);
1976 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1977 #define I830_BATCH_LIMIT (256*1024)
1978 #define I830_TLB_ENTRIES (2)
1979 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1981 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1982 u64 offset
, u32 len
,
1983 unsigned dispatch_flags
)
1985 struct intel_engine_cs
*engine
= req
->engine
;
1986 u32 cs_offset
= engine
->scratch
.gtt_offset
;
1989 ret
= intel_ring_begin(req
, 6);
1993 /* Evict the invalid PTE TLBs */
1994 intel_ring_emit(engine
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1995 intel_ring_emit(engine
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1996 intel_ring_emit(engine
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1997 intel_ring_emit(engine
, cs_offset
);
1998 intel_ring_emit(engine
, 0xdeadbeef);
1999 intel_ring_emit(engine
, MI_NOOP
);
2000 intel_ring_advance(engine
);
2002 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
2003 if (len
> I830_BATCH_LIMIT
)
2006 ret
= intel_ring_begin(req
, 6 + 2);
2010 /* Blit the batch (which has now all relocs applied) to the
2011 * stable batch scratch bo area (so that the CS never
2012 * stumbles over its tlb invalidation bug) ...
2014 intel_ring_emit(engine
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
2015 intel_ring_emit(engine
,
2016 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
2017 intel_ring_emit(engine
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
2018 intel_ring_emit(engine
, cs_offset
);
2019 intel_ring_emit(engine
, 4096);
2020 intel_ring_emit(engine
, offset
);
2022 intel_ring_emit(engine
, MI_FLUSH
);
2023 intel_ring_emit(engine
, MI_NOOP
);
2024 intel_ring_advance(engine
);
2026 /* ... and execute it. */
2030 ret
= intel_ring_begin(req
, 2);
2034 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
2035 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
2036 0 : MI_BATCH_NON_SECURE
));
2037 intel_ring_advance(engine
);
2043 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2044 u64 offset
, u32 len
,
2045 unsigned dispatch_flags
)
2047 struct intel_engine_cs
*engine
= req
->engine
;
2050 ret
= intel_ring_begin(req
, 2);
2054 intel_ring_emit(engine
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
2055 intel_ring_emit(engine
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
2056 0 : MI_BATCH_NON_SECURE
));
2057 intel_ring_advance(engine
);
2062 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
2064 struct drm_i915_private
*dev_priv
= engine
->i915
;
2066 if (!dev_priv
->status_page_dmah
)
2069 drm_pci_free(dev_priv
->dev
, dev_priv
->status_page_dmah
);
2070 engine
->status_page
.page_addr
= NULL
;
2073 static void cleanup_status_page(struct intel_engine_cs
*engine
)
2075 struct drm_i915_gem_object
*obj
;
2077 obj
= engine
->status_page
.obj
;
2081 kunmap(sg_page(obj
->pages
->sgl
));
2082 i915_gem_object_ggtt_unpin(obj
);
2083 drm_gem_object_unreference(&obj
->base
);
2084 engine
->status_page
.obj
= NULL
;
2087 static int init_status_page(struct intel_engine_cs
*engine
)
2089 struct drm_i915_gem_object
*obj
= engine
->status_page
.obj
;
2095 obj
= i915_gem_object_create(engine
->i915
->dev
, 4096);
2097 DRM_ERROR("Failed to allocate status page\n");
2098 return PTR_ERR(obj
);
2101 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2106 if (!HAS_LLC(engine
->i915
))
2107 /* On g33, we cannot place HWS above 256MiB, so
2108 * restrict its pinning to the low mappable arena.
2109 * Though this restriction is not documented for
2110 * gen4, gen5, or byt, they also behave similarly
2111 * and hang if the HWS is placed at the top of the
2112 * GTT. To generalise, it appears that all !llc
2113 * platforms have issues with us placing the HWS
2114 * above the mappable region (even though we never
2117 flags
|= PIN_MAPPABLE
;
2118 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
2121 drm_gem_object_unreference(&obj
->base
);
2125 engine
->status_page
.obj
= obj
;
2128 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
2129 engine
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
2130 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
2132 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2133 engine
->name
, engine
->status_page
.gfx_addr
);
2138 static int init_phys_status_page(struct intel_engine_cs
*engine
)
2140 struct drm_i915_private
*dev_priv
= engine
->i915
;
2142 if (!dev_priv
->status_page_dmah
) {
2143 dev_priv
->status_page_dmah
=
2144 drm_pci_alloc(dev_priv
->dev
, PAGE_SIZE
, PAGE_SIZE
);
2145 if (!dev_priv
->status_page_dmah
)
2149 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
2150 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
2155 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2157 GEM_BUG_ON(ringbuf
->vma
== NULL
);
2158 GEM_BUG_ON(ringbuf
->virtual_start
== NULL
);
2160 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
2161 i915_gem_object_unpin_map(ringbuf
->obj
);
2163 i915_vma_unpin_iomap(ringbuf
->vma
);
2164 ringbuf
->virtual_start
= NULL
;
2166 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2167 ringbuf
->vma
= NULL
;
2170 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private
*dev_priv
,
2171 struct intel_ringbuffer
*ringbuf
)
2173 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2174 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2175 unsigned flags
= PIN_OFFSET_BIAS
| 4096;
2179 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2180 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, flags
);
2184 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2188 addr
= i915_gem_object_pin_map(obj
);
2190 ret
= PTR_ERR(addr
);
2194 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
2195 flags
| PIN_MAPPABLE
);
2199 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2203 /* Access through the GTT requires the device to be awake. */
2204 assert_rpm_wakelock_held(dev_priv
);
2206 addr
= i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj
));
2208 ret
= PTR_ERR(addr
);
2213 ringbuf
->virtual_start
= addr
;
2214 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2218 i915_gem_object_ggtt_unpin(obj
);
2222 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2224 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2225 ringbuf
->obj
= NULL
;
2228 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2229 struct intel_ringbuffer
*ringbuf
)
2231 struct drm_i915_gem_object
*obj
;
2235 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2237 obj
= i915_gem_object_create(dev
, ringbuf
->size
);
2239 return PTR_ERR(obj
);
2241 /* mark ring buffers as read-only from GPU side by default */
2249 struct intel_ringbuffer
*
2250 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2252 struct intel_ringbuffer
*ring
;
2255 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2257 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2259 return ERR_PTR(-ENOMEM
);
2262 ring
->engine
= engine
;
2263 list_add(&ring
->link
, &engine
->buffers
);
2266 /* Workaround an erratum on the i830 which causes a hang if
2267 * the TAIL pointer points to within the last 2 cachelines
2270 ring
->effective_size
= size
;
2271 if (IS_I830(engine
->i915
) || IS_845G(engine
->i915
))
2272 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2274 ring
->last_retired_head
= -1;
2275 intel_ring_update_space(ring
);
2277 ret
= intel_alloc_ringbuffer_obj(engine
->i915
->dev
, ring
);
2279 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2281 list_del(&ring
->link
);
2283 return ERR_PTR(ret
);
2290 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2292 intel_destroy_ringbuffer_obj(ring
);
2293 list_del(&ring
->link
);
2297 static int intel_init_ring_buffer(struct drm_device
*dev
,
2298 struct intel_engine_cs
*engine
)
2300 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2301 struct intel_ringbuffer
*ringbuf
;
2304 WARN_ON(engine
->buffer
);
2306 engine
->i915
= dev_priv
;
2307 INIT_LIST_HEAD(&engine
->active_list
);
2308 INIT_LIST_HEAD(&engine
->request_list
);
2309 INIT_LIST_HEAD(&engine
->execlist_queue
);
2310 INIT_LIST_HEAD(&engine
->buffers
);
2311 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2312 memset(engine
->semaphore
.sync_seqno
, 0,
2313 sizeof(engine
->semaphore
.sync_seqno
));
2315 init_waitqueue_head(&engine
->irq_queue
);
2317 ringbuf
= intel_engine_create_ringbuffer(engine
, 32 * PAGE_SIZE
);
2318 if (IS_ERR(ringbuf
)) {
2319 ret
= PTR_ERR(ringbuf
);
2322 engine
->buffer
= ringbuf
;
2324 if (I915_NEED_GFX_HWS(dev_priv
)) {
2325 ret
= init_status_page(engine
);
2329 WARN_ON(engine
->id
!= RCS
);
2330 ret
= init_phys_status_page(engine
);
2335 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ringbuf
);
2337 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2339 intel_destroy_ringbuffer_obj(ringbuf
);
2343 ret
= i915_cmd_parser_init_ring(engine
);
2350 intel_cleanup_engine(engine
);
2354 void intel_cleanup_engine(struct intel_engine_cs
*engine
)
2356 struct drm_i915_private
*dev_priv
;
2358 if (!intel_engine_initialized(engine
))
2361 dev_priv
= engine
->i915
;
2363 if (engine
->buffer
) {
2364 intel_stop_engine(engine
);
2365 WARN_ON(!IS_GEN2(dev_priv
) && (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2367 intel_unpin_ringbuffer_obj(engine
->buffer
);
2368 intel_ringbuffer_free(engine
->buffer
);
2369 engine
->buffer
= NULL
;
2372 if (engine
->cleanup
)
2373 engine
->cleanup(engine
);
2375 if (I915_NEED_GFX_HWS(dev_priv
)) {
2376 cleanup_status_page(engine
);
2378 WARN_ON(engine
->id
!= RCS
);
2379 cleanup_phys_status_page(engine
);
2382 i915_cmd_parser_fini_ring(engine
);
2383 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2384 engine
->i915
= NULL
;
2387 int intel_engine_idle(struct intel_engine_cs
*engine
)
2389 struct drm_i915_gem_request
*req
;
2391 /* Wait upon the last request to be completed */
2392 if (list_empty(&engine
->request_list
))
2395 req
= list_entry(engine
->request_list
.prev
,
2396 struct drm_i915_gem_request
,
2399 /* Make sure we do not trigger any retires */
2400 return __i915_wait_request(req
,
2401 req
->i915
->mm
.interruptible
,
2405 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2409 /* Flush enough space to reduce the likelihood of waiting after
2410 * we start building the request - in which case we will just
2411 * have to repeat work.
2413 request
->reserved_space
+= LEGACY_REQUEST_SIZE
;
2415 request
->ringbuf
= request
->engine
->buffer
;
2417 ret
= intel_ring_begin(request
, 0);
2421 request
->reserved_space
-= LEGACY_REQUEST_SIZE
;
2425 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2427 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2428 struct intel_engine_cs
*engine
= req
->engine
;
2429 struct drm_i915_gem_request
*target
;
2431 intel_ring_update_space(ringbuf
);
2432 if (ringbuf
->space
>= bytes
)
2436 * Space is reserved in the ringbuffer for finalising the request,
2437 * as that cannot be allowed to fail. During request finalisation,
2438 * reserved_space is set to 0 to stop the overallocation and the
2439 * assumption is that then we never need to wait (which has the
2440 * risk of failing with EINTR).
2442 * See also i915_gem_request_alloc() and i915_add_request().
2444 GEM_BUG_ON(!req
->reserved_space
);
2446 list_for_each_entry(target
, &engine
->request_list
, list
) {
2450 * The request queue is per-engine, so can contain requests
2451 * from multiple ringbuffers. Here, we must ignore any that
2452 * aren't from the ringbuffer we're considering.
2454 if (target
->ringbuf
!= ringbuf
)
2457 /* Would completion of this request free enough space? */
2458 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
2464 if (WARN_ON(&target
->list
== &engine
->request_list
))
2467 return i915_wait_request(target
);
2470 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2472 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
2473 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2474 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2475 int bytes
= num_dwords
* sizeof(u32
);
2476 int total_bytes
, wait_bytes
;
2477 bool need_wrap
= false;
2479 total_bytes
= bytes
+ req
->reserved_space
;
2481 if (unlikely(bytes
> remain_usable
)) {
2483 * Not enough space for the basic request. So need to flush
2484 * out the remainder and then wait for base + reserved.
2486 wait_bytes
= remain_actual
+ total_bytes
;
2488 } else if (unlikely(total_bytes
> remain_usable
)) {
2490 * The base request will fit but the reserved space
2491 * falls off the end. So we don't need an immediate wrap
2492 * and only need to effectively wait for the reserved
2493 * size space from the start of ringbuffer.
2495 wait_bytes
= remain_actual
+ req
->reserved_space
;
2497 /* No wrapping required, just waiting. */
2498 wait_bytes
= total_bytes
;
2501 if (wait_bytes
> ringbuf
->space
) {
2502 int ret
= wait_for_space(req
, wait_bytes
);
2506 intel_ring_update_space(ringbuf
);
2507 if (unlikely(ringbuf
->space
< wait_bytes
))
2511 if (unlikely(need_wrap
)) {
2512 GEM_BUG_ON(remain_actual
> ringbuf
->space
);
2513 GEM_BUG_ON(ringbuf
->tail
+ remain_actual
> ringbuf
->size
);
2515 /* Fill the tail with MI_NOOP */
2516 memset(ringbuf
->virtual_start
+ ringbuf
->tail
,
2519 ringbuf
->space
-= remain_actual
;
2522 ringbuf
->space
-= bytes
;
2523 GEM_BUG_ON(ringbuf
->space
< 0);
2527 /* Align the ring tail to a cacheline boundary */
2528 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2530 struct intel_engine_cs
*engine
= req
->engine
;
2531 int num_dwords
= (engine
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2534 if (num_dwords
== 0)
2537 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2538 ret
= intel_ring_begin(req
, num_dwords
);
2542 while (num_dwords
--)
2543 intel_ring_emit(engine
, MI_NOOP
);
2545 intel_ring_advance(engine
);
2550 void intel_ring_init_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
2552 struct drm_i915_private
*dev_priv
= engine
->i915
;
2554 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2555 * so long as the semaphore value in the register/page is greater
2556 * than the sync value), so whenever we reset the seqno,
2557 * so long as we reset the tracking semaphore value to 0, it will
2558 * always be before the next request's seqno. If we don't reset
2559 * the semaphore value, then when the seqno moves backwards all
2560 * future waits will complete instantly (causing rendering corruption).
2562 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
2563 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
2564 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
2565 if (HAS_VEBOX(dev_priv
))
2566 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
2568 if (dev_priv
->semaphore_obj
) {
2569 struct drm_i915_gem_object
*obj
= dev_priv
->semaphore_obj
;
2570 struct page
*page
= i915_gem_object_get_dirty_page(obj
, 0);
2571 void *semaphores
= kmap(page
);
2572 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
2573 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
2576 memset(engine
->semaphore
.sync_seqno
, 0,
2577 sizeof(engine
->semaphore
.sync_seqno
));
2579 engine
->set_seqno(engine
, seqno
);
2580 engine
->last_submitted_seqno
= seqno
;
2582 engine
->hangcheck
.seqno
= seqno
;
2585 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*engine
,
2588 struct drm_i915_private
*dev_priv
= engine
->i915
;
2590 /* Every tail move must follow the sequence below */
2592 /* Disable notification that the ring is IDLE. The GT
2593 * will then assume that it is busy and bring it out of rc6.
2595 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2596 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2598 /* Clear the context id. Here be magic! */
2599 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2601 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2602 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2603 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2605 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2607 /* Now that the ring is fully powered up, update the tail */
2608 I915_WRITE_TAIL(engine
, value
);
2609 POSTING_READ(RING_TAIL(engine
->mmio_base
));
2611 /* Let the ring send IDLE messages to the GT again,
2612 * and so let it sleep to conserve power when idle.
2614 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2615 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2618 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2619 u32 invalidate
, u32 flush
)
2621 struct intel_engine_cs
*engine
= req
->engine
;
2625 ret
= intel_ring_begin(req
, 4);
2630 if (INTEL_GEN(req
->i915
) >= 8)
2633 /* We always require a command barrier so that subsequent
2634 * commands, such as breadcrumb interrupts, are strictly ordered
2635 * wrt the contents of the write cache being flushed to memory
2636 * (and thus being coherent from the CPU).
2638 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2641 * Bspec vol 1c.5 - video engine command streamer:
2642 * "If ENABLED, all TLBs will be invalidated once the flush
2643 * operation is complete. This bit is only valid when the
2644 * Post-Sync Operation field is a value of 1h or 3h."
2646 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2647 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2649 intel_ring_emit(engine
, cmd
);
2650 intel_ring_emit(engine
,
2651 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2652 if (INTEL_GEN(req
->i915
) >= 8) {
2653 intel_ring_emit(engine
, 0); /* upper addr */
2654 intel_ring_emit(engine
, 0); /* value */
2656 intel_ring_emit(engine
, 0);
2657 intel_ring_emit(engine
, MI_NOOP
);
2659 intel_ring_advance(engine
);
2664 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2665 u64 offset
, u32 len
,
2666 unsigned dispatch_flags
)
2668 struct intel_engine_cs
*engine
= req
->engine
;
2669 bool ppgtt
= USES_PPGTT(engine
->dev
) &&
2670 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2673 ret
= intel_ring_begin(req
, 4);
2677 /* FIXME(BDW): Address space and security selectors. */
2678 intel_ring_emit(engine
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2679 (dispatch_flags
& I915_DISPATCH_RS
?
2680 MI_BATCH_RESOURCE_STREAMER
: 0));
2681 intel_ring_emit(engine
, lower_32_bits(offset
));
2682 intel_ring_emit(engine
, upper_32_bits(offset
));
2683 intel_ring_emit(engine
, MI_NOOP
);
2684 intel_ring_advance(engine
);
2690 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2691 u64 offset
, u32 len
,
2692 unsigned dispatch_flags
)
2694 struct intel_engine_cs
*engine
= req
->engine
;
2697 ret
= intel_ring_begin(req
, 2);
2701 intel_ring_emit(engine
,
2702 MI_BATCH_BUFFER_START
|
2703 (dispatch_flags
& I915_DISPATCH_SECURE
?
2704 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2705 (dispatch_flags
& I915_DISPATCH_RS
?
2706 MI_BATCH_RESOURCE_STREAMER
: 0));
2707 /* bit0-7 is the length on GEN6+ */
2708 intel_ring_emit(engine
, offset
);
2709 intel_ring_advance(engine
);
2715 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2716 u64 offset
, u32 len
,
2717 unsigned dispatch_flags
)
2719 struct intel_engine_cs
*engine
= req
->engine
;
2722 ret
= intel_ring_begin(req
, 2);
2726 intel_ring_emit(engine
,
2727 MI_BATCH_BUFFER_START
|
2728 (dispatch_flags
& I915_DISPATCH_SECURE
?
2729 0 : MI_BATCH_NON_SECURE_I965
));
2730 /* bit0-7 is the length on GEN6+ */
2731 intel_ring_emit(engine
, offset
);
2732 intel_ring_advance(engine
);
2737 /* Blitter support (SandyBridge+) */
2739 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2740 u32 invalidate
, u32 flush
)
2742 struct intel_engine_cs
*engine
= req
->engine
;
2746 ret
= intel_ring_begin(req
, 4);
2751 if (INTEL_GEN(req
->i915
) >= 8)
2754 /* We always require a command barrier so that subsequent
2755 * commands, such as breadcrumb interrupts, are strictly ordered
2756 * wrt the contents of the write cache being flushed to memory
2757 * (and thus being coherent from the CPU).
2759 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2762 * Bspec vol 1c.3 - blitter engine command streamer:
2763 * "If ENABLED, all TLBs will be invalidated once the flush
2764 * operation is complete. This bit is only valid when the
2765 * Post-Sync Operation field is a value of 1h or 3h."
2767 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2768 cmd
|= MI_INVALIDATE_TLB
;
2769 intel_ring_emit(engine
, cmd
);
2770 intel_ring_emit(engine
,
2771 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2772 if (INTEL_GEN(req
->i915
) >= 8) {
2773 intel_ring_emit(engine
, 0); /* upper addr */
2774 intel_ring_emit(engine
, 0); /* value */
2776 intel_ring_emit(engine
, 0);
2777 intel_ring_emit(engine
, MI_NOOP
);
2779 intel_ring_advance(engine
);
2784 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2788 struct drm_i915_gem_object
*obj
;
2791 engine
->name
= "render ring";
2793 engine
->exec_id
= I915_EXEC_RENDER
;
2795 engine
->mmio_base
= RENDER_RING_BASE
;
2797 if (INTEL_GEN(dev_priv
) >= 8) {
2798 if (i915_semaphore_is_enabled(dev_priv
)) {
2799 obj
= i915_gem_object_create(dev
, 4096);
2801 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2802 i915
.semaphores
= 0;
2804 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2805 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2807 drm_gem_object_unreference(&obj
->base
);
2808 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2809 i915
.semaphores
= 0;
2811 dev_priv
->semaphore_obj
= obj
;
2815 engine
->init_context
= intel_rcs_ctx_init
;
2816 engine
->add_request
= gen8_render_add_request
;
2817 engine
->flush
= gen8_render_ring_flush
;
2818 engine
->irq_get
= gen8_ring_get_irq
;
2819 engine
->irq_put
= gen8_ring_put_irq
;
2820 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2821 engine
->get_seqno
= ring_get_seqno
;
2822 engine
->set_seqno
= ring_set_seqno
;
2823 if (i915_semaphore_is_enabled(dev_priv
)) {
2824 WARN_ON(!dev_priv
->semaphore_obj
);
2825 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2826 engine
->semaphore
.signal
= gen8_rcs_signal
;
2827 GEN8_RING_SEMAPHORE_INIT(engine
);
2829 } else if (INTEL_GEN(dev_priv
) >= 6) {
2830 engine
->init_context
= intel_rcs_ctx_init
;
2831 engine
->add_request
= gen6_add_request
;
2832 engine
->flush
= gen7_render_ring_flush
;
2833 if (IS_GEN6(dev_priv
))
2834 engine
->flush
= gen6_render_ring_flush
;
2835 engine
->irq_get
= gen6_ring_get_irq
;
2836 engine
->irq_put
= gen6_ring_put_irq
;
2837 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2838 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2839 engine
->get_seqno
= ring_get_seqno
;
2840 engine
->set_seqno
= ring_set_seqno
;
2841 if (i915_semaphore_is_enabled(dev_priv
)) {
2842 engine
->semaphore
.sync_to
= gen6_ring_sync
;
2843 engine
->semaphore
.signal
= gen6_signal
;
2845 * The current semaphore is only applied on pre-gen8
2846 * platform. And there is no VCS2 ring on the pre-gen8
2847 * platform. So the semaphore between RCS and VCS2 is
2848 * initialized as INVALID. Gen8 will initialize the
2849 * sema between VCS2 and RCS later.
2851 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2852 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2853 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2854 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2855 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2856 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2857 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2858 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2859 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2860 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2862 } else if (IS_GEN5(dev_priv
)) {
2863 engine
->add_request
= pc_render_add_request
;
2864 engine
->flush
= gen4_render_ring_flush
;
2865 engine
->get_seqno
= pc_render_get_seqno
;
2866 engine
->set_seqno
= pc_render_set_seqno
;
2867 engine
->irq_get
= gen5_ring_get_irq
;
2868 engine
->irq_put
= gen5_ring_put_irq
;
2869 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2870 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2872 engine
->add_request
= i9xx_add_request
;
2873 if (INTEL_GEN(dev_priv
) < 4)
2874 engine
->flush
= gen2_render_ring_flush
;
2876 engine
->flush
= gen4_render_ring_flush
;
2877 engine
->get_seqno
= ring_get_seqno
;
2878 engine
->set_seqno
= ring_set_seqno
;
2879 if (IS_GEN2(dev_priv
)) {
2880 engine
->irq_get
= i8xx_ring_get_irq
;
2881 engine
->irq_put
= i8xx_ring_put_irq
;
2883 engine
->irq_get
= i9xx_ring_get_irq
;
2884 engine
->irq_put
= i9xx_ring_put_irq
;
2886 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2888 engine
->write_tail
= ring_write_tail
;
2890 if (IS_HASWELL(dev_priv
))
2891 engine
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2892 else if (IS_GEN8(dev_priv
))
2893 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2894 else if (INTEL_GEN(dev_priv
) >= 6)
2895 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2896 else if (INTEL_GEN(dev_priv
) >= 4)
2897 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2898 else if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
2899 engine
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2901 engine
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2902 engine
->init_hw
= init_render_ring
;
2903 engine
->cleanup
= render_ring_cleanup
;
2905 /* Workaround batchbuffer to combat CS tlb bug. */
2906 if (HAS_BROKEN_CS_TLB(dev_priv
)) {
2907 obj
= i915_gem_object_create(dev
, I830_WA_SIZE
);
2909 DRM_ERROR("Failed to allocate batch bo\n");
2910 return PTR_ERR(obj
);
2913 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2915 drm_gem_object_unreference(&obj
->base
);
2916 DRM_ERROR("Failed to ping batch bo\n");
2920 engine
->scratch
.obj
= obj
;
2921 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2924 ret
= intel_init_ring_buffer(dev
, engine
);
2928 if (INTEL_GEN(dev_priv
) >= 5) {
2929 ret
= intel_init_pipe_control(engine
);
2937 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2940 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2942 engine
->name
= "bsd ring";
2944 engine
->exec_id
= I915_EXEC_BSD
;
2947 engine
->write_tail
= ring_write_tail
;
2948 if (INTEL_GEN(dev_priv
) >= 6) {
2949 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2950 /* gen6 bsd needs a special wa for tail updates */
2951 if (IS_GEN6(dev_priv
))
2952 engine
->write_tail
= gen6_bsd_ring_write_tail
;
2953 engine
->flush
= gen6_bsd_ring_flush
;
2954 engine
->add_request
= gen6_add_request
;
2955 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2956 engine
->get_seqno
= ring_get_seqno
;
2957 engine
->set_seqno
= ring_set_seqno
;
2958 if (INTEL_GEN(dev_priv
) >= 8) {
2959 engine
->irq_enable_mask
=
2960 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2961 engine
->irq_get
= gen8_ring_get_irq
;
2962 engine
->irq_put
= gen8_ring_put_irq
;
2963 engine
->dispatch_execbuffer
=
2964 gen8_ring_dispatch_execbuffer
;
2965 if (i915_semaphore_is_enabled(dev_priv
)) {
2966 engine
->semaphore
.sync_to
= gen8_ring_sync
;
2967 engine
->semaphore
.signal
= gen8_xcs_signal
;
2968 GEN8_RING_SEMAPHORE_INIT(engine
);
2971 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2972 engine
->irq_get
= gen6_ring_get_irq
;
2973 engine
->irq_put
= gen6_ring_put_irq
;
2974 engine
->dispatch_execbuffer
=
2975 gen6_ring_dispatch_execbuffer
;
2976 if (i915_semaphore_is_enabled(dev_priv
)) {
2977 engine
->semaphore
.sync_to
= gen6_ring_sync
;
2978 engine
->semaphore
.signal
= gen6_signal
;
2979 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2980 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2981 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2982 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2983 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2984 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2985 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2986 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2987 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2988 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2992 engine
->mmio_base
= BSD_RING_BASE
;
2993 engine
->flush
= bsd_ring_flush
;
2994 engine
->add_request
= i9xx_add_request
;
2995 engine
->get_seqno
= ring_get_seqno
;
2996 engine
->set_seqno
= ring_set_seqno
;
2997 if (IS_GEN5(dev_priv
)) {
2998 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2999 engine
->irq_get
= gen5_ring_get_irq
;
3000 engine
->irq_put
= gen5_ring_put_irq
;
3002 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
3003 engine
->irq_get
= i9xx_ring_get_irq
;
3004 engine
->irq_put
= i9xx_ring_put_irq
;
3006 engine
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
3008 engine
->init_hw
= init_ring_common
;
3010 return intel_init_ring_buffer(dev
, engine
);
3014 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3016 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
3018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3019 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
3021 engine
->name
= "bsd2 ring";
3023 engine
->exec_id
= I915_EXEC_BSD
;
3026 engine
->write_tail
= ring_write_tail
;
3027 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
3028 engine
->flush
= gen6_bsd_ring_flush
;
3029 engine
->add_request
= gen6_add_request
;
3030 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3031 engine
->get_seqno
= ring_get_seqno
;
3032 engine
->set_seqno
= ring_set_seqno
;
3033 engine
->irq_enable_mask
=
3034 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
3035 engine
->irq_get
= gen8_ring_get_irq
;
3036 engine
->irq_put
= gen8_ring_put_irq
;
3037 engine
->dispatch_execbuffer
=
3038 gen8_ring_dispatch_execbuffer
;
3039 if (i915_semaphore_is_enabled(dev_priv
)) {
3040 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3041 engine
->semaphore
.signal
= gen8_xcs_signal
;
3042 GEN8_RING_SEMAPHORE_INIT(engine
);
3044 engine
->init_hw
= init_ring_common
;
3046 return intel_init_ring_buffer(dev
, engine
);
3049 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
3051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3052 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
3054 engine
->name
= "blitter ring";
3056 engine
->exec_id
= I915_EXEC_BLT
;
3059 engine
->mmio_base
= BLT_RING_BASE
;
3060 engine
->write_tail
= ring_write_tail
;
3061 engine
->flush
= gen6_ring_flush
;
3062 engine
->add_request
= gen6_add_request
;
3063 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3064 engine
->get_seqno
= ring_get_seqno
;
3065 engine
->set_seqno
= ring_set_seqno
;
3066 if (INTEL_GEN(dev_priv
) >= 8) {
3067 engine
->irq_enable_mask
=
3068 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
3069 engine
->irq_get
= gen8_ring_get_irq
;
3070 engine
->irq_put
= gen8_ring_put_irq
;
3071 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3072 if (i915_semaphore_is_enabled(dev_priv
)) {
3073 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3074 engine
->semaphore
.signal
= gen8_xcs_signal
;
3075 GEN8_RING_SEMAPHORE_INIT(engine
);
3078 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
3079 engine
->irq_get
= gen6_ring_get_irq
;
3080 engine
->irq_put
= gen6_ring_put_irq
;
3081 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3082 if (i915_semaphore_is_enabled(dev_priv
)) {
3083 engine
->semaphore
.signal
= gen6_signal
;
3084 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3086 * The current semaphore is only applied on pre-gen8
3087 * platform. And there is no VCS2 ring on the pre-gen8
3088 * platform. So the semaphore between BCS and VCS2 is
3089 * initialized as INVALID. Gen8 will initialize the
3090 * sema between BCS and VCS2 later.
3092 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
3093 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
3094 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
3095 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
3096 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3097 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
3098 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
3099 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
3100 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
3101 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3104 engine
->init_hw
= init_ring_common
;
3106 return intel_init_ring_buffer(dev
, engine
);
3109 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
3111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3112 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
3114 engine
->name
= "video enhancement ring";
3116 engine
->exec_id
= I915_EXEC_VEBOX
;
3119 engine
->mmio_base
= VEBOX_RING_BASE
;
3120 engine
->write_tail
= ring_write_tail
;
3121 engine
->flush
= gen6_ring_flush
;
3122 engine
->add_request
= gen6_add_request
;
3123 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
3124 engine
->get_seqno
= ring_get_seqno
;
3125 engine
->set_seqno
= ring_set_seqno
;
3127 if (INTEL_GEN(dev_priv
) >= 8) {
3128 engine
->irq_enable_mask
=
3129 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3130 engine
->irq_get
= gen8_ring_get_irq
;
3131 engine
->irq_put
= gen8_ring_put_irq
;
3132 engine
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3133 if (i915_semaphore_is_enabled(dev_priv
)) {
3134 engine
->semaphore
.sync_to
= gen8_ring_sync
;
3135 engine
->semaphore
.signal
= gen8_xcs_signal
;
3136 GEN8_RING_SEMAPHORE_INIT(engine
);
3139 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3140 engine
->irq_get
= hsw_vebox_get_irq
;
3141 engine
->irq_put
= hsw_vebox_put_irq
;
3142 engine
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3143 if (i915_semaphore_is_enabled(dev_priv
)) {
3144 engine
->semaphore
.sync_to
= gen6_ring_sync
;
3145 engine
->semaphore
.signal
= gen6_signal
;
3146 engine
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
3147 engine
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
3148 engine
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
3149 engine
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
3150 engine
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3151 engine
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
3152 engine
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
3153 engine
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
3154 engine
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
3155 engine
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3158 engine
->init_hw
= init_ring_common
;
3160 return intel_init_ring_buffer(dev
, engine
);
3164 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3166 struct intel_engine_cs
*engine
= req
->engine
;
3169 if (!engine
->gpu_caches_dirty
)
3172 ret
= engine
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3176 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3178 engine
->gpu_caches_dirty
= false;
3183 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3185 struct intel_engine_cs
*engine
= req
->engine
;
3186 uint32_t flush_domains
;
3190 if (engine
->gpu_caches_dirty
)
3191 flush_domains
= I915_GEM_GPU_DOMAINS
;
3193 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3197 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3199 engine
->gpu_caches_dirty
= false;
3204 intel_stop_engine(struct intel_engine_cs
*engine
)
3208 if (!intel_engine_initialized(engine
))
3211 ret
= intel_engine_idle(engine
);
3213 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",