drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 #include <linux/hashtable.h>
   5 #include "i915_gem_batch_pool.h"
   6
   7 #define I915_CMD_HASH_ORDER 9
   8
   9 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  10  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
  11  * to give some inclination as to some of the magic values used in the various
  12  * workarounds!
  13  */
  14 #define CACHELINE_BYTES 64
  15 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
  16
  17 /*
  18  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
  19  * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
  20  * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
  21  *
  22  * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
  23  * cacheline, the Head Pointer must not be greater than the Tail
  24  * Pointer."
  25  */
  26 #define I915_RING_FREE_SPACE 64
  27
  28 struct  intel_hw_status_page {
  29         u32             *page_addr;
  30         unsigned int    gfx_addr;
  31         struct          drm_i915_gem_object *obj;
  32 };
  33
  34 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  35 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  36
  37 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  38 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  39
  40 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  41 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  42
  43 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  44 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  45
  46 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  47 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  48
  49 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
  50 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
  51
  52 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
  53  * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
  54  */
  55 #define i915_semaphore_seqno_size sizeof(uint64_t)
  56 #define GEN8_SIGNAL_OFFSET(__ring, to)                       \
  57         (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
  58         ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) +   \
  59         (i915_semaphore_seqno_size * (to)))
  60
  61 #define GEN8_WAIT_OFFSET(__ring, from)                       \
  62         (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
  63         ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
  64         (i915_semaphore_seqno_size * (__ring)->id))
  65
  66 #define GEN8_RING_SEMAPHORE_INIT do { \
  67         if (!dev_priv->semaphore_obj) { \
  68                 break; \
  69         } \
  70         ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
  71         ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
  72         ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
  73         ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
  74         ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
  75         ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
  76         } while(0)
  77
  78 enum intel_ring_hangcheck_action {
  79         HANGCHECK_IDLE = 0,
  80         HANGCHECK_WAIT,
  81         HANGCHECK_ACTIVE,
  82         HANGCHECK_ACTIVE_LOOP,
  83         HANGCHECK_KICK,
  84         HANGCHECK_HUNG,
  85 };
  86
  87 #define HANGCHECK_SCORE_RING_HUNG 31
  88
  89 struct intel_ring_hangcheck {
  90         u64 acthd;
  91         u64 max_acthd;
  92         u32 seqno;
  93         int score;
  94         enum intel_ring_hangcheck_action action;
  95         int deadlock;
  96 };
  97
  98 struct intel_ringbuffer {
  99         struct drm_i915_gem_object *obj;
 100         void __iomem *virtual_start;
 101
 102         struct intel_engine_cs *ring;
 103         struct list_head link;
 104
 105         u32 head;
 106         u32 tail;
 107         int space;
 108         int size;
 109         int effective_size;
 110         int reserved_size;
 111         int reserved_tail;
 112         bool reserved_in_use;
 113
 114         /** We track the position of the requests in the ring buffer, and
 115          * when each is retired we increment last_retired_head as the GPU
 116          * must have finished processing the request and so we know we
 117          * can advance the ringbuffer up to that position.
 118          *
 119          * last_retired_head is set to -1 after the value is consumed so
 120          * we can detect new retirements.
 121          */
 122         u32 last_retired_head;
 123 };
 124
 125 struct  intel_context;
 126 struct drm_i915_reg_descriptor;
 127
 128 /*
 129  * we use a single page to load ctx workarounds so all of these
 130  * values are referred in terms of dwords
 131  *
 132  * struct i915_wa_ctx_bb:
 133  *  offset: specifies batch starting position, also helpful in case
 134  *    if we want to have multiple batches at different offsets based on
 135  *    some criteria. It is not a requirement at the moment but provides
 136  *    an option for future use.
 137  *  size: size of the batch in DWORDS
 138  */
 139 struct  i915_ctx_workarounds {
 140         struct i915_wa_ctx_bb {
 141                 u32 offset;
 142                 u32 size;
 143         } indirect_ctx, per_ctx;
 144         struct drm_i915_gem_object *obj;
 145 };
 146
 147 struct  intel_engine_cs {
 148         const char      *name;
 149         enum intel_ring_id {
 150                 RCS = 0x0,
 151                 VCS,
 152                 BCS,
 153                 VECS,
 154                 VCS2
 155         } id;
 156 #define I915_NUM_RINGS 5
 157 #define LAST_USER_RING (VECS + 1)
 158         u32             mmio_base;
 159         struct          drm_device *dev;
 160         struct intel_ringbuffer *buffer;
 161         struct list_head buffers;
 162
 163         /*
 164          * A pool of objects to use as shadow copies of client batch buffers
 165          * when the command parser is enabled. Prevents the client from
 166          * modifying the batch contents after software parsing.
 167          */
 168         struct i915_gem_batch_pool batch_pool;
 169
 170         struct intel_hw_status_page status_page;
 171         struct i915_ctx_workarounds wa_ctx;
 172
 173         unsigned irq_refcount; /* protected by dev_priv->irq_lock */
 174         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
 175         struct drm_i915_gem_request *trace_irq_req;
 176         bool __must_check (*irq_get)(struct intel_engine_cs *ring);
 177         void            (*irq_put)(struct intel_engine_cs *ring);
 178
 179         int             (*init_hw)(struct intel_engine_cs *ring);
 180
 181         int             (*init_context)(struct drm_i915_gem_request *req);
 182
 183         void            (*write_tail)(struct intel_engine_cs *ring,
 184                                       u32 value);
 185         int __must_check (*flush)(struct drm_i915_gem_request *req,
 186                                   u32   invalidate_domains,
 187                                   u32   flush_domains);
 188         int             (*add_request)(struct drm_i915_gem_request *req);
 189         /* Some chipsets are not quite as coherent as advertised and need
 190          * an expensive kick to force a true read of the up-to-date seqno.
 191          * However, the up-to-date seqno is not always required and the last
 192          * seen value is good enough. Note that the seqno will always be
 193          * monotonic, even if not coherent.
 194          */
 195         u32             (*get_seqno)(struct intel_engine_cs *ring,
 196                                      bool lazy_coherency);
 197         void            (*set_seqno)(struct intel_engine_cs *ring,
 198                                      u32 seqno);
 199         int             (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
 200                                                u64 offset, u32 length,
 201                                                unsigned dispatch_flags);
 202 #define I915_DISPATCH_SECURE 0x1
 203 #define I915_DISPATCH_PINNED 0x2
 204 #define I915_DISPATCH_RS     0x4
 205         void            (*cleanup)(struct intel_engine_cs *ring);
 206
 207         /* GEN8 signal/wait table - never trust comments!
 208          *        signal to     signal to    signal to   signal to      signal to
 209          *          RCS            VCS          BCS        VECS          VCS2
 210          *      --------------------------------------------------------------------
 211          *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
 212          *      |-------------------------------------------------------------------
 213          *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
 214          *      |-------------------------------------------------------------------
 215          *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
 216          *      |-------------------------------------------------------------------
 217          * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
 218          *      |-------------------------------------------------------------------
 219          * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
 220          *      |-------------------------------------------------------------------
 221          *
 222          * Generalization:
 223          *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
 224          *  ie. transpose of g(x, y)
 225          *
 226          *       sync from      sync from    sync from    sync from     sync from
 227          *          RCS            VCS          BCS        VECS          VCS2
 228          *      --------------------------------------------------------------------
 229          *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
 230          *      |-------------------------------------------------------------------
 231          *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
 232          *      |-------------------------------------------------------------------
 233          *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
 234          *      |-------------------------------------------------------------------
 235          * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
 236          *      |-------------------------------------------------------------------
 237          * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
 238          *      |-------------------------------------------------------------------
 239          *
 240          * Generalization:
 241          *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
 242          *  ie. transpose of f(x, y)
 243          */
 244         struct {
 245                 u32     sync_seqno[I915_NUM_RINGS-1];
 246
 247                 union {
 248                         struct {
 249                                 /* our mbox written by others */
 250                                 u32             wait[I915_NUM_RINGS];
 251                                 /* mboxes this ring signals to */
 252                                 u32             signal[I915_NUM_RINGS];
 253                         } mbox;
 254                         u64             signal_ggtt[I915_NUM_RINGS];
 255                 };
 256
 257                 /* AKA wait() */
 258                 int     (*sync_to)(struct drm_i915_gem_request *to_req,
 259                                    struct intel_engine_cs *from,
 260                                    u32 seqno);
 261                 int     (*signal)(struct drm_i915_gem_request *signaller_req,
 262                                   /* num_dwords needed by caller */
 263                                   unsigned int num_dwords);
 264         } semaphore;
 265
 266         /* Execlists */
 267         spinlock_t execlist_lock;
 268         struct list_head execlist_queue;
 269         struct list_head execlist_retired_req_list;
 270         u8 next_context_status_buffer;
 271         u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
 272         int             (*emit_request)(struct drm_i915_gem_request *request);
 273         int             (*emit_flush)(struct drm_i915_gem_request *request,
 274                                       u32 invalidate_domains,
 275                                       u32 flush_domains);
 276         int             (*emit_bb_start)(struct drm_i915_gem_request *req,
 277                                          u64 offset, unsigned dispatch_flags);
 278
 279         /**
 280          * List of objects currently involved in rendering from the
 281          * ringbuffer.
 282          *
 283          * Includes buffers having the contents of their GPU caches
 284          * flushed, not necessarily primitives.  last_read_req
 285          * represents when the rendering involved will be completed.
 286          *
 287          * A reference is held on the buffer while on this list.
 288          */
 289         struct list_head active_list;
 290
 291         /**
 292          * List of breadcrumbs associated with GPU requests currently
 293          * outstanding.
 294          */
 295         struct list_head request_list;
 296
 297         /**
 298          * Seqno of request most recently submitted to request_list.
 299          * Used exclusively by hang checker to avoid grabbing lock while
 300          * inspecting request list.
 301          */
 302         u32 last_submitted_seqno;
 303
 304         bool gpu_caches_dirty;
 305
 306         wait_queue_head_t irq_queue;
 307
 308         struct intel_context *default_context;
 309         struct intel_context *last_context;
 310
 311         struct intel_ring_hangcheck hangcheck;
 312
 313         struct {
 314                 struct drm_i915_gem_object *obj;
 315                 u32 gtt_offset;
 316                 volatile u32 *cpu_page;
 317         } scratch;
 318
 319         bool needs_cmd_parser;
 320
 321         /*
 322          * Table of commands the command parser needs to know about
 323          * for this ring.
 324          */
 325         DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
 326
 327         /*
 328          * Table of registers allowed in commands that read/write registers.
 329          */
 330         const struct drm_i915_reg_descriptor *reg_table;
 331         int reg_count;
 332
 333         /*
 334          * Table of registers allowed in commands that read/write registers, but
 335          * only from the DRM master.
 336          */
 337         const struct drm_i915_reg_descriptor *master_reg_table;
 338         int master_reg_count;
 339
 340         /*
 341          * Returns the bitmask for the length field of the specified command.
 342          * Return 0 for an unrecognized/invalid command.
 343          *
 344          * If the command parser finds an entry for a command in the ring's
 345          * cmd_tables, it gets the command's length based on the table entry.
 346          * If not, it calls this function to determine the per-ring length field
 347          * encoding for the command (i.e. certain opcode ranges use certain bits
 348          * to encode the command length in the header).
 349          */
 350         u32 (*get_cmd_length_mask)(u32 cmd_header);
 351 };
 352
 353 bool intel_ring_initialized(struct intel_engine_cs *ring);
 354
 355 static inline unsigned
 356 intel_ring_flag(struct intel_engine_cs *ring)
 357 {
 358         return 1 << ring->id;
 359 }
 360
 361 static inline u32
 362 intel_ring_sync_index(struct intel_engine_cs *ring,
 363                       struct intel_engine_cs *other)
 364 {
 365         int idx;
 366
 367         /*
 368          * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
 369          * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
 370          * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
 371          * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
 372          * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
 373          */
 374
 375         idx = (other - ring) - 1;
 376         if (idx < 0)
 377                 idx += I915_NUM_RINGS;
 378
 379         return idx;
 380 }
 381
 382 static inline void
 383 intel_flush_status_page(struct intel_engine_cs *ring, int reg)
 384 {
 385         drm_clflush_virt_range(&ring->status_page.page_addr[reg],
 386                                sizeof(uint32_t));
 387 }
 388
 389 static inline u32
 390 intel_read_status_page(struct intel_engine_cs *ring,
 391                        int reg)
 392 {
 393         /* Ensure that the compiler doesn't optimize away the load. */
 394         barrier();
 395         return ring->status_page.page_addr[reg];
 396 }
 397
 398 static inline void
 399 intel_write_status_page(struct intel_engine_cs *ring,
 400                         int reg, u32 value)
 401 {
 402         ring->status_page.page_addr[reg] = value;
 403 }
 404
 405 /**
 406  * Reads a dword out of the status page, which is written to from the command
 407  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 408  * MI_STORE_DATA_IMM.
 409  *
 410  * The following dwords have a reserved meaning:
 411  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 412  * 0x04: ring 0 head pointer
 413  * 0x05: ring 1 head pointer (915-class)
 414  * 0x06: ring 2 head pointer (915-class)
 415  * 0x10-0x1b: Context status DWords (GM45)
 416  * 0x1f: Last written status offset. (GM45)
 417  * 0x20-0x2f: Reserved (Gen6+)
 418  *
 419  * The area from dword 0x30 to 0x3ff is available for driver usage.
 420  */
 421 #define I915_GEM_HWS_INDEX              0x30
 422 #define I915_GEM_HWS_SCRATCH_INDEX      0x40
 423 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 424
 425 struct intel_ringbuffer *
 426 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
 427 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
 428                                      struct intel_ringbuffer *ringbuf);
 429 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
 430 void intel_ringbuffer_free(struct intel_ringbuffer *ring);
 431
 432 void intel_stop_ring_buffer(struct intel_engine_cs *ring);
 433 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
 434
 435 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
 436
 437 int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
 438 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
 439 static inline void intel_ring_emit(struct intel_engine_cs *ring,
 440                                    u32 data)
 441 {
 442         struct intel_ringbuffer *ringbuf = ring->buffer;
 443         iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
 444         ringbuf->tail += 4;
 445 }
 446 static inline void intel_ring_emit_reg(struct intel_engine_cs *ring,
 447                                        u32 reg)
 448 {
 449         intel_ring_emit(ring, reg);
 450 }
 451 static inline void intel_ring_advance(struct intel_engine_cs *ring)
 452 {
 453         struct intel_ringbuffer *ringbuf = ring->buffer;
 454         ringbuf->tail &= ringbuf->size - 1;
 455 }
 456 int __intel_ring_space(int head, int tail, int size);
 457 void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
 458 int intel_ring_space(struct intel_ringbuffer *ringbuf);
 459 bool intel_ring_stopped(struct intel_engine_cs *ring);
 460
 461 int __must_check intel_ring_idle(struct intel_engine_cs *ring);
 462 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
 463 int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
 464 int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
 465
 466 void intel_fini_pipe_control(struct intel_engine_cs *ring);
 467 int intel_init_pipe_control(struct intel_engine_cs *ring);
 468
 469 int intel_init_render_ring_buffer(struct drm_device *dev);
 470 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 471 int intel_init_bsd2_ring_buffer(struct drm_device *dev);
 472 int intel_init_blt_ring_buffer(struct drm_device *dev);
 473 int intel_init_vebox_ring_buffer(struct drm_device *dev);
 474
 475 u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
 476
 477 int init_workarounds_ring(struct intel_engine_cs *ring);
 478
 479 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
 480 {
 481         return ringbuf->tail;
 482 }
 483
 484 /*
 485  * Arbitrary size for largest possible 'add request' sequence. The code paths
 486  * are complex and variable. Empirical measurement shows that the worst case
 487  * is ILK at 136 words. Reserving too much is better than reserving too little
 488  * as that allows for corner cases that might have been missed. So the figure
 489  * has been rounded up to 160 words.
 490  */
 491 #define MIN_SPACE_FOR_ADD_REQUEST       160
 492
 493 /*
 494  * Reserve space in the ring to guarantee that the i915_add_request() call
 495  * will always have sufficient room to do its stuff. The request creation
 496  * code calls this automatically.
 497  */
 498 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size);
 499 /* Cancel the reservation, e.g. because the request is being discarded. */
 500 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf);
 501 /* Use the reserved space - for use by i915_add_request() only. */
 502 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf);
 503 /* Finish with the reserved space - for use by i915_add_request() only. */
 504 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf);
 505
 506 /* Legacy ringbuffer specific portion of reservation code: */
 507 int intel_ring_reserve_space(struct drm_i915_gem_request *request);
 508
 509 #endif /* _INTEL_RINGBUFFER_H_ */