drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 /*
   5  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
   6  * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
   7  * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
   8  *
   9  * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
  10  * cacheline, the Head Pointer must not be greater than the Tail
  11  * Pointer."
  12  */
  13 #define I915_RING_FREE_SPACE 64
  14
  15 struct  intel_hw_status_page {
  16         u32             *page_addr;
  17         unsigned int    gfx_addr;
  18         struct          drm_i915_gem_object *obj;
  19 };
  20
  21 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  22 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  23
  24 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  25 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  26
  27 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  28 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  29
  30 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  31 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  32
  33 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  34 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  35
  36 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
  37
  38 enum intel_ring_hangcheck_action {
  39         HANGCHECK_IDLE = 0,
  40         HANGCHECK_WAIT,
  41         HANGCHECK_ACTIVE,
  42         HANGCHECK_KICK,
  43         HANGCHECK_HUNG,
  44 };
  45
  46 #define HANGCHECK_SCORE_RING_HUNG 31
  47
  48 struct intel_ring_hangcheck {
  49         u64 acthd;
  50         u32 seqno;
  51         int score;
  52         enum intel_ring_hangcheck_action action;
  53         bool deadlock;
  54 };
  55
  56 struct  intel_ring_buffer {
  57         const char      *name;
  58         enum intel_ring_id {
  59                 RCS = 0x0,
  60                 VCS,
  61                 BCS,
  62                 VECS,
  63         } id;
  64 #define I915_NUM_RINGS 4
  65         u32             mmio_base;
  66         void            __iomem *virtual_start;
  67         struct          drm_device *dev;
  68         struct          drm_i915_gem_object *obj;
  69
  70         u32             head;
  71         u32             tail;
  72         int             space;
  73         int             size;
  74         int             effective_size;
  75         struct intel_hw_status_page status_page;
  76
  77         /** We track the position of the requests in the ring buffer, and
  78          * when each is retired we increment last_retired_head as the GPU
  79          * must have finished processing the request and so we know we
  80          * can advance the ringbuffer up to that position.
  81          *
  82          * last_retired_head is set to -1 after the value is consumed so
  83          * we can detect new retirements.
  84          */
  85         u32             last_retired_head;
  86
  87         unsigned irq_refcount; /* protected by dev_priv->irq_lock */
  88         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
  89         u32             trace_irq_seqno;
  90         u32             sync_seqno[I915_NUM_RINGS-1];
  91         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  92         void            (*irq_put)(struct intel_ring_buffer *ring);
  93
  94         int             (*init)(struct intel_ring_buffer *ring);
  95
  96         void            (*write_tail)(struct intel_ring_buffer *ring,
  97                                       u32 value);
  98         int __must_check (*flush)(struct intel_ring_buffer *ring,
  99                                   u32   invalidate_domains,
 100                                   u32   flush_domains);
 101         int             (*add_request)(struct intel_ring_buffer *ring);
 102         /* Some chipsets are not quite as coherent as advertised and need
 103          * an expensive kick to force a true read of the up-to-date seqno.
 104          * However, the up-to-date seqno is not always required and the last
 105          * seen value is good enough. Note that the seqno will always be
 106          * monotonic, even if not coherent.
 107          */
 108         u32             (*get_seqno)(struct intel_ring_buffer *ring,
 109                                      bool lazy_coherency);
 110         void            (*set_seqno)(struct intel_ring_buffer *ring,
 111                                      u32 seqno);
 112         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
 113                                                u32 offset, u32 length,
 114                                                unsigned flags);
 115 #define I915_DISPATCH_SECURE 0x1
 116 #define I915_DISPATCH_PINNED 0x2
 117         void            (*cleanup)(struct intel_ring_buffer *ring);
 118         int             (*sync_to)(struct intel_ring_buffer *ring,
 119                                    struct intel_ring_buffer *to,
 120                                    u32 seqno);
 121
 122         /* our mbox written by others */
 123         u32             semaphore_register[I915_NUM_RINGS];
 124         /* mboxes this ring signals to */
 125         u32             signal_mbox[I915_NUM_RINGS];
 126
 127         /**
 128          * List of objects currently involved in rendering from the
 129          * ringbuffer.
 130          *
 131          * Includes buffers having the contents of their GPU caches
 132          * flushed, not necessarily primitives.  last_rendering_seqno
 133          * represents when the rendering involved will be completed.
 134          *
 135          * A reference is held on the buffer while on this list.
 136          */
 137         struct list_head active_list;
 138
 139         /**
 140          * List of breadcrumbs associated with GPU requests currently
 141          * outstanding.
 142          */
 143         struct list_head request_list;
 144
 145         /**
 146          * Do we have some not yet emitted requests outstanding?
 147          */
 148         struct drm_i915_gem_request *preallocated_lazy_request;
 149         u32 outstanding_lazy_seqno;
 150         bool gpu_caches_dirty;
 151         bool fbc_dirty;
 152
 153         wait_queue_head_t irq_queue;
 154
 155         struct i915_hw_context *default_context;
 156         struct i915_hw_context *last_context;
 157
 158         struct intel_ring_hangcheck hangcheck;
 159
 160         struct {
 161                 struct drm_i915_gem_object *obj;
 162                 u32 gtt_offset;
 163                 volatile u32 *cpu_page;
 164         } scratch;
 165
 166         /*
 167          * Tables of commands the command parser needs to know about
 168          * for this ring.
 169          */
 170         const struct drm_i915_cmd_table *cmd_tables;
 171         int cmd_table_count;
 172
 173         /*
 174          * Table of registers allowed in commands that read/write registers.
 175          */
 176         const u32 *reg_table;
 177         int reg_count;
 178
 179         /*
 180          * Table of registers allowed in commands that read/write registers, but
 181          * only from the DRM master.
 182          */
 183         const u32 *master_reg_table;
 184         int master_reg_count;
 185
 186         /*
 187          * Returns the bitmask for the length field of the specified command.
 188          * Return 0 for an unrecognized/invalid command.
 189          *
 190          * If the command parser finds an entry for a command in the ring's
 191          * cmd_tables, it gets the command's length based on the table entry.
 192          * If not, it calls this function to determine the per-ring length field
 193          * encoding for the command (i.e. certain opcode ranges use certain bits
 194          * to encode the command length in the header).
 195          */
 196         u32 (*get_cmd_length_mask)(u32 cmd_header);
 197 };
 198
 199 static inline bool
 200 intel_ring_initialized(struct intel_ring_buffer *ring)
 201 {
 202         return ring->obj != NULL;
 203 }
 204
 205 static inline unsigned
 206 intel_ring_flag(struct intel_ring_buffer *ring)
 207 {
 208         return 1 << ring->id;
 209 }
 210
 211 static inline u32
 212 intel_ring_sync_index(struct intel_ring_buffer *ring,
 213                       struct intel_ring_buffer *other)
 214 {
 215         int idx;
 216
 217         /*
 218          * cs -> 0 = vcs, 1 = bcs
 219          * vcs -> 0 = bcs, 1 = cs,
 220          * bcs -> 0 = cs, 1 = vcs.
 221          */
 222
 223         idx = (other - ring) - 1;
 224         if (idx < 0)
 225                 idx += I915_NUM_RINGS;
 226
 227         return idx;
 228 }
 229
 230 static inline u32
 231 intel_read_status_page(struct intel_ring_buffer *ring,
 232                        int reg)
 233 {
 234         /* Ensure that the compiler doesn't optimize away the load. */
 235         barrier();
 236         return ring->status_page.page_addr[reg];
 237 }
 238
 239 static inline void
 240 intel_write_status_page(struct intel_ring_buffer *ring,
 241                         int reg, u32 value)
 242 {
 243         ring->status_page.page_addr[reg] = value;
 244 }
 245
 246 /**
 247  * Reads a dword out of the status page, which is written to from the command
 248  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 249  * MI_STORE_DATA_IMM.
 250  *
 251  * The following dwords have a reserved meaning:
 252  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 253  * 0x04: ring 0 head pointer
 254  * 0x05: ring 1 head pointer (915-class)
 255  * 0x06: ring 2 head pointer (915-class)
 256  * 0x10-0x1b: Context status DWords (GM45)
 257  * 0x1f: Last written status offset. (GM45)
 258  *
 259  * The area from dword 0x20 to 0x3ff is available for driver usage.
 260  */
 261 #define I915_GEM_HWS_INDEX              0x20
 262 #define I915_GEM_HWS_SCRATCH_INDEX      0x30
 263 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 264
 265 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 266
 267 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 268 int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
 269 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 270                                    u32 data)
 271 {
 272         iowrite32(data, ring->virtual_start + ring->tail);
 273         ring->tail += 4;
 274 }
 275 static inline void intel_ring_advance(struct intel_ring_buffer *ring)
 276 {
 277         ring->tail &= ring->size - 1;
 278 }
 279 void __intel_ring_advance(struct intel_ring_buffer *ring);
 280
 281 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 282 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
 283 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
 284 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 285
 286 int intel_init_render_ring_buffer(struct drm_device *dev);
 287 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 288 int intel_init_blt_ring_buffer(struct drm_device *dev);
 289 int intel_init_vebox_ring_buffer(struct drm_device *dev);
 290
 291 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 292 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 293
 294 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
 295 {
 296         return ring->tail;
 297 }
 298
 299 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
 300 {
 301         BUG_ON(ring->outstanding_lazy_seqno == 0);
 302         return ring->outstanding_lazy_seqno;
 303 }
 304
 305 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 306 {
 307         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 308                 ring->trace_irq_seqno = seqno;
 309 }
 310
 311 /* DRI warts */
 312 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 313
 314 #endif /* _INTEL_RINGBUFFER_H_ */