2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
33 #include "intel_drv.h"
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
52 #define GEN9_ENABLE_DC5(dev) 0
53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
57 i < (power_domains)->power_well_count && \
58 ((power_well) = &(power_domains)->power_wells[i]); \
60 if ((power_well)->domains & (domain_mask))
62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63 for (i = (power_domains)->power_well_count - 1; \
64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
66 if ((power_well)->domains & (domain_mask))
68 bool intel_display_power_well_is_enabled(struct drm_i915_private
*dev_priv
,
71 static void intel_power_well_enable(struct drm_i915_private
*dev_priv
,
72 struct i915_power_well
*power_well
)
74 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
75 power_well
->ops
->enable(dev_priv
, power_well
);
76 power_well
->hw_enabled
= true;
79 static void intel_power_well_disable(struct drm_i915_private
*dev_priv
,
80 struct i915_power_well
*power_well
)
82 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
83 power_well
->hw_enabled
= false;
84 power_well
->ops
->disable(dev_priv
, power_well
);
88 * We should only use the power well if we explicitly asked the hardware to
89 * enable it, so check if it's enabled and also check if we've requested it to
92 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
93 struct i915_power_well
*power_well
)
95 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
96 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
100 * __intel_display_power_is_enabled - unlocked check for a power domain
101 * @dev_priv: i915 device instance
102 * @domain: power domain to check
104 * This is the unlocked version of intel_display_power_is_enabled() and should
105 * only be used from error capture and recovery code where deadlocks are
109 * True when the power domain is enabled, false otherwise.
111 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
112 enum intel_display_power_domain domain
)
114 struct i915_power_domains
*power_domains
;
115 struct i915_power_well
*power_well
;
119 if (dev_priv
->pm
.suspended
)
122 power_domains
= &dev_priv
->power_domains
;
126 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
127 if (power_well
->always_on
)
130 if (!power_well
->hw_enabled
) {
140 * intel_display_power_is_enabled - check for a power domain
141 * @dev_priv: i915 device instance
142 * @domain: power domain to check
144 * This function can be used to check the hw power domain state. It is mostly
145 * used in hardware state readout functions. Everywhere else code should rely
146 * upon explicit power domain reference counting to ensure that the hardware
147 * block is powered up before accessing it.
149 * Callers must hold the relevant modesetting locks to ensure that concurrent
150 * threads can't disable the power well while the caller tries to read a few
154 * True when the power domain is enabled, false otherwise.
156 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
157 enum intel_display_power_domain domain
)
159 struct i915_power_domains
*power_domains
;
162 power_domains
= &dev_priv
->power_domains
;
164 mutex_lock(&power_domains
->lock
);
165 ret
= __intel_display_power_is_enabled(dev_priv
, domain
);
166 mutex_unlock(&power_domains
->lock
);
172 * intel_display_set_init_power - set the initial power domain state
173 * @dev_priv: i915 device instance
174 * @enable: whether to enable or disable the initial power domain state
176 * For simplicity our driver load/unload and system suspend/resume code assumes
177 * that all power domains are always enabled. This functions controls the state
178 * of this little hack. While the initial power domain state is enabled runtime
179 * pm is effectively disabled.
181 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
184 if (dev_priv
->power_domains
.init_power_on
== enable
)
188 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
190 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
192 dev_priv
->power_domains
.init_power_on
= enable
;
196 * Starting with Haswell, we have a "Power Down Well" that can be turned off
197 * when not needed anymore. We have 4 registers that can request the power well
198 * to be enabled, and it will only be disabled if none of the registers is
199 * requesting it to be enabled.
201 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
203 struct drm_device
*dev
= dev_priv
->dev
;
206 * After we re-enable the power well, if we touch VGA register 0x3d5
207 * we'll get unclaimed register interrupts. This stops after we write
208 * anything to the VGA MSR register. The vgacon module uses this
209 * register all the time, so if we unbind our driver and, as a
210 * consequence, bind vgacon, we'll get stuck in an infinite loop at
211 * console_unlock(). So make here we touch the VGA MSR register, making
212 * sure vgacon can keep working normally without triggering interrupts
213 * and error messages.
215 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
216 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
217 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
219 if (IS_BROADWELL(dev
))
220 gen8_irq_power_well_post_enable(dev_priv
,
221 1 << PIPE_C
| 1 << PIPE_B
);
224 static void skl_power_well_post_enable(struct drm_i915_private
*dev_priv
,
225 struct i915_power_well
*power_well
)
227 struct drm_device
*dev
= dev_priv
->dev
;
230 * After we re-enable the power well, if we touch VGA register 0x3d5
231 * we'll get unclaimed register interrupts. This stops after we write
232 * anything to the VGA MSR register. The vgacon module uses this
233 * register all the time, so if we unbind our driver and, as a
234 * consequence, bind vgacon, we'll get stuck in an infinite loop at
235 * console_unlock(). So make here we touch the VGA MSR register, making
236 * sure vgacon can keep working normally without triggering interrupts
237 * and error messages.
239 if (power_well
->data
== SKL_DISP_PW_2
) {
240 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
241 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
242 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
244 gen8_irq_power_well_post_enable(dev_priv
,
245 1 << PIPE_C
| 1 << PIPE_B
);
248 if (power_well
->data
== SKL_DISP_PW_1
) {
249 intel_prepare_ddi(dev
);
250 gen8_irq_power_well_post_enable(dev_priv
, 1 << PIPE_A
);
254 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
255 struct i915_power_well
*power_well
, bool enable
)
257 bool is_enabled
, enable_requested
;
260 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
261 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
262 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
265 if (!enable_requested
)
266 I915_WRITE(HSW_PWR_WELL_DRIVER
,
267 HSW_PWR_WELL_ENABLE_REQUEST
);
270 DRM_DEBUG_KMS("Enabling power well\n");
271 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
272 HSW_PWR_WELL_STATE_ENABLED
), 20))
273 DRM_ERROR("Timeout enabling power well\n");
274 hsw_power_well_post_enable(dev_priv
);
278 if (enable_requested
) {
279 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
280 POSTING_READ(HSW_PWR_WELL_DRIVER
);
281 DRM_DEBUG_KMS("Requesting to disable the power well\n");
286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
287 BIT(POWER_DOMAIN_TRANSCODER_A) | \
288 BIT(POWER_DOMAIN_PIPE_B) | \
289 BIT(POWER_DOMAIN_TRANSCODER_B) | \
290 BIT(POWER_DOMAIN_PIPE_C) | \
291 BIT(POWER_DOMAIN_TRANSCODER_C) | \
292 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
293 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
294 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
295 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
297 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
298 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
299 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
300 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
301 BIT(POWER_DOMAIN_AUX_B) | \
302 BIT(POWER_DOMAIN_AUX_C) | \
303 BIT(POWER_DOMAIN_AUX_D) | \
304 BIT(POWER_DOMAIN_AUDIO) | \
305 BIT(POWER_DOMAIN_VGA) | \
306 BIT(POWER_DOMAIN_INIT))
307 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
308 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
309 BIT(POWER_DOMAIN_PLLS) | \
310 BIT(POWER_DOMAIN_PIPE_A) | \
311 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
312 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
313 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
314 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
315 BIT(POWER_DOMAIN_AUX_A) | \
316 BIT(POWER_DOMAIN_INIT))
317 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
318 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
319 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
320 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
321 BIT(POWER_DOMAIN_INIT))
322 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
323 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
324 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
325 BIT(POWER_DOMAIN_INIT))
326 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
327 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
328 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
329 BIT(POWER_DOMAIN_INIT))
330 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
331 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
332 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
333 BIT(POWER_DOMAIN_INIT))
334 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
335 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
336 BIT(POWER_DOMAIN_PLLS) | \
337 BIT(POWER_DOMAIN_INIT))
338 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
339 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
340 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
341 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
342 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
343 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
344 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
345 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
346 BIT(POWER_DOMAIN_INIT))
348 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
349 BIT(POWER_DOMAIN_TRANSCODER_A) | \
350 BIT(POWER_DOMAIN_PIPE_B) | \
351 BIT(POWER_DOMAIN_TRANSCODER_B) | \
352 BIT(POWER_DOMAIN_PIPE_C) | \
353 BIT(POWER_DOMAIN_TRANSCODER_C) | \
354 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
355 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
356 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
357 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
358 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
359 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
360 BIT(POWER_DOMAIN_AUX_B) | \
361 BIT(POWER_DOMAIN_AUX_C) | \
362 BIT(POWER_DOMAIN_AUDIO) | \
363 BIT(POWER_DOMAIN_VGA) | \
364 BIT(POWER_DOMAIN_INIT))
365 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
366 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
367 BIT(POWER_DOMAIN_PIPE_A) | \
368 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
369 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
370 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
371 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
372 BIT(POWER_DOMAIN_AUX_A) | \
373 BIT(POWER_DOMAIN_PLLS) | \
374 BIT(POWER_DOMAIN_INIT))
375 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
376 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
377 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
378 BIT(POWER_DOMAIN_INIT))
380 static void assert_can_enable_dc9(struct drm_i915_private
*dev_priv
)
382 struct drm_device
*dev
= dev_priv
->dev
;
384 WARN(!IS_BROXTON(dev
), "Platform doesn't support DC9.\n");
385 WARN((I915_READ(DC_STATE_EN
) & DC_STATE_EN_DC9
),
386 "DC9 already programmed to be enabled.\n");
387 WARN(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
,
388 "DC5 still not disabled to enable DC9.\n");
389 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on.\n");
390 WARN(intel_irqs_enabled(dev_priv
), "Interrupts not disabled yet.\n");
393 * TODO: check for the following to verify the conditions to enter DC9
394 * state are satisfied:
395 * 1] Check relevant display engine registers to verify if mode set
396 * disable sequence was followed.
397 * 2] Check if display uninitialize sequence is initialized.
401 static void assert_can_disable_dc9(struct drm_i915_private
*dev_priv
)
403 WARN(intel_irqs_enabled(dev_priv
), "Interrupts not disabled yet.\n");
404 WARN(!(I915_READ(DC_STATE_EN
) & DC_STATE_EN_DC9
),
405 "DC9 already programmed to be disabled.\n");
406 WARN(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
,
407 "DC5 still not disabled.\n");
410 * TODO: check for the following to verify DC9 state was indeed
411 * entered before programming to disable it:
412 * 1] Check relevant display engine registers to verify if mode
413 * set disable sequence was followed.
414 * 2] Check if display uninitialize sequence is initialized.
418 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
)
422 assert_can_enable_dc9(dev_priv
);
424 DRM_DEBUG_KMS("Enabling DC9\n");
426 val
= I915_READ(DC_STATE_EN
);
427 val
|= DC_STATE_EN_DC9
;
428 I915_WRITE(DC_STATE_EN
, val
);
429 POSTING_READ(DC_STATE_EN
);
432 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
)
436 assert_can_disable_dc9(dev_priv
);
438 DRM_DEBUG_KMS("Disabling DC9\n");
440 val
= I915_READ(DC_STATE_EN
);
441 val
&= ~DC_STATE_EN_DC9
;
442 I915_WRITE(DC_STATE_EN
, val
);
443 POSTING_READ(DC_STATE_EN
);
446 static void gen9_set_dc_state_debugmask_memory_up(
447 struct drm_i915_private
*dev_priv
)
451 /* The below bit doesn't need to be cleared ever afterwards */
452 val
= I915_READ(DC_STATE_DEBUG
);
453 if (!(val
& DC_STATE_DEBUG_MASK_MEMORY_UP
)) {
454 val
|= DC_STATE_DEBUG_MASK_MEMORY_UP
;
455 I915_WRITE(DC_STATE_DEBUG
, val
);
456 POSTING_READ(DC_STATE_DEBUG
);
460 static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv
)
462 struct drm_device
*dev
= dev_priv
->dev
;
463 bool pg2_enabled
= intel_display_power_well_is_enabled(dev_priv
,
466 WARN_ONCE(!IS_SKYLAKE(dev
), "Platform doesn't support DC5.\n");
467 WARN_ONCE(!HAS_RUNTIME_PM(dev
), "Runtime PM not enabled.\n");
468 WARN_ONCE(pg2_enabled
, "PG2 not disabled to enable DC5.\n");
470 WARN_ONCE((I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
),
471 "DC5 already programmed to be enabled.\n");
472 WARN_ONCE(dev_priv
->pm
.suspended
,
473 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
475 assert_csr_loaded(dev_priv
);
478 static void assert_can_disable_dc5(struct drm_i915_private
*dev_priv
)
480 bool pg2_enabled
= intel_display_power_well_is_enabled(dev_priv
,
483 * During initialization, the firmware may not be loaded yet.
484 * We still want to make sure that the DC enabling flag is cleared.
486 if (dev_priv
->power_domains
.initializing
)
489 WARN_ONCE(!pg2_enabled
, "PG2 not enabled to disable DC5.\n");
490 WARN_ONCE(dev_priv
->pm
.suspended
,
491 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
494 static void gen9_enable_dc5(struct drm_i915_private
*dev_priv
)
498 assert_can_enable_dc5(dev_priv
);
500 DRM_DEBUG_KMS("Enabling DC5\n");
502 gen9_set_dc_state_debugmask_memory_up(dev_priv
);
504 val
= I915_READ(DC_STATE_EN
);
505 val
&= ~DC_STATE_EN_UPTO_DC5_DC6_MASK
;
506 val
|= DC_STATE_EN_UPTO_DC5
;
507 I915_WRITE(DC_STATE_EN
, val
);
508 POSTING_READ(DC_STATE_EN
);
511 static void gen9_disable_dc5(struct drm_i915_private
*dev_priv
)
515 assert_can_disable_dc5(dev_priv
);
517 DRM_DEBUG_KMS("Disabling DC5\n");
519 val
= I915_READ(DC_STATE_EN
);
520 val
&= ~DC_STATE_EN_UPTO_DC5
;
521 I915_WRITE(DC_STATE_EN
, val
);
522 POSTING_READ(DC_STATE_EN
);
525 static void assert_can_enable_dc6(struct drm_i915_private
*dev_priv
)
527 struct drm_device
*dev
= dev_priv
->dev
;
529 WARN_ONCE(!IS_SKYLAKE(dev
), "Platform doesn't support DC6.\n");
530 WARN_ONCE(!HAS_RUNTIME_PM(dev
), "Runtime PM not enabled.\n");
531 WARN_ONCE(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
532 "Backlight is not disabled.\n");
533 WARN_ONCE((I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC6
),
534 "DC6 already programmed to be enabled.\n");
536 assert_csr_loaded(dev_priv
);
539 static void assert_can_disable_dc6(struct drm_i915_private
*dev_priv
)
542 * During initialization, the firmware may not be loaded yet.
543 * We still want to make sure that the DC enabling flag is cleared.
545 if (dev_priv
->power_domains
.initializing
)
548 assert_csr_loaded(dev_priv
);
549 WARN_ONCE(!(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC6
),
550 "DC6 already programmed to be disabled.\n");
553 static void skl_enable_dc6(struct drm_i915_private
*dev_priv
)
557 assert_can_enable_dc6(dev_priv
);
559 DRM_DEBUG_KMS("Enabling DC6\n");
561 gen9_set_dc_state_debugmask_memory_up(dev_priv
);
563 val
= I915_READ(DC_STATE_EN
);
564 val
&= ~DC_STATE_EN_UPTO_DC5_DC6_MASK
;
565 val
|= DC_STATE_EN_UPTO_DC6
;
566 I915_WRITE(DC_STATE_EN
, val
);
567 POSTING_READ(DC_STATE_EN
);
570 static void skl_disable_dc6(struct drm_i915_private
*dev_priv
)
574 assert_can_disable_dc6(dev_priv
);
576 DRM_DEBUG_KMS("Disabling DC6\n");
578 val
= I915_READ(DC_STATE_EN
);
579 val
&= ~DC_STATE_EN_UPTO_DC6
;
580 I915_WRITE(DC_STATE_EN
, val
);
581 POSTING_READ(DC_STATE_EN
);
584 static void skl_set_power_well(struct drm_i915_private
*dev_priv
,
585 struct i915_power_well
*power_well
, bool enable
)
587 struct drm_device
*dev
= dev_priv
->dev
;
588 uint32_t tmp
, fuse_status
;
589 uint32_t req_mask
, state_mask
;
590 bool is_enabled
, enable_requested
, check_fuse_status
= false;
592 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
593 fuse_status
= I915_READ(SKL_FUSE_STATUS
);
595 switch (power_well
->data
) {
597 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
598 SKL_FUSE_PG0_DIST_STATUS
), 1)) {
599 DRM_ERROR("PG0 not enabled\n");
604 if (!(fuse_status
& SKL_FUSE_PG1_DIST_STATUS
)) {
605 DRM_ERROR("PG1 in disabled state\n");
609 case SKL_DISP_PW_DDI_A_E
:
610 case SKL_DISP_PW_DDI_B
:
611 case SKL_DISP_PW_DDI_C
:
612 case SKL_DISP_PW_DDI_D
:
613 case SKL_DISP_PW_MISC_IO
:
616 WARN(1, "Unknown power well %lu\n", power_well
->data
);
620 req_mask
= SKL_POWER_WELL_REQ(power_well
->data
);
621 enable_requested
= tmp
& req_mask
;
622 state_mask
= SKL_POWER_WELL_STATE(power_well
->data
);
623 is_enabled
= tmp
& state_mask
;
626 if (!enable_requested
) {
627 WARN((tmp
& state_mask
) &&
628 !I915_READ(HSW_PWR_WELL_BIOS
),
629 "Invalid for power well status to be enabled, unless done by the BIOS, \
630 when request is to disable!\n");
631 if ((GEN9_ENABLE_DC5(dev
) || SKL_ENABLE_DC6(dev
)) &&
632 power_well
->data
== SKL_DISP_PW_2
) {
633 if (SKL_ENABLE_DC6(dev
)) {
634 skl_disable_dc6(dev_priv
);
636 * DDI buffer programming unnecessary during driver-load/resume
637 * as it's already done during modeset initialization then.
638 * It's also invalid here as encoder list is still uninitialized.
640 if (!dev_priv
->power_domains
.initializing
)
641 intel_prepare_ddi(dev
);
643 gen9_disable_dc5(dev_priv
);
646 I915_WRITE(HSW_PWR_WELL_DRIVER
, tmp
| req_mask
);
650 DRM_DEBUG_KMS("Enabling %s\n", power_well
->name
);
651 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
653 DRM_ERROR("%s enable timeout\n",
655 check_fuse_status
= true;
658 if (enable_requested
) {
659 if (IS_SKYLAKE(dev
) &&
660 (power_well
->data
== SKL_DISP_PW_1
) &&
661 (intel_csr_load_status_get(dev_priv
) == FW_LOADED
))
662 DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
664 I915_WRITE(HSW_PWR_WELL_DRIVER
, tmp
& ~req_mask
);
665 POSTING_READ(HSW_PWR_WELL_DRIVER
);
666 DRM_DEBUG_KMS("Disabling %s\n", power_well
->name
);
669 if ((GEN9_ENABLE_DC5(dev
) || SKL_ENABLE_DC6(dev
)) &&
670 power_well
->data
== SKL_DISP_PW_2
) {
671 enum csr_state state
;
672 /* TODO: wait for a completion event or
673 * similar here instead of busy
674 * waiting using wait_for function.
676 wait_for((state
= intel_csr_load_status_get(dev_priv
)) !=
677 FW_UNINITIALIZED
, 1000);
678 if (state
!= FW_LOADED
)
679 DRM_DEBUG("CSR firmware not ready (%d)\n",
682 if (SKL_ENABLE_DC6(dev
))
683 skl_enable_dc6(dev_priv
);
685 gen9_enable_dc5(dev_priv
);
690 if (check_fuse_status
) {
691 if (power_well
->data
== SKL_DISP_PW_1
) {
692 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
693 SKL_FUSE_PG1_DIST_STATUS
), 1))
694 DRM_ERROR("PG1 distributing status timeout\n");
695 } else if (power_well
->data
== SKL_DISP_PW_2
) {
696 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
697 SKL_FUSE_PG2_DIST_STATUS
), 1))
698 DRM_ERROR("PG2 distributing status timeout\n");
702 if (enable
&& !is_enabled
)
703 skl_power_well_post_enable(dev_priv
, power_well
);
706 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
707 struct i915_power_well
*power_well
)
709 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
712 * We're taking over the BIOS, so clear any requests made by it since
713 * the driver is in charge now.
715 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
716 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
719 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
720 struct i915_power_well
*power_well
)
722 hsw_set_power_well(dev_priv
, power_well
, true);
725 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
726 struct i915_power_well
*power_well
)
728 hsw_set_power_well(dev_priv
, power_well
, false);
731 static bool skl_power_well_enabled(struct drm_i915_private
*dev_priv
,
732 struct i915_power_well
*power_well
)
734 uint32_t mask
= SKL_POWER_WELL_REQ(power_well
->data
) |
735 SKL_POWER_WELL_STATE(power_well
->data
);
737 return (I915_READ(HSW_PWR_WELL_DRIVER
) & mask
) == mask
;
740 static void skl_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
741 struct i915_power_well
*power_well
)
743 skl_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
745 /* Clear any request made by BIOS as driver is taking over */
746 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
749 static void skl_power_well_enable(struct drm_i915_private
*dev_priv
,
750 struct i915_power_well
*power_well
)
752 skl_set_power_well(dev_priv
, power_well
, true);
755 static void skl_power_well_disable(struct drm_i915_private
*dev_priv
,
756 struct i915_power_well
*power_well
)
758 skl_set_power_well(dev_priv
, power_well
, false);
761 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
762 struct i915_power_well
*power_well
)
766 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
767 struct i915_power_well
*power_well
)
772 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
773 struct i915_power_well
*power_well
, bool enable
)
775 enum punit_power_well power_well_id
= power_well
->data
;
780 mask
= PUNIT_PWRGT_MASK(power_well_id
);
781 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
782 PUNIT_PWRGT_PWR_GATE(power_well_id
);
784 mutex_lock(&dev_priv
->rps
.hw_lock
);
787 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
792 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
795 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
797 if (wait_for(COND
, 100))
798 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
800 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
805 mutex_unlock(&dev_priv
->rps
.hw_lock
);
808 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
809 struct i915_power_well
*power_well
)
811 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
814 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
815 struct i915_power_well
*power_well
)
817 vlv_set_power_well(dev_priv
, power_well
, true);
820 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
821 struct i915_power_well
*power_well
)
823 vlv_set_power_well(dev_priv
, power_well
, false);
826 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
827 struct i915_power_well
*power_well
)
829 int power_well_id
= power_well
->data
;
830 bool enabled
= false;
835 mask
= PUNIT_PWRGT_MASK(power_well_id
);
836 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
838 mutex_lock(&dev_priv
->rps
.hw_lock
);
840 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
842 * We only ever set the power-on and power-gate states, anything
843 * else is unexpected.
845 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
846 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
851 * A transient state at this point would mean some unexpected party
852 * is poking at the power controls too.
854 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
855 WARN_ON(ctrl
!= state
);
857 mutex_unlock(&dev_priv
->rps
.hw_lock
);
862 static void vlv_display_power_well_init(struct drm_i915_private
*dev_priv
)
867 * Enable the CRI clock source so we can get at the
868 * display and the reference clock for VGA
869 * hotplug / manual detection. Supposedly DSI also
870 * needs the ref clock up and running.
872 * CHV DPLL B/C have some issues if VGA mode is enabled.
874 for_each_pipe(dev_priv
->dev
, pipe
) {
875 u32 val
= I915_READ(DPLL(pipe
));
877 val
|= DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
879 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
881 I915_WRITE(DPLL(pipe
), val
);
884 spin_lock_irq(&dev_priv
->irq_lock
);
885 valleyview_enable_display_irqs(dev_priv
);
886 spin_unlock_irq(&dev_priv
->irq_lock
);
889 * During driver initialization/resume we can avoid restoring the
890 * part of the HW/SW state that will be inited anyway explicitly.
892 if (dev_priv
->power_domains
.initializing
)
895 intel_hpd_init(dev_priv
);
897 i915_redisable_vga_power_on(dev_priv
->dev
);
900 static void vlv_display_power_well_deinit(struct drm_i915_private
*dev_priv
)
902 spin_lock_irq(&dev_priv
->irq_lock
);
903 valleyview_disable_display_irqs(dev_priv
);
904 spin_unlock_irq(&dev_priv
->irq_lock
);
906 vlv_power_sequencer_reset(dev_priv
);
909 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
910 struct i915_power_well
*power_well
)
912 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
914 vlv_set_power_well(dev_priv
, power_well
, true);
916 vlv_display_power_well_init(dev_priv
);
919 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
920 struct i915_power_well
*power_well
)
922 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
924 vlv_display_power_well_deinit(dev_priv
);
926 vlv_set_power_well(dev_priv
, power_well
, false);
929 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
930 struct i915_power_well
*power_well
)
932 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
934 /* since ref/cri clock was enabled */
935 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
937 vlv_set_power_well(dev_priv
, power_well
, true);
940 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
941 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
942 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
943 * b. The other bits such as sfr settings / modesel may all
946 * This should only be done on init and resume from S3 with
947 * both PLLs disabled, or we risk losing DPIO and PLL
950 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
953 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
954 struct i915_power_well
*power_well
)
958 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
960 for_each_pipe(dev_priv
, pipe
)
961 assert_pll_disabled(dev_priv
, pipe
);
963 /* Assert common reset */
964 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
966 vlv_set_power_well(dev_priv
, power_well
, false);
969 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
971 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
974 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
975 struct i915_power_well
*power_well
;
978 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
979 if (power_well
->data
== power_well_id
)
986 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
988 static void assert_chv_phy_status(struct drm_i915_private
*dev_priv
)
990 struct i915_power_well
*cmn_bc
=
991 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
992 struct i915_power_well
*cmn_d
=
993 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_D
);
994 u32 phy_control
= dev_priv
->chv_phy_control
;
996 u32 phy_status_mask
= 0xffffffff;
1000 * The BIOS can leave the PHY is some weird state
1001 * where it doesn't fully power down some parts.
1002 * Disable the asserts until the PHY has been fully
1003 * reset (ie. the power well has been disabled at
1006 if (!dev_priv
->chv_phy_assert
[DPIO_PHY0
])
1007 phy_status_mask
&= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH0
) |
1008 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 0) |
1009 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 1) |
1010 PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH1
) |
1011 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 0) |
1012 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 1));
1014 if (!dev_priv
->chv_phy_assert
[DPIO_PHY1
])
1015 phy_status_mask
&= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1
, DPIO_CH0
) |
1016 PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 0) |
1017 PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 1));
1019 if (cmn_bc
->ops
->is_enabled(dev_priv
, cmn_bc
)) {
1020 phy_status
|= PHY_POWERGOOD(DPIO_PHY0
);
1022 /* this assumes override is only used to enable lanes */
1023 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH0
)) == 0)
1024 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH0
);
1026 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH1
)) == 0)
1027 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
);
1029 /* CL1 is on whenever anything is on in either channel */
1030 if (BITS_SET(phy_control
,
1031 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH0
) |
1032 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
)))
1033 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH0
);
1036 * The DPLLB check accounts for the pipe B + port A usage
1037 * with CL2 powered up but all the lanes in the second channel
1040 if (BITS_SET(phy_control
,
1041 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
)) &&
1042 (I915_READ(DPLL(PIPE_B
)) & DPLL_VCO_ENABLE
) == 0)
1043 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH1
);
1045 if (BITS_SET(phy_control
,
1046 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0
, DPIO_CH0
)))
1047 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 0);
1048 if (BITS_SET(phy_control
,
1049 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0
, DPIO_CH0
)))
1050 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 1);
1052 if (BITS_SET(phy_control
,
1053 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0
, DPIO_CH1
)))
1054 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 0);
1055 if (BITS_SET(phy_control
,
1056 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0
, DPIO_CH1
)))
1057 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 1);
1060 if (cmn_d
->ops
->is_enabled(dev_priv
, cmn_d
)) {
1061 phy_status
|= PHY_POWERGOOD(DPIO_PHY1
);
1063 /* this assumes override is only used to enable lanes */
1064 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1
, DPIO_CH0
)) == 0)
1065 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1
, DPIO_CH0
);
1067 if (BITS_SET(phy_control
,
1068 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1
, DPIO_CH0
)))
1069 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY1
, DPIO_CH0
);
1071 if (BITS_SET(phy_control
,
1072 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1
, DPIO_CH0
)))
1073 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 0);
1074 if (BITS_SET(phy_control
,
1075 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1
, DPIO_CH0
)))
1076 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 1);
1079 phy_status
&= phy_status_mask
;
1082 * The PHY may be busy with some initial calibration and whatnot,
1083 * so the power state can take a while to actually change.
1085 if (wait_for((tmp
= I915_READ(DISPLAY_PHY_STATUS
) & phy_status_mask
) == phy_status
, 10))
1086 WARN(phy_status
!= tmp
,
1087 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1088 tmp
, phy_status
, dev_priv
->chv_phy_control
);
1093 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
1094 struct i915_power_well
*power_well
)
1100 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
1101 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
1103 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1111 /* since ref/cri clock was enabled */
1112 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1113 vlv_set_power_well(dev_priv
, power_well
, true);
1115 /* Poll for phypwrgood signal */
1116 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
1117 DRM_ERROR("Display PHY %d is not power up\n", phy
);
1119 mutex_lock(&dev_priv
->sb_lock
);
1121 /* Enable dynamic power down */
1122 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW28
);
1123 tmp
|= DPIO_DYNPWRDOWNEN_CH0
| DPIO_CL1POWERDOWNEN
|
1124 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ
;
1125 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW28
, tmp
);
1127 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1128 tmp
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW6_CH1
);
1129 tmp
|= DPIO_DYNPWRDOWNEN_CH1
;
1130 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW6_CH1
, tmp
);
1133 * Force the non-existing CL2 off. BXT does this
1134 * too, so maybe it saves some power even though
1135 * CL2 doesn't exist?
1137 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
1138 tmp
|= DPIO_CL2_LDOFUSE_PWRENB
;
1139 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, tmp
);
1142 mutex_unlock(&dev_priv
->sb_lock
);
1144 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(phy
);
1145 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1147 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1148 phy
, dev_priv
->chv_phy_control
);
1150 assert_chv_phy_status(dev_priv
);
1153 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
1154 struct i915_power_well
*power_well
)
1158 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
1159 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
1161 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1163 assert_pll_disabled(dev_priv
, PIPE_A
);
1164 assert_pll_disabled(dev_priv
, PIPE_B
);
1167 assert_pll_disabled(dev_priv
, PIPE_C
);
1170 dev_priv
->chv_phy_control
&= ~PHY_COM_LANE_RESET_DEASSERT(phy
);
1171 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1173 vlv_set_power_well(dev_priv
, power_well
, false);
1175 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1176 phy
, dev_priv
->chv_phy_control
);
1178 /* PHY is fully reset now, so we can enable the PHY state asserts */
1179 dev_priv
->chv_phy_assert
[phy
] = true;
1181 assert_chv_phy_status(dev_priv
);
1184 static void assert_chv_phy_powergate(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1185 enum dpio_channel ch
, bool override
, unsigned int mask
)
1187 enum pipe pipe
= phy
== DPIO_PHY0
? PIPE_A
: PIPE_C
;
1188 u32 reg
, val
, expected
, actual
;
1191 * The BIOS can leave the PHY is some weird state
1192 * where it doesn't fully power down some parts.
1193 * Disable the asserts until the PHY has been fully
1194 * reset (ie. the power well has been disabled at
1197 if (!dev_priv
->chv_phy_assert
[phy
])
1201 reg
= _CHV_CMN_DW0_CH0
;
1203 reg
= _CHV_CMN_DW6_CH1
;
1205 mutex_lock(&dev_priv
->sb_lock
);
1206 val
= vlv_dpio_read(dev_priv
, pipe
, reg
);
1207 mutex_unlock(&dev_priv
->sb_lock
);
1210 * This assumes !override is only used when the port is disabled.
1211 * All lanes should power down even without the override when
1212 * the port is disabled.
1214 if (!override
|| mask
== 0xf) {
1215 expected
= DPIO_ALLDL_POWERDOWN
| DPIO_ANYDL_POWERDOWN
;
1217 * If CH1 common lane is not active anymore
1218 * (eg. for pipe B DPLL) the entire channel will
1219 * shut down, which causes the common lane registers
1220 * to read as 0. That means we can't actually check
1221 * the lane power down status bits, but as the entire
1222 * register reads as 0 it's a good indication that the
1223 * channel is indeed entirely powered down.
1225 if (ch
== DPIO_CH1
&& val
== 0)
1227 } else if (mask
!= 0x0) {
1228 expected
= DPIO_ANYDL_POWERDOWN
;
1234 actual
= val
>> DPIO_ANYDL_POWERDOWN_SHIFT_CH0
;
1236 actual
= val
>> DPIO_ANYDL_POWERDOWN_SHIFT_CH1
;
1237 actual
&= DPIO_ALLDL_POWERDOWN
| DPIO_ANYDL_POWERDOWN
;
1239 WARN(actual
!= expected
,
1240 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1241 !!(actual
& DPIO_ALLDL_POWERDOWN
), !!(actual
& DPIO_ANYDL_POWERDOWN
),
1242 !!(expected
& DPIO_ALLDL_POWERDOWN
), !!(expected
& DPIO_ANYDL_POWERDOWN
),
1246 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1247 enum dpio_channel ch
, bool override
)
1249 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1252 mutex_lock(&power_domains
->lock
);
1254 was_override
= dev_priv
->chv_phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1256 if (override
== was_override
)
1260 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1262 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1264 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1266 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1267 phy
, ch
, dev_priv
->chv_phy_control
);
1269 assert_chv_phy_status(dev_priv
);
1272 mutex_unlock(&power_domains
->lock
);
1274 return was_override
;
1277 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1278 bool override
, unsigned int mask
)
1280 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1281 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1282 enum dpio_phy phy
= vlv_dport_to_phy(enc_to_dig_port(&encoder
->base
));
1283 enum dpio_channel ch
= vlv_dport_to_channel(enc_to_dig_port(&encoder
->base
));
1285 mutex_lock(&power_domains
->lock
);
1287 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy
, ch
);
1288 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD(mask
, phy
, ch
);
1291 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1293 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1295 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1297 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1298 phy
, ch
, mask
, dev_priv
->chv_phy_control
);
1300 assert_chv_phy_status(dev_priv
);
1302 assert_chv_phy_powergate(dev_priv
, phy
, ch
, override
, mask
);
1304 mutex_unlock(&power_domains
->lock
);
1307 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
1308 struct i915_power_well
*power_well
)
1310 enum pipe pipe
= power_well
->data
;
1314 mutex_lock(&dev_priv
->rps
.hw_lock
);
1316 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
1318 * We only ever set the power-on and power-gate states, anything
1319 * else is unexpected.
1321 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
1322 enabled
= state
== DP_SSS_PWR_ON(pipe
);
1325 * A transient state at this point would mean some unexpected party
1326 * is poking at the power controls too.
1328 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
1329 WARN_ON(ctrl
<< 16 != state
);
1331 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1336 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
1337 struct i915_power_well
*power_well
,
1340 enum pipe pipe
= power_well
->data
;
1344 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
1346 mutex_lock(&dev_priv
->rps
.hw_lock
);
1349 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1354 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
1355 ctrl
&= ~DP_SSC_MASK(pipe
);
1356 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
1357 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
1359 if (wait_for(COND
, 100))
1360 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1362 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
1367 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1370 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
1371 struct i915_power_well
*power_well
)
1373 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1375 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
1378 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
1379 struct i915_power_well
*power_well
)
1381 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1383 chv_set_pipe_power_well(dev_priv
, power_well
, true);
1385 vlv_display_power_well_init(dev_priv
);
1388 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
1389 struct i915_power_well
*power_well
)
1391 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1393 vlv_display_power_well_deinit(dev_priv
);
1395 chv_set_pipe_power_well(dev_priv
, power_well
, false);
1399 * intel_display_power_get - grab a power domain reference
1400 * @dev_priv: i915 device instance
1401 * @domain: power domain to reference
1403 * This function grabs a power domain reference for @domain and ensures that the
1404 * power domain and all its parents are powered up. Therefore users should only
1405 * grab a reference to the innermost power domain they need.
1407 * Any power domain reference obtained by this function must have a symmetric
1408 * call to intel_display_power_put() to release the reference again.
1410 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1411 enum intel_display_power_domain domain
)
1413 struct i915_power_domains
*power_domains
;
1414 struct i915_power_well
*power_well
;
1417 intel_runtime_pm_get(dev_priv
);
1419 power_domains
= &dev_priv
->power_domains
;
1421 mutex_lock(&power_domains
->lock
);
1423 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
1424 if (!power_well
->count
++)
1425 intel_power_well_enable(dev_priv
, power_well
);
1428 power_domains
->domain_use_count
[domain
]++;
1430 mutex_unlock(&power_domains
->lock
);
1434 * intel_display_power_put - release a power domain reference
1435 * @dev_priv: i915 device instance
1436 * @domain: power domain to reference
1438 * This function drops the power domain reference obtained by
1439 * intel_display_power_get() and might power down the corresponding hardware
1440 * block right away if this is the last reference.
1442 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1443 enum intel_display_power_domain domain
)
1445 struct i915_power_domains
*power_domains
;
1446 struct i915_power_well
*power_well
;
1449 power_domains
= &dev_priv
->power_domains
;
1451 mutex_lock(&power_domains
->lock
);
1453 WARN_ON(!power_domains
->domain_use_count
[domain
]);
1454 power_domains
->domain_use_count
[domain
]--;
1456 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
1457 WARN_ON(!power_well
->count
);
1459 if (!--power_well
->count
&& i915
.disable_power_well
)
1460 intel_power_well_disable(dev_priv
, power_well
);
1463 mutex_unlock(&power_domains
->lock
);
1465 intel_runtime_pm_put(dev_priv
);
1468 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1469 BIT(POWER_DOMAIN_PIPE_A) | \
1470 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1471 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
1472 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
1473 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1474 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1475 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1476 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1477 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1478 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1479 BIT(POWER_DOMAIN_PORT_CRT) | \
1480 BIT(POWER_DOMAIN_PLLS) | \
1481 BIT(POWER_DOMAIN_AUX_A) | \
1482 BIT(POWER_DOMAIN_AUX_B) | \
1483 BIT(POWER_DOMAIN_AUX_C) | \
1484 BIT(POWER_DOMAIN_AUX_D) | \
1485 BIT(POWER_DOMAIN_INIT))
1486 #define HSW_DISPLAY_POWER_DOMAINS ( \
1487 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1488 BIT(POWER_DOMAIN_INIT))
1490 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1491 HSW_ALWAYS_ON_POWER_DOMAINS | \
1492 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1493 #define BDW_DISPLAY_POWER_DOMAINS ( \
1494 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1495 BIT(POWER_DOMAIN_INIT))
1497 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1498 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1500 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1501 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1502 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1503 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1504 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1505 BIT(POWER_DOMAIN_PORT_CRT) | \
1506 BIT(POWER_DOMAIN_AUX_B) | \
1507 BIT(POWER_DOMAIN_AUX_C) | \
1508 BIT(POWER_DOMAIN_INIT))
1510 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1511 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1512 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1513 BIT(POWER_DOMAIN_AUX_B) | \
1514 BIT(POWER_DOMAIN_INIT))
1516 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1517 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1518 BIT(POWER_DOMAIN_AUX_B) | \
1519 BIT(POWER_DOMAIN_INIT))
1521 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1522 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1523 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1524 BIT(POWER_DOMAIN_AUX_C) | \
1525 BIT(POWER_DOMAIN_INIT))
1527 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1528 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1529 BIT(POWER_DOMAIN_AUX_C) | \
1530 BIT(POWER_DOMAIN_INIT))
1532 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1533 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1534 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1535 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1536 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1537 BIT(POWER_DOMAIN_AUX_B) | \
1538 BIT(POWER_DOMAIN_AUX_C) | \
1539 BIT(POWER_DOMAIN_INIT))
1541 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1542 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1543 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1544 BIT(POWER_DOMAIN_AUX_D) | \
1545 BIT(POWER_DOMAIN_INIT))
1547 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
1548 .sync_hw
= i9xx_always_on_power_well_noop
,
1549 .enable
= i9xx_always_on_power_well_noop
,
1550 .disable
= i9xx_always_on_power_well_noop
,
1551 .is_enabled
= i9xx_always_on_power_well_enabled
,
1554 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
1555 .sync_hw
= chv_pipe_power_well_sync_hw
,
1556 .enable
= chv_pipe_power_well_enable
,
1557 .disable
= chv_pipe_power_well_disable
,
1558 .is_enabled
= chv_pipe_power_well_enabled
,
1561 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
1562 .sync_hw
= vlv_power_well_sync_hw
,
1563 .enable
= chv_dpio_cmn_power_well_enable
,
1564 .disable
= chv_dpio_cmn_power_well_disable
,
1565 .is_enabled
= vlv_power_well_enabled
,
1568 static struct i915_power_well i9xx_always_on_power_well
[] = {
1570 .name
= "always-on",
1572 .domains
= POWER_DOMAIN_MASK
,
1573 .ops
= &i9xx_always_on_power_well_ops
,
1577 static const struct i915_power_well_ops hsw_power_well_ops
= {
1578 .sync_hw
= hsw_power_well_sync_hw
,
1579 .enable
= hsw_power_well_enable
,
1580 .disable
= hsw_power_well_disable
,
1581 .is_enabled
= hsw_power_well_enabled
,
1584 static const struct i915_power_well_ops skl_power_well_ops
= {
1585 .sync_hw
= skl_power_well_sync_hw
,
1586 .enable
= skl_power_well_enable
,
1587 .disable
= skl_power_well_disable
,
1588 .is_enabled
= skl_power_well_enabled
,
1591 static struct i915_power_well hsw_power_wells
[] = {
1593 .name
= "always-on",
1595 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
1596 .ops
= &i9xx_always_on_power_well_ops
,
1600 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
1601 .ops
= &hsw_power_well_ops
,
1605 static struct i915_power_well bdw_power_wells
[] = {
1607 .name
= "always-on",
1609 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
1610 .ops
= &i9xx_always_on_power_well_ops
,
1614 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
1615 .ops
= &hsw_power_well_ops
,
1619 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
1620 .sync_hw
= vlv_power_well_sync_hw
,
1621 .enable
= vlv_display_power_well_enable
,
1622 .disable
= vlv_display_power_well_disable
,
1623 .is_enabled
= vlv_power_well_enabled
,
1626 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
1627 .sync_hw
= vlv_power_well_sync_hw
,
1628 .enable
= vlv_dpio_cmn_power_well_enable
,
1629 .disable
= vlv_dpio_cmn_power_well_disable
,
1630 .is_enabled
= vlv_power_well_enabled
,
1633 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
1634 .sync_hw
= vlv_power_well_sync_hw
,
1635 .enable
= vlv_power_well_enable
,
1636 .disable
= vlv_power_well_disable
,
1637 .is_enabled
= vlv_power_well_enabled
,
1640 static struct i915_power_well vlv_power_wells
[] = {
1642 .name
= "always-on",
1644 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
1645 .ops
= &i9xx_always_on_power_well_ops
,
1649 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
1650 .data
= PUNIT_POWER_WELL_DISP2D
,
1651 .ops
= &vlv_display_power_well_ops
,
1654 .name
= "dpio-tx-b-01",
1655 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1656 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1657 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1658 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1659 .ops
= &vlv_dpio_power_well_ops
,
1660 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
1663 .name
= "dpio-tx-b-23",
1664 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1665 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1666 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1667 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1668 .ops
= &vlv_dpio_power_well_ops
,
1669 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
1672 .name
= "dpio-tx-c-01",
1673 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1674 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1675 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1676 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1677 .ops
= &vlv_dpio_power_well_ops
,
1678 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
1681 .name
= "dpio-tx-c-23",
1682 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1683 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1684 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1685 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1686 .ops
= &vlv_dpio_power_well_ops
,
1687 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
1690 .name
= "dpio-common",
1691 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
1692 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
1693 .ops
= &vlv_dpio_cmn_power_well_ops
,
1697 static struct i915_power_well chv_power_wells
[] = {
1699 .name
= "always-on",
1701 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
1702 .ops
= &i9xx_always_on_power_well_ops
,
1707 * Pipe A power well is the new disp2d well. Pipe B and C
1708 * power wells don't actually exist. Pipe A power well is
1709 * required for any pipe to work.
1711 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
1713 .ops
= &chv_pipe_power_well_ops
,
1716 .name
= "dpio-common-bc",
1717 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
,
1718 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
1719 .ops
= &chv_dpio_cmn_power_well_ops
,
1722 .name
= "dpio-common-d",
1723 .domains
= CHV_DPIO_CMN_D_POWER_DOMAINS
,
1724 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
1725 .ops
= &chv_dpio_cmn_power_well_ops
,
1729 bool intel_display_power_well_is_enabled(struct drm_i915_private
*dev_priv
,
1732 struct i915_power_well
*power_well
;
1735 power_well
= lookup_power_well(dev_priv
, power_well_id
);
1736 ret
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
1741 static struct i915_power_well skl_power_wells
[] = {
1743 .name
= "always-on",
1745 .domains
= SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
,
1746 .ops
= &i9xx_always_on_power_well_ops
,
1749 .name
= "power well 1",
1750 .domains
= SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS
,
1751 .ops
= &skl_power_well_ops
,
1752 .data
= SKL_DISP_PW_1
,
1755 .name
= "MISC IO power well",
1756 .domains
= SKL_DISPLAY_MISC_IO_POWER_DOMAINS
,
1757 .ops
= &skl_power_well_ops
,
1758 .data
= SKL_DISP_PW_MISC_IO
,
1761 .name
= "power well 2",
1762 .domains
= SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS
,
1763 .ops
= &skl_power_well_ops
,
1764 .data
= SKL_DISP_PW_2
,
1767 .name
= "DDI A/E power well",
1768 .domains
= SKL_DISPLAY_DDI_A_E_POWER_DOMAINS
,
1769 .ops
= &skl_power_well_ops
,
1770 .data
= SKL_DISP_PW_DDI_A_E
,
1773 .name
= "DDI B power well",
1774 .domains
= SKL_DISPLAY_DDI_B_POWER_DOMAINS
,
1775 .ops
= &skl_power_well_ops
,
1776 .data
= SKL_DISP_PW_DDI_B
,
1779 .name
= "DDI C power well",
1780 .domains
= SKL_DISPLAY_DDI_C_POWER_DOMAINS
,
1781 .ops
= &skl_power_well_ops
,
1782 .data
= SKL_DISP_PW_DDI_C
,
1785 .name
= "DDI D power well",
1786 .domains
= SKL_DISPLAY_DDI_D_POWER_DOMAINS
,
1787 .ops
= &skl_power_well_ops
,
1788 .data
= SKL_DISP_PW_DDI_D
,
1792 static struct i915_power_well bxt_power_wells
[] = {
1794 .name
= "always-on",
1796 .domains
= BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS
,
1797 .ops
= &i9xx_always_on_power_well_ops
,
1800 .name
= "power well 1",
1801 .domains
= BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
,
1802 .ops
= &skl_power_well_ops
,
1803 .data
= SKL_DISP_PW_1
,
1806 .name
= "power well 2",
1807 .domains
= BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS
,
1808 .ops
= &skl_power_well_ops
,
1809 .data
= SKL_DISP_PW_2
,
1813 #define set_power_wells(power_domains, __power_wells) ({ \
1814 (power_domains)->power_wells = (__power_wells); \
1815 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1819 * intel_power_domains_init - initializes the power domain structures
1820 * @dev_priv: i915 device instance
1822 * Initializes the power domain structures for @dev_priv depending upon the
1823 * supported platform.
1825 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
1827 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1829 mutex_init(&power_domains
->lock
);
1832 * The enabling order will be from lower to higher indexed wells,
1833 * the disabling order is reversed.
1835 if (IS_HASWELL(dev_priv
->dev
)) {
1836 set_power_wells(power_domains
, hsw_power_wells
);
1837 } else if (IS_BROADWELL(dev_priv
->dev
)) {
1838 set_power_wells(power_domains
, bdw_power_wells
);
1839 } else if (IS_SKYLAKE(dev_priv
->dev
)) {
1840 set_power_wells(power_domains
, skl_power_wells
);
1841 } else if (IS_BROXTON(dev_priv
->dev
)) {
1842 set_power_wells(power_domains
, bxt_power_wells
);
1843 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1844 set_power_wells(power_domains
, chv_power_wells
);
1845 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
1846 set_power_wells(power_domains
, vlv_power_wells
);
1848 set_power_wells(power_domains
, i9xx_always_on_power_well
);
1854 static void intel_runtime_pm_disable(struct drm_i915_private
*dev_priv
)
1856 struct drm_device
*dev
= dev_priv
->dev
;
1857 struct device
*device
= &dev
->pdev
->dev
;
1859 if (!HAS_RUNTIME_PM(dev
))
1862 if (!intel_enable_rc6(dev
))
1865 /* Make sure we're not suspended first. */
1866 pm_runtime_get_sync(device
);
1870 * intel_power_domains_fini - finalizes the power domain structures
1871 * @dev_priv: i915 device instance
1873 * Finalizes the power domain structures for @dev_priv depending upon the
1874 * supported platform. This function also disables runtime pm and ensures that
1875 * the device stays powered up so that the driver can be reloaded.
1877 void intel_power_domains_fini(struct drm_i915_private
*dev_priv
)
1879 intel_runtime_pm_disable(dev_priv
);
1881 /* The i915.ko module is still not prepared to be loaded when
1882 * the power well is not enabled, so just enable it in case
1883 * we're going to unload/reload. */
1884 intel_display_set_init_power(dev_priv
, true);
1887 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
1889 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1890 struct i915_power_well
*power_well
;
1893 mutex_lock(&power_domains
->lock
);
1894 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
1895 power_well
->ops
->sync_hw(dev_priv
, power_well
);
1896 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
1899 mutex_unlock(&power_domains
->lock
);
1902 static void chv_phy_control_init(struct drm_i915_private
*dev_priv
)
1904 struct i915_power_well
*cmn_bc
=
1905 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
1906 struct i915_power_well
*cmn_d
=
1907 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_D
);
1910 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1911 * workaround never ever read DISPLAY_PHY_CONTROL, and
1912 * instead maintain a shadow copy ourselves. Use the actual
1913 * power well state and lane status to reconstruct the
1914 * expected initial value.
1916 dev_priv
->chv_phy_control
=
1917 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS
, DPIO_PHY0
) |
1918 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS
, DPIO_PHY1
) |
1919 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY0
, DPIO_CH0
) |
1920 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY0
, DPIO_CH1
) |
1921 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY1
, DPIO_CH0
);
1924 * If all lanes are disabled we leave the override disabled
1925 * with all power down bits cleared to match the state we
1926 * would use after disabling the port. Otherwise enable the
1927 * override and set the lane powerdown bits accding to the
1928 * current lane status.
1930 if (cmn_bc
->ops
->is_enabled(dev_priv
, cmn_bc
)) {
1931 uint32_t status
= I915_READ(DPLL(PIPE_A
));
1934 mask
= status
& DPLL_PORTB_READY_MASK
;
1938 dev_priv
->chv_phy_control
|=
1939 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH0
);
1941 dev_priv
->chv_phy_control
|=
1942 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY0
, DPIO_CH0
);
1944 mask
= (status
& DPLL_PORTC_READY_MASK
) >> 4;
1948 dev_priv
->chv_phy_control
|=
1949 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH1
);
1951 dev_priv
->chv_phy_control
|=
1952 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY0
, DPIO_CH1
);
1954 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0
);
1956 dev_priv
->chv_phy_assert
[DPIO_PHY0
] = false;
1958 dev_priv
->chv_phy_assert
[DPIO_PHY0
] = true;
1961 if (cmn_d
->ops
->is_enabled(dev_priv
, cmn_d
)) {
1962 uint32_t status
= I915_READ(DPIO_PHY_STATUS
);
1965 mask
= status
& DPLL_PORTD_READY_MASK
;
1970 dev_priv
->chv_phy_control
|=
1971 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1
, DPIO_CH0
);
1973 dev_priv
->chv_phy_control
|=
1974 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY1
, DPIO_CH0
);
1976 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1
);
1978 dev_priv
->chv_phy_assert
[DPIO_PHY1
] = false;
1980 dev_priv
->chv_phy_assert
[DPIO_PHY1
] = true;
1983 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1985 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
1986 dev_priv
->chv_phy_control
);
1989 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
1991 struct i915_power_well
*cmn
=
1992 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
1993 struct i915_power_well
*disp2d
=
1994 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
1996 /* If the display might be already active skip this */
1997 if (cmn
->ops
->is_enabled(dev_priv
, cmn
) &&
1998 disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
1999 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
2002 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2004 /* cmnlane needs DPLL registers */
2005 disp2d
->ops
->enable(dev_priv
, disp2d
);
2008 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2009 * Need to assert and de-assert PHY SB reset by gating the
2010 * common lane power, then un-gating it.
2011 * Simply ungating isn't enough to reset the PHY enough to get
2012 * ports and lanes running.
2014 cmn
->ops
->disable(dev_priv
, cmn
);
2018 * intel_power_domains_init_hw - initialize hardware power domain state
2019 * @dev_priv: i915 device instance
2021 * This function initializes the hardware power domain state and enables all
2022 * power domains using intel_display_set_init_power().
2024 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
2026 struct drm_device
*dev
= dev_priv
->dev
;
2027 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2029 power_domains
->initializing
= true;
2031 if (IS_CHERRYVIEW(dev
)) {
2032 mutex_lock(&power_domains
->lock
);
2033 chv_phy_control_init(dev_priv
);
2034 mutex_unlock(&power_domains
->lock
);
2035 } else if (IS_VALLEYVIEW(dev
)) {
2036 mutex_lock(&power_domains
->lock
);
2037 vlv_cmnlane_wa(dev_priv
);
2038 mutex_unlock(&power_domains
->lock
);
2041 /* For now, we need the power well to be always enabled. */
2042 intel_display_set_init_power(dev_priv
, true);
2043 intel_power_domains_resume(dev_priv
);
2044 power_domains
->initializing
= false;
2048 * intel_aux_display_runtime_get - grab an auxiliary power domain reference
2049 * @dev_priv: i915 device instance
2051 * This function grabs a power domain reference for the auxiliary power domain
2052 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2053 * parents are powered up. Therefore users should only grab a reference to the
2054 * innermost power domain they need.
2056 * Any power domain reference obtained by this function must have a symmetric
2057 * call to intel_aux_display_runtime_put() to release the reference again.
2059 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
2061 intel_runtime_pm_get(dev_priv
);
2065 * intel_aux_display_runtime_put - release an auxiliary power domain reference
2066 * @dev_priv: i915 device instance
2068 * This function drops the auxiliary power domain reference obtained by
2069 * intel_aux_display_runtime_get() and might power down the corresponding
2070 * hardware block right away if this is the last reference.
2072 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
2074 intel_runtime_pm_put(dev_priv
);
2078 * intel_runtime_pm_get - grab a runtime pm reference
2079 * @dev_priv: i915 device instance
2081 * This function grabs a device-level runtime pm reference (mostly used for GEM
2082 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2084 * Any runtime pm reference obtained by this function must have a symmetric
2085 * call to intel_runtime_pm_put() to release the reference again.
2087 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
2089 struct drm_device
*dev
= dev_priv
->dev
;
2090 struct device
*device
= &dev
->pdev
->dev
;
2092 if (!HAS_RUNTIME_PM(dev
))
2095 pm_runtime_get_sync(device
);
2096 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
2100 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2101 * @dev_priv: i915 device instance
2103 * This function grabs a device-level runtime pm reference (mostly used for GEM
2104 * code to ensure the GTT or GT is on).
2106 * It will _not_ power up the device but instead only check that it's powered
2107 * on. Therefore it is only valid to call this functions from contexts where
2108 * the device is known to be powered up and where trying to power it up would
2109 * result in hilarity and deadlocks. That pretty much means only the system
2110 * suspend/resume code where this is used to grab runtime pm references for
2111 * delayed setup down in work items.
2113 * Any runtime pm reference obtained by this function must have a symmetric
2114 * call to intel_runtime_pm_put() to release the reference again.
2116 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
2118 struct drm_device
*dev
= dev_priv
->dev
;
2119 struct device
*device
= &dev
->pdev
->dev
;
2121 if (!HAS_RUNTIME_PM(dev
))
2124 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
2125 pm_runtime_get_noresume(device
);
2129 * intel_runtime_pm_put - release a runtime pm reference
2130 * @dev_priv: i915 device instance
2132 * This function drops the device-level runtime pm reference obtained by
2133 * intel_runtime_pm_get() and might power down the corresponding
2134 * hardware block right away if this is the last reference.
2136 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
2138 struct drm_device
*dev
= dev_priv
->dev
;
2139 struct device
*device
= &dev
->pdev
->dev
;
2141 if (!HAS_RUNTIME_PM(dev
))
2144 pm_runtime_mark_last_busy(device
);
2145 pm_runtime_put_autosuspend(device
);
2149 * intel_runtime_pm_enable - enable runtime pm
2150 * @dev_priv: i915 device instance
2152 * This function enables runtime pm at the end of the driver load sequence.
2154 * Note that this function does currently not enable runtime pm for the
2155 * subordinate display power domains. That is only done on the first modeset
2156 * using intel_display_set_init_power().
2158 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
)
2160 struct drm_device
*dev
= dev_priv
->dev
;
2161 struct device
*device
= &dev
->pdev
->dev
;
2163 if (!HAS_RUNTIME_PM(dev
))
2167 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2170 if (!intel_enable_rc6(dev
)) {
2171 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2175 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
2176 pm_runtime_mark_last_busy(device
);
2177 pm_runtime_use_autosuspend(device
);
2179 pm_runtime_put_autosuspend(device
);