2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
33 #include "intel_drv.h"
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
57 for_each_if ((power_well)->domains & (domain_mask))
59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
63 for_each_if ((power_well)->domains & (domain_mask))
65 bool intel_display_power_well_is_enabled(struct drm_i915_private
*dev_priv
,
69 intel_display_power_domain_str(enum intel_display_power_domain domain
)
72 case POWER_DOMAIN_PIPE_A
:
74 case POWER_DOMAIN_PIPE_B
:
76 case POWER_DOMAIN_PIPE_C
:
78 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
79 return "PIPE_A_PANEL_FITTER";
80 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
81 return "PIPE_B_PANEL_FITTER";
82 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
83 return "PIPE_C_PANEL_FITTER";
84 case POWER_DOMAIN_TRANSCODER_A
:
85 return "TRANSCODER_A";
86 case POWER_DOMAIN_TRANSCODER_B
:
87 return "TRANSCODER_B";
88 case POWER_DOMAIN_TRANSCODER_C
:
89 return "TRANSCODER_C";
90 case POWER_DOMAIN_TRANSCODER_EDP
:
91 return "TRANSCODER_EDP";
92 case POWER_DOMAIN_TRANSCODER_DSI_A
:
93 return "TRANSCODER_DSI_A";
94 case POWER_DOMAIN_TRANSCODER_DSI_C
:
95 return "TRANSCODER_DSI_C";
96 case POWER_DOMAIN_PORT_DDI_A_LANES
:
97 return "PORT_DDI_A_LANES";
98 case POWER_DOMAIN_PORT_DDI_B_LANES
:
99 return "PORT_DDI_B_LANES";
100 case POWER_DOMAIN_PORT_DDI_C_LANES
:
101 return "PORT_DDI_C_LANES";
102 case POWER_DOMAIN_PORT_DDI_D_LANES
:
103 return "PORT_DDI_D_LANES";
104 case POWER_DOMAIN_PORT_DDI_E_LANES
:
105 return "PORT_DDI_E_LANES";
106 case POWER_DOMAIN_PORT_DSI
:
108 case POWER_DOMAIN_PORT_CRT
:
110 case POWER_DOMAIN_PORT_OTHER
:
112 case POWER_DOMAIN_VGA
:
114 case POWER_DOMAIN_AUDIO
:
116 case POWER_DOMAIN_PLLS
:
118 case POWER_DOMAIN_AUX_A
:
120 case POWER_DOMAIN_AUX_B
:
122 case POWER_DOMAIN_AUX_C
:
124 case POWER_DOMAIN_AUX_D
:
126 case POWER_DOMAIN_GMBUS
:
128 case POWER_DOMAIN_INIT
:
130 case POWER_DOMAIN_MODESET
:
133 MISSING_CASE(domain
);
138 static void intel_power_well_enable(struct drm_i915_private
*dev_priv
,
139 struct i915_power_well
*power_well
)
141 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
142 power_well
->ops
->enable(dev_priv
, power_well
);
143 power_well
->hw_enabled
= true;
146 static void intel_power_well_disable(struct drm_i915_private
*dev_priv
,
147 struct i915_power_well
*power_well
)
149 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
150 power_well
->hw_enabled
= false;
151 power_well
->ops
->disable(dev_priv
, power_well
);
155 * We should only use the power well if we explicitly asked the hardware to
156 * enable it, so check if it's enabled and also check if we've requested it to
159 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
160 struct i915_power_well
*power_well
)
162 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
163 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
167 * __intel_display_power_is_enabled - unlocked check for a power domain
168 * @dev_priv: i915 device instance
169 * @domain: power domain to check
171 * This is the unlocked version of intel_display_power_is_enabled() and should
172 * only be used from error capture and recovery code where deadlocks are
176 * True when the power domain is enabled, false otherwise.
178 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
179 enum intel_display_power_domain domain
)
181 struct i915_power_domains
*power_domains
;
182 struct i915_power_well
*power_well
;
186 if (dev_priv
->pm
.suspended
)
189 power_domains
= &dev_priv
->power_domains
;
193 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
194 if (power_well
->always_on
)
197 if (!power_well
->hw_enabled
) {
207 * intel_display_power_is_enabled - check for a power domain
208 * @dev_priv: i915 device instance
209 * @domain: power domain to check
211 * This function can be used to check the hw power domain state. It is mostly
212 * used in hardware state readout functions. Everywhere else code should rely
213 * upon explicit power domain reference counting to ensure that the hardware
214 * block is powered up before accessing it.
216 * Callers must hold the relevant modesetting locks to ensure that concurrent
217 * threads can't disable the power well while the caller tries to read a few
221 * True when the power domain is enabled, false otherwise.
223 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
224 enum intel_display_power_domain domain
)
226 struct i915_power_domains
*power_domains
;
229 power_domains
= &dev_priv
->power_domains
;
231 mutex_lock(&power_domains
->lock
);
232 ret
= __intel_display_power_is_enabled(dev_priv
, domain
);
233 mutex_unlock(&power_domains
->lock
);
239 * intel_display_set_init_power - set the initial power domain state
240 * @dev_priv: i915 device instance
241 * @enable: whether to enable or disable the initial power domain state
243 * For simplicity our driver load/unload and system suspend/resume code assumes
244 * that all power domains are always enabled. This functions controls the state
245 * of this little hack. While the initial power domain state is enabled runtime
246 * pm is effectively disabled.
248 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
251 if (dev_priv
->power_domains
.init_power_on
== enable
)
255 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
257 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
259 dev_priv
->power_domains
.init_power_on
= enable
;
263 * Starting with Haswell, we have a "Power Down Well" that can be turned off
264 * when not needed anymore. We have 4 registers that can request the power well
265 * to be enabled, and it will only be disabled if none of the registers is
266 * requesting it to be enabled.
268 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
270 struct drm_device
*dev
= dev_priv
->dev
;
273 * After we re-enable the power well, if we touch VGA register 0x3d5
274 * we'll get unclaimed register interrupts. This stops after we write
275 * anything to the VGA MSR register. The vgacon module uses this
276 * register all the time, so if we unbind our driver and, as a
277 * consequence, bind vgacon, we'll get stuck in an infinite loop at
278 * console_unlock(). So make here we touch the VGA MSR register, making
279 * sure vgacon can keep working normally without triggering interrupts
280 * and error messages.
282 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
283 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
284 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
286 if (IS_BROADWELL(dev
))
287 gen8_irq_power_well_post_enable(dev_priv
,
288 1 << PIPE_C
| 1 << PIPE_B
);
291 static void hsw_power_well_pre_disable(struct drm_i915_private
*dev_priv
)
293 if (IS_BROADWELL(dev_priv
))
294 gen8_irq_power_well_pre_disable(dev_priv
,
295 1 << PIPE_C
| 1 << PIPE_B
);
298 static void skl_power_well_post_enable(struct drm_i915_private
*dev_priv
,
299 struct i915_power_well
*power_well
)
301 struct drm_device
*dev
= dev_priv
->dev
;
304 * After we re-enable the power well, if we touch VGA register 0x3d5
305 * we'll get unclaimed register interrupts. This stops after we write
306 * anything to the VGA MSR register. The vgacon module uses this
307 * register all the time, so if we unbind our driver and, as a
308 * consequence, bind vgacon, we'll get stuck in an infinite loop at
309 * console_unlock(). So make here we touch the VGA MSR register, making
310 * sure vgacon can keep working normally without triggering interrupts
311 * and error messages.
313 if (power_well
->data
== SKL_DISP_PW_2
) {
314 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
315 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
316 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
318 gen8_irq_power_well_post_enable(dev_priv
,
319 1 << PIPE_C
| 1 << PIPE_B
);
323 static void skl_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
324 struct i915_power_well
*power_well
)
326 if (power_well
->data
== SKL_DISP_PW_2
)
327 gen8_irq_power_well_pre_disable(dev_priv
,
328 1 << PIPE_C
| 1 << PIPE_B
);
331 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
332 struct i915_power_well
*power_well
, bool enable
)
334 bool is_enabled
, enable_requested
;
337 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
338 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
339 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
342 if (!enable_requested
)
343 I915_WRITE(HSW_PWR_WELL_DRIVER
,
344 HSW_PWR_WELL_ENABLE_REQUEST
);
347 DRM_DEBUG_KMS("Enabling power well\n");
348 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
349 HSW_PWR_WELL_STATE_ENABLED
), 20))
350 DRM_ERROR("Timeout enabling power well\n");
351 hsw_power_well_post_enable(dev_priv
);
355 if (enable_requested
) {
356 hsw_power_well_pre_disable(dev_priv
);
357 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
358 POSTING_READ(HSW_PWR_WELL_DRIVER
);
359 DRM_DEBUG_KMS("Requesting to disable the power well\n");
364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
365 BIT(POWER_DOMAIN_TRANSCODER_A) | \
366 BIT(POWER_DOMAIN_PIPE_B) | \
367 BIT(POWER_DOMAIN_TRANSCODER_B) | \
368 BIT(POWER_DOMAIN_PIPE_C) | \
369 BIT(POWER_DOMAIN_TRANSCODER_C) | \
370 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
371 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
372 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
373 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
374 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
375 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
376 BIT(POWER_DOMAIN_AUX_B) | \
377 BIT(POWER_DOMAIN_AUX_C) | \
378 BIT(POWER_DOMAIN_AUX_D) | \
379 BIT(POWER_DOMAIN_AUDIO) | \
380 BIT(POWER_DOMAIN_VGA) | \
381 BIT(POWER_DOMAIN_INIT))
382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
383 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
384 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
385 BIT(POWER_DOMAIN_INIT))
386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
387 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
388 BIT(POWER_DOMAIN_INIT))
389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
390 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
391 BIT(POWER_DOMAIN_INIT))
392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
393 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
394 BIT(POWER_DOMAIN_INIT))
395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
396 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
397 BIT(POWER_DOMAIN_MODESET) | \
398 BIT(POWER_DOMAIN_AUX_A) | \
399 BIT(POWER_DOMAIN_INIT))
400 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
401 (POWER_DOMAIN_MASK & ~( \
402 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
403 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
404 BIT(POWER_DOMAIN_INIT))
406 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
407 BIT(POWER_DOMAIN_TRANSCODER_A) | \
408 BIT(POWER_DOMAIN_PIPE_B) | \
409 BIT(POWER_DOMAIN_TRANSCODER_B) | \
410 BIT(POWER_DOMAIN_PIPE_C) | \
411 BIT(POWER_DOMAIN_TRANSCODER_C) | \
412 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
413 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
414 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
415 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
416 BIT(POWER_DOMAIN_AUX_B) | \
417 BIT(POWER_DOMAIN_AUX_C) | \
418 BIT(POWER_DOMAIN_AUDIO) | \
419 BIT(POWER_DOMAIN_VGA) | \
420 BIT(POWER_DOMAIN_GMBUS) | \
421 BIT(POWER_DOMAIN_INIT))
422 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
423 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
424 BIT(POWER_DOMAIN_PIPE_A) | \
425 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
426 BIT(POWER_DOMAIN_TRANSCODER_DSI_A) | \
427 BIT(POWER_DOMAIN_TRANSCODER_DSI_C) | \
428 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
429 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
430 BIT(POWER_DOMAIN_PORT_DSI) | \
431 BIT(POWER_DOMAIN_AUX_A) | \
432 BIT(POWER_DOMAIN_PLLS) | \
433 BIT(POWER_DOMAIN_INIT))
434 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
435 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
436 BIT(POWER_DOMAIN_MODESET) | \
437 BIT(POWER_DOMAIN_AUX_A) | \
438 BIT(POWER_DOMAIN_INIT))
439 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
440 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
441 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
442 BIT(POWER_DOMAIN_INIT))
444 static void assert_can_enable_dc9(struct drm_i915_private
*dev_priv
)
446 struct drm_device
*dev
= dev_priv
->dev
;
448 WARN(!IS_BROXTON(dev
), "Platform doesn't support DC9.\n");
449 WARN((I915_READ(DC_STATE_EN
) & DC_STATE_EN_DC9
),
450 "DC9 already programmed to be enabled.\n");
451 WARN(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
,
452 "DC5 still not disabled to enable DC9.\n");
453 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on.\n");
454 WARN(intel_irqs_enabled(dev_priv
), "Interrupts not disabled yet.\n");
457 * TODO: check for the following to verify the conditions to enter DC9
458 * state are satisfied:
459 * 1] Check relevant display engine registers to verify if mode set
460 * disable sequence was followed.
461 * 2] Check if display uninitialize sequence is initialized.
465 static void assert_can_disable_dc9(struct drm_i915_private
*dev_priv
)
467 WARN(intel_irqs_enabled(dev_priv
), "Interrupts not disabled yet.\n");
468 WARN(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
,
469 "DC5 still not disabled.\n");
472 * TODO: check for the following to verify DC9 state was indeed
473 * entered before programming to disable it:
474 * 1] Check relevant display engine registers to verify if mode
475 * set disable sequence was followed.
476 * 2] Check if display uninitialize sequence is initialized.
480 static void gen9_write_dc_state(struct drm_i915_private
*dev_priv
,
487 I915_WRITE(DC_STATE_EN
, state
);
489 /* It has been observed that disabling the dc6 state sometimes
490 * doesn't stick and dmc keeps returning old value. Make sure
491 * the write really sticks enough times and also force rewrite until
492 * we are confident that state is exactly what we want.
495 v
= I915_READ(DC_STATE_EN
);
498 I915_WRITE(DC_STATE_EN
, state
);
501 } else if (rereads
++ > 5) {
505 } while (rewrites
< 100);
508 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
511 /* Most of the times we need one retry, avoid spam */
513 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
517 static void gen9_set_dc_state(struct drm_i915_private
*dev_priv
, uint32_t state
)
522 mask
= DC_STATE_EN_UPTO_DC5
;
523 if (IS_BROXTON(dev_priv
))
524 mask
|= DC_STATE_EN_DC9
;
526 mask
|= DC_STATE_EN_UPTO_DC6
;
528 if (WARN_ON_ONCE(state
& ~dev_priv
->csr
.allowed_dc_mask
))
529 state
&= dev_priv
->csr
.allowed_dc_mask
;
531 val
= I915_READ(DC_STATE_EN
);
532 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
535 /* Check if DMC is ignoring our DC state requests */
536 if ((val
& mask
) != dev_priv
->csr
.dc_state
)
537 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
538 dev_priv
->csr
.dc_state
, val
& mask
);
543 gen9_write_dc_state(dev_priv
, val
);
545 dev_priv
->csr
.dc_state
= val
& mask
;
548 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
)
550 assert_can_enable_dc9(dev_priv
);
552 DRM_DEBUG_KMS("Enabling DC9\n");
554 gen9_set_dc_state(dev_priv
, DC_STATE_EN_DC9
);
557 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
)
559 assert_can_disable_dc9(dev_priv
);
561 DRM_DEBUG_KMS("Disabling DC9\n");
563 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
566 static void assert_csr_loaded(struct drm_i915_private
*dev_priv
)
568 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
569 "CSR program storage start is NULL\n");
570 WARN_ONCE(!I915_READ(CSR_SSP_BASE
), "CSR SSP Base Not fine\n");
571 WARN_ONCE(!I915_READ(CSR_HTP_SKL
), "CSR HTP Not fine\n");
574 static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv
)
576 struct drm_device
*dev
= dev_priv
->dev
;
577 bool pg2_enabled
= intel_display_power_well_is_enabled(dev_priv
,
580 WARN_ONCE(!IS_SKYLAKE(dev
) && !IS_KABYLAKE(dev
),
581 "Platform doesn't support DC5.\n");
582 WARN_ONCE(!HAS_RUNTIME_PM(dev
), "Runtime PM not enabled.\n");
583 WARN_ONCE(pg2_enabled
, "PG2 not disabled to enable DC5.\n");
585 WARN_ONCE((I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
),
586 "DC5 already programmed to be enabled.\n");
587 assert_rpm_wakelock_held(dev_priv
);
589 assert_csr_loaded(dev_priv
);
592 static void gen9_enable_dc5(struct drm_i915_private
*dev_priv
)
594 assert_can_enable_dc5(dev_priv
);
596 DRM_DEBUG_KMS("Enabling DC5\n");
598 gen9_set_dc_state(dev_priv
, DC_STATE_EN_UPTO_DC5
);
601 static void assert_can_enable_dc6(struct drm_i915_private
*dev_priv
)
603 struct drm_device
*dev
= dev_priv
->dev
;
605 WARN_ONCE(!IS_SKYLAKE(dev
) && !IS_KABYLAKE(dev
),
606 "Platform doesn't support DC6.\n");
607 WARN_ONCE(!HAS_RUNTIME_PM(dev
), "Runtime PM not enabled.\n");
608 WARN_ONCE(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
609 "Backlight is not disabled.\n");
610 WARN_ONCE((I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC6
),
611 "DC6 already programmed to be enabled.\n");
613 assert_csr_loaded(dev_priv
);
616 void skl_enable_dc6(struct drm_i915_private
*dev_priv
)
618 assert_can_enable_dc6(dev_priv
);
620 DRM_DEBUG_KMS("Enabling DC6\n");
622 gen9_set_dc_state(dev_priv
, DC_STATE_EN_UPTO_DC6
);
626 void skl_disable_dc6(struct drm_i915_private
*dev_priv
)
628 DRM_DEBUG_KMS("Disabling DC6\n");
630 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
633 static void skl_set_power_well(struct drm_i915_private
*dev_priv
,
634 struct i915_power_well
*power_well
, bool enable
)
636 uint32_t tmp
, fuse_status
;
637 uint32_t req_mask
, state_mask
;
638 bool is_enabled
, enable_requested
, check_fuse_status
= false;
640 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
641 fuse_status
= I915_READ(SKL_FUSE_STATUS
);
643 switch (power_well
->data
) {
645 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
646 SKL_FUSE_PG0_DIST_STATUS
), 1)) {
647 DRM_ERROR("PG0 not enabled\n");
652 if (!(fuse_status
& SKL_FUSE_PG1_DIST_STATUS
)) {
653 DRM_ERROR("PG1 in disabled state\n");
657 case SKL_DISP_PW_DDI_A_E
:
658 case SKL_DISP_PW_DDI_B
:
659 case SKL_DISP_PW_DDI_C
:
660 case SKL_DISP_PW_DDI_D
:
661 case SKL_DISP_PW_MISC_IO
:
664 WARN(1, "Unknown power well %lu\n", power_well
->data
);
668 req_mask
= SKL_POWER_WELL_REQ(power_well
->data
);
669 enable_requested
= tmp
& req_mask
;
670 state_mask
= SKL_POWER_WELL_STATE(power_well
->data
);
671 is_enabled
= tmp
& state_mask
;
673 if (!enable
&& enable_requested
)
674 skl_power_well_pre_disable(dev_priv
, power_well
);
677 if (!enable_requested
) {
678 WARN((tmp
& state_mask
) &&
679 !I915_READ(HSW_PWR_WELL_BIOS
),
680 "Invalid for power well status to be enabled, unless done by the BIOS, \
681 when request is to disable!\n");
682 I915_WRITE(HSW_PWR_WELL_DRIVER
, tmp
| req_mask
);
686 DRM_DEBUG_KMS("Enabling %s\n", power_well
->name
);
687 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
689 DRM_ERROR("%s enable timeout\n",
691 check_fuse_status
= true;
694 if (enable_requested
) {
695 I915_WRITE(HSW_PWR_WELL_DRIVER
, tmp
& ~req_mask
);
696 POSTING_READ(HSW_PWR_WELL_DRIVER
);
697 DRM_DEBUG_KMS("Disabling %s\n", power_well
->name
);
701 if (check_fuse_status
) {
702 if (power_well
->data
== SKL_DISP_PW_1
) {
703 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
704 SKL_FUSE_PG1_DIST_STATUS
), 1))
705 DRM_ERROR("PG1 distributing status timeout\n");
706 } else if (power_well
->data
== SKL_DISP_PW_2
) {
707 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
708 SKL_FUSE_PG2_DIST_STATUS
), 1))
709 DRM_ERROR("PG2 distributing status timeout\n");
713 if (enable
&& !is_enabled
)
714 skl_power_well_post_enable(dev_priv
, power_well
);
717 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
718 struct i915_power_well
*power_well
)
720 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
723 * We're taking over the BIOS, so clear any requests made by it since
724 * the driver is in charge now.
726 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
727 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
730 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
731 struct i915_power_well
*power_well
)
733 hsw_set_power_well(dev_priv
, power_well
, true);
736 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
737 struct i915_power_well
*power_well
)
739 hsw_set_power_well(dev_priv
, power_well
, false);
742 static bool skl_power_well_enabled(struct drm_i915_private
*dev_priv
,
743 struct i915_power_well
*power_well
)
745 uint32_t mask
= SKL_POWER_WELL_REQ(power_well
->data
) |
746 SKL_POWER_WELL_STATE(power_well
->data
);
748 return (I915_READ(HSW_PWR_WELL_DRIVER
) & mask
) == mask
;
751 static void skl_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
752 struct i915_power_well
*power_well
)
754 skl_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
756 /* Clear any request made by BIOS as driver is taking over */
757 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
760 static void skl_power_well_enable(struct drm_i915_private
*dev_priv
,
761 struct i915_power_well
*power_well
)
763 skl_set_power_well(dev_priv
, power_well
, true);
766 static void skl_power_well_disable(struct drm_i915_private
*dev_priv
,
767 struct i915_power_well
*power_well
)
769 skl_set_power_well(dev_priv
, power_well
, false);
772 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
*dev_priv
,
773 struct i915_power_well
*power_well
)
775 return (I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5_DC6_MASK
) == 0;
778 static void gen9_dc_off_power_well_enable(struct drm_i915_private
*dev_priv
,
779 struct i915_power_well
*power_well
)
781 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
784 static void gen9_dc_off_power_well_disable(struct drm_i915_private
*dev_priv
,
785 struct i915_power_well
*power_well
)
787 if (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC6
)
788 skl_enable_dc6(dev_priv
);
789 else if (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
)
790 gen9_enable_dc5(dev_priv
);
793 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
794 struct i915_power_well
*power_well
)
796 if (power_well
->count
> 0)
797 gen9_dc_off_power_well_enable(dev_priv
, power_well
);
799 gen9_dc_off_power_well_disable(dev_priv
, power_well
);
802 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
803 struct i915_power_well
*power_well
)
807 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
808 struct i915_power_well
*power_well
)
813 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
814 struct i915_power_well
*power_well
, bool enable
)
816 enum punit_power_well power_well_id
= power_well
->data
;
821 mask
= PUNIT_PWRGT_MASK(power_well_id
);
822 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
823 PUNIT_PWRGT_PWR_GATE(power_well_id
);
825 mutex_lock(&dev_priv
->rps
.hw_lock
);
828 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
833 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
836 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
838 if (wait_for(COND
, 100))
839 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
841 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
846 mutex_unlock(&dev_priv
->rps
.hw_lock
);
849 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
850 struct i915_power_well
*power_well
)
852 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
855 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
856 struct i915_power_well
*power_well
)
858 vlv_set_power_well(dev_priv
, power_well
, true);
861 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
862 struct i915_power_well
*power_well
)
864 vlv_set_power_well(dev_priv
, power_well
, false);
867 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
868 struct i915_power_well
*power_well
)
870 int power_well_id
= power_well
->data
;
871 bool enabled
= false;
876 mask
= PUNIT_PWRGT_MASK(power_well_id
);
877 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
879 mutex_lock(&dev_priv
->rps
.hw_lock
);
881 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
883 * We only ever set the power-on and power-gate states, anything
884 * else is unexpected.
886 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
887 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
892 * A transient state at this point would mean some unexpected party
893 * is poking at the power controls too.
895 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
896 WARN_ON(ctrl
!= state
);
898 mutex_unlock(&dev_priv
->rps
.hw_lock
);
903 static void vlv_display_power_well_init(struct drm_i915_private
*dev_priv
)
908 * Enable the CRI clock source so we can get at the
909 * display and the reference clock for VGA
910 * hotplug / manual detection. Supposedly DSI also
911 * needs the ref clock up and running.
913 * CHV DPLL B/C have some issues if VGA mode is enabled.
915 for_each_pipe(dev_priv
->dev
, pipe
) {
916 u32 val
= I915_READ(DPLL(pipe
));
918 val
|= DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
920 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
922 I915_WRITE(DPLL(pipe
), val
);
925 spin_lock_irq(&dev_priv
->irq_lock
);
926 valleyview_enable_display_irqs(dev_priv
);
927 spin_unlock_irq(&dev_priv
->irq_lock
);
930 * During driver initialization/resume we can avoid restoring the
931 * part of the HW/SW state that will be inited anyway explicitly.
933 if (dev_priv
->power_domains
.initializing
)
936 intel_hpd_init(dev_priv
);
938 i915_redisable_vga_power_on(dev_priv
->dev
);
941 static void vlv_display_power_well_deinit(struct drm_i915_private
*dev_priv
)
943 spin_lock_irq(&dev_priv
->irq_lock
);
944 valleyview_disable_display_irqs(dev_priv
);
945 spin_unlock_irq(&dev_priv
->irq_lock
);
947 /* make sure we're done processing display irqs */
948 synchronize_irq(dev_priv
->dev
->irq
);
950 vlv_power_sequencer_reset(dev_priv
);
953 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
954 struct i915_power_well
*power_well
)
956 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
958 vlv_set_power_well(dev_priv
, power_well
, true);
960 vlv_display_power_well_init(dev_priv
);
963 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
964 struct i915_power_well
*power_well
)
966 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
968 vlv_display_power_well_deinit(dev_priv
);
970 vlv_set_power_well(dev_priv
, power_well
, false);
973 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
974 struct i915_power_well
*power_well
)
976 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
978 /* since ref/cri clock was enabled */
979 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
981 vlv_set_power_well(dev_priv
, power_well
, true);
984 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
985 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
986 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
987 * b. The other bits such as sfr settings / modesel may all
990 * This should only be done on init and resume from S3 with
991 * both PLLs disabled, or we risk losing DPIO and PLL
994 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
997 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
998 struct i915_power_well
*power_well
)
1002 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
1004 for_each_pipe(dev_priv
, pipe
)
1005 assert_pll_disabled(dev_priv
, pipe
);
1007 /* Assert common reset */
1008 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
1010 vlv_set_power_well(dev_priv
, power_well
, false);
1013 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1015 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
1018 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1021 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
1022 struct i915_power_well
*power_well
;
1024 power_well
= &power_domains
->power_wells
[i
];
1025 if (power_well
->data
== power_well_id
)
1032 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1034 static void assert_chv_phy_status(struct drm_i915_private
*dev_priv
)
1036 struct i915_power_well
*cmn_bc
=
1037 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
1038 struct i915_power_well
*cmn_d
=
1039 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_D
);
1040 u32 phy_control
= dev_priv
->chv_phy_control
;
1042 u32 phy_status_mask
= 0xffffffff;
1046 * The BIOS can leave the PHY is some weird state
1047 * where it doesn't fully power down some parts.
1048 * Disable the asserts until the PHY has been fully
1049 * reset (ie. the power well has been disabled at
1052 if (!dev_priv
->chv_phy_assert
[DPIO_PHY0
])
1053 phy_status_mask
&= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH0
) |
1054 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 0) |
1055 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 1) |
1056 PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH1
) |
1057 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 0) |
1058 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 1));
1060 if (!dev_priv
->chv_phy_assert
[DPIO_PHY1
])
1061 phy_status_mask
&= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1
, DPIO_CH0
) |
1062 PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 0) |
1063 PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 1));
1065 if (cmn_bc
->ops
->is_enabled(dev_priv
, cmn_bc
)) {
1066 phy_status
|= PHY_POWERGOOD(DPIO_PHY0
);
1068 /* this assumes override is only used to enable lanes */
1069 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH0
)) == 0)
1070 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH0
);
1072 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH1
)) == 0)
1073 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
);
1075 /* CL1 is on whenever anything is on in either channel */
1076 if (BITS_SET(phy_control
,
1077 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH0
) |
1078 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
)))
1079 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH0
);
1082 * The DPLLB check accounts for the pipe B + port A usage
1083 * with CL2 powered up but all the lanes in the second channel
1086 if (BITS_SET(phy_control
,
1087 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
)) &&
1088 (I915_READ(DPLL(PIPE_B
)) & DPLL_VCO_ENABLE
) == 0)
1089 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH1
);
1091 if (BITS_SET(phy_control
,
1092 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0
, DPIO_CH0
)))
1093 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 0);
1094 if (BITS_SET(phy_control
,
1095 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0
, DPIO_CH0
)))
1096 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 1);
1098 if (BITS_SET(phy_control
,
1099 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0
, DPIO_CH1
)))
1100 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 0);
1101 if (BITS_SET(phy_control
,
1102 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0
, DPIO_CH1
)))
1103 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 1);
1106 if (cmn_d
->ops
->is_enabled(dev_priv
, cmn_d
)) {
1107 phy_status
|= PHY_POWERGOOD(DPIO_PHY1
);
1109 /* this assumes override is only used to enable lanes */
1110 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1
, DPIO_CH0
)) == 0)
1111 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1
, DPIO_CH0
);
1113 if (BITS_SET(phy_control
,
1114 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1
, DPIO_CH0
)))
1115 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY1
, DPIO_CH0
);
1117 if (BITS_SET(phy_control
,
1118 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1
, DPIO_CH0
)))
1119 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 0);
1120 if (BITS_SET(phy_control
,
1121 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1
, DPIO_CH0
)))
1122 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 1);
1125 phy_status
&= phy_status_mask
;
1128 * The PHY may be busy with some initial calibration and whatnot,
1129 * so the power state can take a while to actually change.
1131 if (wait_for((tmp
= I915_READ(DISPLAY_PHY_STATUS
) & phy_status_mask
) == phy_status
, 10))
1132 WARN(phy_status
!= tmp
,
1133 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1134 tmp
, phy_status
, dev_priv
->chv_phy_control
);
1139 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
1140 struct i915_power_well
*power_well
)
1146 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
1147 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
1149 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1157 /* since ref/cri clock was enabled */
1158 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1159 vlv_set_power_well(dev_priv
, power_well
, true);
1161 /* Poll for phypwrgood signal */
1162 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
1163 DRM_ERROR("Display PHY %d is not power up\n", phy
);
1165 mutex_lock(&dev_priv
->sb_lock
);
1167 /* Enable dynamic power down */
1168 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW28
);
1169 tmp
|= DPIO_DYNPWRDOWNEN_CH0
| DPIO_CL1POWERDOWNEN
|
1170 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ
;
1171 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW28
, tmp
);
1173 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1174 tmp
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW6_CH1
);
1175 tmp
|= DPIO_DYNPWRDOWNEN_CH1
;
1176 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW6_CH1
, tmp
);
1179 * Force the non-existing CL2 off. BXT does this
1180 * too, so maybe it saves some power even though
1181 * CL2 doesn't exist?
1183 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
1184 tmp
|= DPIO_CL2_LDOFUSE_PWRENB
;
1185 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, tmp
);
1188 mutex_unlock(&dev_priv
->sb_lock
);
1190 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(phy
);
1191 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1193 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1194 phy
, dev_priv
->chv_phy_control
);
1196 assert_chv_phy_status(dev_priv
);
1199 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
1200 struct i915_power_well
*power_well
)
1204 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
1205 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
1207 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1209 assert_pll_disabled(dev_priv
, PIPE_A
);
1210 assert_pll_disabled(dev_priv
, PIPE_B
);
1213 assert_pll_disabled(dev_priv
, PIPE_C
);
1216 dev_priv
->chv_phy_control
&= ~PHY_COM_LANE_RESET_DEASSERT(phy
);
1217 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1219 vlv_set_power_well(dev_priv
, power_well
, false);
1221 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1222 phy
, dev_priv
->chv_phy_control
);
1224 /* PHY is fully reset now, so we can enable the PHY state asserts */
1225 dev_priv
->chv_phy_assert
[phy
] = true;
1227 assert_chv_phy_status(dev_priv
);
1230 static void assert_chv_phy_powergate(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1231 enum dpio_channel ch
, bool override
, unsigned int mask
)
1233 enum pipe pipe
= phy
== DPIO_PHY0
? PIPE_A
: PIPE_C
;
1234 u32 reg
, val
, expected
, actual
;
1237 * The BIOS can leave the PHY is some weird state
1238 * where it doesn't fully power down some parts.
1239 * Disable the asserts until the PHY has been fully
1240 * reset (ie. the power well has been disabled at
1243 if (!dev_priv
->chv_phy_assert
[phy
])
1247 reg
= _CHV_CMN_DW0_CH0
;
1249 reg
= _CHV_CMN_DW6_CH1
;
1251 mutex_lock(&dev_priv
->sb_lock
);
1252 val
= vlv_dpio_read(dev_priv
, pipe
, reg
);
1253 mutex_unlock(&dev_priv
->sb_lock
);
1256 * This assumes !override is only used when the port is disabled.
1257 * All lanes should power down even without the override when
1258 * the port is disabled.
1260 if (!override
|| mask
== 0xf) {
1261 expected
= DPIO_ALLDL_POWERDOWN
| DPIO_ANYDL_POWERDOWN
;
1263 * If CH1 common lane is not active anymore
1264 * (eg. for pipe B DPLL) the entire channel will
1265 * shut down, which causes the common lane registers
1266 * to read as 0. That means we can't actually check
1267 * the lane power down status bits, but as the entire
1268 * register reads as 0 it's a good indication that the
1269 * channel is indeed entirely powered down.
1271 if (ch
== DPIO_CH1
&& val
== 0)
1273 } else if (mask
!= 0x0) {
1274 expected
= DPIO_ANYDL_POWERDOWN
;
1280 actual
= val
>> DPIO_ANYDL_POWERDOWN_SHIFT_CH0
;
1282 actual
= val
>> DPIO_ANYDL_POWERDOWN_SHIFT_CH1
;
1283 actual
&= DPIO_ALLDL_POWERDOWN
| DPIO_ANYDL_POWERDOWN
;
1285 WARN(actual
!= expected
,
1286 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1287 !!(actual
& DPIO_ALLDL_POWERDOWN
), !!(actual
& DPIO_ANYDL_POWERDOWN
),
1288 !!(expected
& DPIO_ALLDL_POWERDOWN
), !!(expected
& DPIO_ANYDL_POWERDOWN
),
1292 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1293 enum dpio_channel ch
, bool override
)
1295 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1298 mutex_lock(&power_domains
->lock
);
1300 was_override
= dev_priv
->chv_phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1302 if (override
== was_override
)
1306 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1308 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1310 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1312 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1313 phy
, ch
, dev_priv
->chv_phy_control
);
1315 assert_chv_phy_status(dev_priv
);
1318 mutex_unlock(&power_domains
->lock
);
1320 return was_override
;
1323 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1324 bool override
, unsigned int mask
)
1326 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1327 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1328 enum dpio_phy phy
= vlv_dport_to_phy(enc_to_dig_port(&encoder
->base
));
1329 enum dpio_channel ch
= vlv_dport_to_channel(enc_to_dig_port(&encoder
->base
));
1331 mutex_lock(&power_domains
->lock
);
1333 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy
, ch
);
1334 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD(mask
, phy
, ch
);
1337 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1339 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1341 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1343 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1344 phy
, ch
, mask
, dev_priv
->chv_phy_control
);
1346 assert_chv_phy_status(dev_priv
);
1348 assert_chv_phy_powergate(dev_priv
, phy
, ch
, override
, mask
);
1350 mutex_unlock(&power_domains
->lock
);
1353 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
1354 struct i915_power_well
*power_well
)
1356 enum pipe pipe
= power_well
->data
;
1360 mutex_lock(&dev_priv
->rps
.hw_lock
);
1362 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
1364 * We only ever set the power-on and power-gate states, anything
1365 * else is unexpected.
1367 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
1368 enabled
= state
== DP_SSS_PWR_ON(pipe
);
1371 * A transient state at this point would mean some unexpected party
1372 * is poking at the power controls too.
1374 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
1375 WARN_ON(ctrl
<< 16 != state
);
1377 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1382 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
1383 struct i915_power_well
*power_well
,
1386 enum pipe pipe
= power_well
->data
;
1390 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
1392 mutex_lock(&dev_priv
->rps
.hw_lock
);
1395 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1400 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
1401 ctrl
&= ~DP_SSC_MASK(pipe
);
1402 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
1403 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
1405 if (wait_for(COND
, 100))
1406 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1408 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
1413 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1416 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
1417 struct i915_power_well
*power_well
)
1419 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1421 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
1424 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
1425 struct i915_power_well
*power_well
)
1427 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1429 chv_set_pipe_power_well(dev_priv
, power_well
, true);
1431 vlv_display_power_well_init(dev_priv
);
1434 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
1435 struct i915_power_well
*power_well
)
1437 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1439 vlv_display_power_well_deinit(dev_priv
);
1441 chv_set_pipe_power_well(dev_priv
, power_well
, false);
1445 __intel_display_power_get_domain(struct drm_i915_private
*dev_priv
,
1446 enum intel_display_power_domain domain
)
1448 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1449 struct i915_power_well
*power_well
;
1452 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
1453 if (!power_well
->count
++)
1454 intel_power_well_enable(dev_priv
, power_well
);
1457 power_domains
->domain_use_count
[domain
]++;
1461 * intel_display_power_get - grab a power domain reference
1462 * @dev_priv: i915 device instance
1463 * @domain: power domain to reference
1465 * This function grabs a power domain reference for @domain and ensures that the
1466 * power domain and all its parents are powered up. Therefore users should only
1467 * grab a reference to the innermost power domain they need.
1469 * Any power domain reference obtained by this function must have a symmetric
1470 * call to intel_display_power_put() to release the reference again.
1472 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1473 enum intel_display_power_domain domain
)
1475 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1477 intel_runtime_pm_get(dev_priv
);
1479 mutex_lock(&power_domains
->lock
);
1481 __intel_display_power_get_domain(dev_priv
, domain
);
1483 mutex_unlock(&power_domains
->lock
);
1487 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1488 * @dev_priv: i915 device instance
1489 * @domain: power domain to reference
1491 * This function grabs a power domain reference for @domain and ensures that the
1492 * power domain and all its parents are powered up. Therefore users should only
1493 * grab a reference to the innermost power domain they need.
1495 * Any power domain reference obtained by this function must have a symmetric
1496 * call to intel_display_power_put() to release the reference again.
1498 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1499 enum intel_display_power_domain domain
)
1501 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1504 if (!intel_runtime_pm_get_if_in_use(dev_priv
))
1507 mutex_lock(&power_domains
->lock
);
1509 if (__intel_display_power_is_enabled(dev_priv
, domain
)) {
1510 __intel_display_power_get_domain(dev_priv
, domain
);
1516 mutex_unlock(&power_domains
->lock
);
1519 intel_runtime_pm_put(dev_priv
);
1525 * intel_display_power_put - release a power domain reference
1526 * @dev_priv: i915 device instance
1527 * @domain: power domain to reference
1529 * This function drops the power domain reference obtained by
1530 * intel_display_power_get() and might power down the corresponding hardware
1531 * block right away if this is the last reference.
1533 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1534 enum intel_display_power_domain domain
)
1536 struct i915_power_domains
*power_domains
;
1537 struct i915_power_well
*power_well
;
1540 power_domains
= &dev_priv
->power_domains
;
1542 mutex_lock(&power_domains
->lock
);
1544 WARN(!power_domains
->domain_use_count
[domain
],
1545 "Use count on domain %s is already zero\n",
1546 intel_display_power_domain_str(domain
));
1547 power_domains
->domain_use_count
[domain
]--;
1549 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
1550 WARN(!power_well
->count
,
1551 "Use count on power well %s is already zero",
1554 if (!--power_well
->count
)
1555 intel_power_well_disable(dev_priv
, power_well
);
1558 mutex_unlock(&power_domains
->lock
);
1560 intel_runtime_pm_put(dev_priv
);
1563 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1564 BIT(POWER_DOMAIN_PIPE_A) | \
1565 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1566 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1567 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1568 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1569 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1570 BIT(POWER_DOMAIN_PORT_CRT) | \
1571 BIT(POWER_DOMAIN_PLLS) | \
1572 BIT(POWER_DOMAIN_AUX_A) | \
1573 BIT(POWER_DOMAIN_AUX_B) | \
1574 BIT(POWER_DOMAIN_AUX_C) | \
1575 BIT(POWER_DOMAIN_AUX_D) | \
1576 BIT(POWER_DOMAIN_GMBUS) | \
1577 BIT(POWER_DOMAIN_INIT))
1578 #define HSW_DISPLAY_POWER_DOMAINS ( \
1579 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1580 BIT(POWER_DOMAIN_INIT))
1582 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1583 HSW_ALWAYS_ON_POWER_DOMAINS | \
1584 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1585 #define BDW_DISPLAY_POWER_DOMAINS ( \
1586 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1587 BIT(POWER_DOMAIN_INIT))
1589 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1590 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1592 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1593 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1594 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1595 BIT(POWER_DOMAIN_PORT_CRT) | \
1596 BIT(POWER_DOMAIN_AUX_B) | \
1597 BIT(POWER_DOMAIN_AUX_C) | \
1598 BIT(POWER_DOMAIN_INIT))
1600 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1601 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1602 BIT(POWER_DOMAIN_AUX_B) | \
1603 BIT(POWER_DOMAIN_INIT))
1605 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1606 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1607 BIT(POWER_DOMAIN_AUX_B) | \
1608 BIT(POWER_DOMAIN_INIT))
1610 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1611 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1612 BIT(POWER_DOMAIN_AUX_C) | \
1613 BIT(POWER_DOMAIN_INIT))
1615 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1616 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1617 BIT(POWER_DOMAIN_AUX_C) | \
1618 BIT(POWER_DOMAIN_INIT))
1620 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1621 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1622 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1623 BIT(POWER_DOMAIN_AUX_B) | \
1624 BIT(POWER_DOMAIN_AUX_C) | \
1625 BIT(POWER_DOMAIN_INIT))
1627 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1628 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1629 BIT(POWER_DOMAIN_AUX_D) | \
1630 BIT(POWER_DOMAIN_INIT))
1632 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
1633 .sync_hw
= i9xx_always_on_power_well_noop
,
1634 .enable
= i9xx_always_on_power_well_noop
,
1635 .disable
= i9xx_always_on_power_well_noop
,
1636 .is_enabled
= i9xx_always_on_power_well_enabled
,
1639 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
1640 .sync_hw
= chv_pipe_power_well_sync_hw
,
1641 .enable
= chv_pipe_power_well_enable
,
1642 .disable
= chv_pipe_power_well_disable
,
1643 .is_enabled
= chv_pipe_power_well_enabled
,
1646 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
1647 .sync_hw
= vlv_power_well_sync_hw
,
1648 .enable
= chv_dpio_cmn_power_well_enable
,
1649 .disable
= chv_dpio_cmn_power_well_disable
,
1650 .is_enabled
= vlv_power_well_enabled
,
1653 static struct i915_power_well i9xx_always_on_power_well
[] = {
1655 .name
= "always-on",
1657 .domains
= POWER_DOMAIN_MASK
,
1658 .ops
= &i9xx_always_on_power_well_ops
,
1662 static const struct i915_power_well_ops hsw_power_well_ops
= {
1663 .sync_hw
= hsw_power_well_sync_hw
,
1664 .enable
= hsw_power_well_enable
,
1665 .disable
= hsw_power_well_disable
,
1666 .is_enabled
= hsw_power_well_enabled
,
1669 static const struct i915_power_well_ops skl_power_well_ops
= {
1670 .sync_hw
= skl_power_well_sync_hw
,
1671 .enable
= skl_power_well_enable
,
1672 .disable
= skl_power_well_disable
,
1673 .is_enabled
= skl_power_well_enabled
,
1676 static const struct i915_power_well_ops gen9_dc_off_power_well_ops
= {
1677 .sync_hw
= gen9_dc_off_power_well_sync_hw
,
1678 .enable
= gen9_dc_off_power_well_enable
,
1679 .disable
= gen9_dc_off_power_well_disable
,
1680 .is_enabled
= gen9_dc_off_power_well_enabled
,
1683 static struct i915_power_well hsw_power_wells
[] = {
1685 .name
= "always-on",
1687 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
1688 .ops
= &i9xx_always_on_power_well_ops
,
1692 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
1693 .ops
= &hsw_power_well_ops
,
1697 static struct i915_power_well bdw_power_wells
[] = {
1699 .name
= "always-on",
1701 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
1702 .ops
= &i9xx_always_on_power_well_ops
,
1706 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
1707 .ops
= &hsw_power_well_ops
,
1711 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
1712 .sync_hw
= vlv_power_well_sync_hw
,
1713 .enable
= vlv_display_power_well_enable
,
1714 .disable
= vlv_display_power_well_disable
,
1715 .is_enabled
= vlv_power_well_enabled
,
1718 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
1719 .sync_hw
= vlv_power_well_sync_hw
,
1720 .enable
= vlv_dpio_cmn_power_well_enable
,
1721 .disable
= vlv_dpio_cmn_power_well_disable
,
1722 .is_enabled
= vlv_power_well_enabled
,
1725 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
1726 .sync_hw
= vlv_power_well_sync_hw
,
1727 .enable
= vlv_power_well_enable
,
1728 .disable
= vlv_power_well_disable
,
1729 .is_enabled
= vlv_power_well_enabled
,
1732 static struct i915_power_well vlv_power_wells
[] = {
1734 .name
= "always-on",
1736 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
1737 .ops
= &i9xx_always_on_power_well_ops
,
1738 .data
= PUNIT_POWER_WELL_ALWAYS_ON
,
1742 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
1743 .data
= PUNIT_POWER_WELL_DISP2D
,
1744 .ops
= &vlv_display_power_well_ops
,
1747 .name
= "dpio-tx-b-01",
1748 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1749 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1750 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1751 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1752 .ops
= &vlv_dpio_power_well_ops
,
1753 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
1756 .name
= "dpio-tx-b-23",
1757 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1758 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1759 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1760 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1761 .ops
= &vlv_dpio_power_well_ops
,
1762 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
1765 .name
= "dpio-tx-c-01",
1766 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1767 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1768 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1769 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1770 .ops
= &vlv_dpio_power_well_ops
,
1771 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
1774 .name
= "dpio-tx-c-23",
1775 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1776 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1777 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1778 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1779 .ops
= &vlv_dpio_power_well_ops
,
1780 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
1783 .name
= "dpio-common",
1784 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
1785 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
1786 .ops
= &vlv_dpio_cmn_power_well_ops
,
1790 static struct i915_power_well chv_power_wells
[] = {
1792 .name
= "always-on",
1794 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
1795 .ops
= &i9xx_always_on_power_well_ops
,
1800 * Pipe A power well is the new disp2d well. Pipe B and C
1801 * power wells don't actually exist. Pipe A power well is
1802 * required for any pipe to work.
1804 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
1806 .ops
= &chv_pipe_power_well_ops
,
1809 .name
= "dpio-common-bc",
1810 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
,
1811 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
1812 .ops
= &chv_dpio_cmn_power_well_ops
,
1815 .name
= "dpio-common-d",
1816 .domains
= CHV_DPIO_CMN_D_POWER_DOMAINS
,
1817 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
1818 .ops
= &chv_dpio_cmn_power_well_ops
,
1822 bool intel_display_power_well_is_enabled(struct drm_i915_private
*dev_priv
,
1825 struct i915_power_well
*power_well
;
1828 power_well
= lookup_power_well(dev_priv
, power_well_id
);
1829 ret
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
1834 static struct i915_power_well skl_power_wells
[] = {
1836 .name
= "always-on",
1838 .domains
= SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
,
1839 .ops
= &i9xx_always_on_power_well_ops
,
1840 .data
= SKL_DISP_PW_ALWAYS_ON
,
1843 .name
= "power well 1",
1844 /* Handled by the DMC firmware */
1846 .ops
= &skl_power_well_ops
,
1847 .data
= SKL_DISP_PW_1
,
1850 .name
= "MISC IO power well",
1851 /* Handled by the DMC firmware */
1853 .ops
= &skl_power_well_ops
,
1854 .data
= SKL_DISP_PW_MISC_IO
,
1858 .domains
= SKL_DISPLAY_DC_OFF_POWER_DOMAINS
,
1859 .ops
= &gen9_dc_off_power_well_ops
,
1860 .data
= SKL_DISP_PW_DC_OFF
,
1863 .name
= "power well 2",
1864 .domains
= SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS
,
1865 .ops
= &skl_power_well_ops
,
1866 .data
= SKL_DISP_PW_2
,
1869 .name
= "DDI A/E power well",
1870 .domains
= SKL_DISPLAY_DDI_A_E_POWER_DOMAINS
,
1871 .ops
= &skl_power_well_ops
,
1872 .data
= SKL_DISP_PW_DDI_A_E
,
1875 .name
= "DDI B power well",
1876 .domains
= SKL_DISPLAY_DDI_B_POWER_DOMAINS
,
1877 .ops
= &skl_power_well_ops
,
1878 .data
= SKL_DISP_PW_DDI_B
,
1881 .name
= "DDI C power well",
1882 .domains
= SKL_DISPLAY_DDI_C_POWER_DOMAINS
,
1883 .ops
= &skl_power_well_ops
,
1884 .data
= SKL_DISP_PW_DDI_C
,
1887 .name
= "DDI D power well",
1888 .domains
= SKL_DISPLAY_DDI_D_POWER_DOMAINS
,
1889 .ops
= &skl_power_well_ops
,
1890 .data
= SKL_DISP_PW_DDI_D
,
1894 void skl_pw1_misc_io_init(struct drm_i915_private
*dev_priv
)
1896 struct i915_power_well
*well
;
1898 if (!(IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)))
1901 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_1
);
1902 intel_power_well_enable(dev_priv
, well
);
1904 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_MISC_IO
);
1905 intel_power_well_enable(dev_priv
, well
);
1908 void skl_pw1_misc_io_fini(struct drm_i915_private
*dev_priv
)
1910 struct i915_power_well
*well
;
1912 if (!(IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)))
1915 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_1
);
1916 intel_power_well_disable(dev_priv
, well
);
1918 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_MISC_IO
);
1919 intel_power_well_disable(dev_priv
, well
);
1922 static struct i915_power_well bxt_power_wells
[] = {
1924 .name
= "always-on",
1926 .domains
= BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS
,
1927 .ops
= &i9xx_always_on_power_well_ops
,
1930 .name
= "power well 1",
1931 .domains
= BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
,
1932 .ops
= &skl_power_well_ops
,
1933 .data
= SKL_DISP_PW_1
,
1937 .domains
= BXT_DISPLAY_DC_OFF_POWER_DOMAINS
,
1938 .ops
= &gen9_dc_off_power_well_ops
,
1939 .data
= SKL_DISP_PW_DC_OFF
,
1942 .name
= "power well 2",
1943 .domains
= BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS
,
1944 .ops
= &skl_power_well_ops
,
1945 .data
= SKL_DISP_PW_2
,
1950 sanitize_disable_power_well_option(const struct drm_i915_private
*dev_priv
,
1951 int disable_power_well
)
1953 if (disable_power_well
>= 0)
1954 return !!disable_power_well
;
1956 if (IS_BROXTON(dev_priv
)) {
1957 DRM_DEBUG_KMS("Disabling display power well support\n");
1964 static uint32_t get_allowed_dc_mask(const struct drm_i915_private
*dev_priv
,
1971 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1974 } else if (IS_BROXTON(dev_priv
)) {
1977 * DC9 has a separate HW flow from the rest of the DC states,
1978 * not depending on the DMC firmware. It's needed by system
1979 * suspend/resume, so allow it unconditionally.
1981 mask
= DC_STATE_EN_DC9
;
1987 if (!i915
.disable_power_well
)
1990 if (enable_dc
>= 0 && enable_dc
<= max_dc
) {
1991 requested_dc
= enable_dc
;
1992 } else if (enable_dc
== -1) {
1993 requested_dc
= max_dc
;
1994 } else if (enable_dc
> max_dc
&& enable_dc
<= 2) {
1995 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
1997 requested_dc
= max_dc
;
1999 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc
);
2000 requested_dc
= max_dc
;
2003 if (requested_dc
> 1)
2004 mask
|= DC_STATE_EN_UPTO_DC6
;
2005 if (requested_dc
> 0)
2006 mask
|= DC_STATE_EN_UPTO_DC5
;
2008 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask
);
2013 #define set_power_wells(power_domains, __power_wells) ({ \
2014 (power_domains)->power_wells = (__power_wells); \
2015 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2019 * intel_power_domains_init - initializes the power domain structures
2020 * @dev_priv: i915 device instance
2022 * Initializes the power domain structures for @dev_priv depending upon the
2023 * supported platform.
2025 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
2027 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2029 i915
.disable_power_well
= sanitize_disable_power_well_option(dev_priv
,
2030 i915
.disable_power_well
);
2031 dev_priv
->csr
.allowed_dc_mask
= get_allowed_dc_mask(dev_priv
,
2034 BUILD_BUG_ON(POWER_DOMAIN_NUM
> 31);
2036 mutex_init(&power_domains
->lock
);
2039 * The enabling order will be from lower to higher indexed wells,
2040 * the disabling order is reversed.
2042 if (IS_HASWELL(dev_priv
->dev
)) {
2043 set_power_wells(power_domains
, hsw_power_wells
);
2044 } else if (IS_BROADWELL(dev_priv
->dev
)) {
2045 set_power_wells(power_domains
, bdw_power_wells
);
2046 } else if (IS_SKYLAKE(dev_priv
->dev
) || IS_KABYLAKE(dev_priv
->dev
)) {
2047 set_power_wells(power_domains
, skl_power_wells
);
2048 } else if (IS_BROXTON(dev_priv
->dev
)) {
2049 set_power_wells(power_domains
, bxt_power_wells
);
2050 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
2051 set_power_wells(power_domains
, chv_power_wells
);
2052 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
2053 set_power_wells(power_domains
, vlv_power_wells
);
2055 set_power_wells(power_domains
, i9xx_always_on_power_well
);
2062 * intel_power_domains_fini - finalizes the power domain structures
2063 * @dev_priv: i915 device instance
2065 * Finalizes the power domain structures for @dev_priv depending upon the
2066 * supported platform. This function also disables runtime pm and ensures that
2067 * the device stays powered up so that the driver can be reloaded.
2069 void intel_power_domains_fini(struct drm_i915_private
*dev_priv
)
2071 struct device
*device
= &dev_priv
->dev
->pdev
->dev
;
2074 * The i915.ko module is still not prepared to be loaded when
2075 * the power well is not enabled, so just enable it in case
2076 * we're going to unload/reload.
2077 * The following also reacquires the RPM reference the core passed
2078 * to the driver during loading, which is dropped in
2079 * intel_runtime_pm_enable(). We have to hand back the control of the
2080 * device to the core with this reference held.
2082 intel_display_set_init_power(dev_priv
, true);
2084 /* Remove the refcount we took to keep power well support disabled. */
2085 if (!i915
.disable_power_well
)
2086 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
2089 * Remove the refcount we took in intel_runtime_pm_enable() in case
2090 * the platform doesn't support runtime PM.
2092 if (!HAS_RUNTIME_PM(dev_priv
))
2093 pm_runtime_put(device
);
2096 static void intel_power_domains_sync_hw(struct drm_i915_private
*dev_priv
)
2098 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2099 struct i915_power_well
*power_well
;
2102 mutex_lock(&power_domains
->lock
);
2103 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
2104 power_well
->ops
->sync_hw(dev_priv
, power_well
);
2105 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
2108 mutex_unlock(&power_domains
->lock
);
2111 static void skl_display_core_init(struct drm_i915_private
*dev_priv
,
2114 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2117 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
2119 /* enable PCH reset handshake */
2120 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
2121 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
2123 /* enable PG1 and Misc I/O */
2124 mutex_lock(&power_domains
->lock
);
2125 skl_pw1_misc_io_init(dev_priv
);
2126 mutex_unlock(&power_domains
->lock
);
2131 skl_init_cdclk(dev_priv
);
2133 if (dev_priv
->csr
.dmc_payload
)
2134 intel_csr_load_program(dev_priv
);
2137 static void skl_display_core_uninit(struct drm_i915_private
*dev_priv
)
2139 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2141 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
2143 skl_uninit_cdclk(dev_priv
);
2145 /* The spec doesn't call for removing the reset handshake flag */
2146 /* disable PG1 and Misc I/O */
2147 mutex_lock(&power_domains
->lock
);
2148 skl_pw1_misc_io_fini(dev_priv
);
2149 mutex_unlock(&power_domains
->lock
);
2152 static void chv_phy_control_init(struct drm_i915_private
*dev_priv
)
2154 struct i915_power_well
*cmn_bc
=
2155 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
2156 struct i915_power_well
*cmn_d
=
2157 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_D
);
2160 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2161 * workaround never ever read DISPLAY_PHY_CONTROL, and
2162 * instead maintain a shadow copy ourselves. Use the actual
2163 * power well state and lane status to reconstruct the
2164 * expected initial value.
2166 dev_priv
->chv_phy_control
=
2167 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS
, DPIO_PHY0
) |
2168 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS
, DPIO_PHY1
) |
2169 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY0
, DPIO_CH0
) |
2170 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY0
, DPIO_CH1
) |
2171 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY1
, DPIO_CH0
);
2174 * If all lanes are disabled we leave the override disabled
2175 * with all power down bits cleared to match the state we
2176 * would use after disabling the port. Otherwise enable the
2177 * override and set the lane powerdown bits accding to the
2178 * current lane status.
2180 if (cmn_bc
->ops
->is_enabled(dev_priv
, cmn_bc
)) {
2181 uint32_t status
= I915_READ(DPLL(PIPE_A
));
2184 mask
= status
& DPLL_PORTB_READY_MASK
;
2188 dev_priv
->chv_phy_control
|=
2189 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH0
);
2191 dev_priv
->chv_phy_control
|=
2192 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY0
, DPIO_CH0
);
2194 mask
= (status
& DPLL_PORTC_READY_MASK
) >> 4;
2198 dev_priv
->chv_phy_control
|=
2199 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH1
);
2201 dev_priv
->chv_phy_control
|=
2202 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY0
, DPIO_CH1
);
2204 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0
);
2206 dev_priv
->chv_phy_assert
[DPIO_PHY0
] = false;
2208 dev_priv
->chv_phy_assert
[DPIO_PHY0
] = true;
2211 if (cmn_d
->ops
->is_enabled(dev_priv
, cmn_d
)) {
2212 uint32_t status
= I915_READ(DPIO_PHY_STATUS
);
2215 mask
= status
& DPLL_PORTD_READY_MASK
;
2220 dev_priv
->chv_phy_control
|=
2221 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1
, DPIO_CH0
);
2223 dev_priv
->chv_phy_control
|=
2224 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY1
, DPIO_CH0
);
2226 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1
);
2228 dev_priv
->chv_phy_assert
[DPIO_PHY1
] = false;
2230 dev_priv
->chv_phy_assert
[DPIO_PHY1
] = true;
2233 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
2235 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2236 dev_priv
->chv_phy_control
);
2239 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
2241 struct i915_power_well
*cmn
=
2242 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
2243 struct i915_power_well
*disp2d
=
2244 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
2246 /* If the display might be already active skip this */
2247 if (cmn
->ops
->is_enabled(dev_priv
, cmn
) &&
2248 disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
2249 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
2252 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2254 /* cmnlane needs DPLL registers */
2255 disp2d
->ops
->enable(dev_priv
, disp2d
);
2258 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2259 * Need to assert and de-assert PHY SB reset by gating the
2260 * common lane power, then un-gating it.
2261 * Simply ungating isn't enough to reset the PHY enough to get
2262 * ports and lanes running.
2264 cmn
->ops
->disable(dev_priv
, cmn
);
2268 * intel_power_domains_init_hw - initialize hardware power domain state
2269 * @dev_priv: i915 device instance
2271 * This function initializes the hardware power domain state and enables all
2272 * power domains using intel_display_set_init_power().
2274 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
)
2276 struct drm_device
*dev
= dev_priv
->dev
;
2277 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2279 power_domains
->initializing
= true;
2281 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
2282 skl_display_core_init(dev_priv
, resume
);
2283 } else if (IS_CHERRYVIEW(dev
)) {
2284 mutex_lock(&power_domains
->lock
);
2285 chv_phy_control_init(dev_priv
);
2286 mutex_unlock(&power_domains
->lock
);
2287 } else if (IS_VALLEYVIEW(dev
)) {
2288 mutex_lock(&power_domains
->lock
);
2289 vlv_cmnlane_wa(dev_priv
);
2290 mutex_unlock(&power_domains
->lock
);
2293 /* For now, we need the power well to be always enabled. */
2294 intel_display_set_init_power(dev_priv
, true);
2295 /* Disable power support if the user asked so. */
2296 if (!i915
.disable_power_well
)
2297 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
2298 intel_power_domains_sync_hw(dev_priv
);
2299 power_domains
->initializing
= false;
2303 * intel_power_domains_suspend - suspend power domain state
2304 * @dev_priv: i915 device instance
2306 * This function prepares the hardware power domain state before entering
2307 * system suspend. It must be paired with intel_power_domains_init_hw().
2309 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
)
2312 * Even if power well support was disabled we still want to disable
2313 * power wells while we are system suspended.
2315 if (!i915
.disable_power_well
)
2316 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
2318 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
2319 skl_display_core_uninit(dev_priv
);
2323 * intel_runtime_pm_get - grab a runtime pm reference
2324 * @dev_priv: i915 device instance
2326 * This function grabs a device-level runtime pm reference (mostly used for GEM
2327 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2329 * Any runtime pm reference obtained by this function must have a symmetric
2330 * call to intel_runtime_pm_put() to release the reference again.
2332 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
2334 struct drm_device
*dev
= dev_priv
->dev
;
2335 struct device
*device
= &dev
->pdev
->dev
;
2337 pm_runtime_get_sync(device
);
2339 atomic_inc(&dev_priv
->pm
.wakeref_count
);
2340 assert_rpm_wakelock_held(dev_priv
);
2344 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2345 * @dev_priv: i915 device instance
2347 * This function grabs a device-level runtime pm reference if the device is
2348 * already in use and ensures that it is powered up.
2350 * Any runtime pm reference obtained by this function must have a symmetric
2351 * call to intel_runtime_pm_put() to release the reference again.
2353 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
)
2355 struct drm_device
*dev
= dev_priv
->dev
;
2356 struct device
*device
= &dev
->pdev
->dev
;
2358 if (IS_ENABLED(CONFIG_PM
)) {
2359 int ret
= pm_runtime_get_if_in_use(device
);
2362 * In cases runtime PM is disabled by the RPM core and we get
2363 * an -EINVAL return value we are not supposed to call this
2364 * function, since the power state is undefined. This applies
2365 * atm to the late/early system suspend/resume handlers.
2367 WARN_ON_ONCE(ret
< 0);
2372 atomic_inc(&dev_priv
->pm
.wakeref_count
);
2373 assert_rpm_wakelock_held(dev_priv
);
2379 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2380 * @dev_priv: i915 device instance
2382 * This function grabs a device-level runtime pm reference (mostly used for GEM
2383 * code to ensure the GTT or GT is on).
2385 * It will _not_ power up the device but instead only check that it's powered
2386 * on. Therefore it is only valid to call this functions from contexts where
2387 * the device is known to be powered up and where trying to power it up would
2388 * result in hilarity and deadlocks. That pretty much means only the system
2389 * suspend/resume code where this is used to grab runtime pm references for
2390 * delayed setup down in work items.
2392 * Any runtime pm reference obtained by this function must have a symmetric
2393 * call to intel_runtime_pm_put() to release the reference again.
2395 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
2397 struct drm_device
*dev
= dev_priv
->dev
;
2398 struct device
*device
= &dev
->pdev
->dev
;
2400 assert_rpm_wakelock_held(dev_priv
);
2401 pm_runtime_get_noresume(device
);
2403 atomic_inc(&dev_priv
->pm
.wakeref_count
);
2407 * intel_runtime_pm_put - release a runtime pm reference
2408 * @dev_priv: i915 device instance
2410 * This function drops the device-level runtime pm reference obtained by
2411 * intel_runtime_pm_get() and might power down the corresponding
2412 * hardware block right away if this is the last reference.
2414 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
2416 struct drm_device
*dev
= dev_priv
->dev
;
2417 struct device
*device
= &dev
->pdev
->dev
;
2419 assert_rpm_wakelock_held(dev_priv
);
2420 if (atomic_dec_and_test(&dev_priv
->pm
.wakeref_count
))
2421 atomic_inc(&dev_priv
->pm
.atomic_seq
);
2423 pm_runtime_mark_last_busy(device
);
2424 pm_runtime_put_autosuspend(device
);
2428 * intel_runtime_pm_enable - enable runtime pm
2429 * @dev_priv: i915 device instance
2431 * This function enables runtime pm at the end of the driver load sequence.
2433 * Note that this function does currently not enable runtime pm for the
2434 * subordinate display power domains. That is only done on the first modeset
2435 * using intel_display_set_init_power().
2437 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
)
2439 struct drm_device
*dev
= dev_priv
->dev
;
2440 struct device
*device
= &dev
->pdev
->dev
;
2442 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
2443 pm_runtime_mark_last_busy(device
);
2446 * Take a permanent reference to disable the RPM functionality and drop
2447 * it only when unloading the driver. Use the low level get/put helpers,
2448 * so the driver's own RPM reference tracking asserts also work on
2449 * platforms without RPM support.
2451 if (!HAS_RUNTIME_PM(dev
)) {
2452 pm_runtime_dont_use_autosuspend(device
);
2453 pm_runtime_get_sync(device
);
2455 pm_runtime_use_autosuspend(device
);
2459 * The core calls the driver load handler with an RPM reference held.
2460 * We drop that here and will reacquire it during unloading in
2461 * intel_power_domains_fini().
2463 pm_runtime_put_autosuspend(device
);