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Merge tag 'virtio-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
1 /*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
31
32 #include "i915_drv.h"
33 #include "intel_drv.h"
34
35 /**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
53 for (i = 0; \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
56 i++) \
57 if ((power_well)->domains & (domain_mask))
58
59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
62 i--) \
63 if ((power_well)->domains & (domain_mask))
64
65 /*
66 * We should only use the power well if we explicitly asked the hardware to
67 * enable it, so check if it's enabled and also check if we've requested it to
68 * be enabled.
69 */
70 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
71 struct i915_power_well *power_well)
72 {
73 return I915_READ(HSW_PWR_WELL_DRIVER) ==
74 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
75 }
76
77 /**
78 * __intel_display_power_is_enabled - unlocked check for a power domain
79 * @dev_priv: i915 device instance
80 * @domain: power domain to check
81 *
82 * This is the unlocked version of intel_display_power_is_enabled() and should
83 * only be used from error capture and recovery code where deadlocks are
84 * possible.
85 *
86 * Returns:
87 * True when the power domain is enabled, false otherwise.
88 */
89 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
90 enum intel_display_power_domain domain)
91 {
92 struct i915_power_domains *power_domains;
93 struct i915_power_well *power_well;
94 bool is_enabled;
95 int i;
96
97 if (dev_priv->pm.suspended)
98 return false;
99
100 power_domains = &dev_priv->power_domains;
101
102 is_enabled = true;
103
104 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
105 if (power_well->always_on)
106 continue;
107
108 if (!power_well->hw_enabled) {
109 is_enabled = false;
110 break;
111 }
112 }
113
114 return is_enabled;
115 }
116
117 /**
118 * intel_display_power_is_enabled - check for a power domain
119 * @dev_priv: i915 device instance
120 * @domain: power domain to check
121 *
122 * This function can be used to check the hw power domain state. It is mostly
123 * used in hardware state readout functions. Everywhere else code should rely
124 * upon explicit power domain reference counting to ensure that the hardware
125 * block is powered up before accessing it.
126 *
127 * Callers must hold the relevant modesetting locks to ensure that concurrent
128 * threads can't disable the power well while the caller tries to read a few
129 * registers.
130 *
131 * Returns:
132 * True when the power domain is enabled, false otherwise.
133 */
134 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
135 enum intel_display_power_domain domain)
136 {
137 struct i915_power_domains *power_domains;
138 bool ret;
139
140 power_domains = &dev_priv->power_domains;
141
142 mutex_lock(&power_domains->lock);
143 ret = __intel_display_power_is_enabled(dev_priv, domain);
144 mutex_unlock(&power_domains->lock);
145
146 return ret;
147 }
148
149 /**
150 * intel_display_set_init_power - set the initial power domain state
151 * @dev_priv: i915 device instance
152 * @enable: whether to enable or disable the initial power domain state
153 *
154 * For simplicity our driver load/unload and system suspend/resume code assumes
155 * that all power domains are always enabled. This functions controls the state
156 * of this little hack. While the initial power domain state is enabled runtime
157 * pm is effectively disabled.
158 */
159 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
160 bool enable)
161 {
162 if (dev_priv->power_domains.init_power_on == enable)
163 return;
164
165 if (enable)
166 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
167 else
168 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
169
170 dev_priv->power_domains.init_power_on = enable;
171 }
172
173 /*
174 * Starting with Haswell, we have a "Power Down Well" that can be turned off
175 * when not needed anymore. We have 4 registers that can request the power well
176 * to be enabled, and it will only be disabled if none of the registers is
177 * requesting it to be enabled.
178 */
179 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
180 {
181 struct drm_device *dev = dev_priv->dev;
182
183 /*
184 * After we re-enable the power well, if we touch VGA register 0x3d5
185 * we'll get unclaimed register interrupts. This stops after we write
186 * anything to the VGA MSR register. The vgacon module uses this
187 * register all the time, so if we unbind our driver and, as a
188 * consequence, bind vgacon, we'll get stuck in an infinite loop at
189 * console_unlock(). So make here we touch the VGA MSR register, making
190 * sure vgacon can keep working normally without triggering interrupts
191 * and error messages.
192 */
193 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
194 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
195 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
196
197 if (IS_BROADWELL(dev))
198 gen8_irq_power_well_post_enable(dev_priv,
199 1 << PIPE_C | 1 << PIPE_B);
200 }
201
202 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
203 struct i915_power_well *power_well)
204 {
205 struct drm_device *dev = dev_priv->dev;
206
207 /*
208 * After we re-enable the power well, if we touch VGA register 0x3d5
209 * we'll get unclaimed register interrupts. This stops after we write
210 * anything to the VGA MSR register. The vgacon module uses this
211 * register all the time, so if we unbind our driver and, as a
212 * consequence, bind vgacon, we'll get stuck in an infinite loop at
213 * console_unlock(). So make here we touch the VGA MSR register, making
214 * sure vgacon can keep working normally without triggering interrupts
215 * and error messages.
216 */
217 if (power_well->data == SKL_DISP_PW_2) {
218 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
219 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
220 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
221
222 gen8_irq_power_well_post_enable(dev_priv,
223 1 << PIPE_C | 1 << PIPE_B);
224 }
225
226 if (power_well->data == SKL_DISP_PW_1) {
227 intel_prepare_ddi(dev);
228 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
229 }
230 }
231
232 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
233 struct i915_power_well *power_well, bool enable)
234 {
235 bool is_enabled, enable_requested;
236 uint32_t tmp;
237
238 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
239 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
240 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
241
242 if (enable) {
243 if (!enable_requested)
244 I915_WRITE(HSW_PWR_WELL_DRIVER,
245 HSW_PWR_WELL_ENABLE_REQUEST);
246
247 if (!is_enabled) {
248 DRM_DEBUG_KMS("Enabling power well\n");
249 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
250 HSW_PWR_WELL_STATE_ENABLED), 20))
251 DRM_ERROR("Timeout enabling power well\n");
252 hsw_power_well_post_enable(dev_priv);
253 }
254
255 } else {
256 if (enable_requested) {
257 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
258 POSTING_READ(HSW_PWR_WELL_DRIVER);
259 DRM_DEBUG_KMS("Requesting to disable the power well\n");
260 }
261 }
262 }
263
264 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
265 BIT(POWER_DOMAIN_TRANSCODER_A) | \
266 BIT(POWER_DOMAIN_PIPE_B) | \
267 BIT(POWER_DOMAIN_TRANSCODER_B) | \
268 BIT(POWER_DOMAIN_PIPE_C) | \
269 BIT(POWER_DOMAIN_TRANSCODER_C) | \
270 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
271 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
272 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
273 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
274 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
275 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
276 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
277 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
278 BIT(POWER_DOMAIN_AUX_B) | \
279 BIT(POWER_DOMAIN_AUX_C) | \
280 BIT(POWER_DOMAIN_AUX_D) | \
281 BIT(POWER_DOMAIN_AUDIO) | \
282 BIT(POWER_DOMAIN_VGA) | \
283 BIT(POWER_DOMAIN_INIT))
284 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
285 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
286 BIT(POWER_DOMAIN_PLLS) | \
287 BIT(POWER_DOMAIN_PIPE_A) | \
288 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
289 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
290 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
291 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
292 BIT(POWER_DOMAIN_AUX_A) | \
293 BIT(POWER_DOMAIN_INIT))
294 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
295 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
297 BIT(POWER_DOMAIN_INIT))
298 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
299 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
300 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
301 BIT(POWER_DOMAIN_INIT))
302 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
303 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
304 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
305 BIT(POWER_DOMAIN_INIT))
306 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
307 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
308 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
309 BIT(POWER_DOMAIN_INIT))
310 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
311 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS)
312 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
313 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
314 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
315 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
316 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
317 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
318 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
319 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
320 BIT(POWER_DOMAIN_INIT))
321
322 static void skl_set_power_well(struct drm_i915_private *dev_priv,
323 struct i915_power_well *power_well, bool enable)
324 {
325 uint32_t tmp, fuse_status;
326 uint32_t req_mask, state_mask;
327 bool is_enabled, enable_requested, check_fuse_status = false;
328
329 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
330 fuse_status = I915_READ(SKL_FUSE_STATUS);
331
332 switch (power_well->data) {
333 case SKL_DISP_PW_1:
334 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
335 SKL_FUSE_PG0_DIST_STATUS), 1)) {
336 DRM_ERROR("PG0 not enabled\n");
337 return;
338 }
339 break;
340 case SKL_DISP_PW_2:
341 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
342 DRM_ERROR("PG1 in disabled state\n");
343 return;
344 }
345 break;
346 case SKL_DISP_PW_DDI_A_E:
347 case SKL_DISP_PW_DDI_B:
348 case SKL_DISP_PW_DDI_C:
349 case SKL_DISP_PW_DDI_D:
350 case SKL_DISP_PW_MISC_IO:
351 break;
352 default:
353 WARN(1, "Unknown power well %lu\n", power_well->data);
354 return;
355 }
356
357 req_mask = SKL_POWER_WELL_REQ(power_well->data);
358 enable_requested = tmp & req_mask;
359 state_mask = SKL_POWER_WELL_STATE(power_well->data);
360 is_enabled = tmp & state_mask;
361
362 if (enable) {
363 if (!enable_requested) {
364 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
365 }
366
367 if (!is_enabled) {
368 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
369 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
370 state_mask), 1))
371 DRM_ERROR("%s enable timeout\n",
372 power_well->name);
373 check_fuse_status = true;
374 }
375 } else {
376 if (enable_requested) {
377 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
378 POSTING_READ(HSW_PWR_WELL_DRIVER);
379 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
380 }
381 }
382
383 if (check_fuse_status) {
384 if (power_well->data == SKL_DISP_PW_1) {
385 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
386 SKL_FUSE_PG1_DIST_STATUS), 1))
387 DRM_ERROR("PG1 distributing status timeout\n");
388 } else if (power_well->data == SKL_DISP_PW_2) {
389 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
390 SKL_FUSE_PG2_DIST_STATUS), 1))
391 DRM_ERROR("PG2 distributing status timeout\n");
392 }
393 }
394
395 if (enable && !is_enabled)
396 skl_power_well_post_enable(dev_priv, power_well);
397 }
398
399 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
400 struct i915_power_well *power_well)
401 {
402 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
403
404 /*
405 * We're taking over the BIOS, so clear any requests made by it since
406 * the driver is in charge now.
407 */
408 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
409 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
410 }
411
412 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
413 struct i915_power_well *power_well)
414 {
415 hsw_set_power_well(dev_priv, power_well, true);
416 }
417
418 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
419 struct i915_power_well *power_well)
420 {
421 hsw_set_power_well(dev_priv, power_well, false);
422 }
423
424 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
425 struct i915_power_well *power_well)
426 {
427 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
428 SKL_POWER_WELL_STATE(power_well->data);
429
430 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
431 }
432
433 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
434 struct i915_power_well *power_well)
435 {
436 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
437
438 /* Clear any request made by BIOS as driver is taking over */
439 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
440 }
441
442 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
443 struct i915_power_well *power_well)
444 {
445 skl_set_power_well(dev_priv, power_well, true);
446 }
447
448 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
449 struct i915_power_well *power_well)
450 {
451 skl_set_power_well(dev_priv, power_well, false);
452 }
453
454 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
455 struct i915_power_well *power_well)
456 {
457 }
458
459 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
460 struct i915_power_well *power_well)
461 {
462 return true;
463 }
464
465 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
466 struct i915_power_well *power_well, bool enable)
467 {
468 enum punit_power_well power_well_id = power_well->data;
469 u32 mask;
470 u32 state;
471 u32 ctrl;
472
473 mask = PUNIT_PWRGT_MASK(power_well_id);
474 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
475 PUNIT_PWRGT_PWR_GATE(power_well_id);
476
477 mutex_lock(&dev_priv->rps.hw_lock);
478
479 #define COND \
480 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
481
482 if (COND)
483 goto out;
484
485 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
486 ctrl &= ~mask;
487 ctrl |= state;
488 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
489
490 if (wait_for(COND, 100))
491 DRM_ERROR("timout setting power well state %08x (%08x)\n",
492 state,
493 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
494
495 #undef COND
496
497 out:
498 mutex_unlock(&dev_priv->rps.hw_lock);
499 }
500
501 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
502 struct i915_power_well *power_well)
503 {
504 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
505 }
506
507 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
508 struct i915_power_well *power_well)
509 {
510 vlv_set_power_well(dev_priv, power_well, true);
511 }
512
513 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
514 struct i915_power_well *power_well)
515 {
516 vlv_set_power_well(dev_priv, power_well, false);
517 }
518
519 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
520 struct i915_power_well *power_well)
521 {
522 int power_well_id = power_well->data;
523 bool enabled = false;
524 u32 mask;
525 u32 state;
526 u32 ctrl;
527
528 mask = PUNIT_PWRGT_MASK(power_well_id);
529 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
530
531 mutex_lock(&dev_priv->rps.hw_lock);
532
533 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
534 /*
535 * We only ever set the power-on and power-gate states, anything
536 * else is unexpected.
537 */
538 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
539 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
540 if (state == ctrl)
541 enabled = true;
542
543 /*
544 * A transient state at this point would mean some unexpected party
545 * is poking at the power controls too.
546 */
547 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
548 WARN_ON(ctrl != state);
549
550 mutex_unlock(&dev_priv->rps.hw_lock);
551
552 return enabled;
553 }
554
555 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
556 struct i915_power_well *power_well)
557 {
558 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
559
560 vlv_set_power_well(dev_priv, power_well, true);
561
562 spin_lock_irq(&dev_priv->irq_lock);
563 valleyview_enable_display_irqs(dev_priv);
564 spin_unlock_irq(&dev_priv->irq_lock);
565
566 /*
567 * During driver initialization/resume we can avoid restoring the
568 * part of the HW/SW state that will be inited anyway explicitly.
569 */
570 if (dev_priv->power_domains.initializing)
571 return;
572
573 intel_hpd_init(dev_priv);
574
575 i915_redisable_vga_power_on(dev_priv->dev);
576 }
577
578 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
579 struct i915_power_well *power_well)
580 {
581 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
582
583 spin_lock_irq(&dev_priv->irq_lock);
584 valleyview_disable_display_irqs(dev_priv);
585 spin_unlock_irq(&dev_priv->irq_lock);
586
587 vlv_set_power_well(dev_priv, power_well, false);
588
589 vlv_power_sequencer_reset(dev_priv);
590 }
591
592 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
593 struct i915_power_well *power_well)
594 {
595 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
596
597 /*
598 * Enable the CRI clock source so we can get at the
599 * display and the reference clock for VGA
600 * hotplug / manual detection.
601 */
602 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
603 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
604 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
605
606 vlv_set_power_well(dev_priv, power_well, true);
607
608 /*
609 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
610 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
611 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
612 * b. The other bits such as sfr settings / modesel may all
613 * be set to 0.
614 *
615 * This should only be done on init and resume from S3 with
616 * both PLLs disabled, or we risk losing DPIO and PLL
617 * synchronization.
618 */
619 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
620 }
621
622 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
623 struct i915_power_well *power_well)
624 {
625 enum pipe pipe;
626
627 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
628
629 for_each_pipe(dev_priv, pipe)
630 assert_pll_disabled(dev_priv, pipe);
631
632 /* Assert common reset */
633 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
634
635 vlv_set_power_well(dev_priv, power_well, false);
636 }
637
638 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
639 struct i915_power_well *power_well)
640 {
641 enum dpio_phy phy;
642
643 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
644 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
645
646 /*
647 * Enable the CRI clock source so we can get at the
648 * display and the reference clock for VGA
649 * hotplug / manual detection.
650 */
651 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
652 phy = DPIO_PHY0;
653 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
654 DPLL_REFA_CLK_ENABLE_VLV);
655 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
656 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
657 } else {
658 phy = DPIO_PHY1;
659 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
660 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
661 }
662 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
663 vlv_set_power_well(dev_priv, power_well, true);
664
665 /* Poll for phypwrgood signal */
666 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
667 DRM_ERROR("Display PHY %d is not power up\n", phy);
668
669 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
670 PHY_COM_LANE_RESET_DEASSERT(phy));
671 }
672
673 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
674 struct i915_power_well *power_well)
675 {
676 enum dpio_phy phy;
677
678 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
679 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
680
681 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
682 phy = DPIO_PHY0;
683 assert_pll_disabled(dev_priv, PIPE_A);
684 assert_pll_disabled(dev_priv, PIPE_B);
685 } else {
686 phy = DPIO_PHY1;
687 assert_pll_disabled(dev_priv, PIPE_C);
688 }
689
690 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
691 ~PHY_COM_LANE_RESET_DEASSERT(phy));
692
693 vlv_set_power_well(dev_priv, power_well, false);
694 }
695
696 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
697 struct i915_power_well *power_well)
698 {
699 enum pipe pipe = power_well->data;
700 bool enabled;
701 u32 state, ctrl;
702
703 mutex_lock(&dev_priv->rps.hw_lock);
704
705 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
706 /*
707 * We only ever set the power-on and power-gate states, anything
708 * else is unexpected.
709 */
710 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
711 enabled = state == DP_SSS_PWR_ON(pipe);
712
713 /*
714 * A transient state at this point would mean some unexpected party
715 * is poking at the power controls too.
716 */
717 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
718 WARN_ON(ctrl << 16 != state);
719
720 mutex_unlock(&dev_priv->rps.hw_lock);
721
722 return enabled;
723 }
724
725 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
726 struct i915_power_well *power_well,
727 bool enable)
728 {
729 enum pipe pipe = power_well->data;
730 u32 state;
731 u32 ctrl;
732
733 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
734
735 mutex_lock(&dev_priv->rps.hw_lock);
736
737 #define COND \
738 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
739
740 if (COND)
741 goto out;
742
743 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
744 ctrl &= ~DP_SSC_MASK(pipe);
745 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
746 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
747
748 if (wait_for(COND, 100))
749 DRM_ERROR("timout setting power well state %08x (%08x)\n",
750 state,
751 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
752
753 #undef COND
754
755 out:
756 mutex_unlock(&dev_priv->rps.hw_lock);
757 }
758
759 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
760 struct i915_power_well *power_well)
761 {
762 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
763 }
764
765 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
766 struct i915_power_well *power_well)
767 {
768 WARN_ON_ONCE(power_well->data != PIPE_A &&
769 power_well->data != PIPE_B &&
770 power_well->data != PIPE_C);
771
772 chv_set_pipe_power_well(dev_priv, power_well, true);
773
774 if (power_well->data == PIPE_A) {
775 spin_lock_irq(&dev_priv->irq_lock);
776 valleyview_enable_display_irqs(dev_priv);
777 spin_unlock_irq(&dev_priv->irq_lock);
778
779 /*
780 * During driver initialization/resume we can avoid restoring the
781 * part of the HW/SW state that will be inited anyway explicitly.
782 */
783 if (dev_priv->power_domains.initializing)
784 return;
785
786 intel_hpd_init(dev_priv);
787
788 i915_redisable_vga_power_on(dev_priv->dev);
789 }
790 }
791
792 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
793 struct i915_power_well *power_well)
794 {
795 WARN_ON_ONCE(power_well->data != PIPE_A &&
796 power_well->data != PIPE_B &&
797 power_well->data != PIPE_C);
798
799 if (power_well->data == PIPE_A) {
800 spin_lock_irq(&dev_priv->irq_lock);
801 valleyview_disable_display_irqs(dev_priv);
802 spin_unlock_irq(&dev_priv->irq_lock);
803 }
804
805 chv_set_pipe_power_well(dev_priv, power_well, false);
806
807 if (power_well->data == PIPE_A)
808 vlv_power_sequencer_reset(dev_priv);
809 }
810
811 /**
812 * intel_display_power_get - grab a power domain reference
813 * @dev_priv: i915 device instance
814 * @domain: power domain to reference
815 *
816 * This function grabs a power domain reference for @domain and ensures that the
817 * power domain and all its parents are powered up. Therefore users should only
818 * grab a reference to the innermost power domain they need.
819 *
820 * Any power domain reference obtained by this function must have a symmetric
821 * call to intel_display_power_put() to release the reference again.
822 */
823 void intel_display_power_get(struct drm_i915_private *dev_priv,
824 enum intel_display_power_domain domain)
825 {
826 struct i915_power_domains *power_domains;
827 struct i915_power_well *power_well;
828 int i;
829
830 intel_runtime_pm_get(dev_priv);
831
832 power_domains = &dev_priv->power_domains;
833
834 mutex_lock(&power_domains->lock);
835
836 for_each_power_well(i, power_well, BIT(domain), power_domains) {
837 if (!power_well->count++) {
838 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
839 power_well->ops->enable(dev_priv, power_well);
840 power_well->hw_enabled = true;
841 }
842 }
843
844 power_domains->domain_use_count[domain]++;
845
846 mutex_unlock(&power_domains->lock);
847 }
848
849 /**
850 * intel_display_power_put - release a power domain reference
851 * @dev_priv: i915 device instance
852 * @domain: power domain to reference
853 *
854 * This function drops the power domain reference obtained by
855 * intel_display_power_get() and might power down the corresponding hardware
856 * block right away if this is the last reference.
857 */
858 void intel_display_power_put(struct drm_i915_private *dev_priv,
859 enum intel_display_power_domain domain)
860 {
861 struct i915_power_domains *power_domains;
862 struct i915_power_well *power_well;
863 int i;
864
865 power_domains = &dev_priv->power_domains;
866
867 mutex_lock(&power_domains->lock);
868
869 WARN_ON(!power_domains->domain_use_count[domain]);
870 power_domains->domain_use_count[domain]--;
871
872 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
873 WARN_ON(!power_well->count);
874
875 if (!--power_well->count && i915.disable_power_well) {
876 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
877 power_well->hw_enabled = false;
878 power_well->ops->disable(dev_priv, power_well);
879 }
880 }
881
882 mutex_unlock(&power_domains->lock);
883
884 intel_runtime_pm_put(dev_priv);
885 }
886
887 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
888
889 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
890 BIT(POWER_DOMAIN_PIPE_A) | \
891 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
892 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
893 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
894 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
895 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
896 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
897 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
898 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
899 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
900 BIT(POWER_DOMAIN_PORT_CRT) | \
901 BIT(POWER_DOMAIN_PLLS) | \
902 BIT(POWER_DOMAIN_AUX_A) | \
903 BIT(POWER_DOMAIN_AUX_B) | \
904 BIT(POWER_DOMAIN_AUX_C) | \
905 BIT(POWER_DOMAIN_AUX_D) | \
906 BIT(POWER_DOMAIN_INIT))
907 #define HSW_DISPLAY_POWER_DOMAINS ( \
908 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
909 BIT(POWER_DOMAIN_INIT))
910
911 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
912 HSW_ALWAYS_ON_POWER_DOMAINS | \
913 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
914 #define BDW_DISPLAY_POWER_DOMAINS ( \
915 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
916 BIT(POWER_DOMAIN_INIT))
917
918 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
919 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
920
921 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
922 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
923 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
924 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
925 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
926 BIT(POWER_DOMAIN_PORT_CRT) | \
927 BIT(POWER_DOMAIN_AUX_B) | \
928 BIT(POWER_DOMAIN_AUX_C) | \
929 BIT(POWER_DOMAIN_INIT))
930
931 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
932 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
933 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
934 BIT(POWER_DOMAIN_AUX_B) | \
935 BIT(POWER_DOMAIN_INIT))
936
937 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
938 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
939 BIT(POWER_DOMAIN_AUX_B) | \
940 BIT(POWER_DOMAIN_INIT))
941
942 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
943 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
944 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
945 BIT(POWER_DOMAIN_AUX_C) | \
946 BIT(POWER_DOMAIN_INIT))
947
948 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
949 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
950 BIT(POWER_DOMAIN_AUX_C) | \
951 BIT(POWER_DOMAIN_INIT))
952
953 #define CHV_PIPE_A_POWER_DOMAINS ( \
954 BIT(POWER_DOMAIN_PIPE_A) | \
955 BIT(POWER_DOMAIN_INIT))
956
957 #define CHV_PIPE_B_POWER_DOMAINS ( \
958 BIT(POWER_DOMAIN_PIPE_B) | \
959 BIT(POWER_DOMAIN_INIT))
960
961 #define CHV_PIPE_C_POWER_DOMAINS ( \
962 BIT(POWER_DOMAIN_PIPE_C) | \
963 BIT(POWER_DOMAIN_INIT))
964
965 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
966 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
967 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
968 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
969 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
970 BIT(POWER_DOMAIN_AUX_B) | \
971 BIT(POWER_DOMAIN_AUX_C) | \
972 BIT(POWER_DOMAIN_INIT))
973
974 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
975 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
976 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
977 BIT(POWER_DOMAIN_AUX_D) | \
978 BIT(POWER_DOMAIN_INIT))
979
980 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
981 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
982 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
983 BIT(POWER_DOMAIN_AUX_D) | \
984 BIT(POWER_DOMAIN_INIT))
985
986 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
987 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
988 BIT(POWER_DOMAIN_AUX_D) | \
989 BIT(POWER_DOMAIN_INIT))
990
991 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
992 .sync_hw = i9xx_always_on_power_well_noop,
993 .enable = i9xx_always_on_power_well_noop,
994 .disable = i9xx_always_on_power_well_noop,
995 .is_enabled = i9xx_always_on_power_well_enabled,
996 };
997
998 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
999 .sync_hw = chv_pipe_power_well_sync_hw,
1000 .enable = chv_pipe_power_well_enable,
1001 .disable = chv_pipe_power_well_disable,
1002 .is_enabled = chv_pipe_power_well_enabled,
1003 };
1004
1005 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1006 .sync_hw = vlv_power_well_sync_hw,
1007 .enable = chv_dpio_cmn_power_well_enable,
1008 .disable = chv_dpio_cmn_power_well_disable,
1009 .is_enabled = vlv_power_well_enabled,
1010 };
1011
1012 static struct i915_power_well i9xx_always_on_power_well[] = {
1013 {
1014 .name = "always-on",
1015 .always_on = 1,
1016 .domains = POWER_DOMAIN_MASK,
1017 .ops = &i9xx_always_on_power_well_ops,
1018 },
1019 };
1020
1021 static const struct i915_power_well_ops hsw_power_well_ops = {
1022 .sync_hw = hsw_power_well_sync_hw,
1023 .enable = hsw_power_well_enable,
1024 .disable = hsw_power_well_disable,
1025 .is_enabled = hsw_power_well_enabled,
1026 };
1027
1028 static const struct i915_power_well_ops skl_power_well_ops = {
1029 .sync_hw = skl_power_well_sync_hw,
1030 .enable = skl_power_well_enable,
1031 .disable = skl_power_well_disable,
1032 .is_enabled = skl_power_well_enabled,
1033 };
1034
1035 static struct i915_power_well hsw_power_wells[] = {
1036 {
1037 .name = "always-on",
1038 .always_on = 1,
1039 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1040 .ops = &i9xx_always_on_power_well_ops,
1041 },
1042 {
1043 .name = "display",
1044 .domains = HSW_DISPLAY_POWER_DOMAINS,
1045 .ops = &hsw_power_well_ops,
1046 },
1047 };
1048
1049 static struct i915_power_well bdw_power_wells[] = {
1050 {
1051 .name = "always-on",
1052 .always_on = 1,
1053 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1054 .ops = &i9xx_always_on_power_well_ops,
1055 },
1056 {
1057 .name = "display",
1058 .domains = BDW_DISPLAY_POWER_DOMAINS,
1059 .ops = &hsw_power_well_ops,
1060 },
1061 };
1062
1063 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1064 .sync_hw = vlv_power_well_sync_hw,
1065 .enable = vlv_display_power_well_enable,
1066 .disable = vlv_display_power_well_disable,
1067 .is_enabled = vlv_power_well_enabled,
1068 };
1069
1070 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1071 .sync_hw = vlv_power_well_sync_hw,
1072 .enable = vlv_dpio_cmn_power_well_enable,
1073 .disable = vlv_dpio_cmn_power_well_disable,
1074 .is_enabled = vlv_power_well_enabled,
1075 };
1076
1077 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1078 .sync_hw = vlv_power_well_sync_hw,
1079 .enable = vlv_power_well_enable,
1080 .disable = vlv_power_well_disable,
1081 .is_enabled = vlv_power_well_enabled,
1082 };
1083
1084 static struct i915_power_well vlv_power_wells[] = {
1085 {
1086 .name = "always-on",
1087 .always_on = 1,
1088 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1089 .ops = &i9xx_always_on_power_well_ops,
1090 },
1091 {
1092 .name = "display",
1093 .domains = VLV_DISPLAY_POWER_DOMAINS,
1094 .data = PUNIT_POWER_WELL_DISP2D,
1095 .ops = &vlv_display_power_well_ops,
1096 },
1097 {
1098 .name = "dpio-tx-b-01",
1099 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1100 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1101 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1102 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1103 .ops = &vlv_dpio_power_well_ops,
1104 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1105 },
1106 {
1107 .name = "dpio-tx-b-23",
1108 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1109 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1110 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1111 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1112 .ops = &vlv_dpio_power_well_ops,
1113 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1114 },
1115 {
1116 .name = "dpio-tx-c-01",
1117 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1118 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1119 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1120 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1121 .ops = &vlv_dpio_power_well_ops,
1122 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1123 },
1124 {
1125 .name = "dpio-tx-c-23",
1126 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1127 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1128 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1129 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1130 .ops = &vlv_dpio_power_well_ops,
1131 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1132 },
1133 {
1134 .name = "dpio-common",
1135 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1136 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1137 .ops = &vlv_dpio_cmn_power_well_ops,
1138 },
1139 };
1140
1141 static struct i915_power_well chv_power_wells[] = {
1142 {
1143 .name = "always-on",
1144 .always_on = 1,
1145 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1146 .ops = &i9xx_always_on_power_well_ops,
1147 },
1148 #if 0
1149 {
1150 .name = "display",
1151 .domains = VLV_DISPLAY_POWER_DOMAINS,
1152 .data = PUNIT_POWER_WELL_DISP2D,
1153 .ops = &vlv_display_power_well_ops,
1154 },
1155 #endif
1156 {
1157 .name = "pipe-a",
1158 /*
1159 * FIXME: pipe A power well seems to be the new disp2d well.
1160 * At least all registers seem to be housed there. Figure
1161 * out if this a a temporary situation in pre-production
1162 * hardware or a permanent state of affairs.
1163 */
1164 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
1165 .data = PIPE_A,
1166 .ops = &chv_pipe_power_well_ops,
1167 },
1168 #if 0
1169 {
1170 .name = "pipe-b",
1171 .domains = CHV_PIPE_B_POWER_DOMAINS,
1172 .data = PIPE_B,
1173 .ops = &chv_pipe_power_well_ops,
1174 },
1175 {
1176 .name = "pipe-c",
1177 .domains = CHV_PIPE_C_POWER_DOMAINS,
1178 .data = PIPE_C,
1179 .ops = &chv_pipe_power_well_ops,
1180 },
1181 #endif
1182 {
1183 .name = "dpio-common-bc",
1184 /*
1185 * XXX: cmnreset for one PHY seems to disturb the other.
1186 * As a workaround keep both powered on at the same
1187 * time for now.
1188 */
1189 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
1190 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1191 .ops = &chv_dpio_cmn_power_well_ops,
1192 },
1193 {
1194 .name = "dpio-common-d",
1195 /*
1196 * XXX: cmnreset for one PHY seems to disturb the other.
1197 * As a workaround keep both powered on at the same
1198 * time for now.
1199 */
1200 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
1201 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1202 .ops = &chv_dpio_cmn_power_well_ops,
1203 },
1204 #if 0
1205 {
1206 .name = "dpio-tx-b-01",
1207 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1208 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1209 .ops = &vlv_dpio_power_well_ops,
1210 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1211 },
1212 {
1213 .name = "dpio-tx-b-23",
1214 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1215 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1216 .ops = &vlv_dpio_power_well_ops,
1217 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1218 },
1219 {
1220 .name = "dpio-tx-c-01",
1221 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1222 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1223 .ops = &vlv_dpio_power_well_ops,
1224 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1225 },
1226 {
1227 .name = "dpio-tx-c-23",
1228 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1229 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1230 .ops = &vlv_dpio_power_well_ops,
1231 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1232 },
1233 {
1234 .name = "dpio-tx-d-01",
1235 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1236 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1237 .ops = &vlv_dpio_power_well_ops,
1238 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
1239 },
1240 {
1241 .name = "dpio-tx-d-23",
1242 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1243 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1244 .ops = &vlv_dpio_power_well_ops,
1245 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
1246 },
1247 #endif
1248 };
1249
1250 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1251 enum punit_power_well power_well_id)
1252 {
1253 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1254 struct i915_power_well *power_well;
1255 int i;
1256
1257 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1258 if (power_well->data == power_well_id)
1259 return power_well;
1260 }
1261
1262 return NULL;
1263 }
1264
1265 static struct i915_power_well skl_power_wells[] = {
1266 {
1267 .name = "always-on",
1268 .always_on = 1,
1269 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1270 .ops = &i9xx_always_on_power_well_ops,
1271 },
1272 {
1273 .name = "power well 1",
1274 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1275 .ops = &skl_power_well_ops,
1276 .data = SKL_DISP_PW_1,
1277 },
1278 {
1279 .name = "MISC IO power well",
1280 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1281 .ops = &skl_power_well_ops,
1282 .data = SKL_DISP_PW_MISC_IO,
1283 },
1284 {
1285 .name = "power well 2",
1286 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1287 .ops = &skl_power_well_ops,
1288 .data = SKL_DISP_PW_2,
1289 },
1290 {
1291 .name = "DDI A/E power well",
1292 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1293 .ops = &skl_power_well_ops,
1294 .data = SKL_DISP_PW_DDI_A_E,
1295 },
1296 {
1297 .name = "DDI B power well",
1298 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1299 .ops = &skl_power_well_ops,
1300 .data = SKL_DISP_PW_DDI_B,
1301 },
1302 {
1303 .name = "DDI C power well",
1304 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1305 .ops = &skl_power_well_ops,
1306 .data = SKL_DISP_PW_DDI_C,
1307 },
1308 {
1309 .name = "DDI D power well",
1310 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1311 .ops = &skl_power_well_ops,
1312 .data = SKL_DISP_PW_DDI_D,
1313 },
1314 };
1315
1316 #define set_power_wells(power_domains, __power_wells) ({ \
1317 (power_domains)->power_wells = (__power_wells); \
1318 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1319 })
1320
1321 /**
1322 * intel_power_domains_init - initializes the power domain structures
1323 * @dev_priv: i915 device instance
1324 *
1325 * Initializes the power domain structures for @dev_priv depending upon the
1326 * supported platform.
1327 */
1328 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1329 {
1330 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1331
1332 mutex_init(&power_domains->lock);
1333
1334 /*
1335 * The enabling order will be from lower to higher indexed wells,
1336 * the disabling order is reversed.
1337 */
1338 if (IS_HASWELL(dev_priv->dev)) {
1339 set_power_wells(power_domains, hsw_power_wells);
1340 } else if (IS_BROADWELL(dev_priv->dev)) {
1341 set_power_wells(power_domains, bdw_power_wells);
1342 } else if (IS_SKYLAKE(dev_priv->dev)) {
1343 set_power_wells(power_domains, skl_power_wells);
1344 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1345 set_power_wells(power_domains, chv_power_wells);
1346 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1347 set_power_wells(power_domains, vlv_power_wells);
1348 } else {
1349 set_power_wells(power_domains, i9xx_always_on_power_well);
1350 }
1351
1352 return 0;
1353 }
1354
1355 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1356 {
1357 struct drm_device *dev = dev_priv->dev;
1358 struct device *device = &dev->pdev->dev;
1359
1360 if (!HAS_RUNTIME_PM(dev))
1361 return;
1362
1363 if (!intel_enable_rc6(dev))
1364 return;
1365
1366 /* Make sure we're not suspended first. */
1367 pm_runtime_get_sync(device);
1368 pm_runtime_disable(device);
1369 }
1370
1371 /**
1372 * intel_power_domains_fini - finalizes the power domain structures
1373 * @dev_priv: i915 device instance
1374 *
1375 * Finalizes the power domain structures for @dev_priv depending upon the
1376 * supported platform. This function also disables runtime pm and ensures that
1377 * the device stays powered up so that the driver can be reloaded.
1378 */
1379 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1380 {
1381 intel_runtime_pm_disable(dev_priv);
1382
1383 /* The i915.ko module is still not prepared to be loaded when
1384 * the power well is not enabled, so just enable it in case
1385 * we're going to unload/reload. */
1386 intel_display_set_init_power(dev_priv, true);
1387 }
1388
1389 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1390 {
1391 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1392 struct i915_power_well *power_well;
1393 int i;
1394
1395 mutex_lock(&power_domains->lock);
1396 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1397 power_well->ops->sync_hw(dev_priv, power_well);
1398 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1399 power_well);
1400 }
1401 mutex_unlock(&power_domains->lock);
1402 }
1403
1404 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1405 {
1406 struct i915_power_well *cmn =
1407 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1408 struct i915_power_well *disp2d =
1409 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1410
1411 /* If the display might be already active skip this */
1412 if (cmn->ops->is_enabled(dev_priv, cmn) &&
1413 disp2d->ops->is_enabled(dev_priv, disp2d) &&
1414 I915_READ(DPIO_CTL) & DPIO_CMNRST)
1415 return;
1416
1417 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1418
1419 /* cmnlane needs DPLL registers */
1420 disp2d->ops->enable(dev_priv, disp2d);
1421
1422 /*
1423 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1424 * Need to assert and de-assert PHY SB reset by gating the
1425 * common lane power, then un-gating it.
1426 * Simply ungating isn't enough to reset the PHY enough to get
1427 * ports and lanes running.
1428 */
1429 cmn->ops->disable(dev_priv, cmn);
1430 }
1431
1432 /**
1433 * intel_power_domains_init_hw - initialize hardware power domain state
1434 * @dev_priv: i915 device instance
1435 *
1436 * This function initializes the hardware power domain state and enables all
1437 * power domains using intel_display_set_init_power().
1438 */
1439 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1440 {
1441 struct drm_device *dev = dev_priv->dev;
1442 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1443
1444 power_domains->initializing = true;
1445
1446 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
1447 mutex_lock(&power_domains->lock);
1448 vlv_cmnlane_wa(dev_priv);
1449 mutex_unlock(&power_domains->lock);
1450 }
1451
1452 /* For now, we need the power well to be always enabled. */
1453 intel_display_set_init_power(dev_priv, true);
1454 intel_power_domains_resume(dev_priv);
1455 power_domains->initializing = false;
1456 }
1457
1458 /**
1459 * intel_aux_display_runtime_get - grab an auxiliary power domain reference
1460 * @dev_priv: i915 device instance
1461 *
1462 * This function grabs a power domain reference for the auxiliary power domain
1463 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1464 * parents are powered up. Therefore users should only grab a reference to the
1465 * innermost power domain they need.
1466 *
1467 * Any power domain reference obtained by this function must have a symmetric
1468 * call to intel_aux_display_runtime_put() to release the reference again.
1469 */
1470 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
1471 {
1472 intel_runtime_pm_get(dev_priv);
1473 }
1474
1475 /**
1476 * intel_aux_display_runtime_put - release an auxiliary power domain reference
1477 * @dev_priv: i915 device instance
1478 *
1479 * This function drops the auxiliary power domain reference obtained by
1480 * intel_aux_display_runtime_get() and might power down the corresponding
1481 * hardware block right away if this is the last reference.
1482 */
1483 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
1484 {
1485 intel_runtime_pm_put(dev_priv);
1486 }
1487
1488 /**
1489 * intel_runtime_pm_get - grab a runtime pm reference
1490 * @dev_priv: i915 device instance
1491 *
1492 * This function grabs a device-level runtime pm reference (mostly used for GEM
1493 * code to ensure the GTT or GT is on) and ensures that it is powered up.
1494 *
1495 * Any runtime pm reference obtained by this function must have a symmetric
1496 * call to intel_runtime_pm_put() to release the reference again.
1497 */
1498 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
1499 {
1500 struct drm_device *dev = dev_priv->dev;
1501 struct device *device = &dev->pdev->dev;
1502
1503 if (!HAS_RUNTIME_PM(dev))
1504 return;
1505
1506 pm_runtime_get_sync(device);
1507 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
1508 }
1509
1510 /**
1511 * intel_runtime_pm_get_noresume - grab a runtime pm reference
1512 * @dev_priv: i915 device instance
1513 *
1514 * This function grabs a device-level runtime pm reference (mostly used for GEM
1515 * code to ensure the GTT or GT is on).
1516 *
1517 * It will _not_ power up the device but instead only check that it's powered
1518 * on. Therefore it is only valid to call this functions from contexts where
1519 * the device is known to be powered up and where trying to power it up would
1520 * result in hilarity and deadlocks. That pretty much means only the system
1521 * suspend/resume code where this is used to grab runtime pm references for
1522 * delayed setup down in work items.
1523 *
1524 * Any runtime pm reference obtained by this function must have a symmetric
1525 * call to intel_runtime_pm_put() to release the reference again.
1526 */
1527 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
1528 {
1529 struct drm_device *dev = dev_priv->dev;
1530 struct device *device = &dev->pdev->dev;
1531
1532 if (!HAS_RUNTIME_PM(dev))
1533 return;
1534
1535 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
1536 pm_runtime_get_noresume(device);
1537 }
1538
1539 /**
1540 * intel_runtime_pm_put - release a runtime pm reference
1541 * @dev_priv: i915 device instance
1542 *
1543 * This function drops the device-level runtime pm reference obtained by
1544 * intel_runtime_pm_get() and might power down the corresponding
1545 * hardware block right away if this is the last reference.
1546 */
1547 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
1548 {
1549 struct drm_device *dev = dev_priv->dev;
1550 struct device *device = &dev->pdev->dev;
1551
1552 if (!HAS_RUNTIME_PM(dev))
1553 return;
1554
1555 pm_runtime_mark_last_busy(device);
1556 pm_runtime_put_autosuspend(device);
1557 }
1558
1559 /**
1560 * intel_runtime_pm_enable - enable runtime pm
1561 * @dev_priv: i915 device instance
1562 *
1563 * This function enables runtime pm at the end of the driver load sequence.
1564 *
1565 * Note that this function does currently not enable runtime pm for the
1566 * subordinate display power domains. That is only done on the first modeset
1567 * using intel_display_set_init_power().
1568 */
1569 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
1570 {
1571 struct drm_device *dev = dev_priv->dev;
1572 struct device *device = &dev->pdev->dev;
1573
1574 if (!HAS_RUNTIME_PM(dev))
1575 return;
1576
1577 pm_runtime_set_active(device);
1578
1579 /*
1580 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1581 * requirement.
1582 */
1583 if (!intel_enable_rc6(dev)) {
1584 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1585 return;
1586 }
1587
1588 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
1589 pm_runtime_mark_last_busy(device);
1590 pm_runtime_use_autosuspend(device);
1591
1592 pm_runtime_put_autosuspend(device);
1593 }
1594
Linux kernel - Deliverables
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