drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_plane_helper.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static bool
  42 format_is_yuv(uint32_t format)
  43 {
  44         switch (format) {
  45         case DRM_FORMAT_YUYV:
  46         case DRM_FORMAT_UYVY:
  47         case DRM_FORMAT_VYUY:
  48         case DRM_FORMAT_YVYU:
  49                 return true;
  50         default:
  51                 return false;
  52         }
  53 }
  54
  55 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
  56 {
  57         /* paranoia */
  58         if (!mode->crtc_htotal)
  59                 return 1;
  60
  61         return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
  62 }
  63
  64 /**
  65  * intel_pipe_update_start() - start update of a set of display registers
  66  * @crtc: the crtc of which the registers are going to be updated
  67  * @start_vbl_count: vblank counter return pointer used for error checking
  68  *
  69  * Mark the start of an update to pipe registers that should be updated
  70  * atomically regarding vblank. If the next vblank will happens within
  71  * the next 100 us, this function waits until the vblank passes.
  72  *
  73  * After a successful call to this function, interrupts will be disabled
  74  * until a subsequent call to intel_pipe_update_end(). That is done to
  75  * avoid random delays. The value written to @start_vbl_count should be
  76  * supplied to intel_pipe_update_end() for error checking.
  77  *
  78  * Return: true if the call was successful
  79  */
  80 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
  81 {
  82         struct drm_device *dev = crtc->base.dev;
  83         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
  84         enum pipe pipe = crtc->pipe;
  85         long timeout = msecs_to_jiffies_timeout(1);
  86         int scanline, min, max, vblank_start;
  87         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  88         DEFINE_WAIT(wait);
  89
  90         vblank_start = mode->crtc_vblank_start;
  91         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  92                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  93
  94         /* FIXME needs to be calibrated sensibly */
  95         min = vblank_start - usecs_to_scanlines(mode, 100);
  96         max = vblank_start - 1;
  97
  98         if (min <= 0 || max <= 0)
  99                 return false;
 100
 101         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 102                 return false;
 103
 104         local_irq_disable();
 105
 106         trace_i915_pipe_update_start(crtc, min, max);
 107
 108         for (;;) {
 109                 /*
 110                  * prepare_to_wait() has a memory barrier, which guarantees
 111                  * other CPUs can see the task state update by the time we
 112                  * read the scanline.
 113                  */
 114                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 115
 116                 scanline = intel_get_crtc_scanline(crtc);
 117                 if (scanline < min || scanline > max)
 118                         break;
 119
 120                 if (timeout <= 0) {
 121                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 122                                   pipe_name(crtc->pipe));
 123                         break;
 124                 }
 125
 126                 local_irq_enable();
 127
 128                 timeout = schedule_timeout(timeout);
 129
 130                 local_irq_disable();
 131         }
 132
 133         finish_wait(wq, &wait);
 134
 135         drm_crtc_vblank_put(&crtc->base);
 136
 137         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 138
 139         trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
 140
 141         return true;
 142 }
 143
 144 /**
 145  * intel_pipe_update_end() - end update of a set of display registers
 146  * @crtc: the crtc of which the registers were updated
 147  * @start_vbl_count: start vblank counter (used for error checking)
 148  *
 149  * Mark the end of an update started with intel_pipe_update_start(). This
 150  * re-enables interrupts and verifies the update was actually completed
 151  * before a vblank using the value of @start_vbl_count.
 152  */
 153 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
 154 {
 155         struct drm_device *dev = crtc->base.dev;
 156         enum pipe pipe = crtc->pipe;
 157         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 158
 159         trace_i915_pipe_update_end(crtc, end_vbl_count);
 160
 161         local_irq_enable();
 162
 163         if (start_vbl_count != end_vbl_count)
 164                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
 165                           pipe_name(pipe), start_vbl_count, end_vbl_count);
 166 }
 167
 168 static void intel_update_primary_plane(struct intel_crtc *crtc)
 169 {
 170         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 171         int reg = DSPCNTR(crtc->plane);
 172
 173         if (crtc->primary_enabled)
 174                 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 175         else
 176                 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 177 }
 178
 179 static void
 180 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 181                  struct drm_framebuffer *fb,
 182                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 183                  unsigned int crtc_w, unsigned int crtc_h,
 184                  uint32_t x, uint32_t y,
 185                  uint32_t src_w, uint32_t src_h)
 186 {
 187         struct drm_device *dev = drm_plane->dev;
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 190         const int pipe = intel_plane->pipe;
 191         const int plane = intel_plane->plane + 1;
 192         u32 plane_ctl, stride_div;
 193         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 194
 195         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
 196
 197         /* Mask out pixel format bits in case we change it */
 198         plane_ctl &= ~PLANE_CTL_FORMAT_MASK;
 199         plane_ctl &= ~PLANE_CTL_ORDER_RGBX;
 200         plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK;
 201         plane_ctl &= ~PLANE_CTL_TILED_MASK;
 202         plane_ctl &= ~PLANE_CTL_ALPHA_MASK;
 203         plane_ctl &= ~PLANE_CTL_ROTATE_MASK;
 204
 205         /* Trickle feed has to be enabled */
 206         plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE;
 207
 208         switch (fb->pixel_format) {
 209         case DRM_FORMAT_RGB565:
 210                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
 211                 break;
 212         case DRM_FORMAT_XBGR8888:
 213                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
 214                 break;
 215         case DRM_FORMAT_XRGB8888:
 216                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
 217                 break;
 218         /*
 219          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
 220          * to be already pre-multiplied. We need to add a knob (or a different
 221          * DRM_FORMAT) for user-space to configure that.
 222          */
 223         case DRM_FORMAT_ABGR8888:
 224                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
 225                              PLANE_CTL_ORDER_RGBX |
 226                              PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 227                 break;
 228         case DRM_FORMAT_ARGB8888:
 229                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
 230                              PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 231                 break;
 232         case DRM_FORMAT_YUYV:
 233                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
 234                 break;
 235         case DRM_FORMAT_YVYU:
 236                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
 237                 break;
 238         case DRM_FORMAT_UYVY:
 239                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
 240                 break;
 241         case DRM_FORMAT_VYUY:
 242                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 243                 break;
 244         default:
 245                 BUG();
 246         }
 247
 248         switch (fb->modifier[0]) {
 249         case DRM_FORMAT_MOD_NONE:
 250                 break;
 251         case I915_FORMAT_MOD_X_TILED:
 252                 plane_ctl |= PLANE_CTL_TILED_X;
 253                 break;
 254         case I915_FORMAT_MOD_Y_TILED:
 255                 plane_ctl |= PLANE_CTL_TILED_Y;
 256                 break;
 257         case I915_FORMAT_MOD_Yf_TILED:
 258                 plane_ctl |= PLANE_CTL_TILED_YF;
 259                 break;
 260         default:
 261                 MISSING_CASE(fb->modifier[0]);
 262         }
 263
 264         if (drm_plane->state->rotation == BIT(DRM_ROTATE_180))
 265                 plane_ctl |= PLANE_CTL_ROTATE_180;
 266
 267         plane_ctl |= PLANE_CTL_ENABLE;
 268         plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 269
 270         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 271                                        pixel_size, true,
 272                                        src_w != crtc_w || src_h != crtc_h);
 273
 274         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
 275                                                fb->pixel_format);
 276
 277         /* Sizes are 0 based */
 278         src_w--;
 279         src_h--;
 280         crtc_w--;
 281         crtc_h--;
 282
 283         I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
 284         I915_WRITE(PLANE_STRIDE(pipe, plane), fb->pitches[0] / stride_div);
 285         I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 286         I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 287         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 288         I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj));
 289         POSTING_READ(PLANE_SURF(pipe, plane));
 290 }
 291
 292 static void
 293 skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
 294 {
 295         struct drm_device *dev = drm_plane->dev;
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 298         const int pipe = intel_plane->pipe;
 299         const int plane = intel_plane->plane + 1;
 300
 301         I915_WRITE(PLANE_CTL(pipe, plane),
 302                    I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE);
 303
 304         /* Activate double buffered register update */
 305         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 306         POSTING_READ(PLANE_CTL(pipe, plane));
 307
 308         intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false);
 309 }
 310
 311 static int
 312 skl_update_colorkey(struct drm_plane *drm_plane,
 313                     struct drm_intel_sprite_colorkey *key)
 314 {
 315         struct drm_device *dev = drm_plane->dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 318         const int pipe = intel_plane->pipe;
 319         const int plane = intel_plane->plane;
 320         u32 plane_ctl;
 321
 322         I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 323         I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 324         I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 325
 326         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
 327         plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK;
 328         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 329                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 330         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 331                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 332         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 333
 334         POSTING_READ(PLANE_CTL(pipe, plane));
 335
 336         return 0;
 337 }
 338
 339 static void
 340 skl_get_colorkey(struct drm_plane *drm_plane,
 341                  struct drm_intel_sprite_colorkey *key)
 342 {
 343         struct drm_device *dev = drm_plane->dev;
 344         struct drm_i915_private *dev_priv = dev->dev_private;
 345         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 346         const int pipe = intel_plane->pipe;
 347         const int plane = intel_plane->plane;
 348         u32 plane_ctl;
 349
 350         key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane));
 351         key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane));
 352         key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane));
 353
 354         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
 355
 356         switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MASK) {
 357         case PLANE_CTL_KEY_ENABLE_DESTINATION:
 358                 key->flags = I915_SET_COLORKEY_DESTINATION;
 359                 break;
 360         case PLANE_CTL_KEY_ENABLE_SOURCE:
 361                 key->flags = I915_SET_COLORKEY_SOURCE;
 362                 break;
 363         default:
 364                 key->flags = I915_SET_COLORKEY_NONE;
 365         }
 366 }
 367
 368 static void
 369 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 370 {
 371         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 372         int plane = intel_plane->plane;
 373
 374         /* Seems RGB data bypasses the CSC always */
 375         if (!format_is_yuv(format))
 376                 return;
 377
 378         /*
 379          * BT.601 limited range YCbCr -> full range RGB
 380          *
 381          * |r|   | 6537 4769     0|   |cr  |
 382          * |g| = |-3330 4769 -1605| x |y-64|
 383          * |b|   |    0 4769  8263|   |cb  |
 384          *
 385          * Cb and Cr apparently come in as signed already, so no
 386          * need for any offset. For Y we need to remove the offset.
 387          */
 388         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 389         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 390         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 391
 392         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 393         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 394         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 395         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 396         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 397
 398         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 399         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 400         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 401
 402         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 403         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 404         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 405 }
 406
 407 static void
 408 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 409                  struct drm_framebuffer *fb,
 410                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 411                  unsigned int crtc_w, unsigned int crtc_h,
 412                  uint32_t x, uint32_t y,
 413                  uint32_t src_w, uint32_t src_h)
 414 {
 415         struct drm_device *dev = dplane->dev;
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         struct intel_plane *intel_plane = to_intel_plane(dplane);
 418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 419         int pipe = intel_plane->pipe;
 420         int plane = intel_plane->plane;
 421         u32 sprctl;
 422         unsigned long sprsurf_offset, linear_offset;
 423         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 424
 425         sprctl = I915_READ(SPCNTR(pipe, plane));
 426
 427         /* Mask out pixel format bits in case we change it */
 428         sprctl &= ~SP_PIXFORMAT_MASK;
 429         sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
 430         sprctl &= ~SP_TILED;
 431         sprctl &= ~SP_ROTATE_180;
 432
 433         switch (fb->pixel_format) {
 434         case DRM_FORMAT_YUYV:
 435                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 436                 break;
 437         case DRM_FORMAT_YVYU:
 438                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 439                 break;
 440         case DRM_FORMAT_UYVY:
 441                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 442                 break;
 443         case DRM_FORMAT_VYUY:
 444                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 445                 break;
 446         case DRM_FORMAT_RGB565:
 447                 sprctl |= SP_FORMAT_BGR565;
 448                 break;
 449         case DRM_FORMAT_XRGB8888:
 450                 sprctl |= SP_FORMAT_BGRX8888;
 451                 break;
 452         case DRM_FORMAT_ARGB8888:
 453                 sprctl |= SP_FORMAT_BGRA8888;
 454                 break;
 455         case DRM_FORMAT_XBGR2101010:
 456                 sprctl |= SP_FORMAT_RGBX1010102;
 457                 break;
 458         case DRM_FORMAT_ABGR2101010:
 459                 sprctl |= SP_FORMAT_RGBA1010102;
 460                 break;
 461         case DRM_FORMAT_XBGR8888:
 462                 sprctl |= SP_FORMAT_RGBX8888;
 463                 break;
 464         case DRM_FORMAT_ABGR8888:
 465                 sprctl |= SP_FORMAT_RGBA8888;
 466                 break;
 467         default:
 468                 /*
 469                  * If we get here one of the upper layers failed to filter
 470                  * out the unsupported plane formats
 471                  */
 472                 BUG();
 473                 break;
 474         }
 475
 476         /*
 477          * Enable gamma to match primary/cursor plane behaviour.
 478          * FIXME should be user controllable via propertiesa.
 479          */
 480         sprctl |= SP_GAMMA_ENABLE;
 481
 482         if (obj->tiling_mode != I915_TILING_NONE)
 483                 sprctl |= SP_TILED;
 484
 485         sprctl |= SP_ENABLE;
 486
 487         intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
 488                                        pixel_size, true,
 489                                        src_w != crtc_w || src_h != crtc_h);
 490
 491         /* Sizes are 0 based */
 492         src_w--;
 493         src_h--;
 494         crtc_w--;
 495         crtc_h--;
 496
 497         linear_offset = y * fb->pitches[0] + x * pixel_size;
 498         sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
 499                                                         obj->tiling_mode,
 500                                                         pixel_size,
 501                                                         fb->pitches[0]);
 502         linear_offset -= sprsurf_offset;
 503
 504         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
 505                 sprctl |= SP_ROTATE_180;
 506
 507                 x += src_w;
 508                 y += src_h;
 509                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 510         }
 511
 512         intel_update_primary_plane(intel_crtc);
 513
 514         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 515                 chv_update_csc(intel_plane, fb->pixel_format);
 516
 517         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 518         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 519
 520         if (obj->tiling_mode != I915_TILING_NONE)
 521                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 522         else
 523                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 524
 525         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 526
 527         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 528         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 529         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 530                    sprsurf_offset);
 531
 532         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 533 }
 534
 535 static void
 536 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 537 {
 538         struct drm_device *dev = dplane->dev;
 539         struct drm_i915_private *dev_priv = dev->dev_private;
 540         struct intel_plane *intel_plane = to_intel_plane(dplane);
 541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 542         int pipe = intel_plane->pipe;
 543         int plane = intel_plane->plane;
 544
 545         intel_update_primary_plane(intel_crtc);
 546
 547         I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
 548                    ~SP_ENABLE);
 549         /* Activate double buffered register update */
 550         I915_WRITE(SPSURF(pipe, plane), 0);
 551
 552         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 553
 554         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 555 }
 556
 557 static int
 558 vlv_update_colorkey(struct drm_plane *dplane,
 559                     struct drm_intel_sprite_colorkey *key)
 560 {
 561         struct drm_device *dev = dplane->dev;
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         struct intel_plane *intel_plane = to_intel_plane(dplane);
 564         int pipe = intel_plane->pipe;
 565         int plane = intel_plane->plane;
 566         u32 sprctl;
 567
 568         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 569                 return -EINVAL;
 570
 571         I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 572         I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 573         I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 574
 575         sprctl = I915_READ(SPCNTR(pipe, plane));
 576         sprctl &= ~SP_SOURCE_KEY;
 577         if (key->flags & I915_SET_COLORKEY_SOURCE)
 578                 sprctl |= SP_SOURCE_KEY;
 579         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 580
 581         POSTING_READ(SPKEYMSK(pipe, plane));
 582
 583         return 0;
 584 }
 585
 586 static void
 587 vlv_get_colorkey(struct drm_plane *dplane,
 588                  struct drm_intel_sprite_colorkey *key)
 589 {
 590         struct drm_device *dev = dplane->dev;
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592         struct intel_plane *intel_plane = to_intel_plane(dplane);
 593         int pipe = intel_plane->pipe;
 594         int plane = intel_plane->plane;
 595         u32 sprctl;
 596
 597         key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
 598         key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
 599         key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
 600
 601         sprctl = I915_READ(SPCNTR(pipe, plane));
 602         if (sprctl & SP_SOURCE_KEY)
 603                 key->flags = I915_SET_COLORKEY_SOURCE;
 604         else
 605                 key->flags = I915_SET_COLORKEY_NONE;
 606 }
 607
 608 static void
 609 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 610                  struct drm_framebuffer *fb,
 611                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 612                  unsigned int crtc_w, unsigned int crtc_h,
 613                  uint32_t x, uint32_t y,
 614                  uint32_t src_w, uint32_t src_h)
 615 {
 616         struct drm_device *dev = plane->dev;
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618         struct intel_plane *intel_plane = to_intel_plane(plane);
 619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 620         int pipe = intel_plane->pipe;
 621         u32 sprctl, sprscale = 0;
 622         unsigned long sprsurf_offset, linear_offset;
 623         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 624
 625         sprctl = I915_READ(SPRCTL(pipe));
 626
 627         /* Mask out pixel format bits in case we change it */
 628         sprctl &= ~SPRITE_PIXFORMAT_MASK;
 629         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
 630         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
 631         sprctl &= ~SPRITE_TILED;
 632         sprctl &= ~SPRITE_ROTATE_180;
 633
 634         switch (fb->pixel_format) {
 635         case DRM_FORMAT_XBGR8888:
 636                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 637                 break;
 638         case DRM_FORMAT_XRGB8888:
 639                 sprctl |= SPRITE_FORMAT_RGBX888;
 640                 break;
 641         case DRM_FORMAT_YUYV:
 642                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 643                 break;
 644         case DRM_FORMAT_YVYU:
 645                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 646                 break;
 647         case DRM_FORMAT_UYVY:
 648                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 649                 break;
 650         case DRM_FORMAT_VYUY:
 651                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 652                 break;
 653         default:
 654                 BUG();
 655         }
 656
 657         /*
 658          * Enable gamma to match primary/cursor plane behaviour.
 659          * FIXME should be user controllable via propertiesa.
 660          */
 661         sprctl |= SPRITE_GAMMA_ENABLE;
 662
 663         if (obj->tiling_mode != I915_TILING_NONE)
 664                 sprctl |= SPRITE_TILED;
 665
 666         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 667                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 668         else
 669                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 670
 671         sprctl |= SPRITE_ENABLE;
 672
 673         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 674                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 675
 676         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 677                                        true,
 678                                        src_w != crtc_w || src_h != crtc_h);
 679
 680         /* Sizes are 0 based */
 681         src_w--;
 682         src_h--;
 683         crtc_w--;
 684         crtc_h--;
 685
 686         if (crtc_w != src_w || crtc_h != src_h)
 687                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 688
 689         linear_offset = y * fb->pitches[0] + x * pixel_size;
 690         sprsurf_offset =
 691                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 692                                                pixel_size, fb->pitches[0]);
 693         linear_offset -= sprsurf_offset;
 694
 695         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 696                 sprctl |= SPRITE_ROTATE_180;
 697
 698                 /* HSW and BDW does this automagically in hardware */
 699                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 700                         x += src_w;
 701                         y += src_h;
 702                         linear_offset += src_h * fb->pitches[0] +
 703                                 src_w * pixel_size;
 704                 }
 705         }
 706
 707         intel_update_primary_plane(intel_crtc);
 708
 709         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 710         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 711
 712         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 713          * register */
 714         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 715                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 716         else if (obj->tiling_mode != I915_TILING_NONE)
 717                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 718         else
 719                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 720
 721         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 722         if (intel_plane->can_scale)
 723                 I915_WRITE(SPRSCALE(pipe), sprscale);
 724         I915_WRITE(SPRCTL(pipe), sprctl);
 725         I915_WRITE(SPRSURF(pipe),
 726                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 727
 728         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 729 }
 730
 731 static void
 732 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 733 {
 734         struct drm_device *dev = plane->dev;
 735         struct drm_i915_private *dev_priv = dev->dev_private;
 736         struct intel_plane *intel_plane = to_intel_plane(plane);
 737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 738         int pipe = intel_plane->pipe;
 739
 740         intel_update_primary_plane(intel_crtc);
 741
 742         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 743         /* Can't leave the scaler enabled... */
 744         if (intel_plane->can_scale)
 745                 I915_WRITE(SPRSCALE(pipe), 0);
 746         /* Activate double buffered register update */
 747         I915_WRITE(SPRSURF(pipe), 0);
 748
 749         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 750
 751         /*
 752          * Avoid underruns when disabling the sprite.
 753          * FIXME remove once watermark updates are done properly.
 754          */
 755         intel_crtc->atomic.wait_vblank = true;
 756         intel_crtc->atomic.update_sprite_watermarks |= (1 << drm_plane_index(plane));
 757 }
 758
 759 static int
 760 ivb_update_colorkey(struct drm_plane *plane,
 761                     struct drm_intel_sprite_colorkey *key)
 762 {
 763         struct drm_device *dev = plane->dev;
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         struct intel_plane *intel_plane;
 766         u32 sprctl;
 767         int ret = 0;
 768
 769         intel_plane = to_intel_plane(plane);
 770
 771         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 772         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 773         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 774
 775         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 776         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 777         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 778                 sprctl |= SPRITE_DEST_KEY;
 779         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 780                 sprctl |= SPRITE_SOURCE_KEY;
 781         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 782
 783         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 784
 785         return ret;
 786 }
 787
 788 static void
 789 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 790 {
 791         struct drm_device *dev = plane->dev;
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793         struct intel_plane *intel_plane;
 794         u32 sprctl;
 795
 796         intel_plane = to_intel_plane(plane);
 797
 798         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 799         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 800         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 801         key->flags = 0;
 802
 803         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 804
 805         if (sprctl & SPRITE_DEST_KEY)
 806                 key->flags = I915_SET_COLORKEY_DESTINATION;
 807         else if (sprctl & SPRITE_SOURCE_KEY)
 808                 key->flags = I915_SET_COLORKEY_SOURCE;
 809         else
 810                 key->flags = I915_SET_COLORKEY_NONE;
 811 }
 812
 813 static void
 814 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 815                  struct drm_framebuffer *fb,
 816                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 817                  unsigned int crtc_w, unsigned int crtc_h,
 818                  uint32_t x, uint32_t y,
 819                  uint32_t src_w, uint32_t src_h)
 820 {
 821         struct drm_device *dev = plane->dev;
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         struct intel_plane *intel_plane = to_intel_plane(plane);
 824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 825         int pipe = intel_plane->pipe;
 826         unsigned long dvssurf_offset, linear_offset;
 827         u32 dvscntr, dvsscale;
 828         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 829
 830         dvscntr = I915_READ(DVSCNTR(pipe));
 831
 832         /* Mask out pixel format bits in case we change it */
 833         dvscntr &= ~DVS_PIXFORMAT_MASK;
 834         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 835         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 836         dvscntr &= ~DVS_TILED;
 837         dvscntr &= ~DVS_ROTATE_180;
 838
 839         switch (fb->pixel_format) {
 840         case DRM_FORMAT_XBGR8888:
 841                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 842                 break;
 843         case DRM_FORMAT_XRGB8888:
 844                 dvscntr |= DVS_FORMAT_RGBX888;
 845                 break;
 846         case DRM_FORMAT_YUYV:
 847                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 848                 break;
 849         case DRM_FORMAT_YVYU:
 850                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 851                 break;
 852         case DRM_FORMAT_UYVY:
 853                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 854                 break;
 855         case DRM_FORMAT_VYUY:
 856                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 857                 break;
 858         default:
 859                 BUG();
 860         }
 861
 862         /*
 863          * Enable gamma to match primary/cursor plane behaviour.
 864          * FIXME should be user controllable via propertiesa.
 865          */
 866         dvscntr |= DVS_GAMMA_ENABLE;
 867
 868         if (obj->tiling_mode != I915_TILING_NONE)
 869                 dvscntr |= DVS_TILED;
 870
 871         if (IS_GEN6(dev))
 872                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 873         dvscntr |= DVS_ENABLE;
 874
 875         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 876                                        pixel_size, true,
 877                                        src_w != crtc_w || src_h != crtc_h);
 878
 879         /* Sizes are 0 based */
 880         src_w--;
 881         src_h--;
 882         crtc_w--;
 883         crtc_h--;
 884
 885         dvsscale = 0;
 886         if (crtc_w != src_w || crtc_h != src_h)
 887                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 888
 889         linear_offset = y * fb->pitches[0] + x * pixel_size;
 890         dvssurf_offset =
 891                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 892                                                pixel_size, fb->pitches[0]);
 893         linear_offset -= dvssurf_offset;
 894
 895         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 896                 dvscntr |= DVS_ROTATE_180;
 897
 898                 x += src_w;
 899                 y += src_h;
 900                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 901         }
 902
 903         intel_update_primary_plane(intel_crtc);
 904
 905         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 906         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 907
 908         if (obj->tiling_mode != I915_TILING_NONE)
 909                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 910         else
 911                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 912
 913         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 914         I915_WRITE(DVSSCALE(pipe), dvsscale);
 915         I915_WRITE(DVSCNTR(pipe), dvscntr);
 916         I915_WRITE(DVSSURF(pipe),
 917                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 918
 919         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 920 }
 921
 922 static void
 923 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 924 {
 925         struct drm_device *dev = plane->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         struct intel_plane *intel_plane = to_intel_plane(plane);
 928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 929         int pipe = intel_plane->pipe;
 930
 931         intel_update_primary_plane(intel_crtc);
 932
 933         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 934         /* Disable the scaler */
 935         I915_WRITE(DVSSCALE(pipe), 0);
 936         /* Flush double buffered register updates */
 937         I915_WRITE(DVSSURF(pipe), 0);
 938
 939         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 940
 941         /*
 942          * Avoid underruns when disabling the sprite.
 943          * FIXME remove once watermark updates are done properly.
 944          */
 945         intel_crtc->atomic.wait_vblank = true;
 946         intel_crtc->atomic.update_sprite_watermarks |= (1 << drm_plane_index(plane));
 947 }
 948
 949 /**
 950  * intel_post_enable_primary - Perform operations after enabling primary plane
 951  * @crtc: the CRTC whose primary plane was just enabled
 952  *
 953  * Performs potentially sleeping operations that must be done after the primary
 954  * plane is enabled, such as updating FBC and IPS.  Note that this may be
 955  * called due to an explicit primary plane update, or due to an implicit
 956  * re-enable that is caused when a sprite plane is updated to no longer
 957  * completely hide the primary plane.
 958  */
 959 void
 960 intel_post_enable_primary(struct drm_crtc *crtc)
 961 {
 962         struct drm_device *dev = crtc->dev;
 963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 964
 965         /*
 966          * BDW signals flip done immediately if the plane
 967          * is disabled, even if the plane enable is already
 968          * armed to occur at the next vblank :(
 969          */
 970         if (IS_BROADWELL(dev))
 971                 intel_wait_for_vblank(dev, intel_crtc->pipe);
 972
 973         /*
 974          * FIXME IPS should be fine as long as one plane is
 975          * enabled, but in practice it seems to have problems
 976          * when going from primary only to sprite only and vice
 977          * versa.
 978          */
 979         hsw_enable_ips(intel_crtc);
 980
 981         mutex_lock(&dev->struct_mutex);
 982         intel_fbc_update(dev);
 983         mutex_unlock(&dev->struct_mutex);
 984 }
 985
 986 /**
 987  * intel_pre_disable_primary - Perform operations before disabling primary plane
 988  * @crtc: the CRTC whose primary plane is to be disabled
 989  *
 990  * Performs potentially sleeping operations that must be done before the
 991  * primary plane is enabled, such as updating FBC and IPS.  Note that this may
 992  * be called due to an explicit primary plane update, or due to an implicit
 993  * disable that is caused when a sprite plane completely hides the primary
 994  * plane.
 995  */
 996 void
 997 intel_pre_disable_primary(struct drm_crtc *crtc)
 998 {
 999         struct drm_device *dev = crtc->dev;
1000         struct drm_i915_private *dev_priv = dev->dev_private;
1001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1002
1003         mutex_lock(&dev->struct_mutex);
1004         if (dev_priv->fbc.crtc == intel_crtc)
1005                 intel_fbc_disable(dev);
1006         mutex_unlock(&dev->struct_mutex);
1007
1008         /*
1009          * FIXME IPS should be fine as long as one plane is
1010          * enabled, but in practice it seems to have problems
1011          * when going from primary only to sprite only and vice
1012          * versa.
1013          */
1014         hsw_disable_ips(intel_crtc);
1015 }
1016
1017 static int
1018 ilk_update_colorkey(struct drm_plane *plane,
1019                     struct drm_intel_sprite_colorkey *key)
1020 {
1021         struct drm_device *dev = plane->dev;
1022         struct drm_i915_private *dev_priv = dev->dev_private;
1023         struct intel_plane *intel_plane;
1024         u32 dvscntr;
1025         int ret = 0;
1026
1027         intel_plane = to_intel_plane(plane);
1028
1029         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
1030         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
1031         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
1032
1033         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
1034         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
1035         if (key->flags & I915_SET_COLORKEY_DESTINATION)
1036                 dvscntr |= DVS_DEST_KEY;
1037         else if (key->flags & I915_SET_COLORKEY_SOURCE)
1038                 dvscntr |= DVS_SOURCE_KEY;
1039         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
1040
1041         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
1042
1043         return ret;
1044 }
1045
1046 static void
1047 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
1048 {
1049         struct drm_device *dev = plane->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         struct intel_plane *intel_plane;
1052         u32 dvscntr;
1053
1054         intel_plane = to_intel_plane(plane);
1055
1056         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
1057         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
1058         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
1059         key->flags = 0;
1060
1061         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
1062
1063         if (dvscntr & DVS_DEST_KEY)
1064                 key->flags = I915_SET_COLORKEY_DESTINATION;
1065         else if (dvscntr & DVS_SOURCE_KEY)
1066                 key->flags = I915_SET_COLORKEY_SOURCE;
1067         else
1068                 key->flags = I915_SET_COLORKEY_NONE;
1069 }
1070
1071 static bool colorkey_enabled(struct intel_plane *intel_plane)
1072 {
1073         struct drm_intel_sprite_colorkey key;
1074
1075         intel_plane->get_colorkey(&intel_plane->base, &key);
1076
1077         return key.flags != I915_SET_COLORKEY_NONE;
1078 }
1079
1080 static int
1081 intel_check_sprite_plane(struct drm_plane *plane,
1082                          struct intel_plane_state *state)
1083 {
1084         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
1085         struct intel_plane *intel_plane = to_intel_plane(plane);
1086         struct drm_framebuffer *fb = state->base.fb;
1087         int crtc_x, crtc_y;
1088         unsigned int crtc_w, crtc_h;
1089         uint32_t src_x, src_y, src_w, src_h;
1090         struct drm_rect *src = &state->src;
1091         struct drm_rect *dst = &state->dst;
1092         const struct drm_rect *clip = &state->clip;
1093         int hscale, vscale;
1094         int max_scale, min_scale;
1095         int pixel_size;
1096
1097         intel_crtc = intel_crtc ? intel_crtc : to_intel_crtc(plane->crtc);
1098
1099         if (!fb) {
1100                 state->visible = false;
1101                 goto finish;
1102         }
1103
1104         /* Don't modify another pipe's plane */
1105         if (intel_plane->pipe != intel_crtc->pipe) {
1106                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
1107                 return -EINVAL;
1108         }
1109
1110         /* FIXME check all gen limits */
1111         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
1112                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
1113                 return -EINVAL;
1114         }
1115
1116         /*
1117          * FIXME the following code does a bunch of fuzzy adjustments to the
1118          * coordinates and sizes. We probably need some way to decide whether
1119          * more strict checking should be done instead.
1120          */
1121         max_scale = intel_plane->max_downscale << 16;
1122         min_scale = intel_plane->can_scale ? 1 : (1 << 16);
1123
1124         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
1125                         state->base.rotation);
1126
1127         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
1128         BUG_ON(hscale < 0);
1129
1130         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
1131         BUG_ON(vscale < 0);
1132
1133         state->visible =  drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
1134
1135         crtc_x = dst->x1;
1136         crtc_y = dst->y1;
1137         crtc_w = drm_rect_width(dst);
1138         crtc_h = drm_rect_height(dst);
1139
1140         if (state->visible) {
1141                 /* check again in case clipping clamped the results */
1142                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
1143                 if (hscale < 0) {
1144                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
1145                         drm_rect_debug_print(src, true);
1146                         drm_rect_debug_print(dst, false);
1147
1148                         return hscale;
1149                 }
1150
1151                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
1152                 if (vscale < 0) {
1153                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
1154                         drm_rect_debug_print(src, true);
1155                         drm_rect_debug_print(dst, false);
1156
1157                         return vscale;
1158                 }
1159
1160                 /* Make the source viewport size an exact multiple of the scaling factors. */
1161                 drm_rect_adjust_size(src,
1162                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
1163                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
1164
1165                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1166                                     state->base.rotation);
1167
1168                 /* sanity check to make sure the src viewport wasn't enlarged */
1169                 WARN_ON(src->x1 < (int) state->base.src_x ||
1170                         src->y1 < (int) state->base.src_y ||
1171                         src->x2 > (int) state->base.src_x + state->base.src_w ||
1172                         src->y2 > (int) state->base.src_y + state->base.src_h);
1173
1174                 /*
1175                  * Hardware doesn't handle subpixel coordinates.
1176                  * Adjust to (macro)pixel boundary, but be careful not to
1177                  * increase the source viewport size, because that could
1178                  * push the downscaling factor out of bounds.
1179                  */
1180                 src_x = src->x1 >> 16;
1181                 src_w = drm_rect_width(src) >> 16;
1182                 src_y = src->y1 >> 16;
1183                 src_h = drm_rect_height(src) >> 16;
1184
1185                 if (format_is_yuv(fb->pixel_format)) {
1186                         src_x &= ~1;
1187                         src_w &= ~1;
1188
1189                         /*
1190                          * Must keep src and dst the
1191                          * same if we can't scale.
1192                          */
1193                         if (!intel_plane->can_scale)
1194                                 crtc_w &= ~1;
1195
1196                         if (crtc_w == 0)
1197                                 state->visible = false;
1198                 }
1199         }
1200
1201         /* Check size restrictions when scaling */
1202         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
1203                 unsigned int width_bytes;
1204
1205                 WARN_ON(!intel_plane->can_scale);
1206
1207                 /* FIXME interlacing min height is 6 */
1208
1209                 if (crtc_w < 3 || crtc_h < 3)
1210                         state->visible = false;
1211
1212                 if (src_w < 3 || src_h < 3)
1213                         state->visible = false;
1214
1215                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
1216                 width_bytes = ((src_x * pixel_size) & 63) +
1217                                         src_w * pixel_size;
1218
1219                 if (src_w > 2048 || src_h > 2048 ||
1220                     width_bytes > 4096 || fb->pitches[0] > 4096) {
1221                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1222                         return -EINVAL;
1223                 }
1224         }
1225
1226         if (state->visible) {
1227                 src->x1 = src_x;
1228                 src->x2 = src_x + src_w;
1229                 src->y1 = src_y;
1230                 src->y2 = src_y + src_h;
1231         }
1232
1233         dst->x1 = crtc_x;
1234         dst->x2 = crtc_x + crtc_w;
1235         dst->y1 = crtc_y;
1236         dst->y2 = crtc_y + crtc_h;
1237
1238 finish:
1239         /*
1240          * If the sprite is completely covering the primary plane,
1241          * we can disable the primary and save power.
1242          */
1243         state->hides_primary = fb != NULL && drm_rect_equals(dst, clip) &&
1244                 !colorkey_enabled(intel_plane);
1245         WARN_ON(state->hides_primary && !state->visible && intel_crtc->active);
1246
1247         if (intel_crtc->active) {
1248                 if (intel_crtc->primary_enabled == state->hides_primary)
1249                         intel_crtc->atomic.wait_for_flips = true;
1250
1251                 if (intel_crtc->primary_enabled && state->hides_primary)
1252                         intel_crtc->atomic.pre_disable_primary = true;
1253
1254                 intel_crtc->atomic.fb_bits |=
1255                         INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
1256
1257                 if (!intel_crtc->primary_enabled && !state->hides_primary)
1258                         intel_crtc->atomic.post_enable_primary = true;
1259         }
1260
1261         return 0;
1262 }
1263
1264 static void
1265 intel_commit_sprite_plane(struct drm_plane *plane,
1266                           struct intel_plane_state *state)
1267 {
1268         struct drm_crtc *crtc = state->base.crtc;
1269         struct intel_crtc *intel_crtc;
1270         struct intel_plane *intel_plane = to_intel_plane(plane);
1271         struct drm_framebuffer *fb = state->base.fb;
1272         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1273         int crtc_x, crtc_y;
1274         unsigned int crtc_w, crtc_h;
1275         uint32_t src_x, src_y, src_w, src_h;
1276
1277         crtc = crtc ? crtc : plane->crtc;
1278         intel_crtc = to_intel_crtc(crtc);
1279
1280         plane->fb = state->base.fb;
1281         intel_plane->obj = obj;
1282
1283         if (intel_crtc->active) {
1284                 intel_crtc->primary_enabled = !state->hides_primary;
1285
1286                 if (state->visible) {
1287                         crtc_x = state->dst.x1;
1288                         crtc_y = state->dst.y1;
1289                         crtc_w = drm_rect_width(&state->dst);
1290                         crtc_h = drm_rect_height(&state->dst);
1291                         src_x = state->src.x1;
1292                         src_y = state->src.y1;
1293                         src_w = drm_rect_width(&state->src);
1294                         src_h = drm_rect_height(&state->src);
1295                         intel_plane->update_plane(plane, crtc, fb, obj,
1296                                                   crtc_x, crtc_y, crtc_w, crtc_h,
1297                                                   src_x, src_y, src_w, src_h);
1298                 } else {
1299                         intel_plane->disable_plane(plane, crtc);
1300                 }
1301         }
1302 }
1303
1304 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1305                               struct drm_file *file_priv)
1306 {
1307         struct drm_intel_sprite_colorkey *set = data;
1308         struct drm_plane *plane;
1309         struct intel_plane *intel_plane;
1310         int ret = 0;
1311
1312         /* Make sure we don't try to enable both src & dest simultaneously */
1313         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1314                 return -EINVAL;
1315
1316         drm_modeset_lock_all(dev);
1317
1318         plane = drm_plane_find(dev, set->plane_id);
1319         if (!plane) {
1320                 ret = -ENOENT;
1321                 goto out_unlock;
1322         }
1323
1324         intel_plane = to_intel_plane(plane);
1325         ret = intel_plane->update_colorkey(plane, set);
1326
1327 out_unlock:
1328         drm_modeset_unlock_all(dev);
1329         return ret;
1330 }
1331
1332 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1333                               struct drm_file *file_priv)
1334 {
1335         struct drm_intel_sprite_colorkey *get = data;
1336         struct drm_plane *plane;
1337         struct intel_plane *intel_plane;
1338         int ret = 0;
1339
1340         drm_modeset_lock_all(dev);
1341
1342         plane = drm_plane_find(dev, get->plane_id);
1343         if (!plane) {
1344                 ret = -ENOENT;
1345                 goto out_unlock;
1346         }
1347
1348         intel_plane = to_intel_plane(plane);
1349         intel_plane->get_colorkey(plane, get);
1350
1351 out_unlock:
1352         drm_modeset_unlock_all(dev);
1353         return ret;
1354 }
1355
1356 int intel_plane_restore(struct drm_plane *plane)
1357 {
1358         if (!plane->crtc || !plane->fb)
1359                 return 0;
1360
1361         return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
1362                                   plane->state->crtc_x, plane->state->crtc_y,
1363                                   plane->state->crtc_w, plane->state->crtc_h,
1364                                   plane->state->src_x, plane->state->src_y,
1365                                   plane->state->src_w, plane->state->src_h);
1366 }
1367
1368 static uint32_t ilk_plane_formats[] = {
1369         DRM_FORMAT_XRGB8888,
1370         DRM_FORMAT_YUYV,
1371         DRM_FORMAT_YVYU,
1372         DRM_FORMAT_UYVY,
1373         DRM_FORMAT_VYUY,
1374 };
1375
1376 static uint32_t snb_plane_formats[] = {
1377         DRM_FORMAT_XBGR8888,
1378         DRM_FORMAT_XRGB8888,
1379         DRM_FORMAT_YUYV,
1380         DRM_FORMAT_YVYU,
1381         DRM_FORMAT_UYVY,
1382         DRM_FORMAT_VYUY,
1383 };
1384
1385 static uint32_t vlv_plane_formats[] = {
1386         DRM_FORMAT_RGB565,
1387         DRM_FORMAT_ABGR8888,
1388         DRM_FORMAT_ARGB8888,
1389         DRM_FORMAT_XBGR8888,
1390         DRM_FORMAT_XRGB8888,
1391         DRM_FORMAT_XBGR2101010,
1392         DRM_FORMAT_ABGR2101010,
1393         DRM_FORMAT_YUYV,
1394         DRM_FORMAT_YVYU,
1395         DRM_FORMAT_UYVY,
1396         DRM_FORMAT_VYUY,
1397 };
1398
1399 static uint32_t skl_plane_formats[] = {
1400         DRM_FORMAT_RGB565,
1401         DRM_FORMAT_ABGR8888,
1402         DRM_FORMAT_ARGB8888,
1403         DRM_FORMAT_XBGR8888,
1404         DRM_FORMAT_XRGB8888,
1405         DRM_FORMAT_YUYV,
1406         DRM_FORMAT_YVYU,
1407         DRM_FORMAT_UYVY,
1408         DRM_FORMAT_VYUY,
1409 };
1410
1411 int
1412 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1413 {
1414         struct intel_plane *intel_plane;
1415         struct intel_plane_state *state;
1416         unsigned long possible_crtcs;
1417         const uint32_t *plane_formats;
1418         int num_plane_formats;
1419         int ret;
1420
1421         if (INTEL_INFO(dev)->gen < 5)
1422                 return -ENODEV;
1423
1424         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1425         if (!intel_plane)
1426                 return -ENOMEM;
1427
1428         state = intel_create_plane_state(&intel_plane->base);
1429         if (!state) {
1430                 kfree(intel_plane);
1431                 return -ENOMEM;
1432         }
1433         intel_plane->base.state = &state->base;
1434
1435         switch (INTEL_INFO(dev)->gen) {
1436         case 5:
1437         case 6:
1438                 intel_plane->can_scale = true;
1439                 intel_plane->max_downscale = 16;
1440                 intel_plane->update_plane = ilk_update_plane;
1441                 intel_plane->disable_plane = ilk_disable_plane;
1442                 intel_plane->update_colorkey = ilk_update_colorkey;
1443                 intel_plane->get_colorkey = ilk_get_colorkey;
1444
1445                 if (IS_GEN6(dev)) {
1446                         plane_formats = snb_plane_formats;
1447                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1448                 } else {
1449                         plane_formats = ilk_plane_formats;
1450                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1451                 }
1452                 break;
1453
1454         case 7:
1455         case 8:
1456                 if (IS_IVYBRIDGE(dev)) {
1457                         intel_plane->can_scale = true;
1458                         intel_plane->max_downscale = 2;
1459                 } else {
1460                         intel_plane->can_scale = false;
1461                         intel_plane->max_downscale = 1;
1462                 }
1463
1464                 if (IS_VALLEYVIEW(dev)) {
1465                         intel_plane->update_plane = vlv_update_plane;
1466                         intel_plane->disable_plane = vlv_disable_plane;
1467                         intel_plane->update_colorkey = vlv_update_colorkey;
1468                         intel_plane->get_colorkey = vlv_get_colorkey;
1469
1470                         plane_formats = vlv_plane_formats;
1471                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1472                 } else {
1473                         intel_plane->update_plane = ivb_update_plane;
1474                         intel_plane->disable_plane = ivb_disable_plane;
1475                         intel_plane->update_colorkey = ivb_update_colorkey;
1476                         intel_plane->get_colorkey = ivb_get_colorkey;
1477
1478                         plane_formats = snb_plane_formats;
1479                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1480                 }
1481                 break;
1482         case 9:
1483                 /*
1484                  * FIXME: Skylake planes can be scaled (with some restrictions),
1485                  * but this is for another time.
1486                  */
1487                 intel_plane->can_scale = false;
1488                 intel_plane->max_downscale = 1;
1489                 intel_plane->update_plane = skl_update_plane;
1490                 intel_plane->disable_plane = skl_disable_plane;
1491                 intel_plane->update_colorkey = skl_update_colorkey;
1492                 intel_plane->get_colorkey = skl_get_colorkey;
1493
1494                 plane_formats = skl_plane_formats;
1495                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1496                 break;
1497         default:
1498                 kfree(intel_plane);
1499                 return -ENODEV;
1500         }
1501
1502         intel_plane->pipe = pipe;
1503         intel_plane->plane = plane;
1504         intel_plane->check_plane = intel_check_sprite_plane;
1505         intel_plane->commit_plane = intel_commit_sprite_plane;
1506         possible_crtcs = (1 << pipe);
1507         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1508                                        &intel_plane_funcs,
1509                                        plane_formats, num_plane_formats,
1510                                        DRM_PLANE_TYPE_OVERLAY);
1511         if (ret) {
1512                 kfree(intel_plane);
1513                 goto out;
1514         }
1515
1516         if (!dev->mode_config.rotation_property)
1517                 dev->mode_config.rotation_property =
1518                         drm_mode_create_rotation_property(dev,
1519                                                           BIT(DRM_ROTATE_0) |
1520                                                           BIT(DRM_ROTATE_180));
1521
1522         if (dev->mode_config.rotation_property)
1523                 drm_object_attach_property(&intel_plane->base.base,
1524                                            dev->mode_config.rotation_property,
1525                                            state->base.rotation);
1526
1527         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1528
1529  out:
1530         return ret;
1531 }