2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
43 format_is_yuv(uint32_t format
)
56 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
60 if (!adjusted_mode
->crtc_htotal
)
63 return DIV_ROUND_UP(usecs
* adjusted_mode
->crtc_clock
,
64 1000 * adjusted_mode
->crtc_htotal
);
68 * intel_pipe_update_start() - start update of a set of display registers
69 * @crtc: the crtc of which the registers are going to be updated
70 * @start_vbl_count: vblank counter return pointer used for error checking
72 * Mark the start of an update to pipe registers that should be updated
73 * atomically regarding vblank. If the next vblank will happens within
74 * the next 100 us, this function waits until the vblank passes.
76 * After a successful call to this function, interrupts will be disabled
77 * until a subsequent call to intel_pipe_update_end(). That is done to
78 * avoid random delays. The value written to @start_vbl_count should be
79 * supplied to intel_pipe_update_end() for error checking.
81 void intel_pipe_update_start(struct intel_crtc
*crtc
)
83 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
84 long timeout
= msecs_to_jiffies_timeout(1);
85 int scanline
, min
, max
, vblank_start
;
86 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
89 vblank_start
= adjusted_mode
->crtc_vblank_start
;
90 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
91 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
93 /* FIXME needs to be calibrated sensibly */
94 min
= vblank_start
- intel_usecs_to_scanlines(adjusted_mode
, 100);
95 max
= vblank_start
- 1;
99 if (min
<= 0 || max
<= 0)
102 if (WARN_ON(drm_crtc_vblank_get(&crtc
->base
)))
105 crtc
->debug
.min_vbl
= min
;
106 crtc
->debug
.max_vbl
= max
;
107 trace_i915_pipe_update_start(crtc
);
111 * prepare_to_wait() has a memory barrier, which guarantees
112 * other CPUs can see the task state update by the time we
115 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
117 scanline
= intel_get_crtc_scanline(crtc
);
118 if (scanline
< min
|| scanline
> max
)
122 DRM_ERROR("Potential atomic update failure on pipe %c\n",
123 pipe_name(crtc
->pipe
));
129 timeout
= schedule_timeout(timeout
);
134 finish_wait(wq
, &wait
);
136 drm_crtc_vblank_put(&crtc
->base
);
138 crtc
->debug
.scanline_start
= scanline
;
139 crtc
->debug
.start_vbl_time
= ktime_get();
140 crtc
->debug
.start_vbl_count
= intel_crtc_get_vblank_counter(crtc
);
142 trace_i915_pipe_update_vblank_evaded(crtc
);
146 * intel_pipe_update_end() - end update of a set of display registers
147 * @crtc: the crtc of which the registers were updated
148 * @start_vbl_count: start vblank counter (used for error checking)
150 * Mark the end of an update started with intel_pipe_update_start(). This
151 * re-enables interrupts and verifies the update was actually completed
152 * before a vblank using the value of @start_vbl_count.
154 void intel_pipe_update_end(struct intel_crtc
*crtc
, struct intel_flip_work
*work
)
156 enum pipe pipe
= crtc
->pipe
;
157 int scanline_end
= intel_get_crtc_scanline(crtc
);
158 u32 end_vbl_count
= intel_crtc_get_vblank_counter(crtc
);
159 ktime_t end_vbl_time
= ktime_get();
162 work
->flip_queued_vblank
= end_vbl_count
;
163 smp_mb__before_atomic();
164 atomic_set(&work
->pending
, 1);
167 trace_i915_pipe_update_end(crtc
, end_vbl_count
, scanline_end
);
169 /* We're still in the vblank-evade critical section, this can't race.
170 * Would be slightly nice to just grab the vblank count and arm the
171 * event outside of the critical section - the spinlock might spin for a
173 if (crtc
->base
.state
->event
) {
174 WARN_ON(drm_crtc_vblank_get(&crtc
->base
) != 0);
176 spin_lock(&crtc
->base
.dev
->event_lock
);
177 drm_crtc_arm_vblank_event(&crtc
->base
, crtc
->base
.state
->event
);
178 spin_unlock(&crtc
->base
.dev
->event_lock
);
180 crtc
->base
.state
->event
= NULL
;
185 if (crtc
->debug
.start_vbl_count
&&
186 crtc
->debug
.start_vbl_count
!= end_vbl_count
) {
187 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
188 pipe_name(pipe
), crtc
->debug
.start_vbl_count
,
190 ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
),
191 crtc
->debug
.min_vbl
, crtc
->debug
.max_vbl
,
192 crtc
->debug
.scanline_start
, scanline_end
);
197 skl_update_plane(struct drm_plane
*drm_plane
,
198 const struct intel_crtc_state
*crtc_state
,
199 const struct intel_plane_state
*plane_state
)
201 struct drm_device
*dev
= drm_plane
->dev
;
202 struct drm_i915_private
*dev_priv
= to_i915(dev
);
203 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
204 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
205 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
206 const int pipe
= intel_plane
->pipe
;
207 const int plane
= intel_plane
->plane
+ 1;
208 u32 plane_ctl
, stride_div
, stride
;
209 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
211 u32 tile_height
, plane_offset
, plane_size
;
212 unsigned int rotation
= plane_state
->base
.rotation
;
213 int x_offset
, y_offset
;
214 int crtc_x
= plane_state
->base
.dst
.x1
;
215 int crtc_y
= plane_state
->base
.dst
.y1
;
216 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
217 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
218 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
219 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
220 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
221 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
223 plane_ctl
= PLANE_CTL_ENABLE
|
224 PLANE_CTL_PIPE_GAMMA_ENABLE
|
225 PLANE_CTL_PIPE_CSC_ENABLE
;
227 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
228 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
230 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
232 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
235 /* Sizes are 0 based */
242 I915_WRITE(PLANE_KEYVAL(pipe
, plane
), key
->min_value
);
243 I915_WRITE(PLANE_KEYMAX(pipe
, plane
), key
->max_value
);
244 I915_WRITE(PLANE_KEYMSK(pipe
, plane
), key
->channel_mask
);
247 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
248 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
249 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
250 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
252 surf_addr
= intel_plane_obj_offset(intel_plane
, obj
, 0);
254 if (intel_rotation_90_or_270(rotation
)) {
255 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
257 /* stride: Surface height in tiles */
258 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
259 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
260 plane_size
= (src_w
<< 16) | src_h
;
261 x_offset
= stride
* tile_height
- y
- (src_h
+ 1);
264 stride
= fb
->pitches
[0] / stride_div
;
265 plane_size
= (src_h
<< 16) | src_w
;
269 plane_offset
= y_offset
<< 16 | x_offset
;
271 I915_WRITE(PLANE_OFFSET(pipe
, plane
), plane_offset
);
272 I915_WRITE(PLANE_STRIDE(pipe
, plane
), stride
);
273 I915_WRITE(PLANE_SIZE(pipe
, plane
), plane_size
);
275 /* program plane scaler */
276 if (plane_state
->scaler_id
>= 0) {
277 int scaler_id
= plane_state
->scaler_id
;
278 const struct intel_scaler
*scaler
;
280 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane
,
281 PS_PLANE_SEL(plane
));
283 scaler
= &crtc_state
->scaler_state
.scalers
[scaler_id
];
285 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
),
286 PS_SCALER_EN
| PS_PLANE_SEL(plane
) | scaler
->mode
);
287 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
288 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (crtc_x
<< 16) | crtc_y
);
289 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
),
290 ((crtc_w
+ 1) << 16)|(crtc_h
+ 1));
292 I915_WRITE(PLANE_POS(pipe
, plane
), 0);
294 I915_WRITE(PLANE_POS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
297 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
298 I915_WRITE(PLANE_SURF(pipe
, plane
), surf_addr
);
299 POSTING_READ(PLANE_SURF(pipe
, plane
));
303 skl_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
305 struct drm_device
*dev
= dplane
->dev
;
306 struct drm_i915_private
*dev_priv
= to_i915(dev
);
307 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
308 const int pipe
= intel_plane
->pipe
;
309 const int plane
= intel_plane
->plane
+ 1;
311 I915_WRITE(PLANE_CTL(pipe
, plane
), 0);
313 I915_WRITE(PLANE_SURF(pipe
, plane
), 0);
314 POSTING_READ(PLANE_SURF(pipe
, plane
));
318 chv_update_csc(struct intel_plane
*intel_plane
, uint32_t format
)
320 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
321 int plane
= intel_plane
->plane
;
323 /* Seems RGB data bypasses the CSC always */
324 if (!format_is_yuv(format
))
328 * BT.601 limited range YCbCr -> full range RGB
330 * |r| | 6537 4769 0| |cr |
331 * |g| = |-3330 4769 -1605| x |y-64|
332 * |b| | 0 4769 8263| |cb |
334 * Cb and Cr apparently come in as signed already, so no
335 * need for any offset. For Y we need to remove the offset.
337 I915_WRITE(SPCSCYGOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
338 I915_WRITE(SPCSCCBOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
339 I915_WRITE(SPCSCCROFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
341 I915_WRITE(SPCSCC01(plane
), SPCSC_C1(4769) | SPCSC_C0(6537));
342 I915_WRITE(SPCSCC23(plane
), SPCSC_C1(-3330) | SPCSC_C0(0));
343 I915_WRITE(SPCSCC45(plane
), SPCSC_C1(-1605) | SPCSC_C0(4769));
344 I915_WRITE(SPCSCC67(plane
), SPCSC_C1(4769) | SPCSC_C0(0));
345 I915_WRITE(SPCSCC8(plane
), SPCSC_C0(8263));
347 I915_WRITE(SPCSCYGICLAMP(plane
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
348 I915_WRITE(SPCSCCBICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
349 I915_WRITE(SPCSCCRICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
351 I915_WRITE(SPCSCYGOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
352 I915_WRITE(SPCSCCBOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
353 I915_WRITE(SPCSCCROCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
357 vlv_update_plane(struct drm_plane
*dplane
,
358 const struct intel_crtc_state
*crtc_state
,
359 const struct intel_plane_state
*plane_state
)
361 struct drm_device
*dev
= dplane
->dev
;
362 struct drm_i915_private
*dev_priv
= to_i915(dev
);
363 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
364 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
365 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
366 int pipe
= intel_plane
->pipe
;
367 int plane
= intel_plane
->plane
;
369 u32 sprsurf_offset
, linear_offset
;
370 unsigned int rotation
= dplane
->state
->rotation
;
371 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
372 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
373 int crtc_x
= plane_state
->base
.dst
.x1
;
374 int crtc_y
= plane_state
->base
.dst
.y1
;
375 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
376 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
377 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
378 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
379 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
380 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
384 switch (fb
->pixel_format
) {
385 case DRM_FORMAT_YUYV
:
386 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
388 case DRM_FORMAT_YVYU
:
389 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
391 case DRM_FORMAT_UYVY
:
392 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
394 case DRM_FORMAT_VYUY
:
395 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
397 case DRM_FORMAT_RGB565
:
398 sprctl
|= SP_FORMAT_BGR565
;
400 case DRM_FORMAT_XRGB8888
:
401 sprctl
|= SP_FORMAT_BGRX8888
;
403 case DRM_FORMAT_ARGB8888
:
404 sprctl
|= SP_FORMAT_BGRA8888
;
406 case DRM_FORMAT_XBGR2101010
:
407 sprctl
|= SP_FORMAT_RGBX1010102
;
409 case DRM_FORMAT_ABGR2101010
:
410 sprctl
|= SP_FORMAT_RGBA1010102
;
412 case DRM_FORMAT_XBGR8888
:
413 sprctl
|= SP_FORMAT_RGBX8888
;
415 case DRM_FORMAT_ABGR8888
:
416 sprctl
|= SP_FORMAT_RGBA8888
;
420 * If we get here one of the upper layers failed to filter
421 * out the unsupported plane formats
428 * Enable gamma to match primary/cursor plane behaviour.
429 * FIXME should be user controllable via propertiesa.
431 sprctl
|= SP_GAMMA_ENABLE
;
433 if (obj
->tiling_mode
!= I915_TILING_NONE
)
436 /* Sizes are 0 based */
442 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
443 sprsurf_offset
= intel_compute_tile_offset(&x
, &y
, fb
, 0,
444 fb
->pitches
[0], rotation
);
445 linear_offset
-= sprsurf_offset
;
447 if (rotation
== DRM_ROTATE_180
) {
448 sprctl
|= SP_ROTATE_180
;
452 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* cpp
;
456 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
457 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
458 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
461 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
462 sprctl
|= SP_SOURCE_KEY
;
464 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
)
465 chv_update_csc(intel_plane
, fb
->pixel_format
);
467 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
468 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
470 if (obj
->tiling_mode
!= I915_TILING_NONE
)
471 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
473 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
475 I915_WRITE(SPCONSTALPHA(pipe
, plane
), 0);
477 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
478 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
479 I915_WRITE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
481 POSTING_READ(SPSURF(pipe
, plane
));
485 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
487 struct drm_device
*dev
= dplane
->dev
;
488 struct drm_i915_private
*dev_priv
= to_i915(dev
);
489 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
490 int pipe
= intel_plane
->pipe
;
491 int plane
= intel_plane
->plane
;
493 I915_WRITE(SPCNTR(pipe
, plane
), 0);
495 I915_WRITE(SPSURF(pipe
, plane
), 0);
496 POSTING_READ(SPSURF(pipe
, plane
));
500 ivb_update_plane(struct drm_plane
*plane
,
501 const struct intel_crtc_state
*crtc_state
,
502 const struct intel_plane_state
*plane_state
)
504 struct drm_device
*dev
= plane
->dev
;
505 struct drm_i915_private
*dev_priv
= to_i915(dev
);
506 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
507 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
508 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
509 enum pipe pipe
= intel_plane
->pipe
;
510 u32 sprctl
, sprscale
= 0;
511 u32 sprsurf_offset
, linear_offset
;
512 unsigned int rotation
= plane_state
->base
.rotation
;
513 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
514 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
515 int crtc_x
= plane_state
->base
.dst
.x1
;
516 int crtc_y
= plane_state
->base
.dst
.y1
;
517 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
518 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
519 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
520 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
521 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
522 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
524 sprctl
= SPRITE_ENABLE
;
526 switch (fb
->pixel_format
) {
527 case DRM_FORMAT_XBGR8888
:
528 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
530 case DRM_FORMAT_XRGB8888
:
531 sprctl
|= SPRITE_FORMAT_RGBX888
;
533 case DRM_FORMAT_YUYV
:
534 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
536 case DRM_FORMAT_YVYU
:
537 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
539 case DRM_FORMAT_UYVY
:
540 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
542 case DRM_FORMAT_VYUY
:
543 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
550 * Enable gamma to match primary/cursor plane behaviour.
551 * FIXME should be user controllable via propertiesa.
553 sprctl
|= SPRITE_GAMMA_ENABLE
;
555 if (obj
->tiling_mode
!= I915_TILING_NONE
)
556 sprctl
|= SPRITE_TILED
;
558 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
559 sprctl
&= ~SPRITE_TRICKLE_FEED_DISABLE
;
561 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
563 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
564 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
566 /* Sizes are 0 based */
572 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
573 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
575 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
576 sprsurf_offset
= intel_compute_tile_offset(&x
, &y
, fb
, 0,
577 fb
->pitches
[0], rotation
);
578 linear_offset
-= sprsurf_offset
;
580 if (rotation
== DRM_ROTATE_180
) {
581 sprctl
|= SPRITE_ROTATE_180
;
583 /* HSW and BDW does this automagically in hardware */
584 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
587 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* cpp
;
592 I915_WRITE(SPRKEYVAL(pipe
), key
->min_value
);
593 I915_WRITE(SPRKEYMAX(pipe
), key
->max_value
);
594 I915_WRITE(SPRKEYMSK(pipe
), key
->channel_mask
);
597 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
598 sprctl
|= SPRITE_DEST_KEY
;
599 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
600 sprctl
|= SPRITE_SOURCE_KEY
;
602 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
603 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
605 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
607 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
608 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
609 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
610 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
612 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
614 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
615 if (intel_plane
->can_scale
)
616 I915_WRITE(SPRSCALE(pipe
), sprscale
);
617 I915_WRITE(SPRCTL(pipe
), sprctl
);
618 I915_WRITE(SPRSURF(pipe
),
619 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
620 POSTING_READ(SPRSURF(pipe
));
624 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
626 struct drm_device
*dev
= plane
->dev
;
627 struct drm_i915_private
*dev_priv
= to_i915(dev
);
628 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
629 int pipe
= intel_plane
->pipe
;
631 I915_WRITE(SPRCTL(pipe
), 0);
632 /* Can't leave the scaler enabled... */
633 if (intel_plane
->can_scale
)
634 I915_WRITE(SPRSCALE(pipe
), 0);
636 I915_WRITE(SPRSURF(pipe
), 0);
637 POSTING_READ(SPRSURF(pipe
));
641 ilk_update_plane(struct drm_plane
*plane
,
642 const struct intel_crtc_state
*crtc_state
,
643 const struct intel_plane_state
*plane_state
)
645 struct drm_device
*dev
= plane
->dev
;
646 struct drm_i915_private
*dev_priv
= to_i915(dev
);
647 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
648 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
649 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
650 int pipe
= intel_plane
->pipe
;
651 u32 dvscntr
, dvsscale
;
652 u32 dvssurf_offset
, linear_offset
;
653 unsigned int rotation
= plane_state
->base
.rotation
;
654 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
655 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
656 int crtc_x
= plane_state
->base
.dst
.x1
;
657 int crtc_y
= plane_state
->base
.dst
.y1
;
658 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
659 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
660 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
661 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
662 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
663 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
665 dvscntr
= DVS_ENABLE
;
667 switch (fb
->pixel_format
) {
668 case DRM_FORMAT_XBGR8888
:
669 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
671 case DRM_FORMAT_XRGB8888
:
672 dvscntr
|= DVS_FORMAT_RGBX888
;
674 case DRM_FORMAT_YUYV
:
675 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
677 case DRM_FORMAT_YVYU
:
678 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
680 case DRM_FORMAT_UYVY
:
681 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
683 case DRM_FORMAT_VYUY
:
684 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
691 * Enable gamma to match primary/cursor plane behaviour.
692 * FIXME should be user controllable via propertiesa.
694 dvscntr
|= DVS_GAMMA_ENABLE
;
696 if (obj
->tiling_mode
!= I915_TILING_NONE
)
697 dvscntr
|= DVS_TILED
;
700 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
702 /* Sizes are 0 based */
709 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
710 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
712 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
713 dvssurf_offset
= intel_compute_tile_offset(&x
, &y
, fb
, 0,
714 fb
->pitches
[0], rotation
);
715 linear_offset
-= dvssurf_offset
;
717 if (rotation
== DRM_ROTATE_180
) {
718 dvscntr
|= DVS_ROTATE_180
;
722 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* cpp
;
726 I915_WRITE(DVSKEYVAL(pipe
), key
->min_value
);
727 I915_WRITE(DVSKEYMAX(pipe
), key
->max_value
);
728 I915_WRITE(DVSKEYMSK(pipe
), key
->channel_mask
);
731 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
732 dvscntr
|= DVS_DEST_KEY
;
733 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
734 dvscntr
|= DVS_SOURCE_KEY
;
736 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
737 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
739 if (obj
->tiling_mode
!= I915_TILING_NONE
)
740 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
742 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
744 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
745 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
746 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
747 I915_WRITE(DVSSURF(pipe
),
748 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
749 POSTING_READ(DVSSURF(pipe
));
753 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
755 struct drm_device
*dev
= plane
->dev
;
756 struct drm_i915_private
*dev_priv
= to_i915(dev
);
757 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
758 int pipe
= intel_plane
->pipe
;
760 I915_WRITE(DVSCNTR(pipe
), 0);
761 /* Disable the scaler */
762 I915_WRITE(DVSSCALE(pipe
), 0);
764 I915_WRITE(DVSSURF(pipe
), 0);
765 POSTING_READ(DVSSURF(pipe
));
769 intel_check_sprite_plane(struct drm_plane
*plane
,
770 struct intel_crtc_state
*crtc_state
,
771 struct intel_plane_state
*state
)
773 struct drm_device
*dev
= plane
->dev
;
774 struct drm_crtc
*crtc
= state
->base
.crtc
;
775 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
776 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
777 struct drm_framebuffer
*fb
= state
->base
.fb
;
779 unsigned int crtc_w
, crtc_h
;
780 uint32_t src_x
, src_y
, src_w
, src_h
;
781 struct drm_rect
*src
= &state
->base
.src
;
782 struct drm_rect
*dst
= &state
->base
.dst
;
783 const struct drm_rect
*clip
= &state
->clip
;
785 int max_scale
, min_scale
;
789 state
->base
.visible
= false;
793 /* Don't modify another pipe's plane */
794 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
795 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
799 /* FIXME check all gen limits */
800 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
801 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
805 /* setup can_scale, min_scale, max_scale */
806 if (INTEL_INFO(dev
)->gen
>= 9) {
807 /* use scaler when colorkey is not required */
808 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
811 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
814 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
815 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
818 can_scale
= intel_plane
->can_scale
;
819 max_scale
= intel_plane
->max_downscale
<< 16;
820 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
824 * FIXME the following code does a bunch of fuzzy adjustments to the
825 * coordinates and sizes. We probably need some way to decide whether
826 * more strict checking should be done instead.
828 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
829 state
->base
.rotation
);
831 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
834 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
837 state
->base
.visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
841 crtc_w
= drm_rect_width(dst
);
842 crtc_h
= drm_rect_height(dst
);
844 if (state
->base
.visible
) {
845 /* check again in case clipping clamped the results */
846 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
848 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
849 drm_rect_debug_print("src: ", src
, true);
850 drm_rect_debug_print("dst: ", dst
, false);
855 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
857 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
858 drm_rect_debug_print("src: ", src
, true);
859 drm_rect_debug_print("dst: ", dst
, false);
864 /* Make the source viewport size an exact multiple of the scaling factors. */
865 drm_rect_adjust_size(src
,
866 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
867 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
869 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
870 state
->base
.rotation
);
872 /* sanity check to make sure the src viewport wasn't enlarged */
873 WARN_ON(src
->x1
< (int) state
->base
.src_x
||
874 src
->y1
< (int) state
->base
.src_y
||
875 src
->x2
> (int) state
->base
.src_x
+ state
->base
.src_w
||
876 src
->y2
> (int) state
->base
.src_y
+ state
->base
.src_h
);
879 * Hardware doesn't handle subpixel coordinates.
880 * Adjust to (macro)pixel boundary, but be careful not to
881 * increase the source viewport size, because that could
882 * push the downscaling factor out of bounds.
884 src_x
= src
->x1
>> 16;
885 src_w
= drm_rect_width(src
) >> 16;
886 src_y
= src
->y1
>> 16;
887 src_h
= drm_rect_height(src
) >> 16;
889 if (format_is_yuv(fb
->pixel_format
)) {
894 * Must keep src and dst the
895 * same if we can't scale.
901 state
->base
.visible
= false;
905 /* Check size restrictions when scaling */
906 if (state
->base
.visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
907 unsigned int width_bytes
;
908 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
912 /* FIXME interlacing min height is 6 */
914 if (crtc_w
< 3 || crtc_h
< 3)
915 state
->base
.visible
= false;
917 if (src_w
< 3 || src_h
< 3)
918 state
->base
.visible
= false;
920 width_bytes
= ((src_x
* cpp
) & 63) + src_w
* cpp
;
922 if (INTEL_INFO(dev
)->gen
< 9 && (src_w
> 2048 || src_h
> 2048 ||
923 width_bytes
> 4096 || fb
->pitches
[0] > 4096)) {
924 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
929 if (state
->base
.visible
) {
930 src
->x1
= src_x
<< 16;
931 src
->x2
= (src_x
+ src_w
) << 16;
932 src
->y1
= src_y
<< 16;
933 src
->y2
= (src_y
+ src_h
) << 16;
937 dst
->x2
= crtc_x
+ crtc_w
;
939 dst
->y2
= crtc_y
+ crtc_h
;
944 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
945 struct drm_file
*file_priv
)
947 struct drm_intel_sprite_colorkey
*set
= data
;
948 struct drm_plane
*plane
;
949 struct drm_plane_state
*plane_state
;
950 struct drm_atomic_state
*state
;
951 struct drm_modeset_acquire_ctx ctx
;
954 /* Make sure we don't try to enable both src & dest simultaneously */
955 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
958 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
959 set
->flags
& I915_SET_COLORKEY_DESTINATION
)
962 plane
= drm_plane_find(dev
, set
->plane_id
);
963 if (!plane
|| plane
->type
!= DRM_PLANE_TYPE_OVERLAY
)
966 drm_modeset_acquire_init(&ctx
, 0);
968 state
= drm_atomic_state_alloc(plane
->dev
);
973 state
->acquire_ctx
= &ctx
;
976 plane_state
= drm_atomic_get_plane_state(state
, plane
);
977 ret
= PTR_ERR_OR_ZERO(plane_state
);
979 to_intel_plane_state(plane_state
)->ckey
= *set
;
980 ret
= drm_atomic_commit(state
);
986 drm_atomic_state_clear(state
);
987 drm_modeset_backoff(&ctx
);
991 drm_atomic_state_free(state
);
994 drm_modeset_drop_locks(&ctx
);
995 drm_modeset_acquire_fini(&ctx
);
999 static const uint32_t ilk_plane_formats
[] = {
1000 DRM_FORMAT_XRGB8888
,
1007 static const uint32_t snb_plane_formats
[] = {
1008 DRM_FORMAT_XBGR8888
,
1009 DRM_FORMAT_XRGB8888
,
1016 static const uint32_t vlv_plane_formats
[] = {
1018 DRM_FORMAT_ABGR8888
,
1019 DRM_FORMAT_ARGB8888
,
1020 DRM_FORMAT_XBGR8888
,
1021 DRM_FORMAT_XRGB8888
,
1022 DRM_FORMAT_XBGR2101010
,
1023 DRM_FORMAT_ABGR2101010
,
1030 static uint32_t skl_plane_formats
[] = {
1032 DRM_FORMAT_ABGR8888
,
1033 DRM_FORMAT_ARGB8888
,
1034 DRM_FORMAT_XBGR8888
,
1035 DRM_FORMAT_XRGB8888
,
1043 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1045 struct intel_plane
*intel_plane
= NULL
;
1046 struct intel_plane_state
*state
= NULL
;
1047 unsigned long possible_crtcs
;
1048 const uint32_t *plane_formats
;
1049 int num_plane_formats
;
1052 if (INTEL_INFO(dev
)->gen
< 5)
1055 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1061 state
= intel_create_plane_state(&intel_plane
->base
);
1066 intel_plane
->base
.state
= &state
->base
;
1068 switch (INTEL_INFO(dev
)->gen
) {
1071 intel_plane
->can_scale
= true;
1072 intel_plane
->max_downscale
= 16;
1073 intel_plane
->update_plane
= ilk_update_plane
;
1074 intel_plane
->disable_plane
= ilk_disable_plane
;
1077 plane_formats
= snb_plane_formats
;
1078 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1080 plane_formats
= ilk_plane_formats
;
1081 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1087 if (IS_IVYBRIDGE(dev
)) {
1088 intel_plane
->can_scale
= true;
1089 intel_plane
->max_downscale
= 2;
1091 intel_plane
->can_scale
= false;
1092 intel_plane
->max_downscale
= 1;
1095 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1096 intel_plane
->update_plane
= vlv_update_plane
;
1097 intel_plane
->disable_plane
= vlv_disable_plane
;
1099 plane_formats
= vlv_plane_formats
;
1100 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1102 intel_plane
->update_plane
= ivb_update_plane
;
1103 intel_plane
->disable_plane
= ivb_disable_plane
;
1105 plane_formats
= snb_plane_formats
;
1106 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1110 intel_plane
->can_scale
= true;
1111 intel_plane
->update_plane
= skl_update_plane
;
1112 intel_plane
->disable_plane
= skl_disable_plane
;
1113 state
->scaler_id
= -1;
1115 plane_formats
= skl_plane_formats
;
1116 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1119 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1124 intel_plane
->pipe
= pipe
;
1125 intel_plane
->plane
= plane
;
1126 intel_plane
->frontbuffer_bit
= INTEL_FRONTBUFFER_SPRITE(pipe
, plane
);
1127 intel_plane
->check_plane
= intel_check_sprite_plane
;
1129 possible_crtcs
= (1 << pipe
);
1131 if (INTEL_INFO(dev
)->gen
>= 9)
1132 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1134 plane_formats
, num_plane_formats
,
1135 DRM_PLANE_TYPE_OVERLAY
,
1136 "plane %d%c", plane
+ 2, pipe_name(pipe
));
1138 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1140 plane_formats
, num_plane_formats
,
1141 DRM_PLANE_TYPE_OVERLAY
,
1142 "sprite %c", sprite_name(pipe
, plane
));
1146 intel_create_rotation_property(dev
, intel_plane
);
1148 drm_plane_helper_add(&intel_plane
->base
, &intel_plane_helper_funcs
);