2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
43 format_is_yuv(uint32_t format
)
56 static int usecs_to_scanlines(const struct drm_display_mode
*mode
, int usecs
)
59 if (!mode
->crtc_htotal
)
62 return DIV_ROUND_UP(usecs
* mode
->crtc_clock
, 1000 * mode
->crtc_htotal
);
66 * intel_pipe_update_start() - start update of a set of display registers
67 * @crtc: the crtc of which the registers are going to be updated
68 * @start_vbl_count: vblank counter return pointer used for error checking
70 * Mark the start of an update to pipe registers that should be updated
71 * atomically regarding vblank. If the next vblank will happens within
72 * the next 100 us, this function waits until the vblank passes.
74 * After a successful call to this function, interrupts will be disabled
75 * until a subsequent call to intel_pipe_update_end(). That is done to
76 * avoid random delays. The value written to @start_vbl_count should be
77 * supplied to intel_pipe_update_end() for error checking.
79 * Return: true if the call was successful
81 bool intel_pipe_update_start(struct intel_crtc
*crtc
, uint32_t *start_vbl_count
)
83 struct drm_device
*dev
= crtc
->base
.dev
;
84 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
85 enum pipe pipe
= crtc
->pipe
;
86 long timeout
= msecs_to_jiffies_timeout(1);
87 int scanline
, min
, max
, vblank_start
;
88 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
91 vblank_start
= mode
->crtc_vblank_start
;
92 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
93 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
95 /* FIXME needs to be calibrated sensibly */
96 min
= vblank_start
- usecs_to_scanlines(mode
, 100);
97 max
= vblank_start
- 1;
99 if (min
<= 0 || max
<= 0)
102 if (WARN_ON(drm_crtc_vblank_get(&crtc
->base
)))
107 trace_i915_pipe_update_start(crtc
, min
, max
);
111 * prepare_to_wait() has a memory barrier, which guarantees
112 * other CPUs can see the task state update by the time we
115 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
117 scanline
= intel_get_crtc_scanline(crtc
);
118 if (scanline
< min
|| scanline
> max
)
122 DRM_ERROR("Potential atomic update failure on pipe %c\n",
123 pipe_name(crtc
->pipe
));
129 timeout
= schedule_timeout(timeout
);
134 finish_wait(wq
, &wait
);
136 drm_crtc_vblank_put(&crtc
->base
);
138 *start_vbl_count
= dev
->driver
->get_vblank_counter(dev
, pipe
);
140 trace_i915_pipe_update_vblank_evaded(crtc
, min
, max
, *start_vbl_count
);
146 * intel_pipe_update_end() - end update of a set of display registers
147 * @crtc: the crtc of which the registers were updated
148 * @start_vbl_count: start vblank counter (used for error checking)
150 * Mark the end of an update started with intel_pipe_update_start(). This
151 * re-enables interrupts and verifies the update was actually completed
152 * before a vblank using the value of @start_vbl_count.
154 void intel_pipe_update_end(struct intel_crtc
*crtc
, u32 start_vbl_count
)
156 struct drm_device
*dev
= crtc
->base
.dev
;
157 enum pipe pipe
= crtc
->pipe
;
158 u32 end_vbl_count
= dev
->driver
->get_vblank_counter(dev
, pipe
);
160 trace_i915_pipe_update_end(crtc
, end_vbl_count
);
164 if (start_vbl_count
!= end_vbl_count
)
165 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
166 pipe_name(pipe
), start_vbl_count
, end_vbl_count
);
170 skl_update_plane(struct drm_plane
*drm_plane
, struct drm_crtc
*crtc
,
171 struct drm_framebuffer
*fb
,
172 int crtc_x
, int crtc_y
,
173 unsigned int crtc_w
, unsigned int crtc_h
,
174 uint32_t x
, uint32_t y
,
175 uint32_t src_w
, uint32_t src_h
)
177 struct drm_device
*dev
= drm_plane
->dev
;
178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
179 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
180 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
181 const int pipe
= intel_plane
->pipe
;
182 const int plane
= intel_plane
->plane
+ 1;
183 u32 plane_ctl
, stride_div
, stride
;
184 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
185 const struct drm_intel_sprite_colorkey
*key
= &intel_plane
->ckey
;
186 unsigned long surf_addr
;
187 u32 tile_height
, plane_offset
, plane_size
;
188 unsigned int rotation
;
189 int x_offset
, y_offset
;
190 struct intel_crtc_state
*crtc_state
= to_intel_crtc(crtc
)->config
;
193 plane_ctl
= PLANE_CTL_ENABLE
|
194 PLANE_CTL_PIPE_CSC_ENABLE
;
196 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
197 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
199 rotation
= drm_plane
->state
->rotation
;
200 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
202 intel_update_sprite_watermarks(drm_plane
, crtc
, src_w
, src_h
,
204 src_w
!= crtc_w
|| src_h
!= crtc_h
);
206 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
209 scaler_id
= to_intel_plane_state(drm_plane
->state
)->scaler_id
;
211 /* Sizes are 0 based */
218 I915_WRITE(PLANE_KEYVAL(pipe
, plane
), key
->min_value
);
219 I915_WRITE(PLANE_KEYMAX(pipe
, plane
), key
->max_value
);
220 I915_WRITE(PLANE_KEYMSK(pipe
, plane
), key
->channel_mask
);
223 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
224 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
225 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
226 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
228 surf_addr
= intel_plane_obj_offset(intel_plane
, obj
);
230 if (intel_rotation_90_or_270(rotation
)) {
231 /* stride: Surface height in tiles */
232 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
234 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
235 plane_size
= (src_w
<< 16) | src_h
;
236 x_offset
= stride
* tile_height
- y
- (src_h
+ 1);
239 stride
= fb
->pitches
[0] / stride_div
;
240 plane_size
= (src_h
<< 16) | src_w
;
244 plane_offset
= y_offset
<< 16 | x_offset
;
246 I915_WRITE(PLANE_OFFSET(pipe
, plane
), plane_offset
);
247 I915_WRITE(PLANE_STRIDE(pipe
, plane
), stride
);
248 I915_WRITE(PLANE_SIZE(pipe
, plane
), plane_size
);
250 /* program plane scaler */
251 if (scaler_id
>= 0) {
252 uint32_t ps_ctrl
= 0;
254 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane
,
255 PS_PLANE_SEL(plane
));
256 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(plane
) |
257 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
258 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
259 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
260 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (crtc_x
<< 16) | crtc_y
);
261 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
),
262 ((crtc_w
+ 1) << 16)|(crtc_h
+ 1));
264 I915_WRITE(PLANE_POS(pipe
, plane
), 0);
266 I915_WRITE(PLANE_POS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
269 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
270 I915_WRITE(PLANE_SURF(pipe
, plane
), surf_addr
);
271 POSTING_READ(PLANE_SURF(pipe
, plane
));
275 skl_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
, bool force
)
277 struct drm_device
*dev
= dplane
->dev
;
278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
279 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
280 const int pipe
= intel_plane
->pipe
;
281 const int plane
= intel_plane
->plane
+ 1;
283 I915_WRITE(PLANE_CTL(pipe
, plane
), 0);
285 I915_WRITE(PLANE_SURF(pipe
, plane
), 0);
286 POSTING_READ(PLANE_SURF(pipe
, plane
));
288 intel_update_sprite_watermarks(dplane
, crtc
, 0, 0, 0, false, false);
292 chv_update_csc(struct intel_plane
*intel_plane
, uint32_t format
)
294 struct drm_i915_private
*dev_priv
= intel_plane
->base
.dev
->dev_private
;
295 int plane
= intel_plane
->plane
;
297 /* Seems RGB data bypasses the CSC always */
298 if (!format_is_yuv(format
))
302 * BT.601 limited range YCbCr -> full range RGB
304 * |r| | 6537 4769 0| |cr |
305 * |g| = |-3330 4769 -1605| x |y-64|
306 * |b| | 0 4769 8263| |cb |
308 * Cb and Cr apparently come in as signed already, so no
309 * need for any offset. For Y we need to remove the offset.
311 I915_WRITE(SPCSCYGOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
312 I915_WRITE(SPCSCCBOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
313 I915_WRITE(SPCSCCROFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
315 I915_WRITE(SPCSCC01(plane
), SPCSC_C1(4769) | SPCSC_C0(6537));
316 I915_WRITE(SPCSCC23(plane
), SPCSC_C1(-3330) | SPCSC_C0(0));
317 I915_WRITE(SPCSCC45(plane
), SPCSC_C1(-1605) | SPCSC_C0(4769));
318 I915_WRITE(SPCSCC67(plane
), SPCSC_C1(4769) | SPCSC_C0(0));
319 I915_WRITE(SPCSCC8(plane
), SPCSC_C0(8263));
321 I915_WRITE(SPCSCYGICLAMP(plane
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
322 I915_WRITE(SPCSCCBICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
323 I915_WRITE(SPCSCCRICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
325 I915_WRITE(SPCSCYGOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
326 I915_WRITE(SPCSCCBOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
327 I915_WRITE(SPCSCCROCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
331 vlv_update_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
,
332 struct drm_framebuffer
*fb
,
333 int crtc_x
, int crtc_y
,
334 unsigned int crtc_w
, unsigned int crtc_h
,
335 uint32_t x
, uint32_t y
,
336 uint32_t src_w
, uint32_t src_h
)
338 struct drm_device
*dev
= dplane
->dev
;
339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
341 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
342 int pipe
= intel_plane
->pipe
;
343 int plane
= intel_plane
->plane
;
345 unsigned long sprsurf_offset
, linear_offset
;
346 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
347 const struct drm_intel_sprite_colorkey
*key
= &intel_plane
->ckey
;
351 switch (fb
->pixel_format
) {
352 case DRM_FORMAT_YUYV
:
353 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
355 case DRM_FORMAT_YVYU
:
356 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
358 case DRM_FORMAT_UYVY
:
359 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
361 case DRM_FORMAT_VYUY
:
362 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
364 case DRM_FORMAT_RGB565
:
365 sprctl
|= SP_FORMAT_BGR565
;
367 case DRM_FORMAT_XRGB8888
:
368 sprctl
|= SP_FORMAT_BGRX8888
;
370 case DRM_FORMAT_ARGB8888
:
371 sprctl
|= SP_FORMAT_BGRA8888
;
373 case DRM_FORMAT_XBGR2101010
:
374 sprctl
|= SP_FORMAT_RGBX1010102
;
376 case DRM_FORMAT_ABGR2101010
:
377 sprctl
|= SP_FORMAT_RGBA1010102
;
379 case DRM_FORMAT_XBGR8888
:
380 sprctl
|= SP_FORMAT_RGBX8888
;
382 case DRM_FORMAT_ABGR8888
:
383 sprctl
|= SP_FORMAT_RGBA8888
;
387 * If we get here one of the upper layers failed to filter
388 * out the unsupported plane formats
395 * Enable gamma to match primary/cursor plane behaviour.
396 * FIXME should be user controllable via propertiesa.
398 sprctl
|= SP_GAMMA_ENABLE
;
400 if (obj
->tiling_mode
!= I915_TILING_NONE
)
403 intel_update_sprite_watermarks(dplane
, crtc
, src_w
, src_h
,
405 src_w
!= crtc_w
|| src_h
!= crtc_h
);
407 /* Sizes are 0 based */
413 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
414 sprsurf_offset
= intel_gen4_compute_page_offset(dev_priv
,
419 linear_offset
-= sprsurf_offset
;
421 if (dplane
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
422 sprctl
|= SP_ROTATE_180
;
426 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* pixel_size
;
430 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
431 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
432 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
435 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
436 sprctl
|= SP_SOURCE_KEY
;
438 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
)
439 chv_update_csc(intel_plane
, fb
->pixel_format
);
441 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
442 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
444 if (obj
->tiling_mode
!= I915_TILING_NONE
)
445 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
447 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
449 I915_WRITE(SPCONSTALPHA(pipe
, plane
), 0);
451 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
452 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
453 I915_WRITE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
455 POSTING_READ(SPSURF(pipe
, plane
));
459 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
, bool force
)
461 struct drm_device
*dev
= dplane
->dev
;
462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
463 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
464 int pipe
= intel_plane
->pipe
;
465 int plane
= intel_plane
->plane
;
467 I915_WRITE(SPCNTR(pipe
, plane
), 0);
469 I915_WRITE(SPSURF(pipe
, plane
), 0);
470 POSTING_READ(SPSURF(pipe
, plane
));
472 intel_update_sprite_watermarks(dplane
, crtc
, 0, 0, 0, false, false);
476 ivb_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
477 struct drm_framebuffer
*fb
,
478 int crtc_x
, int crtc_y
,
479 unsigned int crtc_w
, unsigned int crtc_h
,
480 uint32_t x
, uint32_t y
,
481 uint32_t src_w
, uint32_t src_h
)
483 struct drm_device
*dev
= plane
->dev
;
484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
485 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
486 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
487 enum pipe pipe
= intel_plane
->pipe
;
488 u32 sprctl
, sprscale
= 0;
489 unsigned long sprsurf_offset
, linear_offset
;
490 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
491 const struct drm_intel_sprite_colorkey
*key
= &intel_plane
->ckey
;
493 sprctl
= SPRITE_ENABLE
;
495 switch (fb
->pixel_format
) {
496 case DRM_FORMAT_XBGR8888
:
497 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
499 case DRM_FORMAT_XRGB8888
:
500 sprctl
|= SPRITE_FORMAT_RGBX888
;
502 case DRM_FORMAT_YUYV
:
503 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
505 case DRM_FORMAT_YVYU
:
506 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
508 case DRM_FORMAT_UYVY
:
509 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
511 case DRM_FORMAT_VYUY
:
512 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
519 * Enable gamma to match primary/cursor plane behaviour.
520 * FIXME should be user controllable via propertiesa.
522 sprctl
|= SPRITE_GAMMA_ENABLE
;
524 if (obj
->tiling_mode
!= I915_TILING_NONE
)
525 sprctl
|= SPRITE_TILED
;
527 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
528 sprctl
&= ~SPRITE_TRICKLE_FEED_DISABLE
;
530 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
532 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
533 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
535 intel_update_sprite_watermarks(plane
, crtc
, src_w
, src_h
, pixel_size
,
537 src_w
!= crtc_w
|| src_h
!= crtc_h
);
539 /* Sizes are 0 based */
545 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
546 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
548 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
550 intel_gen4_compute_page_offset(dev_priv
,
551 &x
, &y
, obj
->tiling_mode
,
552 pixel_size
, fb
->pitches
[0]);
553 linear_offset
-= sprsurf_offset
;
555 if (plane
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
556 sprctl
|= SPRITE_ROTATE_180
;
558 /* HSW and BDW does this automagically in hardware */
559 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
562 linear_offset
+= src_h
* fb
->pitches
[0] +
568 I915_WRITE(SPRKEYVAL(pipe
), key
->min_value
);
569 I915_WRITE(SPRKEYMAX(pipe
), key
->max_value
);
570 I915_WRITE(SPRKEYMSK(pipe
), key
->channel_mask
);
573 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
574 sprctl
|= SPRITE_DEST_KEY
;
575 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
576 sprctl
|= SPRITE_SOURCE_KEY
;
578 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
579 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
581 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
583 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
584 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
585 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
586 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
588 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
590 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
591 if (intel_plane
->can_scale
)
592 I915_WRITE(SPRSCALE(pipe
), sprscale
);
593 I915_WRITE(SPRCTL(pipe
), sprctl
);
594 I915_WRITE(SPRSURF(pipe
),
595 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
596 POSTING_READ(SPRSURF(pipe
));
600 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
, bool force
)
602 struct drm_device
*dev
= plane
->dev
;
603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
604 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
605 int pipe
= intel_plane
->pipe
;
607 I915_WRITE(SPRCTL(pipe
), I915_READ(SPRCTL(pipe
)) & ~SPRITE_ENABLE
);
608 /* Can't leave the scaler enabled... */
609 if (intel_plane
->can_scale
)
610 I915_WRITE(SPRSCALE(pipe
), 0);
612 I915_WRITE(SPRSURF(pipe
), 0);
613 POSTING_READ(SPRSURF(pipe
));
617 ilk_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
618 struct drm_framebuffer
*fb
,
619 int crtc_x
, int crtc_y
,
620 unsigned int crtc_w
, unsigned int crtc_h
,
621 uint32_t x
, uint32_t y
,
622 uint32_t src_w
, uint32_t src_h
)
624 struct drm_device
*dev
= plane
->dev
;
625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
626 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
627 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
628 int pipe
= intel_plane
->pipe
;
629 unsigned long dvssurf_offset
, linear_offset
;
630 u32 dvscntr
, dvsscale
;
631 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
632 const struct drm_intel_sprite_colorkey
*key
= &intel_plane
->ckey
;
634 dvscntr
= DVS_ENABLE
;
636 switch (fb
->pixel_format
) {
637 case DRM_FORMAT_XBGR8888
:
638 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
640 case DRM_FORMAT_XRGB8888
:
641 dvscntr
|= DVS_FORMAT_RGBX888
;
643 case DRM_FORMAT_YUYV
:
644 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
646 case DRM_FORMAT_YVYU
:
647 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
649 case DRM_FORMAT_UYVY
:
650 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
652 case DRM_FORMAT_VYUY
:
653 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
660 * Enable gamma to match primary/cursor plane behaviour.
661 * FIXME should be user controllable via propertiesa.
663 dvscntr
|= DVS_GAMMA_ENABLE
;
665 if (obj
->tiling_mode
!= I915_TILING_NONE
)
666 dvscntr
|= DVS_TILED
;
669 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
671 intel_update_sprite_watermarks(plane
, crtc
, src_w
, src_h
,
673 src_w
!= crtc_w
|| src_h
!= crtc_h
);
675 /* Sizes are 0 based */
682 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
683 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
685 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
687 intel_gen4_compute_page_offset(dev_priv
,
688 &x
, &y
, obj
->tiling_mode
,
689 pixel_size
, fb
->pitches
[0]);
690 linear_offset
-= dvssurf_offset
;
692 if (plane
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
693 dvscntr
|= DVS_ROTATE_180
;
697 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* pixel_size
;
701 I915_WRITE(DVSKEYVAL(pipe
), key
->min_value
);
702 I915_WRITE(DVSKEYMAX(pipe
), key
->max_value
);
703 I915_WRITE(DVSKEYMSK(pipe
), key
->channel_mask
);
706 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
707 dvscntr
|= DVS_DEST_KEY
;
708 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
709 dvscntr
|= DVS_SOURCE_KEY
;
711 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
712 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
714 if (obj
->tiling_mode
!= I915_TILING_NONE
)
715 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
717 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
719 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
720 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
721 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
722 I915_WRITE(DVSSURF(pipe
),
723 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
724 POSTING_READ(DVSSURF(pipe
));
728 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
, bool force
)
730 struct drm_device
*dev
= plane
->dev
;
731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
732 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
733 int pipe
= intel_plane
->pipe
;
735 I915_WRITE(DVSCNTR(pipe
), 0);
736 /* Disable the scaler */
737 I915_WRITE(DVSSCALE(pipe
), 0);
739 I915_WRITE(DVSSURF(pipe
), 0);
740 POSTING_READ(DVSSURF(pipe
));
744 intel_check_sprite_plane(struct drm_plane
*plane
,
745 struct intel_plane_state
*state
)
747 struct drm_device
*dev
= plane
->dev
;
748 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
749 struct intel_crtc_state
*crtc_state
;
750 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
751 struct drm_framebuffer
*fb
= state
->base
.fb
;
753 unsigned int crtc_w
, crtc_h
;
754 uint32_t src_x
, src_y
, src_w
, src_h
;
755 struct drm_rect
*src
= &state
->src
;
756 struct drm_rect
*dst
= &state
->dst
;
757 const struct drm_rect
*clip
= &state
->clip
;
759 int max_scale
, min_scale
;
764 intel_crtc
= intel_crtc
? intel_crtc
: to_intel_crtc(plane
->crtc
);
765 crtc_state
= state
->base
.state
?
766 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
769 state
->visible
= false;
773 /* Don't modify another pipe's plane */
774 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
775 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
779 /* FIXME check all gen limits */
780 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
781 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
785 /* setup can_scale, min_scale, max_scale */
786 if (INTEL_INFO(dev
)->gen
>= 9) {
787 /* use scaler when colorkey is not required */
788 if (intel_plane
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
791 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
794 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
795 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
798 can_scale
= intel_plane
->can_scale
;
799 max_scale
= intel_plane
->max_downscale
<< 16;
800 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
804 * FIXME the following code does a bunch of fuzzy adjustments to the
805 * coordinates and sizes. We probably need some way to decide whether
806 * more strict checking should be done instead.
809 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
810 state
->base
.rotation
);
812 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
815 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
818 state
->visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
822 crtc_w
= drm_rect_width(dst
);
823 crtc_h
= drm_rect_height(dst
);
825 if (state
->visible
) {
826 /* check again in case clipping clamped the results */
827 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
829 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
830 drm_rect_debug_print(src
, true);
831 drm_rect_debug_print(dst
, false);
836 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
838 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
839 drm_rect_debug_print(src
, true);
840 drm_rect_debug_print(dst
, false);
845 /* Make the source viewport size an exact multiple of the scaling factors. */
846 drm_rect_adjust_size(src
,
847 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
848 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
850 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
851 state
->base
.rotation
);
853 /* sanity check to make sure the src viewport wasn't enlarged */
854 WARN_ON(src
->x1
< (int) state
->base
.src_x
||
855 src
->y1
< (int) state
->base
.src_y
||
856 src
->x2
> (int) state
->base
.src_x
+ state
->base
.src_w
||
857 src
->y2
> (int) state
->base
.src_y
+ state
->base
.src_h
);
860 * Hardware doesn't handle subpixel coordinates.
861 * Adjust to (macro)pixel boundary, but be careful not to
862 * increase the source viewport size, because that could
863 * push the downscaling factor out of bounds.
865 src_x
= src
->x1
>> 16;
866 src_w
= drm_rect_width(src
) >> 16;
867 src_y
= src
->y1
>> 16;
868 src_h
= drm_rect_height(src
) >> 16;
870 if (format_is_yuv(fb
->pixel_format
)) {
875 * Must keep src and dst the
876 * same if we can't scale.
882 state
->visible
= false;
886 /* Check size restrictions when scaling */
887 if (state
->visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
888 unsigned int width_bytes
;
892 /* FIXME interlacing min height is 6 */
894 if (crtc_w
< 3 || crtc_h
< 3)
895 state
->visible
= false;
897 if (src_w
< 3 || src_h
< 3)
898 state
->visible
= false;
900 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
901 width_bytes
= ((src_x
* pixel_size
) & 63) +
904 if (INTEL_INFO(dev
)->gen
< 9 && (src_w
> 2048 || src_h
> 2048 ||
905 width_bytes
> 4096 || fb
->pitches
[0] > 4096)) {
906 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
911 if (state
->visible
) {
912 src
->x1
= src_x
<< 16;
913 src
->x2
= (src_x
+ src_w
) << 16;
914 src
->y1
= src_y
<< 16;
915 src
->y2
= (src_y
+ src_h
) << 16;
919 dst
->x2
= crtc_x
+ crtc_w
;
921 dst
->y2
= crtc_y
+ crtc_h
;
925 * If the sprite is completely covering the primary plane,
926 * we can disable the primary and save power.
928 if (intel_crtc
->active
) {
929 intel_crtc
->atomic
.fb_bits
|=
930 INTEL_FRONTBUFFER_SPRITE(intel_crtc
->pipe
);
932 if (intel_wm_need_update(plane
, &state
->base
))
933 intel_crtc
->atomic
.update_wm
= true;
935 if (!state
->visible
) {
937 * Avoid underruns when disabling the sprite.
938 * FIXME remove once watermark updates are done properly.
940 intel_crtc
->atomic
.wait_vblank
= true;
941 intel_crtc
->atomic
.update_sprite_watermarks
|=
942 (1 << drm_plane_index(plane
));
946 if (INTEL_INFO(dev
)->gen
>= 9) {
947 ret
= skl_update_scaler_plane(crtc_state
, intel_plane
, state
);
956 intel_commit_sprite_plane(struct drm_plane
*plane
,
957 struct intel_plane_state
*state
)
959 struct drm_crtc
*crtc
= state
->base
.crtc
;
960 struct intel_crtc
*intel_crtc
;
961 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
962 struct drm_framebuffer
*fb
= state
->base
.fb
;
964 unsigned int crtc_w
, crtc_h
;
965 uint32_t src_x
, src_y
, src_w
, src_h
;
967 crtc
= crtc
? crtc
: plane
->crtc
;
968 intel_crtc
= to_intel_crtc(crtc
);
972 if (intel_crtc
->active
) {
973 if (state
->visible
) {
974 crtc_x
= state
->dst
.x1
;
975 crtc_y
= state
->dst
.y1
;
976 crtc_w
= drm_rect_width(&state
->dst
);
977 crtc_h
= drm_rect_height(&state
->dst
);
978 src_x
= state
->src
.x1
>> 16;
979 src_y
= state
->src
.y1
>> 16;
980 src_w
= drm_rect_width(&state
->src
) >> 16;
981 src_h
= drm_rect_height(&state
->src
) >> 16;
982 intel_plane
->update_plane(plane
, crtc
, fb
,
983 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
984 src_x
, src_y
, src_w
, src_h
);
986 intel_plane
->disable_plane(plane
, crtc
, false);
991 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
992 struct drm_file
*file_priv
)
994 struct drm_intel_sprite_colorkey
*set
= data
;
995 struct drm_plane
*plane
;
996 struct intel_plane
*intel_plane
;
999 /* Make sure we don't try to enable both src & dest simultaneously */
1000 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
1003 if (IS_VALLEYVIEW(dev
) &&
1004 set
->flags
& I915_SET_COLORKEY_DESTINATION
)
1007 drm_modeset_lock_all(dev
);
1009 plane
= drm_plane_find(dev
, set
->plane_id
);
1010 if (!plane
|| plane
->type
!= DRM_PLANE_TYPE_OVERLAY
) {
1015 intel_plane
= to_intel_plane(plane
);
1017 if (INTEL_INFO(dev
)->gen
>= 9) {
1018 /* plane scaling and colorkey are mutually exclusive */
1019 if (to_intel_plane_state(plane
->state
)->scaler_id
>= 0) {
1020 DRM_ERROR("colorkey not allowed with scaler\n");
1026 intel_plane
->ckey
= *set
;
1029 * The only way this could fail would be due to
1030 * the current plane state being unsupportable already,
1031 * and we dont't consider that an error for the
1032 * colorkey ioctl. So just ignore any error.
1034 intel_plane_restore(plane
);
1037 drm_modeset_unlock_all(dev
);
1041 int intel_plane_restore(struct drm_plane
*plane
)
1043 if (!plane
->crtc
|| !plane
->state
->fb
)
1046 return drm_plane_helper_update(plane
, plane
->crtc
, plane
->state
->fb
,
1047 plane
->state
->crtc_x
, plane
->state
->crtc_y
,
1048 plane
->state
->crtc_w
, plane
->state
->crtc_h
,
1049 plane
->state
->src_x
, plane
->state
->src_y
,
1050 plane
->state
->src_w
, plane
->state
->src_h
);
1053 static const uint32_t ilk_plane_formats
[] = {
1054 DRM_FORMAT_XRGB8888
,
1061 static const uint32_t snb_plane_formats
[] = {
1062 DRM_FORMAT_XBGR8888
,
1063 DRM_FORMAT_XRGB8888
,
1070 static const uint32_t vlv_plane_formats
[] = {
1072 DRM_FORMAT_ABGR8888
,
1073 DRM_FORMAT_ARGB8888
,
1074 DRM_FORMAT_XBGR8888
,
1075 DRM_FORMAT_XRGB8888
,
1076 DRM_FORMAT_XBGR2101010
,
1077 DRM_FORMAT_ABGR2101010
,
1084 static uint32_t skl_plane_formats
[] = {
1086 DRM_FORMAT_ABGR8888
,
1087 DRM_FORMAT_ARGB8888
,
1088 DRM_FORMAT_XBGR8888
,
1089 DRM_FORMAT_XRGB8888
,
1097 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1099 struct intel_plane
*intel_plane
;
1100 struct intel_plane_state
*state
;
1101 unsigned long possible_crtcs
;
1102 const uint32_t *plane_formats
;
1103 int num_plane_formats
;
1106 if (INTEL_INFO(dev
)->gen
< 5)
1109 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1113 state
= intel_create_plane_state(&intel_plane
->base
);
1118 intel_plane
->base
.state
= &state
->base
;
1120 switch (INTEL_INFO(dev
)->gen
) {
1123 intel_plane
->can_scale
= true;
1124 intel_plane
->max_downscale
= 16;
1125 intel_plane
->update_plane
= ilk_update_plane
;
1126 intel_plane
->disable_plane
= ilk_disable_plane
;
1129 plane_formats
= snb_plane_formats
;
1130 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1132 plane_formats
= ilk_plane_formats
;
1133 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1139 if (IS_IVYBRIDGE(dev
)) {
1140 intel_plane
->can_scale
= true;
1141 intel_plane
->max_downscale
= 2;
1143 intel_plane
->can_scale
= false;
1144 intel_plane
->max_downscale
= 1;
1147 if (IS_VALLEYVIEW(dev
)) {
1148 intel_plane
->update_plane
= vlv_update_plane
;
1149 intel_plane
->disable_plane
= vlv_disable_plane
;
1151 plane_formats
= vlv_plane_formats
;
1152 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1154 intel_plane
->update_plane
= ivb_update_plane
;
1155 intel_plane
->disable_plane
= ivb_disable_plane
;
1157 plane_formats
= snb_plane_formats
;
1158 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1162 intel_plane
->can_scale
= true;
1163 intel_plane
->update_plane
= skl_update_plane
;
1164 intel_plane
->disable_plane
= skl_disable_plane
;
1165 state
->scaler_id
= -1;
1167 plane_formats
= skl_plane_formats
;
1168 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1175 intel_plane
->pipe
= pipe
;
1176 intel_plane
->plane
= plane
;
1177 intel_plane
->check_plane
= intel_check_sprite_plane
;
1178 intel_plane
->commit_plane
= intel_commit_sprite_plane
;
1179 intel_plane
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
1180 possible_crtcs
= (1 << pipe
);
1181 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1183 plane_formats
, num_plane_formats
,
1184 DRM_PLANE_TYPE_OVERLAY
);
1190 intel_create_rotation_property(dev
, intel_plane
);
1192 drm_plane_helper_add(&intel_plane
->base
, &intel_plane_helper_funcs
);