2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names
[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names
) != FW_DOMAIN_ID_COUNT
);
45 if (id
>= 0 && id
< FW_DOMAIN_ID_COUNT
)
46 return forcewake_domain_names
[id
];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain
*d
)
56 WARN_ON(!i915_mmio_reg_valid(d
->reg_set
));
57 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_reset
);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain
*d
)
64 hrtimer_start_range_ns(&d
->timer
,
65 ktime_set(0, NSEC_PER_MSEC
),
71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain
*d
)
73 if (wait_for_atomic((__raw_i915_read32(d
->i915
, d
->reg_ack
) &
74 FORCEWAKE_KERNEL
) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS
))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d
->id
));
81 fw_domain_get(const struct intel_uncore_forcewake_domain
*d
)
83 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_set
);
87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain
*d
)
89 if (wait_for_atomic((__raw_i915_read32(d
->i915
, d
->reg_ack
) &
91 FORCEWAKE_ACK_TIMEOUT_MS
))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d
->id
));
97 fw_domain_put(const struct intel_uncore_forcewake_domain
*d
)
99 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_clear
);
103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain
*d
)
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d
->reg_post
))
107 __raw_posting_read(d
->i915
, d
->reg_post
);
111 fw_domains_get(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
113 struct intel_uncore_forcewake_domain
*d
;
115 for_each_fw_domain_masked(d
, fw_domains
, dev_priv
) {
116 fw_domain_wait_ack_clear(d
);
120 for_each_fw_domain_masked(d
, fw_domains
, dev_priv
)
121 fw_domain_wait_ack(d
);
125 fw_domains_put(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
127 struct intel_uncore_forcewake_domain
*d
;
129 for_each_fw_domain_masked(d
, fw_domains
, dev_priv
) {
131 fw_domain_posting_read(d
);
136 fw_domains_posting_read(struct drm_i915_private
*dev_priv
)
138 struct intel_uncore_forcewake_domain
*d
;
140 /* No need to do for all, just do for first found */
141 for_each_fw_domain(d
, dev_priv
) {
142 fw_domain_posting_read(d
);
148 fw_domains_reset(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
150 struct intel_uncore_forcewake_domain
*d
;
152 if (dev_priv
->uncore
.fw_domains
== 0)
155 for_each_fw_domain_masked(d
, fw_domains
, dev_priv
)
158 fw_domains_posting_read(dev_priv
);
161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
163 /* w/a for a sporadic read returning 0 by waiting for the GT
166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv
, GEN6_GT_THREAD_STATUS_REG
) &
167 GEN6_GT_THREAD_STATUS_CORE_MASK
) == 0, 500))
168 DRM_ERROR("GT thread status wait timed out\n");
171 static void fw_domains_get_with_thread_status(struct drm_i915_private
*dev_priv
,
172 enum forcewake_domains fw_domains
)
174 fw_domains_get(dev_priv
, fw_domains
);
176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
177 __gen6_gt_wait_for_thread_c0(dev_priv
);
180 static void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
184 gtfifodbg
= __raw_i915_read32(dev_priv
, GTFIFODBG
);
185 if (WARN(gtfifodbg
, "GT wake FIFO error 0x%x\n", gtfifodbg
))
186 __raw_i915_write32(dev_priv
, GTFIFODBG
, gtfifodbg
);
189 static void fw_domains_put_with_fifo(struct drm_i915_private
*dev_priv
,
190 enum forcewake_domains fw_domains
)
192 fw_domains_put(dev_priv
, fw_domains
);
193 gen6_gt_check_fifodbg(dev_priv
);
196 static inline u32
fifo_free_entries(struct drm_i915_private
*dev_priv
)
198 u32 count
= __raw_i915_read32(dev_priv
, GTFIFOCTL
);
200 return count
& GT_FIFO_FREE_ENTRIES_MASK
;
203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
207 /* On VLV, FIFO will be shared by both SW and HW.
208 * So, we need to read the FREE_ENTRIES everytime */
209 if (IS_VALLEYVIEW(dev_priv
))
210 dev_priv
->uncore
.fifo_count
= fifo_free_entries(dev_priv
);
212 if (dev_priv
->uncore
.fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
214 u32 fifo
= fifo_free_entries(dev_priv
);
216 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
218 fifo
= fifo_free_entries(dev_priv
);
220 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
222 dev_priv
->uncore
.fifo_count
= fifo
;
224 dev_priv
->uncore
.fifo_count
--;
229 static enum hrtimer_restart
230 intel_uncore_fw_release_timer(struct hrtimer
*timer
)
232 struct intel_uncore_forcewake_domain
*domain
=
233 container_of(timer
, struct intel_uncore_forcewake_domain
, timer
);
234 unsigned long irqflags
;
236 assert_rpm_device_not_suspended(domain
->i915
);
238 spin_lock_irqsave(&domain
->i915
->uncore
.lock
, irqflags
);
239 if (WARN_ON(domain
->wake_count
== 0))
240 domain
->wake_count
++;
242 if (--domain
->wake_count
== 0)
243 domain
->i915
->uncore
.funcs
.force_wake_put(domain
->i915
,
246 spin_unlock_irqrestore(&domain
->i915
->uncore
.lock
, irqflags
);
248 return HRTIMER_NORESTART
;
251 void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
254 unsigned long irqflags
;
255 struct intel_uncore_forcewake_domain
*domain
;
256 int retry_count
= 100;
257 enum forcewake_domains fw
= 0, active_domains
;
259 /* Hold uncore.lock across reset to prevent any register access
260 * with forcewake not set correctly. Wait until all pending
261 * timers are run before holding.
266 for_each_fw_domain(domain
, dev_priv
) {
267 if (hrtimer_cancel(&domain
->timer
) == 0)
270 intel_uncore_fw_release_timer(&domain
->timer
);
273 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
275 for_each_fw_domain(domain
, dev_priv
) {
276 if (hrtimer_active(&domain
->timer
))
277 active_domains
|= domain
->mask
;
280 if (active_domains
== 0)
283 if (--retry_count
== 0) {
284 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
288 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
292 WARN_ON(active_domains
);
294 for_each_fw_domain(domain
, dev_priv
)
295 if (domain
->wake_count
)
299 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, fw
);
301 fw_domains_reset(dev_priv
, FORCEWAKE_ALL
);
303 if (restore
) { /* If reset with a user forcewake, try to restore */
305 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw
);
307 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
))
308 dev_priv
->uncore
.fifo_count
=
309 fifo_free_entries(dev_priv
);
313 assert_forcewakes_inactive(dev_priv
);
315 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
318 static u64
gen9_edram_size(struct drm_i915_private
*dev_priv
)
320 const unsigned int ways
[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
321 const unsigned int sets
[4] = { 1, 1, 2, 2 };
322 const u32 cap
= dev_priv
->edram_cap
;
324 return EDRAM_NUM_BANKS(cap
) *
325 ways
[EDRAM_WAYS_IDX(cap
)] *
326 sets
[EDRAM_SETS_IDX(cap
)] *
330 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
)
332 if (!HAS_EDRAM(dev_priv
))
335 /* The needed capability bits for size calculation
336 * are not there with pre gen9 so return 128MB always.
338 if (INTEL_GEN(dev_priv
) < 9)
339 return 128 * 1024 * 1024;
341 return gen9_edram_size(dev_priv
);
344 static void intel_uncore_edram_detect(struct drm_i915_private
*dev_priv
)
346 if (IS_HASWELL(dev_priv
) ||
347 IS_BROADWELL(dev_priv
) ||
348 INTEL_GEN(dev_priv
) >= 9) {
349 dev_priv
->edram_cap
= __raw_i915_read32(dev_priv
,
352 /* NB: We can't write IDICR yet because we do not have gt funcs
355 dev_priv
->edram_cap
= 0;
358 if (HAS_EDRAM(dev_priv
))
359 DRM_INFO("Found %lluMB of eDRAM\n",
360 intel_uncore_edram_size(dev_priv
) / (1024 * 1024));
364 fpga_check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
368 dbg
= __raw_i915_read32(dev_priv
, FPGA_DBG
);
369 if (likely(!(dbg
& FPGA_DBG_RM_NOCLAIM
)))
372 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
378 vlv_check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
382 cer
= __raw_i915_read32(dev_priv
, CLAIM_ER
);
383 if (likely(!(cer
& (CLAIM_ER_OVERFLOW
| CLAIM_ER_CTR_MASK
))))
386 __raw_i915_write32(dev_priv
, CLAIM_ER
, CLAIM_ER_CLR
);
392 check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
394 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
))
395 return fpga_check_for_unclaimed_mmio(dev_priv
);
397 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
398 return vlv_check_for_unclaimed_mmio(dev_priv
);
403 static void __intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
404 bool restore_forcewake
)
406 /* clear out unclaimed reg detection bit */
407 if (check_for_unclaimed_mmio(dev_priv
))
408 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
410 /* clear out old GT FIFO errors */
411 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
))
412 __raw_i915_write32(dev_priv
, GTFIFODBG
,
413 __raw_i915_read32(dev_priv
, GTFIFODBG
));
415 /* WaDisableShadowRegForCpd:chv */
416 if (IS_CHERRYVIEW(dev_priv
)) {
417 __raw_i915_write32(dev_priv
, GTFIFOCTL
,
418 __raw_i915_read32(dev_priv
, GTFIFOCTL
) |
419 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL
|
420 GT_FIFO_CTL_RC6_POLICY_STALL
);
423 intel_uncore_forcewake_reset(dev_priv
, restore_forcewake
);
426 void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
427 bool restore_forcewake
)
429 __intel_uncore_early_sanitize(dev_priv
, restore_forcewake
);
430 i915_check_and_clear_faults(dev_priv
);
433 void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
)
435 i915
.enable_rc6
= sanitize_rc6_option(dev_priv
, i915
.enable_rc6
);
437 /* BIOS often leaves RC6 enabled, but disable it for hw init */
438 intel_disable_gt_powersave(dev_priv
);
441 static void __intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
442 enum forcewake_domains fw_domains
)
444 struct intel_uncore_forcewake_domain
*domain
;
446 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
449 fw_domains
&= dev_priv
->uncore
.fw_domains
;
451 for_each_fw_domain_masked(domain
, fw_domains
, dev_priv
) {
452 if (domain
->wake_count
++)
453 fw_domains
&= ~domain
->mask
;
457 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
461 * intel_uncore_forcewake_get - grab forcewake domain references
462 * @dev_priv: i915 device instance
463 * @fw_domains: forcewake domains to get reference on
465 * This function can be used get GT's forcewake domain references.
466 * Normal register access will handle the forcewake domains automatically.
467 * However if some sequence requires the GT to not power down a particular
468 * forcewake domains this function should be called at the beginning of the
469 * sequence. And subsequently the reference should be dropped by symmetric
470 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
471 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
473 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
474 enum forcewake_domains fw_domains
)
476 unsigned long irqflags
;
478 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
481 assert_rpm_wakelock_held(dev_priv
);
483 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
484 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
485 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
489 * intel_uncore_forcewake_get__locked - grab forcewake domain references
490 * @dev_priv: i915 device instance
491 * @fw_domains: forcewake domains to get reference on
493 * See intel_uncore_forcewake_get(). This variant places the onus
494 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
496 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
497 enum forcewake_domains fw_domains
)
499 assert_spin_locked(&dev_priv
->uncore
.lock
);
501 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
504 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
507 static void __intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
508 enum forcewake_domains fw_domains
)
510 struct intel_uncore_forcewake_domain
*domain
;
512 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
515 fw_domains
&= dev_priv
->uncore
.fw_domains
;
517 for_each_fw_domain_masked(domain
, fw_domains
, dev_priv
) {
518 if (WARN_ON(domain
->wake_count
== 0))
521 if (--domain
->wake_count
)
524 fw_domain_arm_timer(domain
);
529 * intel_uncore_forcewake_put - release a forcewake domain reference
530 * @dev_priv: i915 device instance
531 * @fw_domains: forcewake domains to put references
533 * This function drops the device-level forcewakes for specified
534 * domains obtained by intel_uncore_forcewake_get().
536 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
537 enum forcewake_domains fw_domains
)
539 unsigned long irqflags
;
541 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
544 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
545 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
546 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
550 * intel_uncore_forcewake_put__locked - grab forcewake domain references
551 * @dev_priv: i915 device instance
552 * @fw_domains: forcewake domains to get reference on
554 * See intel_uncore_forcewake_put(). This variant places the onus
555 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
557 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
558 enum forcewake_domains fw_domains
)
560 assert_spin_locked(&dev_priv
->uncore
.lock
);
562 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
565 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
568 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
)
570 struct intel_uncore_forcewake_domain
*domain
;
572 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
575 for_each_fw_domain(domain
, dev_priv
)
576 WARN_ON(domain
->wake_count
);
579 /* We give fast paths for the really cool registers */
580 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
582 #define __gen6_reg_read_fw_domains(offset) \
584 enum forcewake_domains __fwd; \
585 if (NEEDS_FORCE_WAKE(offset)) \
586 __fwd = FORCEWAKE_RENDER; \
592 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
594 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
595 (REG_RANGE((reg), 0x2000, 0x4000) || \
596 REG_RANGE((reg), 0x5000, 0x8000) || \
597 REG_RANGE((reg), 0xB000, 0x12000) || \
598 REG_RANGE((reg), 0x2E000, 0x30000))
600 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
601 (REG_RANGE((reg), 0x12000, 0x14000) || \
602 REG_RANGE((reg), 0x22000, 0x24000) || \
603 REG_RANGE((reg), 0x30000, 0x40000))
605 #define __vlv_reg_read_fw_domains(offset) \
607 enum forcewake_domains __fwd = 0; \
608 if (!NEEDS_FORCE_WAKE(offset)) \
610 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
611 __fwd = FORCEWAKE_RENDER; \
612 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
613 __fwd = FORCEWAKE_MEDIA; \
617 static const i915_reg_t gen8_shadowed_regs
[] = {
620 RING_TAIL(RENDER_RING_BASE
),
621 RING_TAIL(GEN6_BSD_RING_BASE
),
622 RING_TAIL(VEBOX_RING_BASE
),
623 RING_TAIL(BLT_RING_BASE
),
624 /* TODO: Other registers are not yet used */
627 static bool is_gen8_shadowed(u32 offset
)
630 for (i
= 0; i
< ARRAY_SIZE(gen8_shadowed_regs
); i
++)
631 if (offset
== gen8_shadowed_regs
[i
].reg
)
637 #define __gen8_reg_write_fw_domains(offset) \
639 enum forcewake_domains __fwd; \
640 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
641 __fwd = FORCEWAKE_RENDER; \
647 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
648 (REG_RANGE((reg), 0x2000, 0x4000) || \
649 REG_RANGE((reg), 0x5200, 0x8000) || \
650 REG_RANGE((reg), 0x8300, 0x8500) || \
651 REG_RANGE((reg), 0xB000, 0xB480) || \
652 REG_RANGE((reg), 0xE000, 0xE800))
654 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
655 (REG_RANGE((reg), 0x8800, 0x8900) || \
656 REG_RANGE((reg), 0xD000, 0xD800) || \
657 REG_RANGE((reg), 0x12000, 0x14000) || \
658 REG_RANGE((reg), 0x1A000, 0x1C000) || \
659 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
660 REG_RANGE((reg), 0x30000, 0x38000))
662 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
663 (REG_RANGE((reg), 0x4000, 0x5000) || \
664 REG_RANGE((reg), 0x8000, 0x8300) || \
665 REG_RANGE((reg), 0x8500, 0x8600) || \
666 REG_RANGE((reg), 0x9000, 0xB000) || \
667 REG_RANGE((reg), 0xF000, 0x10000))
669 #define __chv_reg_read_fw_domains(offset) \
671 enum forcewake_domains __fwd = 0; \
672 if (!NEEDS_FORCE_WAKE(offset)) \
674 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
675 __fwd = FORCEWAKE_RENDER; \
676 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
677 __fwd = FORCEWAKE_MEDIA; \
678 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
679 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
683 #define __chv_reg_write_fw_domains(offset) \
685 enum forcewake_domains __fwd = 0; \
686 if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
688 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
689 __fwd = FORCEWAKE_RENDER; \
690 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
691 __fwd = FORCEWAKE_MEDIA; \
692 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
693 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
697 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
698 REG_RANGE((reg), 0xB00, 0x2000)
700 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
701 (REG_RANGE((reg), 0x2000, 0x2700) || \
702 REG_RANGE((reg), 0x3000, 0x4000) || \
703 REG_RANGE((reg), 0x5200, 0x8000) || \
704 REG_RANGE((reg), 0x8140, 0x8160) || \
705 REG_RANGE((reg), 0x8300, 0x8500) || \
706 REG_RANGE((reg), 0x8C00, 0x8D00) || \
707 REG_RANGE((reg), 0xB000, 0xB480) || \
708 REG_RANGE((reg), 0xE000, 0xE900) || \
709 REG_RANGE((reg), 0x24400, 0x24800))
711 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
712 (REG_RANGE((reg), 0x8130, 0x8140) || \
713 REG_RANGE((reg), 0x8800, 0x8A00) || \
714 REG_RANGE((reg), 0xD000, 0xD800) || \
715 REG_RANGE((reg), 0x12000, 0x14000) || \
716 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
717 REG_RANGE((reg), 0x30000, 0x40000))
719 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
720 REG_RANGE((reg), 0x9400, 0x9800)
722 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
723 ((reg) < 0x40000 && \
724 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
725 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
726 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
727 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
729 #define SKL_NEEDS_FORCE_WAKE(reg) \
730 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
732 #define __gen9_reg_read_fw_domains(offset) \
734 enum forcewake_domains __fwd; \
735 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
737 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
738 __fwd = FORCEWAKE_RENDER; \
739 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
740 __fwd = FORCEWAKE_MEDIA; \
741 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
742 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
744 __fwd = FORCEWAKE_BLITTER; \
748 static const i915_reg_t gen9_shadowed_regs
[] = {
749 RING_TAIL(RENDER_RING_BASE
),
750 RING_TAIL(GEN6_BSD_RING_BASE
),
751 RING_TAIL(VEBOX_RING_BASE
),
752 RING_TAIL(BLT_RING_BASE
),
755 /* TODO: Other registers are not yet used */
758 static bool is_gen9_shadowed(u32 offset
)
761 for (i
= 0; i
< ARRAY_SIZE(gen9_shadowed_regs
); i
++)
762 if (offset
== gen9_shadowed_regs
[i
].reg
)
768 #define __gen9_reg_write_fw_domains(offset) \
770 enum forcewake_domains __fwd; \
771 if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
773 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
774 __fwd = FORCEWAKE_RENDER; \
775 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
776 __fwd = FORCEWAKE_MEDIA; \
777 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
778 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
780 __fwd = FORCEWAKE_BLITTER; \
785 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
787 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
788 * the chip from rc6 before touching it for real. MI_MODE is masked,
789 * hence harmless to write 0 into. */
790 __raw_i915_write32(dev_priv
, MI_MODE
, 0);
794 __unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
795 const i915_reg_t reg
,
799 if (WARN(check_for_unclaimed_mmio(dev_priv
),
800 "Unclaimed register detected %s %s register 0x%x\n",
801 before
? "before" : "after",
802 read
? "reading" : "writing to",
803 i915_mmio_reg_offset(reg
)))
804 i915
.mmio_debug
--; /* Only report the first N failures */
808 unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
809 const i915_reg_t reg
,
813 if (likely(!i915
.mmio_debug
))
816 __unclaimed_reg_debug(dev_priv
, reg
, read
, before
);
819 #define GEN2_READ_HEADER(x) \
821 assert_rpm_wakelock_held(dev_priv);
823 #define GEN2_READ_FOOTER \
824 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
827 #define __gen2_read(x) \
829 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
830 GEN2_READ_HEADER(x); \
831 val = __raw_i915_read##x(dev_priv, reg); \
835 #define __gen5_read(x) \
837 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
838 GEN2_READ_HEADER(x); \
839 ilk_dummy_write(dev_priv); \
840 val = __raw_i915_read##x(dev_priv, reg); \
856 #undef GEN2_READ_FOOTER
857 #undef GEN2_READ_HEADER
859 #define GEN6_READ_HEADER(x) \
860 u32 offset = i915_mmio_reg_offset(reg); \
861 unsigned long irqflags; \
863 assert_rpm_wakelock_held(dev_priv); \
864 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
865 unclaimed_reg_debug(dev_priv, reg, true, true)
867 #define GEN6_READ_FOOTER \
868 unclaimed_reg_debug(dev_priv, reg, true, false); \
869 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
870 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
873 static inline void __force_wake_auto(struct drm_i915_private
*dev_priv
,
874 enum forcewake_domains fw_domains
)
876 struct intel_uncore_forcewake_domain
*domain
;
878 if (WARN_ON(!fw_domains
))
881 /* Ideally GCC would be constant-fold and eliminate this loop */
882 for_each_fw_domain_masked(domain
, fw_domains
, dev_priv
) {
883 if (domain
->wake_count
) {
884 fw_domains
&= ~domain
->mask
;
888 fw_domain_arm_timer(domain
);
892 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
895 #define __gen6_read(x) \
897 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
898 enum forcewake_domains fw_engine; \
899 GEN6_READ_HEADER(x); \
900 fw_engine = __gen6_reg_read_fw_domains(offset); \
902 __force_wake_auto(dev_priv, fw_engine); \
903 val = __raw_i915_read##x(dev_priv, reg); \
907 #define __vlv_read(x) \
909 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
910 enum forcewake_domains fw_engine; \
911 GEN6_READ_HEADER(x); \
912 fw_engine = __vlv_reg_read_fw_domains(offset); \
914 __force_wake_auto(dev_priv, fw_engine); \
915 val = __raw_i915_read##x(dev_priv, reg); \
919 #define __chv_read(x) \
921 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
922 enum forcewake_domains fw_engine; \
923 GEN6_READ_HEADER(x); \
924 fw_engine = __chv_reg_read_fw_domains(offset); \
926 __force_wake_auto(dev_priv, fw_engine); \
927 val = __raw_i915_read##x(dev_priv, reg); \
931 #define __gen9_read(x) \
933 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
934 enum forcewake_domains fw_engine; \
935 GEN6_READ_HEADER(x); \
936 fw_engine = __gen9_reg_read_fw_domains(offset); \
938 __force_wake_auto(dev_priv, fw_engine); \
939 val = __raw_i915_read##x(dev_priv, reg); \
964 #undef GEN6_READ_FOOTER
965 #undef GEN6_READ_HEADER
967 #define VGPU_READ_HEADER(x) \
968 unsigned long irqflags; \
970 assert_rpm_device_not_suspended(dev_priv); \
971 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
973 #define VGPU_READ_FOOTER \
974 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
975 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
978 #define __vgpu_read(x) \
980 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
981 VGPU_READ_HEADER(x); \
982 val = __raw_i915_read##x(dev_priv, reg); \
992 #undef VGPU_READ_FOOTER
993 #undef VGPU_READ_HEADER
995 #define GEN2_WRITE_HEADER \
996 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
997 assert_rpm_wakelock_held(dev_priv); \
999 #define GEN2_WRITE_FOOTER
1001 #define __gen2_write(x) \
1003 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1004 GEN2_WRITE_HEADER; \
1005 __raw_i915_write##x(dev_priv, reg, val); \
1006 GEN2_WRITE_FOOTER; \
1009 #define __gen5_write(x) \
1011 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1012 GEN2_WRITE_HEADER; \
1013 ilk_dummy_write(dev_priv); \
1014 __raw_i915_write##x(dev_priv, reg, val); \
1015 GEN2_WRITE_FOOTER; \
1030 #undef GEN2_WRITE_FOOTER
1031 #undef GEN2_WRITE_HEADER
1033 #define GEN6_WRITE_HEADER \
1034 u32 offset = i915_mmio_reg_offset(reg); \
1035 unsigned long irqflags; \
1036 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1037 assert_rpm_wakelock_held(dev_priv); \
1038 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1039 unclaimed_reg_debug(dev_priv, reg, false, true)
1041 #define GEN6_WRITE_FOOTER \
1042 unclaimed_reg_debug(dev_priv, reg, false, false); \
1043 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1045 #define __gen6_write(x) \
1047 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1048 u32 __fifo_ret = 0; \
1049 GEN6_WRITE_HEADER; \
1050 if (NEEDS_FORCE_WAKE(offset)) { \
1051 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1053 __raw_i915_write##x(dev_priv, reg, val); \
1054 if (unlikely(__fifo_ret)) { \
1055 gen6_gt_check_fifodbg(dev_priv); \
1057 GEN6_WRITE_FOOTER; \
1060 #define __hsw_write(x) \
1062 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1063 u32 __fifo_ret = 0; \
1064 GEN6_WRITE_HEADER; \
1065 if (NEEDS_FORCE_WAKE(offset)) { \
1066 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1068 __raw_i915_write##x(dev_priv, reg, val); \
1069 if (unlikely(__fifo_ret)) { \
1070 gen6_gt_check_fifodbg(dev_priv); \
1072 GEN6_WRITE_FOOTER; \
1075 #define __gen8_write(x) \
1077 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1078 enum forcewake_domains fw_engine; \
1079 GEN6_WRITE_HEADER; \
1080 fw_engine = __gen8_reg_write_fw_domains(offset); \
1082 __force_wake_auto(dev_priv, fw_engine); \
1083 __raw_i915_write##x(dev_priv, reg, val); \
1084 GEN6_WRITE_FOOTER; \
1087 #define __chv_write(x) \
1089 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1090 enum forcewake_domains fw_engine; \
1091 GEN6_WRITE_HEADER; \
1092 fw_engine = __chv_reg_write_fw_domains(offset); \
1094 __force_wake_auto(dev_priv, fw_engine); \
1095 __raw_i915_write##x(dev_priv, reg, val); \
1096 GEN6_WRITE_FOOTER; \
1099 #define __gen9_write(x) \
1101 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1103 enum forcewake_domains fw_engine; \
1104 GEN6_WRITE_HEADER; \
1105 fw_engine = __gen9_reg_write_fw_domains(offset); \
1107 __force_wake_auto(dev_priv, fw_engine); \
1108 __raw_i915_write##x(dev_priv, reg, val); \
1109 GEN6_WRITE_FOOTER; \
1138 #undef GEN6_WRITE_FOOTER
1139 #undef GEN6_WRITE_HEADER
1141 #define VGPU_WRITE_HEADER \
1142 unsigned long irqflags; \
1143 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1144 assert_rpm_device_not_suspended(dev_priv); \
1145 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1147 #define VGPU_WRITE_FOOTER \
1148 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1150 #define __vgpu_write(x) \
1151 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1152 i915_reg_t reg, u##x val, bool trace) { \
1153 VGPU_WRITE_HEADER; \
1154 __raw_i915_write##x(dev_priv, reg, val); \
1155 VGPU_WRITE_FOOTER; \
1164 #undef VGPU_WRITE_FOOTER
1165 #undef VGPU_WRITE_HEADER
1167 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1169 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1170 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1171 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1172 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1175 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1177 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1178 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1179 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1180 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1184 static void fw_domain_init(struct drm_i915_private
*dev_priv
,
1185 enum forcewake_domain_id domain_id
,
1189 struct intel_uncore_forcewake_domain
*d
;
1191 if (WARN_ON(domain_id
>= FW_DOMAIN_ID_COUNT
))
1194 d
= &dev_priv
->uncore
.fw_domain
[domain_id
];
1196 WARN_ON(d
->wake_count
);
1199 d
->reg_set
= reg_set
;
1200 d
->reg_ack
= reg_ack
;
1202 if (IS_GEN6(dev_priv
)) {
1204 d
->val_set
= FORCEWAKE_KERNEL
;
1207 /* WaRsClearFWBitsAtReset:bdw,skl */
1208 d
->val_reset
= _MASKED_BIT_DISABLE(0xffff);
1209 d
->val_set
= _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
);
1210 d
->val_clear
= _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
);
1213 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1214 d
->reg_post
= FORCEWAKE_ACK_VLV
;
1215 else if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
) || IS_GEN8(dev_priv
))
1216 d
->reg_post
= ECOBUS
;
1221 BUILD_BUG_ON(FORCEWAKE_RENDER
!= (1 << FW_DOMAIN_ID_RENDER
));
1222 BUILD_BUG_ON(FORCEWAKE_BLITTER
!= (1 << FW_DOMAIN_ID_BLITTER
));
1223 BUILD_BUG_ON(FORCEWAKE_MEDIA
!= (1 << FW_DOMAIN_ID_MEDIA
));
1225 d
->mask
= 1 << domain_id
;
1227 hrtimer_init(&d
->timer
, CLOCK_MONOTONIC
, HRTIMER_MODE_REL
);
1228 d
->timer
.function
= intel_uncore_fw_release_timer
;
1230 dev_priv
->uncore
.fw_domains
|= (1 << domain_id
);
1235 static void intel_uncore_fw_domains_init(struct drm_i915_private
*dev_priv
)
1237 if (INTEL_INFO(dev_priv
)->gen
<= 5)
1240 if (IS_GEN9(dev_priv
)) {
1241 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1242 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1243 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1244 FORCEWAKE_RENDER_GEN9
,
1245 FORCEWAKE_ACK_RENDER_GEN9
);
1246 fw_domain_init(dev_priv
, FW_DOMAIN_ID_BLITTER
,
1247 FORCEWAKE_BLITTER_GEN9
,
1248 FORCEWAKE_ACK_BLITTER_GEN9
);
1249 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1250 FORCEWAKE_MEDIA_GEN9
, FORCEWAKE_ACK_MEDIA_GEN9
);
1251 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1252 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1253 if (!IS_CHERRYVIEW(dev_priv
))
1254 dev_priv
->uncore
.funcs
.force_wake_put
=
1255 fw_domains_put_with_fifo
;
1257 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1258 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1259 FORCEWAKE_VLV
, FORCEWAKE_ACK_VLV
);
1260 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1261 FORCEWAKE_MEDIA_VLV
, FORCEWAKE_ACK_MEDIA_VLV
);
1262 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1263 dev_priv
->uncore
.funcs
.force_wake_get
=
1264 fw_domains_get_with_thread_status
;
1265 if (IS_HASWELL(dev_priv
))
1266 dev_priv
->uncore
.funcs
.force_wake_put
=
1267 fw_domains_put_with_fifo
;
1269 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1270 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1271 FORCEWAKE_MT
, FORCEWAKE_ACK_HSW
);
1272 } else if (IS_IVYBRIDGE(dev_priv
)) {
1275 /* IVB configs may use multi-threaded forcewake */
1277 /* A small trick here - if the bios hasn't configured
1278 * MT forcewake, and if the device is in RC6, then
1279 * force_wake_mt_get will not wake the device and the
1280 * ECOBUS read will return zero. Which will be
1281 * (correctly) interpreted by the test below as MT
1282 * forcewake being disabled.
1284 dev_priv
->uncore
.funcs
.force_wake_get
=
1285 fw_domains_get_with_thread_status
;
1286 dev_priv
->uncore
.funcs
.force_wake_put
=
1287 fw_domains_put_with_fifo
;
1289 /* We need to init first for ECOBUS access and then
1290 * determine later if we want to reinit, in case of MT access is
1291 * not working. In this stage we don't know which flavour this
1292 * ivb is, so it is better to reset also the gen6 fw registers
1293 * before the ecobus check.
1296 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
1297 __raw_posting_read(dev_priv
, ECOBUS
);
1299 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1300 FORCEWAKE_MT
, FORCEWAKE_MT_ACK
);
1302 spin_lock_irq(&dev_priv
->uncore
.lock
);
1303 fw_domains_get_with_thread_status(dev_priv
, FORCEWAKE_ALL
);
1304 ecobus
= __raw_i915_read32(dev_priv
, ECOBUS
);
1305 fw_domains_put_with_fifo(dev_priv
, FORCEWAKE_ALL
);
1306 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1308 if (!(ecobus
& FORCEWAKE_MT_ENABLE
)) {
1309 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1310 DRM_INFO("when using vblank-synced partial screen updates.\n");
1311 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1312 FORCEWAKE
, FORCEWAKE_ACK
);
1314 } else if (IS_GEN6(dev_priv
)) {
1315 dev_priv
->uncore
.funcs
.force_wake_get
=
1316 fw_domains_get_with_thread_status
;
1317 dev_priv
->uncore
.funcs
.force_wake_put
=
1318 fw_domains_put_with_fifo
;
1319 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1320 FORCEWAKE
, FORCEWAKE_ACK
);
1323 /* All future platforms are expected to require complex power gating */
1324 WARN_ON(dev_priv
->uncore
.fw_domains
== 0);
1327 void intel_uncore_init(struct drm_i915_private
*dev_priv
)
1329 i915_check_vgpu(dev_priv
);
1331 intel_uncore_edram_detect(dev_priv
);
1332 intel_uncore_fw_domains_init(dev_priv
);
1333 __intel_uncore_early_sanitize(dev_priv
, false);
1335 dev_priv
->uncore
.unclaimed_mmio_check
= 1;
1337 switch (INTEL_INFO(dev_priv
)->gen
) {
1340 ASSIGN_WRITE_MMIO_VFUNCS(gen9
);
1341 ASSIGN_READ_MMIO_VFUNCS(gen9
);
1344 if (IS_CHERRYVIEW(dev_priv
)) {
1345 ASSIGN_WRITE_MMIO_VFUNCS(chv
);
1346 ASSIGN_READ_MMIO_VFUNCS(chv
);
1349 ASSIGN_WRITE_MMIO_VFUNCS(gen8
);
1350 ASSIGN_READ_MMIO_VFUNCS(gen6
);
1355 if (IS_HASWELL(dev_priv
)) {
1356 ASSIGN_WRITE_MMIO_VFUNCS(hsw
);
1358 ASSIGN_WRITE_MMIO_VFUNCS(gen6
);
1361 if (IS_VALLEYVIEW(dev_priv
)) {
1362 ASSIGN_READ_MMIO_VFUNCS(vlv
);
1364 ASSIGN_READ_MMIO_VFUNCS(gen6
);
1368 ASSIGN_WRITE_MMIO_VFUNCS(gen5
);
1369 ASSIGN_READ_MMIO_VFUNCS(gen5
);
1374 ASSIGN_WRITE_MMIO_VFUNCS(gen2
);
1375 ASSIGN_READ_MMIO_VFUNCS(gen2
);
1379 if (intel_vgpu_active(dev_priv
)) {
1380 ASSIGN_WRITE_MMIO_VFUNCS(vgpu
);
1381 ASSIGN_READ_MMIO_VFUNCS(vgpu
);
1384 i915_check_and_clear_faults(dev_priv
);
1386 #undef ASSIGN_WRITE_MMIO_VFUNCS
1387 #undef ASSIGN_READ_MMIO_VFUNCS
1389 void intel_uncore_fini(struct drm_i915_private
*dev_priv
)
1391 /* Paranoia: make sure we have disabled everything before we exit. */
1392 intel_uncore_sanitize(dev_priv
);
1393 intel_uncore_forcewake_reset(dev_priv
, false);
1396 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1398 static const struct register_whitelist
{
1399 i915_reg_t offset_ldw
, offset_udw
;
1401 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1402 uint32_t gen_bitmask
;
1404 { .offset_ldw
= RING_TIMESTAMP(RENDER_RING_BASE
),
1405 .offset_udw
= RING_TIMESTAMP_UDW(RENDER_RING_BASE
),
1406 .size
= 8, .gen_bitmask
= GEN_RANGE(4, 9) },
1409 int i915_reg_read_ioctl(struct drm_device
*dev
,
1410 void *data
, struct drm_file
*file
)
1412 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1413 struct drm_i915_reg_read
*reg
= data
;
1414 struct register_whitelist
const *entry
= whitelist
;
1416 i915_reg_t offset_ldw
, offset_udw
;
1419 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
1420 if (i915_mmio_reg_offset(entry
->offset_ldw
) == (reg
->offset
& -entry
->size
) &&
1421 (INTEL_INFO(dev
)->gen_mask
& entry
->gen_bitmask
))
1425 if (i
== ARRAY_SIZE(whitelist
))
1428 /* We use the low bits to encode extra flags as the register should
1429 * be naturally aligned (and those that are not so aligned merely
1430 * limit the available flags for that register).
1432 offset_ldw
= entry
->offset_ldw
;
1433 offset_udw
= entry
->offset_udw
;
1435 size
|= reg
->offset
^ i915_mmio_reg_offset(offset_ldw
);
1437 intel_runtime_pm_get(dev_priv
);
1441 reg
->val
= I915_READ64_2x32(offset_ldw
, offset_udw
);
1444 reg
->val
= I915_READ64(offset_ldw
);
1447 reg
->val
= I915_READ(offset_ldw
);
1450 reg
->val
= I915_READ16(offset_ldw
);
1453 reg
->val
= I915_READ8(offset_ldw
);
1461 intel_runtime_pm_put(dev_priv
);
1465 static int i915_reset_complete(struct pci_dev
*pdev
)
1468 pci_read_config_byte(pdev
, I915_GDRST
, &gdrst
);
1469 return (gdrst
& GRDOM_RESET_STATUS
) == 0;
1472 static int i915_do_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1474 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
1476 /* assert reset for at least 20 usec */
1477 pci_write_config_byte(pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1479 pci_write_config_byte(pdev
, I915_GDRST
, 0);
1481 return wait_for(i915_reset_complete(pdev
), 500);
1484 static int g4x_reset_complete(struct pci_dev
*pdev
)
1487 pci_read_config_byte(pdev
, I915_GDRST
, &gdrst
);
1488 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
1491 static int g33_do_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1493 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
1494 pci_write_config_byte(pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1495 return wait_for(g4x_reset_complete(pdev
), 500);
1498 static int g4x_do_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1500 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
1503 pci_write_config_byte(pdev
, I915_GDRST
,
1504 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
1505 ret
= wait_for(g4x_reset_complete(pdev
), 500);
1509 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1510 I915_WRITE(VDECCLK_GATE_D
, I915_READ(VDECCLK_GATE_D
) | VCP_UNIT_CLOCK_GATE_DISABLE
);
1511 POSTING_READ(VDECCLK_GATE_D
);
1513 pci_write_config_byte(pdev
, I915_GDRST
,
1514 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
1515 ret
= wait_for(g4x_reset_complete(pdev
), 500);
1519 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1520 I915_WRITE(VDECCLK_GATE_D
, I915_READ(VDECCLK_GATE_D
) & ~VCP_UNIT_CLOCK_GATE_DISABLE
);
1521 POSTING_READ(VDECCLK_GATE_D
);
1523 pci_write_config_byte(pdev
, I915_GDRST
, 0);
1528 static int ironlake_do_reset(struct drm_i915_private
*dev_priv
,
1529 unsigned engine_mask
)
1533 I915_WRITE(ILK_GDSR
,
1534 ILK_GRDOM_RENDER
| ILK_GRDOM_RESET_ENABLE
);
1535 ret
= intel_wait_for_register(dev_priv
,
1536 ILK_GDSR
, ILK_GRDOM_RESET_ENABLE
, 0,
1541 I915_WRITE(ILK_GDSR
,
1542 ILK_GRDOM_MEDIA
| ILK_GRDOM_RESET_ENABLE
);
1543 ret
= intel_wait_for_register(dev_priv
,
1544 ILK_GDSR
, ILK_GRDOM_RESET_ENABLE
, 0,
1549 I915_WRITE(ILK_GDSR
, 0);
1554 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1555 static int gen6_hw_domain_reset(struct drm_i915_private
*dev_priv
,
1558 /* GEN6_GDRST is not in the gt power well, no need to check
1559 * for fifo space for the write or forcewake the chip for
1562 __raw_i915_write32(dev_priv
, GEN6_GDRST
, hw_domain_mask
);
1564 /* Spin waiting for the device to ack the reset requests */
1565 return intel_wait_for_register_fw(dev_priv
,
1566 GEN6_GDRST
, hw_domain_mask
, 0,
1571 * gen6_reset_engines - reset individual engines
1572 * @dev_priv: i915 device
1573 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1575 * This function will reset the individual engines that are set in engine_mask.
1576 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1578 * Note: It is responsibility of the caller to handle the difference between
1579 * asking full domain reset versus reset for all available individual engines.
1581 * Returns 0 on success, nonzero on error.
1583 static int gen6_reset_engines(struct drm_i915_private
*dev_priv
,
1584 unsigned engine_mask
)
1586 struct intel_engine_cs
*engine
;
1587 const u32 hw_engine_mask
[I915_NUM_ENGINES
] = {
1588 [RCS
] = GEN6_GRDOM_RENDER
,
1589 [BCS
] = GEN6_GRDOM_BLT
,
1590 [VCS
] = GEN6_GRDOM_MEDIA
,
1591 [VCS2
] = GEN8_GRDOM_MEDIA2
,
1592 [VECS
] = GEN6_GRDOM_VECS
,
1597 if (engine_mask
== ALL_ENGINES
) {
1598 hw_mask
= GEN6_GRDOM_FULL
;
1601 for_each_engine_masked(engine
, dev_priv
, engine_mask
)
1602 hw_mask
|= hw_engine_mask
[engine
->id
];
1605 ret
= gen6_hw_domain_reset(dev_priv
, hw_mask
);
1607 intel_uncore_forcewake_reset(dev_priv
, true);
1613 * intel_wait_for_register_fw - wait until register matches expected state
1614 * @dev_priv: the i915 device
1615 * @reg: the register to read
1616 * @mask: mask to apply to register value
1617 * @value: expected value
1618 * @timeout_ms: timeout in millisecond
1620 * This routine waits until the target register @reg contains the expected
1621 * @value after applying the @mask, i.e. it waits until
1622 * (I915_READ_FW(@reg) & @mask) == @value
1623 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1625 * Note that this routine assumes the caller holds forcewake asserted, it is
1626 * not suitable for very long waits. See intel_wait_for_register() if you
1627 * wish to wait without holding forcewake for the duration (i.e. you expect
1628 * the wait to be slow).
1630 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1632 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
1636 const unsigned long timeout_ms
)
1638 #define done ((I915_READ_FW(reg) & mask) == value)
1639 int ret
= wait_for_us(done
, 2);
1641 ret
= wait_for(done
, timeout_ms
);
1647 * intel_wait_for_register - wait until register matches expected state
1648 * @dev_priv: the i915 device
1649 * @reg: the register to read
1650 * @mask: mask to apply to register value
1651 * @value: expected value
1652 * @timeout_ms: timeout in millisecond
1654 * This routine waits until the target register @reg contains the expected
1655 * @value after applying the @mask, i.e. it waits until
1656 * (I915_READ(@reg) & @mask) == @value
1657 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1659 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1661 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
1665 const unsigned long timeout_ms
)
1669 intel_uncore_forcewake_for_reg(dev_priv
, reg
, FW_REG_READ
);
1672 intel_uncore_forcewake_get(dev_priv
, fw
);
1673 ret
= wait_for_us((I915_READ_FW(reg
) & mask
) == value
, 2);
1674 intel_uncore_forcewake_put(dev_priv
, fw
);
1676 ret
= wait_for((I915_READ_NOTRACE(reg
) & mask
) == value
,
1682 static int gen8_request_engine_reset(struct intel_engine_cs
*engine
)
1684 struct drm_i915_private
*dev_priv
= engine
->i915
;
1687 I915_WRITE_FW(RING_RESET_CTL(engine
->mmio_base
),
1688 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET
));
1690 ret
= intel_wait_for_register_fw(dev_priv
,
1691 RING_RESET_CTL(engine
->mmio_base
),
1692 RESET_CTL_READY_TO_RESET
,
1693 RESET_CTL_READY_TO_RESET
,
1696 DRM_ERROR("%s: reset request timeout\n", engine
->name
);
1701 static void gen8_unrequest_engine_reset(struct intel_engine_cs
*engine
)
1703 struct drm_i915_private
*dev_priv
= engine
->i915
;
1705 I915_WRITE_FW(RING_RESET_CTL(engine
->mmio_base
),
1706 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET
));
1709 static int gen8_reset_engines(struct drm_i915_private
*dev_priv
,
1710 unsigned engine_mask
)
1712 struct intel_engine_cs
*engine
;
1714 for_each_engine_masked(engine
, dev_priv
, engine_mask
)
1715 if (gen8_request_engine_reset(engine
))
1718 return gen6_reset_engines(dev_priv
, engine_mask
);
1721 for_each_engine_masked(engine
, dev_priv
, engine_mask
)
1722 gen8_unrequest_engine_reset(engine
);
1727 typedef int (*reset_func
)(struct drm_i915_private
*, unsigned engine_mask
);
1729 static reset_func
intel_get_gpu_reset(struct drm_i915_private
*dev_priv
)
1734 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1735 return gen8_reset_engines
;
1736 else if (INTEL_INFO(dev_priv
)->gen
>= 6)
1737 return gen6_reset_engines
;
1738 else if (IS_GEN5(dev_priv
))
1739 return ironlake_do_reset
;
1740 else if (IS_G4X(dev_priv
))
1741 return g4x_do_reset
;
1742 else if (IS_G33(dev_priv
))
1743 return g33_do_reset
;
1744 else if (INTEL_INFO(dev_priv
)->gen
>= 3)
1745 return i915_do_reset
;
1750 int intel_gpu_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1755 reset
= intel_get_gpu_reset(dev_priv
);
1759 /* If the power well sleeps during the reset, the reset
1760 * request may be dropped and never completes (causing -EIO).
1762 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1763 ret
= reset(dev_priv
, engine_mask
);
1764 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1769 bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
)
1771 return intel_get_gpu_reset(dev_priv
) != NULL
;
1774 int intel_guc_reset(struct drm_i915_private
*dev_priv
)
1777 unsigned long irqflags
;
1779 if (!HAS_GUC(dev_priv
))
1782 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1783 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
1785 ret
= gen6_hw_domain_reset(dev_priv
, GEN9_GRDOM_GUC
);
1787 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
1788 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1793 bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
1795 return check_for_unclaimed_mmio(dev_priv
);
1799 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
)
1801 if (unlikely(i915
.mmio_debug
||
1802 dev_priv
->uncore
.unclaimed_mmio_check
<= 0))
1805 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv
))) {
1806 DRM_DEBUG("Unclaimed register detected, "
1807 "enabling oneshot unclaimed register reporting. "
1808 "Please use i915.mmio_debug=N for more information.\n");
1810 dev_priv
->uncore
.unclaimed_mmio_check
--;
1817 static enum forcewake_domains
1818 intel_uncore_forcewake_for_read(struct drm_i915_private
*dev_priv
,
1821 enum forcewake_domains fw_domains
;
1823 if (intel_vgpu_active(dev_priv
))
1826 switch (INTEL_GEN(dev_priv
)) {
1828 fw_domains
= __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg
));
1831 if (IS_CHERRYVIEW(dev_priv
))
1832 fw_domains
= __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg
));
1834 fw_domains
= __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg
));
1838 if (IS_VALLEYVIEW(dev_priv
))
1839 fw_domains
= __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg
));
1841 fw_domains
= __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg
));
1844 MISSING_CASE(INTEL_INFO(dev_priv
)->gen
);
1845 case 5: /* forcewake was introduced with gen6 */
1852 WARN_ON(fw_domains
& ~dev_priv
->uncore
.fw_domains
);
1857 static enum forcewake_domains
1858 intel_uncore_forcewake_for_write(struct drm_i915_private
*dev_priv
,
1861 enum forcewake_domains fw_domains
;
1863 if (intel_vgpu_active(dev_priv
))
1866 switch (INTEL_GEN(dev_priv
)) {
1868 fw_domains
= __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg
));
1871 if (IS_CHERRYVIEW(dev_priv
))
1872 fw_domains
= __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg
));
1874 fw_domains
= __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg
));
1878 fw_domains
= FORCEWAKE_RENDER
;
1881 MISSING_CASE(INTEL_INFO(dev_priv
)->gen
);
1889 WARN_ON(fw_domains
& ~dev_priv
->uncore
.fw_domains
);
1895 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1897 * @dev_priv: pointer to struct drm_i915_private
1898 * @reg: register in question
1899 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1901 * Returns a set of forcewake domains required to be taken with for example
1902 * intel_uncore_forcewake_get for the specified register to be accessible in the
1903 * specified mode (read, write or read/write) with raw mmio accessors.
1905 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1906 * callers to do FIFO management on their own or risk losing writes.
1908 enum forcewake_domains
1909 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
1910 i915_reg_t reg
, unsigned int op
)
1912 enum forcewake_domains fw_domains
= 0;
1916 if (op
& FW_REG_READ
)
1917 fw_domains
= intel_uncore_forcewake_for_read(dev_priv
, reg
);
1919 if (op
& FW_REG_WRITE
)
1920 fw_domains
|= intel_uncore_forcewake_for_write(dev_priv
, reg
);