drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "hdmi.h"
  19
  20 struct hdmi_phy_8x60 {
  21         struct hdmi_phy base;
  22         struct hdmi *hdmi;
  23 };
  24 #define to_hdmi_phy_8x60(x) container_of(x, struct hdmi_phy_8x60, base)
  25
  26 static void hdmi_phy_8x60_destroy(struct hdmi_phy *phy)
  27 {
  28         struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
  29         kfree(phy_8x60);
  30 }
  31
  32 static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
  33                 unsigned long int pixclock)
  34 {
  35         struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
  36         struct hdmi *hdmi = phy_8x60->hdmi;
  37
  38         /* De-serializer delay D/C for non-lbk mode: */
  39         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG0,
  40                         HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
  41
  42         if (pixclock == 27000000) {
  43                 /* video_format == HDMI_VFRMT_720x480p60_16_9 */
  44                 hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG1,
  45                                 HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
  46                                 HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
  47         } else {
  48                 hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG1,
  49                                 HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
  50                                 HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
  51         }
  52
  53         /* No matter what, start from the power down mode: */
  54         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
  55                         HDMI_8x60_PHY_REG2_PD_PWRGEN |
  56                         HDMI_8x60_PHY_REG2_PD_PLL |
  57                         HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
  58                         HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
  59                         HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
  60                         HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
  61                         HDMI_8x60_PHY_REG2_PD_DESER);
  62
  63         /* Turn PowerGen on: */
  64         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
  65                         HDMI_8x60_PHY_REG2_PD_PLL |
  66                         HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
  67                         HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
  68                         HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
  69                         HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
  70                         HDMI_8x60_PHY_REG2_PD_DESER);
  71
  72         /* Turn PLL power on: */
  73         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
  74                         HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
  75                         HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
  76                         HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
  77                         HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
  78                         HDMI_8x60_PHY_REG2_PD_DESER);
  79
  80         /* Write to HIGH after PLL power down de-assert: */
  81         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG3,
  82                         HDMI_8x60_PHY_REG3_PLL_ENABLE);
  83
  84         /* ASIC power on; PHY REG9 = 0 */
  85         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG9, 0);
  86
  87         /* Enable PLL lock detect, PLL lock det will go high after lock
  88          * Enable the re-time logic
  89          */
  90         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG12,
  91                         HDMI_8x60_PHY_REG12_RETIMING_EN |
  92                         HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
  93
  94         /* Drivers are on: */
  95         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
  96                         HDMI_8x60_PHY_REG2_PD_DESER);
  97
  98         /* If the RX detector is needed: */
  99         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
 100                         HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
 101                         HDMI_8x60_PHY_REG2_PD_DESER);
 102
 103         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG4, 0);
 104         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG5, 0);
 105         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG6, 0);
 106         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG7, 0);
 107         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG8, 0);
 108         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG9, 0);
 109         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG10, 0);
 110         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG11, 0);
 111
 112         /* If we want to use lock enable based on counting: */
 113         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG12,
 114                         HDMI_8x60_PHY_REG12_RETIMING_EN |
 115                         HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
 116                         HDMI_8x60_PHY_REG12_FORCE_LOCK);
 117 }
 118
 119 static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
 120 {
 121         struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
 122         struct hdmi *hdmi = phy_8x60->hdmi;
 123
 124         /* Assert RESET PHY from controller */
 125         hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
 126                         HDMI_PHY_CTRL_SW_RESET);
 127         udelay(10);
 128         /* De-assert RESET PHY from controller */
 129         hdmi_write(hdmi, REG_HDMI_PHY_CTRL, 0);
 130         /* Turn off Driver */
 131         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
 132                         HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
 133                         HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
 134                         HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
 135                         HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
 136                         HDMI_8x60_PHY_REG2_PD_DESER);
 137         udelay(10);
 138         /* Disable PLL */
 139         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG3, 0);
 140         /* Power down PHY, but keep RX-sense: */
 141         hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
 142                         HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
 143                         HDMI_8x60_PHY_REG2_PD_PWRGEN |
 144                         HDMI_8x60_PHY_REG2_PD_PLL |
 145                         HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
 146                         HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
 147                         HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
 148                         HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
 149                         HDMI_8x60_PHY_REG2_PD_DESER);
 150 }
 151
 152 static const struct hdmi_phy_funcs hdmi_phy_8x60_funcs = {
 153                 .destroy = hdmi_phy_8x60_destroy,
 154                 .powerup = hdmi_phy_8x60_powerup,
 155                 .powerdown = hdmi_phy_8x60_powerdown,
 156 };
 157
 158 struct hdmi_phy *hdmi_phy_8x60_init(struct hdmi *hdmi)
 159 {
 160         struct hdmi_phy_8x60 *phy_8x60;
 161         struct hdmi_phy *phy = NULL;
 162         int ret;
 163
 164         phy_8x60 = kzalloc(sizeof(*phy_8x60), GFP_KERNEL);
 165         if (!phy_8x60) {
 166                 ret = -ENOMEM;
 167                 goto fail;
 168         }
 169
 170         phy = &phy_8x60->base;
 171
 172         phy->funcs = &hdmi_phy_8x60_funcs;
 173
 174         phy_8x60->hdmi = hdmi;
 175
 176         return phy;
 177
 178 fail:
 179         if (phy)
 180                 hdmi_phy_8x60_destroy(phy);
 181         return ERR_PTR(ret);
 182 }