drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <mach/clk.h>
  19
  20 #include "mdp4_kms.h"
  21 #include "msm_connector.h"
  22
  23 #include "drm_crtc.h"
  24 #include "drm_crtc_helper.h"
  25
  26
  27 struct mdp4_dtv_encoder {
  28         struct drm_encoder base;
  29         struct clk *src_clk;
  30         struct clk *hdmi_clk;
  31         struct clk *mdp_clk;
  32         unsigned long int pixclock;
  33         bool enabled;
  34         uint32_t bsc;
  35 };
  36 #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base)
  37
  38 static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
  39 {
  40         struct msm_drm_private *priv = encoder->dev->dev_private;
  41         return to_mdp4_kms(priv->kms);
  42 }
  43
  44 #ifdef CONFIG_MSM_BUS_SCALING
  45 #include <mach/board.h>
  46 /* not ironically named at all.. no, really.. */
  47 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
  48 {
  49         struct drm_device *dev = mdp4_dtv_encoder->base.dev;
  50         struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0");
  51
  52         if (!dtv_pdata) {
  53                 dev_err(dev->dev, "could not find dtv pdata\n");
  54                 return;
  55         }
  56
  57         if (dtv_pdata->bus_scale_table) {
  58                 mdp4_dtv_encoder->bsc = msm_bus_scale_register_client(
  59                                 dtv_pdata->bus_scale_table);
  60                 DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc);
  61                 DBG("lcdc_power_save: %p", dtv_pdata->lcdc_power_save);
  62                 if (dtv_pdata->lcdc_power_save)
  63                         dtv_pdata->lcdc_power_save(1);
  64         }
  65 }
  66
  67 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
  68 {
  69         if (mdp4_dtv_encoder->bsc) {
  70                 msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc);
  71                 mdp4_dtv_encoder->bsc = 0;
  72         }
  73 }
  74
  75 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx)
  76 {
  77         if (mdp4_dtv_encoder->bsc) {
  78                 DBG("set bus scaling: %d", idx);
  79                 msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx);
  80         }
  81 }
  82 #else
  83 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
  84 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
  85 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) {}
  86 #endif
  87
  88 static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder)
  89 {
  90         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
  91         bs_fini(mdp4_dtv_encoder);
  92         drm_encoder_cleanup(encoder);
  93         kfree(mdp4_dtv_encoder);
  94 }
  95
  96 static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = {
  97         .destroy = mdp4_dtv_encoder_destroy,
  98 };
  99
 100 static void mdp4_dtv_encoder_dpms(struct drm_encoder *encoder, int mode)
 101 {
 102         struct drm_device *dev = encoder->dev;
 103         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 104         struct msm_connector *msm_connector = get_connector(encoder);
 105         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 106         bool enabled = (mode == DRM_MODE_DPMS_ON);
 107
 108         DBG("mode=%d", mode);
 109
 110         if (enabled == mdp4_dtv_encoder->enabled)
 111                 return;
 112
 113         if (enabled) {
 114                 unsigned long pc = mdp4_dtv_encoder->pixclock;
 115                 int ret;
 116
 117                 bs_set(mdp4_dtv_encoder, 1);
 118
 119                 if (msm_connector)
 120                         msm_connector->funcs->dpms(msm_connector, mode);
 121
 122                 DBG("setting src_clk=%lu", pc);
 123
 124                 ret = clk_set_rate(mdp4_dtv_encoder->src_clk, pc);
 125                 if (ret)
 126                         dev_err(dev->dev, "failed to set src_clk to %lu: %d\n", pc, ret);
 127                 clk_prepare_enable(mdp4_dtv_encoder->src_clk);
 128                 ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk);
 129                 if (ret)
 130                         dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret);
 131                 ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk);
 132                 if (ret)
 133                         dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret);
 134
 135                 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);
 136         } else {
 137                 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 138
 139                 /*
 140                  * Wait for a vsync so we know the ENABLE=0 latched before
 141                  * the (connector) source of the vsync's gets disabled,
 142                  * otherwise we end up in a funny state if we re-enable
 143                  * before the disable latches, which results that some of
 144                  * the settings changes for the new modeset (like new
 145                  * scanout buffer) don't latch properly..
 146                  */
 147                 mdp4_irq_wait(mdp4_kms, MDP4_IRQ_EXTERNAL_VSYNC);
 148
 149                 clk_disable_unprepare(mdp4_dtv_encoder->src_clk);
 150                 clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk);
 151                 clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk);
 152
 153                 if (msm_connector)
 154                         msm_connector->funcs->dpms(msm_connector, mode);
 155
 156                 bs_set(mdp4_dtv_encoder, 0);
 157         }
 158
 159         mdp4_dtv_encoder->enabled = enabled;
 160 }
 161
 162 static bool mdp4_dtv_encoder_mode_fixup(struct drm_encoder *encoder,
 163                 const struct drm_display_mode *mode,
 164                 struct drm_display_mode *adjusted_mode)
 165 {
 166         return true;
 167 }
 168
 169 static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder,
 170                 struct drm_display_mode *mode,
 171                 struct drm_display_mode *adjusted_mode)
 172 {
 173         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 174         struct msm_connector *msm_connector = get_connector(encoder);
 175         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 176         uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
 177         uint32_t display_v_start, display_v_end;
 178         uint32_t hsync_start_x, hsync_end_x;
 179
 180         mode = adjusted_mode;
 181
 182         DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 183                         mode->base.id, mode->name,
 184                         mode->vrefresh, mode->clock,
 185                         mode->hdisplay, mode->hsync_start,
 186                         mode->hsync_end, mode->htotal,
 187                         mode->vdisplay, mode->vsync_start,
 188                         mode->vsync_end, mode->vtotal,
 189                         mode->type, mode->flags);
 190
 191         mdp4_dtv_encoder->pixclock = mode->clock * 1000;
 192
 193         DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock);
 194
 195         ctrl_pol = 0;
 196         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 197                 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW;
 198         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 199                 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW;
 200         /* probably need to get DATA_EN polarity from panel.. */
 201
 202         dtv_hsync_skew = 0;  /* get this from panel? */
 203
 204         hsync_start_x = (mode->htotal - mode->hsync_start);
 205         hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
 206
 207         vsync_period = mode->vtotal * mode->htotal;
 208         vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
 209         display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
 210         display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
 211
 212         mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,
 213                         MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
 214                         MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal));
 215         mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
 216         mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);
 217         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,
 218                         MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) |
 219                         MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x));
 220         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
 221         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
 222         mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);
 223         mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,
 224                         MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY |
 225                         MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff));
 226         mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
 227         mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);
 228         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL,
 229                         MDP4_DTV_ACTIVE_HCTL_START(0) |
 230                         MDP4_DTV_ACTIVE_HCTL_END(0));
 231         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0);
 232         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0);
 233
 234         if (msm_connector)
 235                 msm_connector->funcs->mode_set(msm_connector, mode);
 236 }
 237
 238 static void mdp4_dtv_encoder_prepare(struct drm_encoder *encoder)
 239 {
 240         mdp4_dtv_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 241 }
 242
 243 static void mdp4_dtv_encoder_commit(struct drm_encoder *encoder)
 244 {
 245         mdp4_crtc_set_config(encoder->crtc,
 246                         MDP4_DMA_CONFIG_R_BPC(BPC8) |
 247                         MDP4_DMA_CONFIG_G_BPC(BPC8) |
 248                         MDP4_DMA_CONFIG_B_BPC(BPC8) |
 249                         MDP4_DMA_CONFIG_PACK(0x21));
 250         mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV);
 251         mdp4_dtv_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 252 }
 253
 254 static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = {
 255         .dpms = mdp4_dtv_encoder_dpms,
 256         .mode_fixup = mdp4_dtv_encoder_mode_fixup,
 257         .mode_set = mdp4_dtv_encoder_mode_set,
 258         .prepare = mdp4_dtv_encoder_prepare,
 259         .commit = mdp4_dtv_encoder_commit,
 260 };
 261
 262 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate)
 263 {
 264         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 265         return clk_round_rate(mdp4_dtv_encoder->src_clk, rate);
 266 }
 267
 268 /* initialize encoder */
 269 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev)
 270 {
 271         struct drm_encoder *encoder = NULL;
 272         struct mdp4_dtv_encoder *mdp4_dtv_encoder;
 273         int ret;
 274
 275         mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL);
 276         if (!mdp4_dtv_encoder) {
 277                 ret = -ENOMEM;
 278                 goto fail;
 279         }
 280
 281         encoder = &mdp4_dtv_encoder->base;
 282
 283         drm_encoder_init(dev, encoder, &mdp4_dtv_encoder_funcs,
 284                          DRM_MODE_ENCODER_TMDS);
 285         drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs);
 286
 287         mdp4_dtv_encoder->src_clk = devm_clk_get(dev->dev, "src_clk");
 288         if (IS_ERR(mdp4_dtv_encoder->src_clk)) {
 289                 dev_err(dev->dev, "failed to get src_clk\n");
 290                 ret = PTR_ERR(mdp4_dtv_encoder->src_clk);
 291                 goto fail;
 292         }
 293
 294         mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk");
 295         if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) {
 296                 dev_err(dev->dev, "failed to get hdmi_clk\n");
 297                 ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk);
 298                 goto fail;
 299         }
 300
 301         mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "mdp_clk");
 302         if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) {
 303                 dev_err(dev->dev, "failed to get mdp_clk\n");
 304                 ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk);
 305                 goto fail;
 306         }
 307
 308         bs_init(mdp4_dtv_encoder);
 309
 310         return encoder;
 311
 312 fail:
 313         if (encoder)
 314                 mdp4_dtv_encoder_destroy(encoder);
 315
 316         return ERR_PTR(ret);
 317 }