Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / disp / nv94.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <engine/software.h>
26 #include <engine/disp.h>
27
28 #include <core/class.h>
29
30 #include "nv50.h"
31
32 static struct nouveau_oclass
33 nv94_disp_sclass[] = {
34 { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
35 { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
36 { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
37 { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
38 { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
39 {}
40 };
41
42 static struct nouveau_omthds
43 nv94_disp_base_omthds[] = {
44 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
45 { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
46 { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
47 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
48 { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
49 { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
50 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
51 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
52 { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
53 {},
54 };
55
56 static struct nouveau_oclass
57 nv94_disp_base_oclass[] = {
58 { NV94_DISP_CLASS, &nv50_disp_base_ofuncs, nv94_disp_base_omthds },
59 {}
60 };
61
62 static int
63 nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
64 struct nouveau_oclass *oclass, void *data, u32 size,
65 struct nouveau_object **pobject)
66 {
67 struct nv50_disp_priv *priv;
68 int ret;
69
70 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
71 "display", &priv);
72 *pobject = nv_object(priv);
73 if (ret)
74 return ret;
75
76 nv_engine(priv)->sclass = nv94_disp_base_oclass;
77 nv_engine(priv)->cclass = &nv50_disp_cclass;
78 nv_subdev(priv)->intr = nv50_disp_intr;
79 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
80 priv->sclass = nv94_disp_sclass;
81 priv->head.nr = 2;
82 priv->dac.nr = 3;
83 priv->sor.nr = 4;
84 priv->pior.nr = 3;
85 priv->dac.power = nv50_dac_power;
86 priv->dac.sense = nv50_dac_sense;
87 priv->sor.power = nv50_sor_power;
88 priv->sor.hdmi = nv84_hdmi_ctrl;
89 priv->sor.dp = &nv94_sor_dp_func;
90 priv->pior.power = nv50_pior_power;
91 priv->pior.dp = &nv50_pior_dp_func;
92 return 0;
93 }
94
95 struct nouveau_oclass
96 nv94_disp_oclass = {
97 .handle = NV_ENGINE(DISP, 0x88),
98 .ofuncs = &(struct nouveau_ofuncs) {
99 .ctor = nv94_disp_ctor,
100 .dtor = _nouveau_disp_dtor,
101 .init = _nouveau_disp_init,
102 .fini = _nouveau_disp_fini,
103 },
104 };
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