drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27
  28 #include <subdev/bios.h>
  29 #include <subdev/bios/dcb.h>
  30 #include <subdev/timer.h>
  31
  32 #include "nv50.h"
  33
  34 int
  35 nv50_sor_power(struct nv50_disp_priv *priv, int or, u32 data)
  36 {
  37         const u32 stat = data & NV50_DISP_SOR_PWR_STATE;
  38         const u32 soff = (or * 0x800);
  39         nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
  40         nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
  41         nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
  42         nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000);
  43         return 0;
  44 }
  45
  46 int
  47 nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
  48 {
  49         struct nv50_disp_priv *priv = (void *)object->engine;
  50         struct nouveau_bios *bios = nouveau_bios(priv);
  51         const u16 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12;
  52         const u8  head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3;
  53         const u8  link = (mthd & NV50_DISP_SOR_MTHD_LINK) >> 2;
  54         const u8    or = (mthd & NV50_DISP_SOR_MTHD_OR);
  55         const u16 mask = (0x0100 << head) | (0x0040 << link) | (0x0001 << or);
  56         struct dcb_output outp;
  57         u8  ver, hdr;
  58         u32 data;
  59         int ret = -EINVAL;
  60
  61         if (size < sizeof(u32))
  62                 return -EINVAL;
  63         data = *(u32 *)args;
  64
  65         if (type && !dcb_outp_match(bios, type, mask, &ver, &hdr, &outp))
  66                 return -ENODEV;
  67
  68         switch (mthd & ~0x3f) {
  69         case NV50_DISP_SOR_PWR:
  70                 ret = priv->sor.power(priv, or, data);
  71                 break;
  72         case NVA3_DISP_SOR_HDA_ELD:
  73                 ret = priv->sor.hda_eld(priv, or, args, size);
  74                 break;
  75         case NV84_DISP_SOR_HDMI_PWR:
  76                 ret = priv->sor.hdmi(priv, head, or, data);
  77                 break;
  78         case NV50_DISP_SOR_LVDS_SCRIPT:
  79                 priv->sor.lvdsconf = data & NV50_DISP_SOR_LVDS_SCRIPT_ID;
  80                 ret = 0;
  81                 break;
  82         default:
  83                 BUG_ON(1);
  84         }
  85
  86         return ret;
  87 }