drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc

   1 /* fuc microcode for nve0 PGRAPH/GPC
   2  *
   3  * Copyright 2011 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Ben Skeggs
  24  */
  25
  26 /* To build:
  27  *    m4 nve0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nve0_grgpc.fuc.h
  28  */
  29
  30 /* TODO
  31  * - bracket certain functions with scratch writes, useful for debugging
  32  * - watchdog timer around ctx operations
  33  */
  34
  35 .section #nve0_grgpc_data
  36 include(`nve0.fuc')
  37 gpc_id:                 .b32 0
  38 gpc_mmio_list_head:     .b32 0
  39 gpc_mmio_list_tail:     .b32 0
  40
  41 tpc_count:              .b32 0
  42 tpc_mask:               .b32 0
  43 tpc_mmio_list_head:     .b32 0
  44 tpc_mmio_list_tail:     .b32 0
  45
  46 cmd_queue:              queue_init
  47
  48 // chipset descriptions
  49 chipsets:
  50 .b8  0xe4 0 0 0
  51 .b16 #nve4_gpc_mmio_head
  52 .b16 #nve4_gpc_mmio_tail
  53 .b16 #nve4_tpc_mmio_head
  54 .b16 #nve4_tpc_mmio_tail
  55 .b8  0xe7 0 0 0
  56 .b16 #nve4_gpc_mmio_head
  57 .b16 #nve4_gpc_mmio_tail
  58 .b16 #nve6_tpc_mmio_head
  59 .b16 #nve6_tpc_mmio_tail
  60 .b8  0xe6 0 0 0
  61 .b16 #nve4_gpc_mmio_head
  62 .b16 #nve4_gpc_mmio_tail
  63 .b16 #nve6_tpc_mmio_head
  64 .b16 #nve6_tpc_mmio_tail
  65 .b8  0 0 0 0
  66
  67 // GPC mmio lists
  68 nve4_gpc_mmio_head:
  69 mmctx_data(0x000380, 1)
  70 mmctx_data(0x000400, 2)
  71 mmctx_data(0x00040c, 3)
  72 mmctx_data(0x000450, 9)
  73 mmctx_data(0x000600, 1)
  74 mmctx_data(0x000684, 1)
  75 mmctx_data(0x000700, 5)
  76 mmctx_data(0x000800, 1)
  77 mmctx_data(0x000808, 3)
  78 mmctx_data(0x000828, 1)
  79 mmctx_data(0x000830, 1)
  80 mmctx_data(0x0008d8, 1)
  81 mmctx_data(0x0008e0, 1)
  82 mmctx_data(0x0008e8, 6)
  83 mmctx_data(0x00091c, 1)
  84 mmctx_data(0x000924, 3)
  85 mmctx_data(0x000b00, 1)
  86 mmctx_data(0x000b08, 6)
  87 mmctx_data(0x000bb8, 1)
  88 mmctx_data(0x000c08, 1)
  89 mmctx_data(0x000c10, 8)
  90 mmctx_data(0x000c40, 1)
  91 mmctx_data(0x000c6c, 1)
  92 mmctx_data(0x000c80, 1)
  93 mmctx_data(0x000c8c, 1)
  94 mmctx_data(0x001000, 3)
  95 mmctx_data(0x001014, 1)
  96 mmctx_data(0x003024, 1)
  97 mmctx_data(0x0030c0, 2)
  98 mmctx_data(0x0030e4, 1)
  99 mmctx_data(0x003100, 6)
 100 mmctx_data(0x0031d0, 1)
 101 mmctx_data(0x0031e0, 2)
 102 nve4_gpc_mmio_tail:
 103
 104 // TPC mmio lists
 105 nve4_tpc_mmio_head:
 106 mmctx_data(0x000048, 1)
 107 mmctx_data(0x000064, 1)
 108 mmctx_data(0x000088, 1)
 109 mmctx_data(0x000200, 6)
 110 mmctx_data(0x00021c, 2)
 111 mmctx_data(0x000230, 1)
 112 mmctx_data(0x0002c4, 1)
 113 mmctx_data(0x000400, 3)
 114 mmctx_data(0x000420, 3)
 115 mmctx_data(0x0004e8, 1)
 116 mmctx_data(0x0004f4, 1)
 117 mmctx_data(0x000604, 4)
 118 mmctx_data(0x000644, 22)
 119 mmctx_data(0x0006ac, 2)
 120 mmctx_data(0x0006c8, 1)
 121 mmctx_data(0x000730, 8)
 122 mmctx_data(0x000758, 1)
 123 mmctx_data(0x000778, 1)
 124 nve4_tpc_mmio_tail:
 125
 126 nve6_tpc_mmio_head:
 127 mmctx_data(0x000048, 1)
 128 mmctx_data(0x000064, 1)
 129 mmctx_data(0x000088, 1)
 130 mmctx_data(0x000200, 6)
 131 mmctx_data(0x00021c, 2)
 132 mmctx_data(0x000230, 1)
 133 mmctx_data(0x0002c4, 1)
 134 mmctx_data(0x000400, 3)
 135 mmctx_data(0x000420, 3)
 136 mmctx_data(0x0004e8, 1)
 137 mmctx_data(0x0004f4, 1)
 138 mmctx_data(0x000604, 4)
 139 mmctx_data(0x000644, 22)
 140 mmctx_data(0x0006ac, 2)
 141 mmctx_data(0x0006c8, 1)
 142 mmctx_data(0x000730, 8)
 143 mmctx_data(0x000758, 1)
 144 mmctx_data(0x000770, 1)
 145 mmctx_data(0x000778, 2)
 146 nve6_tpc_mmio_tail:
 147
 148 .section #nve0_grgpc_code
 149 bra #init
 150 define(`include_code')
 151 include(`nve0.fuc')
 152
 153 // reports an exception to the host
 154 //
 155 // In: $r15 error code (see nve0.fuc)
 156 //
 157 error:
 158         push $r14
 159         mov $r14 -0x67ec        // 0x9814
 160         sethi $r14 0x400000
 161         call #nv_wr32           // HUB_CTXCTL_CC_SCRATCH[5] = error code
 162         add b32 $r14 0x41c
 163         mov $r15 1
 164         call #nv_wr32           // HUB_CTXCTL_INTR_UP_SET
 165         pop $r14
 166         ret
 167
 168 // GPC fuc initialisation, executed by triggering ucode start, will
 169 // fall through to main loop after completion.
 170 //
 171 // Input:
 172 //   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
 173 //   CC_SCRATCH[1]: context base
 174 //
 175 // Output:
 176 //   CC_SCRATCH[0]:
 177 //           31:31: set to signal completion
 178 //   CC_SCRATCH[1]:
 179 //            31:0: GPC context size
 180 //
 181 init:
 182         clear b32 $r0
 183         mov $sp $r0
 184
 185         // enable fifo access
 186         mov $r1 0x1200
 187         mov $r2 2
 188         iowr I[$r1 + 0x000] $r2         // FIFO_ENABLE
 189
 190         // setup i0 handler, and route all interrupts to it
 191         mov $r1 #ih
 192         mov $iv0 $r1
 193         mov $r1 0x400
 194         iowr I[$r1 + 0x300] $r0         // INTR_DISPATCH
 195
 196         // enable fifo interrupt
 197         mov $r2 4
 198         iowr I[$r1 + 0x000] $r2         // INTR_EN_SET
 199
 200         // enable interrupts
 201         bset $flags ie0
 202
 203         // figure out which GPC we are, and how many TPCs we have
 204         mov $r1 0x608
 205         shl b32 $r1 6
 206         iord $r2 I[$r1 + 0x000]         // UNITS
 207         mov $r3 1
 208         and $r2 0x1f
 209         shl b32 $r3 $r2
 210         sub b32 $r3 1
 211         st b32 D[$r0 + #tpc_count] $r2
 212         st b32 D[$r0 + #tpc_mask] $r3
 213         add b32 $r1 0x400
 214         iord $r2 I[$r1 + 0x000]         // MYINDEX
 215         st b32 D[$r0 + #gpc_id] $r2
 216
 217         // find context data for this chipset
 218         mov $r2 0x800
 219         shl b32 $r2 6
 220         iord $r2 I[$r2 + 0x000]         // CC_SCRATCH[0]
 221         mov $r1 #chipsets - 12
 222         init_find_chipset:
 223                 add b32 $r1 12
 224                 ld b32 $r3 D[$r1 + 0x00]
 225                 cmpu b32 $r3 $r2
 226                 bra e #init_context
 227                 cmpu b32 $r3 0
 228                 bra ne #init_find_chipset
 229                 // unknown chipset
 230                 ret
 231
 232         // initialise context base, and size tracking
 233         init_context:
 234         mov $r2 0x800
 235         shl b32 $r2 6
 236         iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
 237         clear b32 $r3           // track GPC context size here
 238
 239         // set mmctx base addresses now so we don't have to do it later,
 240         // they don't currently ever change
 241         mov $r4 0x700
 242         shl b32 $r4 6
 243         shr b32 $r5 $r2 8
 244         iowr I[$r4 + 0x000] $r5         // MMCTX_SAVE_SWBASE
 245         iowr I[$r4 + 0x100] $r5         // MMCTX_LOAD_SWBASE
 246
 247         // calculate GPC mmio context size, store the chipset-specific
 248         // mmio list pointers somewhere we can get at them later without
 249         // re-parsing the chipset list
 250         clear b32 $r14
 251         clear b32 $r15
 252         ld b16 $r14 D[$r1 + 4]
 253         ld b16 $r15 D[$r1 + 6]
 254         st b16 D[$r0 + #gpc_mmio_list_head] $r14
 255         st b16 D[$r0 + #gpc_mmio_list_tail] $r15
 256         call #mmctx_size
 257         add b32 $r2 $r15
 258         add b32 $r3 $r15
 259
 260         // calculate per-TPC mmio context size, store the list pointers
 261         ld b16 $r14 D[$r1 + 8]
 262         ld b16 $r15 D[$r1 + 10]
 263         st b16 D[$r0 + #tpc_mmio_list_head] $r14
 264         st b16 D[$r0 + #tpc_mmio_list_tail] $r15
 265         call #mmctx_size
 266         ld b32 $r14 D[$r0 + #tpc_count]
 267         mulu $r14 $r15
 268         add b32 $r2 $r14
 269         add b32 $r3 $r14
 270
 271         // round up base/size to 256 byte boundary (for strand SWBASE)
 272         add b32 $r4 0x1300
 273         shr b32 $r3 2
 274         iowr I[$r4 + 0x000] $r3         // MMCTX_LOAD_COUNT, wtf for?!?
 275         shr b32 $r2 8
 276         shr b32 $r3 6
 277         add b32 $r2 1
 278         add b32 $r3 1
 279         shl b32 $r2 8
 280         shl b32 $r3 8
 281
 282         // calculate size of strand context data
 283         mov b32 $r15 $r2
 284         call #strand_ctx_init
 285         add b32 $r3 $r15
 286
 287         // save context size, and tell HUB we're done
 288         mov $r1 0x800
 289         shl b32 $r1 6
 290         iowr I[$r1 + 0x100] $r3         // CC_SCRATCH[1]  = context size
 291         add b32 $r1 0x800
 292         clear b32 $r2
 293         bset $r2 31
 294         iowr I[$r1 + 0x000] $r2         // CC_SCRATCH[0] |= 0x80000000
 295
 296 // Main program loop, very simple, sleeps until woken up by the interrupt
 297 // handler, pulls a command from the queue and executes its handler
 298 //
 299 main:
 300         bset $flags $p0
 301         sleep $p0
 302         mov $r13 #cmd_queue
 303         call #queue_get
 304         bra $p1 #main
 305
 306         // 0x0000-0x0003 are all context transfers
 307         cmpu b32 $r14 0x04
 308         bra nc #main_not_ctx_xfer
 309                 // fetch $flags and mask off $p1/$p2
 310                 mov $r1 $flags
 311                 mov $r2 0x0006
 312                 not b32 $r2
 313                 and $r1 $r2
 314                 // set $p1/$p2 according to transfer type
 315                 shl b32 $r14 1
 316                 or $r1 $r14
 317                 mov $flags $r1
 318                 // transfer context data
 319                 call #ctx_xfer
 320                 bra #main
 321
 322         main_not_ctx_xfer:
 323         shl b32 $r15 $r14 16
 324         or $r15 E_BAD_COMMAND
 325         call #error
 326         bra #main
 327
 328 // interrupt handler
 329 ih:
 330         push $r8
 331         mov $r8 $flags
 332         push $r8
 333         push $r9
 334         push $r10
 335         push $r11
 336         push $r13
 337         push $r14
 338         push $r15
 339
 340         // incoming fifo command?
 341         iord $r10 I[$r0 + 0x200]        // INTR
 342         and $r11 $r10 0x00000004
 343         bra e #ih_no_fifo
 344                 // queue incoming fifo command for later processing
 345                 mov $r11 0x1900
 346                 mov $r13 #cmd_queue
 347                 iord $r14 I[$r11 + 0x100]       // FIFO_CMD
 348                 iord $r15 I[$r11 + 0x000]       // FIFO_DATA
 349                 call #queue_put
 350                 add b32 $r11 0x400
 351                 mov $r14 1
 352                 iowr I[$r11 + 0x000] $r14       // FIFO_ACK
 353
 354         // ack, and wake up main()
 355         ih_no_fifo:
 356         iowr I[$r0 + 0x100] $r10        // INTR_ACK
 357
 358         pop $r15
 359         pop $r14
 360         pop $r13
 361         pop $r11
 362         pop $r10
 363         pop $r9
 364         pop $r8
 365         mov $flags $r8
 366         pop $r8
 367         bclr $flags $p0
 368         iret
 369
 370 // Set this GPC's bit in HUB_BAR, used to signal completion of various
 371 // activities to the HUB fuc
 372 //
 373 hub_barrier_done:
 374         mov $r15 1
 375         ld b32 $r14 D[$r0 + #gpc_id]
 376         shl b32 $r15 $r14
 377         mov $r14 -0x6be8        // 0x409418 - HUB_BAR_SET
 378         sethi $r14 0x400000
 379         call #nv_wr32
 380         ret
 381
 382 // Disables various things, waits a bit, and re-enables them..
 383 //
 384 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
 385 // good description for the bits we turn off?  Anyways, without this,
 386 // funny things happen.
 387 //
 388 ctx_redswitch:
 389         mov $r14 0x614
 390         shl b32 $r14 6
 391         mov $r15 0x020
 392         iowr I[$r14] $r15       // GPC_RED_SWITCH = POWER
 393         mov $r15 8
 394         ctx_redswitch_delay:
 395                 sub b32 $r15 1
 396                 bra ne #ctx_redswitch_delay
 397         mov $r15 0xa20
 398         iowr I[$r14] $r15       // GPC_RED_SWITCH = UNK11, ENABLE, POWER
 399         ret
 400
 401 // Transfer GPC context data between GPU and storage area
 402 //
 403 // In: $r15 context base address
 404 //     $p1 clear on save, set on load
 405 //     $p2 set if opposite direction done/will be done, so:
 406 //              on save it means: "a load will follow this save"
 407 //              on load it means: "a save preceeded this load"
 408 //
 409 ctx_xfer:
 410         // set context base address
 411         mov $r1 0xa04
 412         shl b32 $r1 6
 413         iowr I[$r1 + 0x000] $r15// MEM_BASE
 414         bra not $p1 #ctx_xfer_not_load
 415                 call #ctx_redswitch
 416         ctx_xfer_not_load:
 417
 418         // strands
 419         mov $r1 0x4afc
 420         sethi $r1 0x20000
 421         mov $r2 0xc
 422         iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
 423         call #strand_wait
 424         mov $r2 0x47fc
 425         sethi $r2 0x20000
 426         iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
 427         xbit $r2 $flags $p1
 428         add b32 $r2 3
 429         iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
 430
 431         // mmio context
 432         xbit $r10 $flags $p1    // direction
 433         or $r10 2               // first
 434         mov $r11 0x0000
 435         sethi $r11 0x500000
 436         ld b32 $r12 D[$r0 + #gpc_id]
 437         shl b32 $r12 15
 438         add b32 $r11 $r12       // base = NV_PGRAPH_GPCn
 439         ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
 440         ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
 441         mov $r14 0              // not multi
 442         call #mmctx_xfer
 443
 444         // per-TPC mmio context
 445         xbit $r10 $flags $p1    // direction
 446         or $r10 4               // last
 447         mov $r11 0x4000
 448         sethi $r11 0x500000     // base = NV_PGRAPH_GPC0_TPC0
 449         ld b32 $r12 D[$r0 + #gpc_id]
 450         shl b32 $r12 15
 451         add b32 $r11 $r12       // base = NV_PGRAPH_GPCn_TPC0
 452         ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
 453         ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
 454         ld b32 $r15 D[$r0 + #tpc_mask]
 455         mov $r14 0x800          // stride = 0x800
 456         call #mmctx_xfer
 457
 458         // wait for strands to finish
 459         call #strand_wait
 460
 461         // if load, or a save without a load following, do some
 462         // unknown stuff that's done after finishing a block of
 463         // strand commands
 464         bra $p1 #ctx_xfer_post
 465         bra not $p2 #ctx_xfer_done
 466         ctx_xfer_post:
 467                 mov $r1 0x4afc
 468                 sethi $r1 0x20000
 469                 mov $r2 0xd
 470                 iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0d
 471                 call #strand_wait
 472
 473         // mark completion in HUB's barrier
 474         ctx_xfer_done:
 475         call #hub_barrier_done
 476         ret
 477
 478 .align 256