2 * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
26 #include <core/class.h>
27 #include <core/handle.h>
29 #include <subdev/fb.h>
31 #include <engine/fifo.h>
32 #include <engine/graph.h>
37 u32 pipe_0x0000
[0x040/4];
38 u32 pipe_0x0040
[0x010/4];
39 u32 pipe_0x0200
[0x0c0/4];
40 u32 pipe_0x4400
[0x080/4];
41 u32 pipe_0x6400
[0x3b0/4];
42 u32 pipe_0x6800
[0x2f0/4];
43 u32 pipe_0x6c00
[0x030/4];
44 u32 pipe_0x7000
[0x130/4];
45 u32 pipe_0x7400
[0x0c0/4];
46 u32 pipe_0x7800
[0x0c0/4];
49 static int nv10_graph_ctx_regs
[] = {
50 NV10_PGRAPH_CTX_SWITCH(0),
51 NV10_PGRAPH_CTX_SWITCH(1),
52 NV10_PGRAPH_CTX_SWITCH(2),
53 NV10_PGRAPH_CTX_SWITCH(3),
54 NV10_PGRAPH_CTX_SWITCH(4),
55 NV10_PGRAPH_CTX_CACHE(0, 0),
56 NV10_PGRAPH_CTX_CACHE(0, 1),
57 NV10_PGRAPH_CTX_CACHE(0, 2),
58 NV10_PGRAPH_CTX_CACHE(0, 3),
59 NV10_PGRAPH_CTX_CACHE(0, 4),
60 NV10_PGRAPH_CTX_CACHE(1, 0),
61 NV10_PGRAPH_CTX_CACHE(1, 1),
62 NV10_PGRAPH_CTX_CACHE(1, 2),
63 NV10_PGRAPH_CTX_CACHE(1, 3),
64 NV10_PGRAPH_CTX_CACHE(1, 4),
65 NV10_PGRAPH_CTX_CACHE(2, 0),
66 NV10_PGRAPH_CTX_CACHE(2, 1),
67 NV10_PGRAPH_CTX_CACHE(2, 2),
68 NV10_PGRAPH_CTX_CACHE(2, 3),
69 NV10_PGRAPH_CTX_CACHE(2, 4),
70 NV10_PGRAPH_CTX_CACHE(3, 0),
71 NV10_PGRAPH_CTX_CACHE(3, 1),
72 NV10_PGRAPH_CTX_CACHE(3, 2),
73 NV10_PGRAPH_CTX_CACHE(3, 3),
74 NV10_PGRAPH_CTX_CACHE(3, 4),
75 NV10_PGRAPH_CTX_CACHE(4, 0),
76 NV10_PGRAPH_CTX_CACHE(4, 1),
77 NV10_PGRAPH_CTX_CACHE(4, 2),
78 NV10_PGRAPH_CTX_CACHE(4, 3),
79 NV10_PGRAPH_CTX_CACHE(4, 4),
80 NV10_PGRAPH_CTX_CACHE(5, 0),
81 NV10_PGRAPH_CTX_CACHE(5, 1),
82 NV10_PGRAPH_CTX_CACHE(5, 2),
83 NV10_PGRAPH_CTX_CACHE(5, 3),
84 NV10_PGRAPH_CTX_CACHE(5, 4),
85 NV10_PGRAPH_CTX_CACHE(6, 0),
86 NV10_PGRAPH_CTX_CACHE(6, 1),
87 NV10_PGRAPH_CTX_CACHE(6, 2),
88 NV10_PGRAPH_CTX_CACHE(6, 3),
89 NV10_PGRAPH_CTX_CACHE(6, 4),
90 NV10_PGRAPH_CTX_CACHE(7, 0),
91 NV10_PGRAPH_CTX_CACHE(7, 1),
92 NV10_PGRAPH_CTX_CACHE(7, 2),
93 NV10_PGRAPH_CTX_CACHE(7, 3),
94 NV10_PGRAPH_CTX_CACHE(7, 4),
96 NV04_PGRAPH_DMA_START_0
,
97 NV04_PGRAPH_DMA_START_1
,
98 NV04_PGRAPH_DMA_LENGTH
,
100 NV10_PGRAPH_DMA_PITCH
,
101 NV04_PGRAPH_BOFFSET0
,
104 NV04_PGRAPH_BOFFSET1
,
107 NV04_PGRAPH_BOFFSET2
,
110 NV04_PGRAPH_BOFFSET3
,
113 NV04_PGRAPH_BOFFSET4
,
116 NV04_PGRAPH_BOFFSET5
,
126 NV04_PGRAPH_BSWIZZLE2
,
127 NV04_PGRAPH_BSWIZZLE5
,
130 NV04_PGRAPH_PATT_COLOR0
,
131 NV04_PGRAPH_PATT_COLOR1
,
132 NV04_PGRAPH_PATT_COLORRAM
, /* 64 values from 0x400900 to 0x4009fc */
196 NV04_PGRAPH_PATTERN
, /* 2 values from 0x400808 to 0x40080c */
198 NV04_PGRAPH_PATTERN_SHAPE
,
199 NV03_PGRAPH_MONO_COLOR0
,
202 NV04_PGRAPH_BETA_AND
,
203 NV04_PGRAPH_BETA_PREMULT
,
219 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL
, /* 8 values from 0x400f00-0x400f1c */
220 NV10_PGRAPH_WINDOWCLIP_VERTICAL
, /* 8 values from 0x400f20-0x400f3c */
237 NV10_PGRAPH_GLOBALSTATE0
,
238 NV10_PGRAPH_GLOBALSTATE1
,
239 NV04_PGRAPH_STORED_FMT
,
240 NV04_PGRAPH_SOURCE_COLOR
,
241 NV03_PGRAPH_ABS_X_RAM
, /* 32 values from 0x400400 to 0x40047c */
242 NV03_PGRAPH_ABS_Y_RAM
, /* 32 values from 0x400480 to 0x4004fc */
305 NV03_PGRAPH_ABS_UCLIP_XMIN
,
306 NV03_PGRAPH_ABS_UCLIP_XMAX
,
307 NV03_PGRAPH_ABS_UCLIP_YMIN
,
308 NV03_PGRAPH_ABS_UCLIP_YMAX
,
313 NV03_PGRAPH_ABS_UCLIPA_XMIN
,
314 NV03_PGRAPH_ABS_UCLIPA_XMAX
,
315 NV03_PGRAPH_ABS_UCLIPA_YMIN
,
316 NV03_PGRAPH_ABS_UCLIPA_YMAX
,
317 NV03_PGRAPH_ABS_ICLIP_XMAX
,
318 NV03_PGRAPH_ABS_ICLIP_YMAX
,
319 NV03_PGRAPH_XY_LOGIC_MISC0
,
320 NV03_PGRAPH_XY_LOGIC_MISC1
,
321 NV03_PGRAPH_XY_LOGIC_MISC2
,
322 NV03_PGRAPH_XY_LOGIC_MISC3
,
327 NV10_PGRAPH_COMBINER0_IN_ALPHA
,
328 NV10_PGRAPH_COMBINER1_IN_ALPHA
,
329 NV10_PGRAPH_COMBINER0_IN_RGB
,
330 NV10_PGRAPH_COMBINER1_IN_RGB
,
331 NV10_PGRAPH_COMBINER_COLOR0
,
332 NV10_PGRAPH_COMBINER_COLOR1
,
333 NV10_PGRAPH_COMBINER0_OUT_ALPHA
,
334 NV10_PGRAPH_COMBINER1_OUT_ALPHA
,
335 NV10_PGRAPH_COMBINER0_OUT_RGB
,
336 NV10_PGRAPH_COMBINER1_OUT_RGB
,
337 NV10_PGRAPH_COMBINER_FINAL0
,
338 NV10_PGRAPH_COMBINER_FINAL1
,
355 NV04_PGRAPH_PASSTHRU_0
,
356 NV04_PGRAPH_PASSTHRU_1
,
357 NV04_PGRAPH_PASSTHRU_2
,
358 NV10_PGRAPH_DIMX_TEXTURE
,
359 NV10_PGRAPH_WDIMX_TEXTURE
,
360 NV10_PGRAPH_DVD_COLORFMT
,
361 NV10_PGRAPH_SCALED_FORMAT
,
362 NV04_PGRAPH_MISC24_0
,
363 NV04_PGRAPH_MISC24_1
,
364 NV04_PGRAPH_MISC24_2
,
371 static int nv17_graph_ctx_regs
[] = {
392 struct nv10_graph_priv
{
393 struct nouveau_graph base
;
394 struct nv10_graph_chan
*chan
[32];
398 struct nv10_graph_chan
{
399 struct nouveau_object base
;
401 int nv10
[ARRAY_SIZE(nv10_graph_ctx_regs
)];
402 int nv17
[ARRAY_SIZE(nv17_graph_ctx_regs
)];
403 struct pipe_state pipe_state
;
408 static inline struct nv10_graph_priv
*
409 nv10_graph_priv(struct nv10_graph_chan
*chan
)
411 return (void *)nv_object(chan
)->engine
;
414 /*******************************************************************************
415 * Graphics object classes
416 ******************************************************************************/
418 #define PIPE_SAVE(priv, state, addr) \
421 nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \
422 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
423 state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \
426 #define PIPE_RESTORE(priv, state, addr) \
429 nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \
430 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
431 nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
434 static struct nouveau_oclass
435 nv10_graph_sclass
[] = {
436 { 0x0012, &nv04_graph_ofuncs
}, /* beta1 */
437 { 0x0019, &nv04_graph_ofuncs
}, /* clip */
438 { 0x0030, &nv04_graph_ofuncs
}, /* null */
439 { 0x0039, &nv04_graph_ofuncs
}, /* m2mf */
440 { 0x0043, &nv04_graph_ofuncs
}, /* rop */
441 { 0x0044, &nv04_graph_ofuncs
}, /* pattern */
442 { 0x004a, &nv04_graph_ofuncs
}, /* gdi */
443 { 0x0052, &nv04_graph_ofuncs
}, /* swzsurf */
444 { 0x005f, &nv04_graph_ofuncs
}, /* blit */
445 { 0x0062, &nv04_graph_ofuncs
}, /* surf2d */
446 { 0x0072, &nv04_graph_ofuncs
}, /* beta4 */
447 { 0x0089, &nv04_graph_ofuncs
}, /* sifm */
448 { 0x008a, &nv04_graph_ofuncs
}, /* ifc */
449 { 0x009f, &nv04_graph_ofuncs
}, /* blit */
450 { 0x0093, &nv04_graph_ofuncs
}, /* surf3d */
451 { 0x0094, &nv04_graph_ofuncs
}, /* ttri */
452 { 0x0095, &nv04_graph_ofuncs
}, /* mtri */
453 { 0x0056, &nv04_graph_ofuncs
}, /* celcius */
457 static struct nouveau_oclass
458 nv15_graph_sclass
[] = {
459 { 0x0012, &nv04_graph_ofuncs
}, /* beta1 */
460 { 0x0019, &nv04_graph_ofuncs
}, /* clip */
461 { 0x0030, &nv04_graph_ofuncs
}, /* null */
462 { 0x0039, &nv04_graph_ofuncs
}, /* m2mf */
463 { 0x0043, &nv04_graph_ofuncs
}, /* rop */
464 { 0x0044, &nv04_graph_ofuncs
}, /* pattern */
465 { 0x004a, &nv04_graph_ofuncs
}, /* gdi */
466 { 0x0052, &nv04_graph_ofuncs
}, /* swzsurf */
467 { 0x005f, &nv04_graph_ofuncs
}, /* blit */
468 { 0x0062, &nv04_graph_ofuncs
}, /* surf2d */
469 { 0x0072, &nv04_graph_ofuncs
}, /* beta4 */
470 { 0x0089, &nv04_graph_ofuncs
}, /* sifm */
471 { 0x008a, &nv04_graph_ofuncs
}, /* ifc */
472 { 0x009f, &nv04_graph_ofuncs
}, /* blit */
473 { 0x0093, &nv04_graph_ofuncs
}, /* surf3d */
474 { 0x0094, &nv04_graph_ofuncs
}, /* ttri */
475 { 0x0095, &nv04_graph_ofuncs
}, /* mtri */
476 { 0x0096, &nv04_graph_ofuncs
}, /* celcius */
481 nv17_graph_mthd_lma_window(struct nouveau_object
*object
, u32 mthd
,
482 void *args
, u32 size
)
484 struct nv10_graph_chan
*chan
= (void *)object
->parent
;
485 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
486 struct pipe_state
*pipe
= &chan
->pipe_state
;
487 u32 pipe_0x0040
[1], pipe_0x64c0
[8], pipe_0x6a80
[3], pipe_0x6ab0
[3];
488 u32 xfmode0
, xfmode1
;
489 u32 data
= *(u32
*)args
;
492 chan
->lma_window
[(mthd
- 0x1638) / 4] = data
;
497 nv04_graph_idle(priv
);
499 PIPE_SAVE(priv
, pipe_0x0040
, 0x0040);
500 PIPE_SAVE(priv
, pipe
->pipe_0x0200
, 0x0200);
502 PIPE_RESTORE(priv
, chan
->lma_window
, 0x6790);
504 nv04_graph_idle(priv
);
506 xfmode0
= nv_rd32(priv
, NV10_PGRAPH_XFMODE0
);
507 xfmode1
= nv_rd32(priv
, NV10_PGRAPH_XFMODE1
);
509 PIPE_SAVE(priv
, pipe
->pipe_0x4400
, 0x4400);
510 PIPE_SAVE(priv
, pipe_0x64c0
, 0x64c0);
511 PIPE_SAVE(priv
, pipe_0x6ab0
, 0x6ab0);
512 PIPE_SAVE(priv
, pipe_0x6a80
, 0x6a80);
514 nv04_graph_idle(priv
);
516 nv_wr32(priv
, NV10_PGRAPH_XFMODE0
, 0x10000000);
517 nv_wr32(priv
, NV10_PGRAPH_XFMODE1
, 0x00000000);
518 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x000064c0);
519 for (i
= 0; i
< 4; i
++)
520 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x3f800000);
521 for (i
= 0; i
< 4; i
++)
522 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000000);
524 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x00006ab0);
525 for (i
= 0; i
< 3; i
++)
526 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x3f800000);
528 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x00006a80);
529 for (i
= 0; i
< 3; i
++)
530 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000000);
532 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x00000040);
533 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000008);
535 PIPE_RESTORE(priv
, pipe
->pipe_0x0200
, 0x0200);
537 nv04_graph_idle(priv
);
539 PIPE_RESTORE(priv
, pipe_0x0040
, 0x0040);
541 nv_wr32(priv
, NV10_PGRAPH_XFMODE0
, xfmode0
);
542 nv_wr32(priv
, NV10_PGRAPH_XFMODE1
, xfmode1
);
544 PIPE_RESTORE(priv
, pipe_0x64c0
, 0x64c0);
545 PIPE_RESTORE(priv
, pipe_0x6ab0
, 0x6ab0);
546 PIPE_RESTORE(priv
, pipe_0x6a80
, 0x6a80);
547 PIPE_RESTORE(priv
, pipe
->pipe_0x4400
, 0x4400);
549 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x000000c0);
550 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000000);
552 nv04_graph_idle(priv
);
558 nv17_graph_mthd_lma_enable(struct nouveau_object
*object
, u32 mthd
,
559 void *args
, u32 size
)
561 struct nv10_graph_chan
*chan
= (void *)object
->parent
;
562 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
564 nv04_graph_idle(priv
);
566 nv_mask(priv
, NV10_PGRAPH_DEBUG_4
, 0x00000100, 0x00000100);
567 nv_mask(priv
, 0x4006b0, 0x08000000, 0x08000000);
571 static struct nouveau_omthds
572 nv17_celcius_omthds
[] = {
573 { 0x1638, nv17_graph_mthd_lma_window
},
574 { 0x163c, nv17_graph_mthd_lma_window
},
575 { 0x1640, nv17_graph_mthd_lma_window
},
576 { 0x1644, nv17_graph_mthd_lma_window
},
577 { 0x1658, nv17_graph_mthd_lma_enable
},
581 static struct nouveau_oclass
582 nv17_graph_sclass
[] = {
583 { 0x0012, &nv04_graph_ofuncs
}, /* beta1 */
584 { 0x0019, &nv04_graph_ofuncs
}, /* clip */
585 { 0x0030, &nv04_graph_ofuncs
}, /* null */
586 { 0x0039, &nv04_graph_ofuncs
}, /* m2mf */
587 { 0x0043, &nv04_graph_ofuncs
}, /* rop */
588 { 0x0044, &nv04_graph_ofuncs
}, /* pattern */
589 { 0x004a, &nv04_graph_ofuncs
}, /* gdi */
590 { 0x0052, &nv04_graph_ofuncs
}, /* swzsurf */
591 { 0x005f, &nv04_graph_ofuncs
}, /* blit */
592 { 0x0062, &nv04_graph_ofuncs
}, /* surf2d */
593 { 0x0072, &nv04_graph_ofuncs
}, /* beta4 */
594 { 0x0089, &nv04_graph_ofuncs
}, /* sifm */
595 { 0x008a, &nv04_graph_ofuncs
}, /* ifc */
596 { 0x009f, &nv04_graph_ofuncs
}, /* blit */
597 { 0x0093, &nv04_graph_ofuncs
}, /* surf3d */
598 { 0x0094, &nv04_graph_ofuncs
}, /* ttri */
599 { 0x0095, &nv04_graph_ofuncs
}, /* mtri */
600 { 0x0099, &nv04_graph_ofuncs
, nv17_celcius_omthds
},
604 /*******************************************************************************
606 ******************************************************************************/
608 static struct nv10_graph_chan
*
609 nv10_graph_channel(struct nv10_graph_priv
*priv
)
611 struct nv10_graph_chan
*chan
= NULL
;
612 if (nv_rd32(priv
, 0x400144) & 0x00010000) {
613 int chid
= nv_rd32(priv
, 0x400148) >> 24;
614 if (chid
< ARRAY_SIZE(priv
->chan
))
615 chan
= priv
->chan
[chid
];
621 nv10_graph_save_pipe(struct nv10_graph_chan
*chan
)
623 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
624 struct pipe_state
*pipe
= &chan
->pipe_state
;
626 PIPE_SAVE(priv
, pipe
->pipe_0x4400
, 0x4400);
627 PIPE_SAVE(priv
, pipe
->pipe_0x0200
, 0x0200);
628 PIPE_SAVE(priv
, pipe
->pipe_0x6400
, 0x6400);
629 PIPE_SAVE(priv
, pipe
->pipe_0x6800
, 0x6800);
630 PIPE_SAVE(priv
, pipe
->pipe_0x6c00
, 0x6c00);
631 PIPE_SAVE(priv
, pipe
->pipe_0x7000
, 0x7000);
632 PIPE_SAVE(priv
, pipe
->pipe_0x7400
, 0x7400);
633 PIPE_SAVE(priv
, pipe
->pipe_0x7800
, 0x7800);
634 PIPE_SAVE(priv
, pipe
->pipe_0x0040
, 0x0040);
635 PIPE_SAVE(priv
, pipe
->pipe_0x0000
, 0x0000);
639 nv10_graph_load_pipe(struct nv10_graph_chan
*chan
)
641 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
642 struct pipe_state
*pipe
= &chan
->pipe_state
;
643 u32 xfmode0
, xfmode1
;
646 nv04_graph_idle(priv
);
647 /* XXX check haiku comments */
648 xfmode0
= nv_rd32(priv
, NV10_PGRAPH_XFMODE0
);
649 xfmode1
= nv_rd32(priv
, NV10_PGRAPH_XFMODE1
);
650 nv_wr32(priv
, NV10_PGRAPH_XFMODE0
, 0x10000000);
651 nv_wr32(priv
, NV10_PGRAPH_XFMODE1
, 0x00000000);
652 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x000064c0);
653 for (i
= 0; i
< 4; i
++)
654 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x3f800000);
655 for (i
= 0; i
< 4; i
++)
656 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000000);
658 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x00006ab0);
659 for (i
= 0; i
< 3; i
++)
660 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x3f800000);
662 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x00006a80);
663 for (i
= 0; i
< 3; i
++)
664 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000000);
666 nv_wr32(priv
, NV10_PGRAPH_PIPE_ADDRESS
, 0x00000040);
667 nv_wr32(priv
, NV10_PGRAPH_PIPE_DATA
, 0x00000008);
670 PIPE_RESTORE(priv
, pipe
->pipe_0x0200
, 0x0200);
671 nv04_graph_idle(priv
);
674 nv_wr32(priv
, NV10_PGRAPH_XFMODE0
, xfmode0
);
675 nv_wr32(priv
, NV10_PGRAPH_XFMODE1
, xfmode1
);
676 PIPE_RESTORE(priv
, pipe
->pipe_0x6400
, 0x6400);
677 PIPE_RESTORE(priv
, pipe
->pipe_0x6800
, 0x6800);
678 PIPE_RESTORE(priv
, pipe
->pipe_0x6c00
, 0x6c00);
679 PIPE_RESTORE(priv
, pipe
->pipe_0x7000
, 0x7000);
680 PIPE_RESTORE(priv
, pipe
->pipe_0x7400
, 0x7400);
681 PIPE_RESTORE(priv
, pipe
->pipe_0x7800
, 0x7800);
682 PIPE_RESTORE(priv
, pipe
->pipe_0x4400
, 0x4400);
683 PIPE_RESTORE(priv
, pipe
->pipe_0x0000
, 0x0000);
684 PIPE_RESTORE(priv
, pipe
->pipe_0x0040
, 0x0040);
685 nv04_graph_idle(priv
);
689 nv10_graph_create_pipe(struct nv10_graph_chan
*chan
)
691 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
692 struct pipe_state
*pipe_state
= &chan
->pipe_state
;
693 u32
*pipe_state_addr
;
695 #define PIPE_INIT(addr) \
697 pipe_state_addr = pipe_state->pipe_##addr; \
699 #define PIPE_INIT_END(addr) \
701 u32 *__end_addr = pipe_state->pipe_##addr + \
702 ARRAY_SIZE(pipe_state->pipe_##addr); \
703 if (pipe_state_addr != __end_addr) \
704 nv_error(priv, "incomplete pipe init for 0x%x : %p/%p\n", \
705 addr, pipe_state_addr, __end_addr); \
707 #define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
710 for (i
= 0; i
< 48; i
++)
711 NV_WRITE_PIPE_INIT(0x00000000);
712 PIPE_INIT_END(0x0200);
715 for (i
= 0; i
< 211; i
++)
716 NV_WRITE_PIPE_INIT(0x00000000);
717 NV_WRITE_PIPE_INIT(0x3f800000);
718 NV_WRITE_PIPE_INIT(0x40000000);
719 NV_WRITE_PIPE_INIT(0x40000000);
720 NV_WRITE_PIPE_INIT(0x40000000);
721 NV_WRITE_PIPE_INIT(0x40000000);
722 NV_WRITE_PIPE_INIT(0x00000000);
723 NV_WRITE_PIPE_INIT(0x00000000);
724 NV_WRITE_PIPE_INIT(0x3f800000);
725 NV_WRITE_PIPE_INIT(0x00000000);
726 NV_WRITE_PIPE_INIT(0x3f000000);
727 NV_WRITE_PIPE_INIT(0x3f000000);
728 NV_WRITE_PIPE_INIT(0x00000000);
729 NV_WRITE_PIPE_INIT(0x00000000);
730 NV_WRITE_PIPE_INIT(0x00000000);
731 NV_WRITE_PIPE_INIT(0x00000000);
732 NV_WRITE_PIPE_INIT(0x3f800000);
733 NV_WRITE_PIPE_INIT(0x00000000);
734 NV_WRITE_PIPE_INIT(0x00000000);
735 NV_WRITE_PIPE_INIT(0x00000000);
736 NV_WRITE_PIPE_INIT(0x00000000);
737 NV_WRITE_PIPE_INIT(0x00000000);
738 NV_WRITE_PIPE_INIT(0x3f800000);
739 NV_WRITE_PIPE_INIT(0x3f800000);
740 NV_WRITE_PIPE_INIT(0x3f800000);
741 NV_WRITE_PIPE_INIT(0x3f800000);
742 PIPE_INIT_END(0x6400);
745 for (i
= 0; i
< 162; i
++)
746 NV_WRITE_PIPE_INIT(0x00000000);
747 NV_WRITE_PIPE_INIT(0x3f800000);
748 for (i
= 0; i
< 25; i
++)
749 NV_WRITE_PIPE_INIT(0x00000000);
750 PIPE_INIT_END(0x6800);
753 NV_WRITE_PIPE_INIT(0x00000000);
754 NV_WRITE_PIPE_INIT(0x00000000);
755 NV_WRITE_PIPE_INIT(0x00000000);
756 NV_WRITE_PIPE_INIT(0x00000000);
757 NV_WRITE_PIPE_INIT(0xbf800000);
758 NV_WRITE_PIPE_INIT(0x00000000);
759 NV_WRITE_PIPE_INIT(0x00000000);
760 NV_WRITE_PIPE_INIT(0x00000000);
761 NV_WRITE_PIPE_INIT(0x00000000);
762 NV_WRITE_PIPE_INIT(0x00000000);
763 NV_WRITE_PIPE_INIT(0x00000000);
764 NV_WRITE_PIPE_INIT(0x00000000);
765 PIPE_INIT_END(0x6c00);
768 NV_WRITE_PIPE_INIT(0x00000000);
769 NV_WRITE_PIPE_INIT(0x00000000);
770 NV_WRITE_PIPE_INIT(0x00000000);
771 NV_WRITE_PIPE_INIT(0x00000000);
772 NV_WRITE_PIPE_INIT(0x00000000);
773 NV_WRITE_PIPE_INIT(0x00000000);
774 NV_WRITE_PIPE_INIT(0x00000000);
775 NV_WRITE_PIPE_INIT(0x00000000);
776 NV_WRITE_PIPE_INIT(0x00000000);
777 NV_WRITE_PIPE_INIT(0x00000000);
778 NV_WRITE_PIPE_INIT(0x00000000);
779 NV_WRITE_PIPE_INIT(0x00000000);
780 NV_WRITE_PIPE_INIT(0x7149f2ca);
781 NV_WRITE_PIPE_INIT(0x00000000);
782 NV_WRITE_PIPE_INIT(0x00000000);
783 NV_WRITE_PIPE_INIT(0x00000000);
784 NV_WRITE_PIPE_INIT(0x7149f2ca);
785 NV_WRITE_PIPE_INIT(0x00000000);
786 NV_WRITE_PIPE_INIT(0x00000000);
787 NV_WRITE_PIPE_INIT(0x00000000);
788 NV_WRITE_PIPE_INIT(0x7149f2ca);
789 NV_WRITE_PIPE_INIT(0x00000000);
790 NV_WRITE_PIPE_INIT(0x00000000);
791 NV_WRITE_PIPE_INIT(0x00000000);
792 NV_WRITE_PIPE_INIT(0x7149f2ca);
793 NV_WRITE_PIPE_INIT(0x00000000);
794 NV_WRITE_PIPE_INIT(0x00000000);
795 NV_WRITE_PIPE_INIT(0x00000000);
796 NV_WRITE_PIPE_INIT(0x7149f2ca);
797 NV_WRITE_PIPE_INIT(0x00000000);
798 NV_WRITE_PIPE_INIT(0x00000000);
799 NV_WRITE_PIPE_INIT(0x00000000);
800 NV_WRITE_PIPE_INIT(0x7149f2ca);
801 NV_WRITE_PIPE_INIT(0x00000000);
802 NV_WRITE_PIPE_INIT(0x00000000);
803 NV_WRITE_PIPE_INIT(0x00000000);
804 NV_WRITE_PIPE_INIT(0x7149f2ca);
805 NV_WRITE_PIPE_INIT(0x00000000);
806 NV_WRITE_PIPE_INIT(0x00000000);
807 NV_WRITE_PIPE_INIT(0x00000000);
808 NV_WRITE_PIPE_INIT(0x7149f2ca);
809 for (i
= 0; i
< 35; i
++)
810 NV_WRITE_PIPE_INIT(0x00000000);
811 PIPE_INIT_END(0x7000);
814 for (i
= 0; i
< 48; i
++)
815 NV_WRITE_PIPE_INIT(0x00000000);
816 PIPE_INIT_END(0x7400);
819 for (i
= 0; i
< 48; i
++)
820 NV_WRITE_PIPE_INIT(0x00000000);
821 PIPE_INIT_END(0x7800);
824 for (i
= 0; i
< 32; i
++)
825 NV_WRITE_PIPE_INIT(0x00000000);
826 PIPE_INIT_END(0x4400);
829 for (i
= 0; i
< 16; i
++)
830 NV_WRITE_PIPE_INIT(0x00000000);
831 PIPE_INIT_END(0x0000);
834 for (i
= 0; i
< 4; i
++)
835 NV_WRITE_PIPE_INIT(0x00000000);
836 PIPE_INIT_END(0x0040);
840 #undef NV_WRITE_PIPE_INIT
844 nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv
*priv
, int reg
)
847 for (i
= 0; i
< ARRAY_SIZE(nv10_graph_ctx_regs
); i
++) {
848 if (nv10_graph_ctx_regs
[i
] == reg
)
851 nv_error(priv
, "unknow offset nv10_ctx_regs %d\n", reg
);
856 nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv
*priv
, int reg
)
859 for (i
= 0; i
< ARRAY_SIZE(nv17_graph_ctx_regs
); i
++) {
860 if (nv17_graph_ctx_regs
[i
] == reg
)
863 nv_error(priv
, "unknow offset nv17_ctx_regs %d\n", reg
);
868 nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan
*chan
, int chid
, u32 inst
)
870 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
871 u32 st2
, st2_dl
, st2_dh
, fifo_ptr
, fifo
[0x60/4];
872 u32 ctx_user
, ctx_switch
[5];
875 /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state
876 * that cannot be restored via MMIO. Do it through the FIFO
880 /* Look for a celsius object */
881 for (i
= 0; i
< 8; i
++) {
882 int class = nv_rd32(priv
, NV10_PGRAPH_CTX_CACHE(i
, 0)) & 0xfff;
884 if (class == 0x56 || class == 0x96 || class == 0x99) {
890 if (subchan
< 0 || !inst
)
893 /* Save the current ctx object */
894 ctx_user
= nv_rd32(priv
, NV10_PGRAPH_CTX_USER
);
895 for (i
= 0; i
< 5; i
++)
896 ctx_switch
[i
] = nv_rd32(priv
, NV10_PGRAPH_CTX_SWITCH(i
));
898 /* Save the FIFO state */
899 st2
= nv_rd32(priv
, NV10_PGRAPH_FFINTFC_ST2
);
900 st2_dl
= nv_rd32(priv
, NV10_PGRAPH_FFINTFC_ST2_DL
);
901 st2_dh
= nv_rd32(priv
, NV10_PGRAPH_FFINTFC_ST2_DH
);
902 fifo_ptr
= nv_rd32(priv
, NV10_PGRAPH_FFINTFC_FIFO_PTR
);
904 for (i
= 0; i
< ARRAY_SIZE(fifo
); i
++)
905 fifo
[i
] = nv_rd32(priv
, 0x4007a0 + 4 * i
);
907 /* Switch to the celsius subchannel */
908 for (i
= 0; i
< 5; i
++)
909 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(i
),
910 nv_rd32(priv
, NV10_PGRAPH_CTX_CACHE(subchan
, i
)));
911 nv_mask(priv
, NV10_PGRAPH_CTX_USER
, 0xe000, subchan
<< 13);
913 /* Inject NV10TCL_DMA_VTXBUF */
914 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_FIFO_PTR
, 0);
915 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_ST2
,
916 0x2c000000 | chid
<< 20 | subchan
<< 16 | 0x18c);
917 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_ST2_DL
, inst
);
918 nv_mask(priv
, NV10_PGRAPH_CTX_CONTROL
, 0, 0x10000);
919 nv_mask(priv
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000001);
920 nv_mask(priv
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000000);
922 /* Restore the FIFO state */
923 for (i
= 0; i
< ARRAY_SIZE(fifo
); i
++)
924 nv_wr32(priv
, 0x4007a0 + 4 * i
, fifo
[i
]);
926 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_FIFO_PTR
, fifo_ptr
);
927 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_ST2
, st2
);
928 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_ST2_DL
, st2_dl
);
929 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_ST2_DH
, st2_dh
);
931 /* Restore the current ctx object */
932 for (i
= 0; i
< 5; i
++)
933 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(i
), ctx_switch
[i
]);
934 nv_wr32(priv
, NV10_PGRAPH_CTX_USER
, ctx_user
);
938 nv10_graph_load_context(struct nv10_graph_chan
*chan
, int chid
)
940 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
944 for (i
= 0; i
< ARRAY_SIZE(nv10_graph_ctx_regs
); i
++)
945 nv_wr32(priv
, nv10_graph_ctx_regs
[i
], chan
->nv10
[i
]);
947 if (nv_device(priv
)->chipset
>= 0x17) {
948 for (i
= 0; i
< ARRAY_SIZE(nv17_graph_ctx_regs
); i
++)
949 nv_wr32(priv
, nv17_graph_ctx_regs
[i
], chan
->nv17
[i
]);
952 nv10_graph_load_pipe(chan
);
954 inst
= nv_rd32(priv
, NV10_PGRAPH_GLOBALSTATE1
) & 0xffff;
955 nv10_graph_load_dma_vtxbuf(chan
, chid
, inst
);
957 nv_wr32(priv
, NV10_PGRAPH_CTX_CONTROL
, 0x10010100);
958 nv_mask(priv
, NV10_PGRAPH_CTX_USER
, 0xff000000, chid
<< 24);
959 nv_mask(priv
, NV10_PGRAPH_FFINTFC_ST2
, 0x30000000, 0x00000000);
964 nv10_graph_unload_context(struct nv10_graph_chan
*chan
)
966 struct nv10_graph_priv
*priv
= nv10_graph_priv(chan
);
969 for (i
= 0; i
< ARRAY_SIZE(nv10_graph_ctx_regs
); i
++)
970 chan
->nv10
[i
] = nv_rd32(priv
, nv10_graph_ctx_regs
[i
]);
972 if (nv_device(priv
)->chipset
>= 0x17) {
973 for (i
= 0; i
< ARRAY_SIZE(nv17_graph_ctx_regs
); i
++)
974 chan
->nv17
[i
] = nv_rd32(priv
, nv17_graph_ctx_regs
[i
]);
977 nv10_graph_save_pipe(chan
);
979 nv_wr32(priv
, NV10_PGRAPH_CTX_CONTROL
, 0x10000000);
980 nv_mask(priv
, NV10_PGRAPH_CTX_USER
, 0xff000000, 0x1f000000);
985 nv10_graph_context_switch(struct nv10_graph_priv
*priv
)
987 struct nv10_graph_chan
*prev
= NULL
;
988 struct nv10_graph_chan
*next
= NULL
;
992 spin_lock_irqsave(&priv
->lock
, flags
);
993 nv04_graph_idle(priv
);
995 /* If previous context is valid, we need to save it */
996 prev
= nv10_graph_channel(priv
);
998 nv10_graph_unload_context(prev
);
1000 /* load context for next channel */
1001 chid
= (nv_rd32(priv
, NV04_PGRAPH_TRAPPED_ADDR
) >> 20) & 0x1f;
1002 next
= priv
->chan
[chid
];
1004 nv10_graph_load_context(next
, chid
);
1006 spin_unlock_irqrestore(&priv
->lock
, flags
);
1009 #define NV_WRITE_CTX(reg, val) do { \
1010 int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \
1012 chan->nv10[offset] = val; \
1015 #define NV17_WRITE_CTX(reg, val) do { \
1016 int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \
1018 chan->nv17[offset] = val; \
1022 nv10_graph_context_ctor(struct nouveau_object
*parent
,
1023 struct nouveau_object
*engine
,
1024 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
1025 struct nouveau_object
**pobject
)
1027 struct nouveau_fifo_chan
*fifo
= (void *)parent
;
1028 struct nv10_graph_priv
*priv
= (void *)engine
;
1029 struct nv10_graph_chan
*chan
;
1030 unsigned long flags
;
1033 ret
= nouveau_object_create(parent
, engine
, oclass
, 0, &chan
);
1034 *pobject
= nv_object(chan
);
1038 spin_lock_irqsave(&priv
->lock
, flags
);
1039 if (priv
->chan
[fifo
->chid
]) {
1040 *pobject
= nv_object(priv
->chan
[fifo
->chid
]);
1041 atomic_inc(&(*pobject
)->refcount
);
1042 spin_unlock_irqrestore(&priv
->lock
, flags
);
1043 nouveau_object_destroy(&chan
->base
);
1047 NV_WRITE_CTX(0x00400e88, 0x08000000);
1048 NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
1049 NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0
, 0x0001ffff);
1050 NV_WRITE_CTX(0x00400e10, 0x00001000);
1051 NV_WRITE_CTX(0x00400e14, 0x00001000);
1052 NV_WRITE_CTX(0x00400e30, 0x00080008);
1053 NV_WRITE_CTX(0x00400e34, 0x00080008);
1054 if (nv_device(priv
)->chipset
>= 0x17) {
1055 /* is it really needed ??? */
1056 NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4
,
1057 nv_rd32(priv
, NV10_PGRAPH_DEBUG_4
));
1058 NV17_WRITE_CTX(0x004006b0, nv_rd32(priv
, 0x004006b0));
1059 NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
1060 NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
1061 NV17_WRITE_CTX(0x00400ec0, 0x00000080);
1062 NV17_WRITE_CTX(0x00400ed0, 0x00000080);
1064 NV_WRITE_CTX(NV10_PGRAPH_CTX_USER
, chan
->chid
<< 24);
1066 nv10_graph_create_pipe(chan
);
1068 priv
->chan
[fifo
->chid
] = chan
;
1069 chan
->chid
= fifo
->chid
;
1070 spin_unlock_irqrestore(&priv
->lock
, flags
);
1075 nv10_graph_context_dtor(struct nouveau_object
*object
)
1077 struct nv10_graph_priv
*priv
= (void *)object
->engine
;
1078 struct nv10_graph_chan
*chan
= (void *)object
;
1079 unsigned long flags
;
1081 spin_lock_irqsave(&priv
->lock
, flags
);
1082 priv
->chan
[chan
->chid
] = NULL
;
1083 spin_unlock_irqrestore(&priv
->lock
, flags
);
1085 nouveau_object_destroy(&chan
->base
);
1089 nv10_graph_context_fini(struct nouveau_object
*object
, bool suspend
)
1091 struct nv10_graph_priv
*priv
= (void *)object
->engine
;
1092 struct nv10_graph_chan
*chan
= (void *)object
;
1093 unsigned long flags
;
1095 spin_lock_irqsave(&priv
->lock
, flags
);
1096 nv_mask(priv
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000000);
1097 if (nv10_graph_channel(priv
) == chan
)
1098 nv10_graph_unload_context(chan
);
1099 nv_mask(priv
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000001);
1100 spin_unlock_irqrestore(&priv
->lock
, flags
);
1102 return nouveau_object_fini(&chan
->base
, suspend
);
1105 static struct nouveau_oclass
1106 nv10_graph_cclass
= {
1107 .handle
= NV_ENGCTX(GR
, 0x10),
1108 .ofuncs
= &(struct nouveau_ofuncs
) {
1109 .ctor
= nv10_graph_context_ctor
,
1110 .dtor
= nv10_graph_context_dtor
,
1111 .init
= nouveau_object_init
,
1112 .fini
= nv10_graph_context_fini
,
1116 /*******************************************************************************
1117 * PGRAPH engine/subdev functions
1118 ******************************************************************************/
1121 nv10_graph_tile_prog(struct nouveau_engine
*engine
, int i
)
1123 struct nouveau_fb_tile
*tile
= &nouveau_fb(engine
)->tile
.region
[i
];
1124 struct nouveau_fifo
*pfifo
= nouveau_fifo(engine
);
1125 struct nv10_graph_priv
*priv
= (void *)engine
;
1126 unsigned long flags
;
1128 pfifo
->pause(pfifo
, &flags
);
1129 nv04_graph_idle(priv
);
1131 nv_wr32(priv
, NV10_PGRAPH_TLIMIT(i
), tile
->limit
);
1132 nv_wr32(priv
, NV10_PGRAPH_TSIZE(i
), tile
->pitch
);
1133 nv_wr32(priv
, NV10_PGRAPH_TILE(i
), tile
->addr
);
1135 pfifo
->start(pfifo
, &flags
);
1138 struct nouveau_bitfield nv10_graph_intr_name
[] = {
1139 { NV_PGRAPH_INTR_NOTIFY
, "NOTIFY" },
1140 { NV_PGRAPH_INTR_ERROR
, "ERROR" },
1144 struct nouveau_bitfield nv10_graph_nstatus
[] = {
1145 { NV10_PGRAPH_NSTATUS_STATE_IN_USE
, "STATE_IN_USE" },
1146 { NV10_PGRAPH_NSTATUS_INVALID_STATE
, "INVALID_STATE" },
1147 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT
, "BAD_ARGUMENT" },
1148 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT
, "PROTECTION_FAULT" },
1153 nv10_graph_intr(struct nouveau_subdev
*subdev
)
1155 struct nv10_graph_priv
*priv
= (void *)subdev
;
1156 struct nv10_graph_chan
*chan
= NULL
;
1157 struct nouveau_namedb
*namedb
= NULL
;
1158 struct nouveau_handle
*handle
= NULL
;
1159 u32 stat
= nv_rd32(priv
, NV03_PGRAPH_INTR
);
1160 u32 nsource
= nv_rd32(priv
, NV03_PGRAPH_NSOURCE
);
1161 u32 nstatus
= nv_rd32(priv
, NV03_PGRAPH_NSTATUS
);
1162 u32 addr
= nv_rd32(priv
, NV04_PGRAPH_TRAPPED_ADDR
);
1163 u32 chid
= (addr
& 0x01f00000) >> 20;
1164 u32 subc
= (addr
& 0x00070000) >> 16;
1165 u32 mthd
= (addr
& 0x00001ffc);
1166 u32 data
= nv_rd32(priv
, NV04_PGRAPH_TRAPPED_DATA
);
1167 u32
class = nv_rd32(priv
, 0x400160 + subc
* 4) & 0xfff;
1169 unsigned long flags
;
1171 spin_lock_irqsave(&priv
->lock
, flags
);
1172 chan
= priv
->chan
[chid
];
1174 namedb
= (void *)nv_pclass(nv_object(chan
), NV_NAMEDB_CLASS
);
1175 spin_unlock_irqrestore(&priv
->lock
, flags
);
1177 if (stat
& NV_PGRAPH_INTR_ERROR
) {
1178 if (chan
&& (nsource
& NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD
)) {
1179 handle
= nouveau_namedb_get_class(namedb
, class);
1180 if (handle
&& !nv_call(handle
->object
, mthd
, data
))
1181 show
&= ~NV_PGRAPH_INTR_ERROR
;
1185 if (stat
& NV_PGRAPH_INTR_CONTEXT_SWITCH
) {
1186 nv_wr32(priv
, NV03_PGRAPH_INTR
, NV_PGRAPH_INTR_CONTEXT_SWITCH
);
1187 stat
&= ~NV_PGRAPH_INTR_CONTEXT_SWITCH
;
1188 show
&= ~NV_PGRAPH_INTR_CONTEXT_SWITCH
;
1189 nv10_graph_context_switch(priv
);
1192 nv_wr32(priv
, NV03_PGRAPH_INTR
, stat
);
1193 nv_wr32(priv
, NV04_PGRAPH_FIFO
, 0x00000001);
1197 nouveau_bitfield_print(nv10_graph_intr_name
, show
);
1198 printk(" nsource:");
1199 nouveau_bitfield_print(nv04_graph_nsource
, nsource
);
1200 printk(" nstatus:");
1201 nouveau_bitfield_print(nv10_graph_nstatus
, nstatus
);
1203 nv_error(priv
, "ch %d/%d class 0x%04x "
1204 "mthd 0x%04x data 0x%08x\n",
1205 chid
, subc
, class, mthd
, data
);
1208 nouveau_namedb_put(handle
);
1212 nv10_graph_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
1213 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
1214 struct nouveau_object
**pobject
)
1216 struct nv10_graph_priv
*priv
;
1219 ret
= nouveau_graph_create(parent
, engine
, oclass
, true, &priv
);
1220 *pobject
= nv_object(priv
);
1224 nv_subdev(priv
)->unit
= 0x00001000;
1225 nv_subdev(priv
)->intr
= nv10_graph_intr
;
1226 nv_engine(priv
)->cclass
= &nv10_graph_cclass
;
1228 if (nv_device(priv
)->chipset
<= 0x10)
1229 nv_engine(priv
)->sclass
= nv10_graph_sclass
;
1231 if (nv_device(priv
)->chipset
< 0x17 ||
1232 nv_device(priv
)->chipset
== 0x1a)
1233 nv_engine(priv
)->sclass
= nv15_graph_sclass
;
1235 nv_engine(priv
)->sclass
= nv17_graph_sclass
;
1237 nv_engine(priv
)->tile_prog
= nv10_graph_tile_prog
;
1238 spin_lock_init(&priv
->lock
);
1243 nv10_graph_dtor(struct nouveau_object
*object
)
1245 struct nv10_graph_priv
*priv
= (void *)object
;
1246 nouveau_graph_destroy(&priv
->base
);
1250 nv10_graph_init(struct nouveau_object
*object
)
1252 struct nouveau_engine
*engine
= nv_engine(object
);
1253 struct nouveau_fb
*pfb
= nouveau_fb(object
);
1254 struct nv10_graph_priv
*priv
= (void *)engine
;
1257 ret
= nouveau_graph_init(&priv
->base
);
1261 nv_wr32(priv
, NV03_PGRAPH_INTR
, 0xFFFFFFFF);
1262 nv_wr32(priv
, NV03_PGRAPH_INTR_EN
, 0xFFFFFFFF);
1264 nv_wr32(priv
, NV04_PGRAPH_DEBUG_0
, 0xFFFFFFFF);
1265 nv_wr32(priv
, NV04_PGRAPH_DEBUG_0
, 0x00000000);
1266 nv_wr32(priv
, NV04_PGRAPH_DEBUG_1
, 0x00118700);
1267 /* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
1268 nv_wr32(priv
, NV04_PGRAPH_DEBUG_2
, 0x25f92ad9);
1269 nv_wr32(priv
, NV04_PGRAPH_DEBUG_3
, 0x55DE0830 | (1 << 29) | (1 << 31));
1271 if (nv_device(priv
)->chipset
>= 0x17) {
1272 nv_wr32(priv
, NV10_PGRAPH_DEBUG_4
, 0x1f000000);
1273 nv_wr32(priv
, 0x400a10, 0x03ff3fb6);
1274 nv_wr32(priv
, 0x400838, 0x002f8684);
1275 nv_wr32(priv
, 0x40083c, 0x00115f3f);
1276 nv_wr32(priv
, 0x4006b0, 0x40000020);
1278 nv_wr32(priv
, NV10_PGRAPH_DEBUG_4
, 0x00000000);
1281 /* Turn all the tiling regions off. */
1282 for (i
= 0; i
< pfb
->tile
.regions
; i
++)
1283 engine
->tile_prog(engine
, i
);
1285 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
1286 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
1287 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
1288 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
1289 nv_wr32(priv
, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
1290 nv_wr32(priv
, NV10_PGRAPH_STATE
, 0xFFFFFFFF);
1292 nv_mask(priv
, NV10_PGRAPH_CTX_USER
, 0xff000000, 0x1f000000);
1293 nv_wr32(priv
, NV10_PGRAPH_CTX_CONTROL
, 0x10000100);
1294 nv_wr32(priv
, NV10_PGRAPH_FFINTFC_ST2
, 0x08000000);
1299 nv10_graph_fini(struct nouveau_object
*object
, bool suspend
)
1301 struct nv10_graph_priv
*priv
= (void *)object
;
1302 return nouveau_graph_fini(&priv
->base
, suspend
);
1305 struct nouveau_oclass
1306 nv10_graph_oclass
= {
1307 .handle
= NV_ENGINE(GR
, 0x10),
1308 .ofuncs
= &(struct nouveau_ofuncs
) {
1309 .ctor
= nv10_graph_ctor
,
1310 .dtor
= nv10_graph_dtor
,
1311 .init
= nv10_graph_init
,
1312 .fini
= nv10_graph_fini
,