2 #include <core/class.h>
3 #include <core/engctx.h>
6 #include <subdev/timer.h>
9 #include <engine/graph.h>
14 /*******************************************************************************
15 * Graphics object classes
16 ******************************************************************************/
18 static struct nouveau_oclass
19 nv30_graph_sclass
[] = {
20 { 0x0012, &nv04_graph_ofuncs
, NULL
}, /* beta1 */
21 { 0x0019, &nv04_graph_ofuncs
, NULL
}, /* clip */
22 { 0x0030, &nv04_graph_ofuncs
, NULL
}, /* null */
23 { 0x0039, &nv04_graph_ofuncs
, NULL
}, /* m2mf */
24 { 0x0043, &nv04_graph_ofuncs
, NULL
}, /* rop */
25 { 0x0044, &nv04_graph_ofuncs
, NULL
}, /* patt */
26 { 0x004a, &nv04_graph_ofuncs
, NULL
}, /* gdi */
27 { 0x0062, &nv04_graph_ofuncs
, NULL
}, /* surf2d */
28 { 0x0072, &nv04_graph_ofuncs
, NULL
}, /* beta4 */
29 { 0x0089, &nv04_graph_ofuncs
, NULL
}, /* sifm */
30 { 0x008a, &nv04_graph_ofuncs
, NULL
}, /* ifc */
31 { 0x009f, &nv04_graph_ofuncs
, NULL
}, /* imageblit */
32 { 0x0362, &nv04_graph_ofuncs
, NULL
}, /* surf2d (nv30) */
33 { 0x0389, &nv04_graph_ofuncs
, NULL
}, /* sifm (nv30) */
34 { 0x038a, &nv04_graph_ofuncs
, NULL
}, /* ifc (nv30) */
35 { 0x039e, &nv04_graph_ofuncs
, NULL
}, /* swzsurf (nv30) */
36 { 0x0397, &nv04_graph_ofuncs
, NULL
}, /* rankine */
40 /*******************************************************************************
42 ******************************************************************************/
45 nv30_graph_context_ctor(struct nouveau_object
*parent
,
46 struct nouveau_object
*engine
,
47 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
48 struct nouveau_object
**pobject
)
50 struct nv20_graph_chan
*chan
;
53 ret
= nouveau_graph_context_create(parent
, engine
, oclass
, NULL
, 0x5f48,
54 16, NVOBJ_FLAG_ZERO_ALLOC
, &chan
);
55 *pobject
= nv_object(chan
);
59 chan
->chid
= nouveau_fifo_chan(parent
)->chid
;
61 nv_wo32(chan
, 0x0028, 0x00000001 | (chan
->chid
<< 24));
62 nv_wo32(chan
, 0x0410, 0x00000101);
63 nv_wo32(chan
, 0x0424, 0x00000111);
64 nv_wo32(chan
, 0x0428, 0x00000060);
65 nv_wo32(chan
, 0x0444, 0x00000080);
66 nv_wo32(chan
, 0x0448, 0xffff0000);
67 nv_wo32(chan
, 0x044c, 0x00000001);
68 nv_wo32(chan
, 0x0460, 0x44400000);
69 nv_wo32(chan
, 0x048c, 0xffff0000);
70 for (i
= 0x04e0; i
< 0x04e8; i
+= 4)
71 nv_wo32(chan
, i
, 0x0fff0000);
72 nv_wo32(chan
, 0x04ec, 0x00011100);
73 for (i
= 0x0508; i
< 0x0548; i
+= 4)
74 nv_wo32(chan
, i
, 0x07ff0000);
75 nv_wo32(chan
, 0x0550, 0x4b7fffff);
76 nv_wo32(chan
, 0x058c, 0x00000080);
77 nv_wo32(chan
, 0x0590, 0x30201000);
78 nv_wo32(chan
, 0x0594, 0x70605040);
79 nv_wo32(chan
, 0x0598, 0xb8a89888);
80 nv_wo32(chan
, 0x059c, 0xf8e8d8c8);
81 nv_wo32(chan
, 0x05b0, 0xb0000000);
82 for (i
= 0x0600; i
< 0x0640; i
+= 4)
83 nv_wo32(chan
, i
, 0x00010588);
84 for (i
= 0x0640; i
< 0x0680; i
+= 4)
85 nv_wo32(chan
, i
, 0x00030303);
86 for (i
= 0x06c0; i
< 0x0700; i
+= 4)
87 nv_wo32(chan
, i
, 0x0008aae4);
88 for (i
= 0x0700; i
< 0x0740; i
+= 4)
89 nv_wo32(chan
, i
, 0x01012000);
90 for (i
= 0x0740; i
< 0x0780; i
+= 4)
91 nv_wo32(chan
, i
, 0x00080008);
92 nv_wo32(chan
, 0x085c, 0x00040000);
93 nv_wo32(chan
, 0x0860, 0x00010000);
94 for (i
= 0x0864; i
< 0x0874; i
+= 4)
95 nv_wo32(chan
, i
, 0x00040004);
96 for (i
= 0x1f18; i
<= 0x3088 ; i
+= 16) {
97 nv_wo32(chan
, i
+ 0, 0x10700ff9);
98 nv_wo32(chan
, i
+ 1, 0x0436086c);
99 nv_wo32(chan
, i
+ 2, 0x000c001b);
101 for (i
= 0x30b8; i
< 0x30c8; i
+= 4)
102 nv_wo32(chan
, i
, 0x0000ffff);
103 nv_wo32(chan
, 0x344c, 0x3f800000);
104 nv_wo32(chan
, 0x3808, 0x3f800000);
105 nv_wo32(chan
, 0x381c, 0x3f800000);
106 nv_wo32(chan
, 0x3848, 0x40000000);
107 nv_wo32(chan
, 0x384c, 0x3f800000);
108 nv_wo32(chan
, 0x3850, 0x3f000000);
109 nv_wo32(chan
, 0x3858, 0x40000000);
110 nv_wo32(chan
, 0x385c, 0x3f800000);
111 nv_wo32(chan
, 0x3864, 0xbf800000);
112 nv_wo32(chan
, 0x386c, 0xbf800000);
116 static struct nouveau_oclass
117 nv30_graph_cclass
= {
118 .handle
= NV_ENGCTX(GR
, 0x30),
119 .ofuncs
= &(struct nouveau_ofuncs
) {
120 .ctor
= nv30_graph_context_ctor
,
121 .dtor
= _nouveau_graph_context_dtor
,
122 .init
= nv20_graph_context_init
,
123 .fini
= nv20_graph_context_fini
,
124 .rd32
= _nouveau_graph_context_rd32
,
125 .wr32
= _nouveau_graph_context_wr32
,
129 /*******************************************************************************
130 * PGRAPH engine/subdev functions
131 ******************************************************************************/
134 nv30_graph_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
135 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
136 struct nouveau_object
**pobject
)
138 struct nv20_graph_priv
*priv
;
141 ret
= nouveau_graph_create(parent
, engine
, oclass
, true, &priv
);
142 *pobject
= nv_object(priv
);
146 ret
= nouveau_gpuobj_new(parent
, NULL
, 32 * 4, 16,
147 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->ctxtab
);
151 nv_subdev(priv
)->unit
= 0x00001000;
152 nv_subdev(priv
)->intr
= nv20_graph_intr
;
153 nv_engine(priv
)->cclass
= &nv30_graph_cclass
;
154 nv_engine(priv
)->sclass
= nv30_graph_sclass
;
155 nv_engine(priv
)->tile_prog
= nv20_graph_tile_prog
;
160 nv30_graph_init(struct nouveau_object
*object
)
162 struct nouveau_engine
*engine
= nv_engine(object
);
163 struct nv20_graph_priv
*priv
= (void *)engine
;
164 struct nouveau_fb
*pfb
= nouveau_fb(object
);
167 ret
= nouveau_graph_init(&priv
->base
);
171 nv_wr32(priv
, NV20_PGRAPH_CHANNEL_CTX_TABLE
, priv
->ctxtab
->addr
>> 4);
173 nv_wr32(priv
, NV03_PGRAPH_INTR
, 0xFFFFFFFF);
174 nv_wr32(priv
, NV03_PGRAPH_INTR_EN
, 0xFFFFFFFF);
176 nv_wr32(priv
, NV04_PGRAPH_DEBUG_0
, 0xFFFFFFFF);
177 nv_wr32(priv
, NV04_PGRAPH_DEBUG_0
, 0x00000000);
178 nv_wr32(priv
, NV04_PGRAPH_DEBUG_1
, 0x401287c0);
179 nv_wr32(priv
, 0x400890, 0x01b463ff);
180 nv_wr32(priv
, NV04_PGRAPH_DEBUG_3
, 0xf2de0475);
181 nv_wr32(priv
, NV10_PGRAPH_DEBUG_4
, 0x00008000);
182 nv_wr32(priv
, NV04_PGRAPH_LIMIT_VIOL_PIX
, 0xf04bdff6);
183 nv_wr32(priv
, 0x400B80, 0x1003d888);
184 nv_wr32(priv
, 0x400B84, 0x0c000000);
185 nv_wr32(priv
, 0x400098, 0x00000000);
186 nv_wr32(priv
, 0x40009C, 0x0005ad00);
187 nv_wr32(priv
, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
188 nv_wr32(priv
, 0x4000a0, 0x00000000);
189 nv_wr32(priv
, 0x4000a4, 0x00000008);
190 nv_wr32(priv
, 0x4008a8, 0xb784a400);
191 nv_wr32(priv
, 0x400ba0, 0x002f8685);
192 nv_wr32(priv
, 0x400ba4, 0x00231f3f);
193 nv_wr32(priv
, 0x4008a4, 0x40000020);
195 if (nv_device(priv
)->chipset
== 0x34) {
196 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0004);
197 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00200201);
198 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0008);
199 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000008);
200 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0000);
201 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000032);
202 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00E00004);
203 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000002);
206 nv_wr32(priv
, 0x4000c0, 0x00000016);
208 /* Turn all the tiling regions off. */
209 for (i
= 0; i
< pfb
->tile
.regions
; i
++)
210 engine
->tile_prog(engine
, i
);
212 nv_wr32(priv
, NV10_PGRAPH_CTX_CONTROL
, 0x10000100);
213 nv_wr32(priv
, NV10_PGRAPH_STATE
, 0xFFFFFFFF);
214 nv_wr32(priv
, 0x0040075c , 0x00000001);
216 /* begin RAM config */
217 /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
218 nv_wr32(priv
, 0x4009A4, nv_rd32(priv
, 0x100200));
219 nv_wr32(priv
, 0x4009A8, nv_rd32(priv
, 0x100204));
220 if (nv_device(priv
)->chipset
!= 0x34) {
221 nv_wr32(priv
, 0x400750, 0x00EA0000);
222 nv_wr32(priv
, 0x400754, nv_rd32(priv
, 0x100200));
223 nv_wr32(priv
, 0x400750, 0x00EA0004);
224 nv_wr32(priv
, 0x400754, nv_rd32(priv
, 0x100204));
229 struct nouveau_oclass
230 nv30_graph_oclass
= {
231 .handle
= NV_ENGINE(GR
, 0x30),
232 .ofuncs
= &(struct nouveau_ofuncs
) {
233 .ctor
= nv30_graph_ctor
,
234 .dtor
= nv20_graph_dtor
,
235 .init
= nv30_graph_init
,
236 .fini
= _nouveau_graph_fini
,