drm/nouveau/mc: port to subdev interfaces
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nvc0.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/devinit.h>
31 #include <subdev/mc.h>
32
33 int
34 nvc0_identify(struct nouveau_device *device)
35 {
36 switch (device->chipset) {
37 case 0xc0:
38 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
39 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
40 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
41 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
42 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
43 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
44 break;
45 case 0xc4:
46 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
47 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
48 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
49 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
50 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
51 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
52 break;
53 case 0xc3:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
58 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
59 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
60 break;
61 case 0xce:
62 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
63 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
64 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
65 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
67 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
68 break;
69 case 0xcf:
70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
71 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
76 break;
77 case 0xc1:
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
82 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
83 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
84 break;
85 case 0xc8:
86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
88 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
91 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
92 break;
93 case 0xd9:
94 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
95 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
96 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
97 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
98 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
99 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
100 break;
101 default:
102 nv_fatal(device, "unknown Fermi chipset\n");
103 return -EINVAL;
104 }
105
106 return 0;
107 }
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