2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/devinit.h>
31 #include <subdev/mc.h>
32 #include <subdev/timer.h>
33 #include <subdev/fb.h>
34 #include <subdev/ltcg.h>
37 nvc0_identify(struct nouveau_device
*device
)
39 switch (device
->chipset
) {
41 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
42 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
43 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
44 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
45 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
46 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
47 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
48 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
49 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
52 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
53 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
54 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
55 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
56 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
57 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
58 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
59 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
60 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
63 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
64 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
65 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
66 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
67 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
68 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
69 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
70 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
71 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
74 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
75 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
76 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
77 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
78 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
79 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
80 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
81 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
82 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
85 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
86 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
87 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
88 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
89 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
90 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
91 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
92 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
93 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
96 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
97 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
98 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
99 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
100 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
101 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
102 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
103 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
104 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
107 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
108 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv50_gpio_oclass
;
109 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
110 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
111 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
112 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
113 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
114 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
115 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
118 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
119 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nvd0_gpio_oclass
;
120 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
121 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nvc0_clock_oclass
;
122 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv50_devinit_oclass
;
123 device
->oclass
[NVDEV_SUBDEV_MC
] = &nvc0_mc_oclass
;
124 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
125 device
->oclass
[NVDEV_SUBDEV_FB
] = &nvc0_fb_oclass
;
126 device
->oclass
[NVDEV_SUBDEV_LTCG
] = &nvc0_ltcg_oclass
;
129 nv_fatal(device
, "unknown Fermi chipset\n");
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