drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/bios.h>
  26 #include <subdev/bios/bit.h>
  27 #include <subdev/bios/pll.h>
  28 #include <subdev/bios/rammap.h>
  29 #include <subdev/bios/timing.h>
  30
  31 #include <subdev/clock/nva3.h>
  32 #include <subdev/clock/pll.h>
  33
  34 #include <core/option.h>
  35
  36 #include "ramfuc.h"
  37
  38 #include "nv50.h"
  39
  40 struct nva3_ramfuc {
  41         struct ramfuc base;
  42         struct ramfuc_reg r_0x004000;
  43         struct ramfuc_reg r_0x004004;
  44         struct ramfuc_reg r_0x004018;
  45         struct ramfuc_reg r_0x004128;
  46         struct ramfuc_reg r_0x004168;
  47         struct ramfuc_reg r_0x100200;
  48         struct ramfuc_reg r_0x100210;
  49         struct ramfuc_reg r_0x100220[9];
  50         struct ramfuc_reg r_0x1002d0;
  51         struct ramfuc_reg r_0x1002d4;
  52         struct ramfuc_reg r_0x1002dc;
  53         struct ramfuc_reg r_0x10053c;
  54         struct ramfuc_reg r_0x1005a0;
  55         struct ramfuc_reg r_0x1005a4;
  56         struct ramfuc_reg r_0x100714;
  57         struct ramfuc_reg r_0x100718;
  58         struct ramfuc_reg r_0x10071c;
  59         struct ramfuc_reg r_0x100760;
  60         struct ramfuc_reg r_0x1007a0;
  61         struct ramfuc_reg r_0x1007e0;
  62         struct ramfuc_reg r_0x10f804;
  63         struct ramfuc_reg r_0x1110e0;
  64         struct ramfuc_reg r_0x111100;
  65         struct ramfuc_reg r_0x111104;
  66         struct ramfuc_reg r_0x611200;
  67         struct ramfuc_reg r_mr[4];
  68 };
  69
  70 struct nva3_ram {
  71         struct nouveau_ram base;
  72         struct nva3_ramfuc fuc;
  73 };
  74
  75 static int
  76 nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
  77 {
  78         struct nouveau_bios *bios = nouveau_bios(pfb);
  79         struct nva3_ram *ram = (void *)pfb->ram;
  80         struct nva3_ramfuc *fuc = &ram->fuc;
  81         struct nva3_clock_info mclk;
  82         u8  ver, cnt, len, strap;
  83         u32 data;
  84         struct {
  85                 u32 data;
  86                 u8  size;
  87         } rammap, ramcfg, timing;
  88         u32 r004018, r100760, ctrl;
  89         u32 unk714, unk718, unk71c;
  90         int ret;
  91
  92         /* lookup memory config data relevant to the target frequency */
  93         rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
  94                                      &cnt, &ramcfg.size);
  95         if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
  96                 nv_error(pfb, "invalid/missing rammap entry\n");
  97                 return -EINVAL;
  98         }
  99
 100         /* locate specific data set for the attached memory */
 101         strap = nvbios_ramcfg_index(nv_subdev(pfb));
 102         if (strap >= cnt) {
 103                 nv_error(pfb, "invalid ramcfg strap\n");
 104                 return -EINVAL;
 105         }
 106
 107         ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
 108         if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
 109                 nv_error(pfb, "invalid/missing ramcfg entry\n");
 110                 return -EINVAL;
 111         }
 112
 113         /* lookup memory timings, if bios says they're present */
 114         strap = nv_ro08(bios, ramcfg.data + 0x01);
 115         if (strap != 0xff) {
 116                 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
 117                                              &cnt, &len);
 118                 if (!timing.data || ver != 0x10 || timing.size < 0x19) {
 119                         nv_error(pfb, "invalid/missing timing entry\n");
 120                         return -EINVAL;
 121                 }
 122         } else {
 123                 timing.data = 0;
 124         }
 125
 126         ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
 127         if (ret < 0) {
 128                 nv_error(pfb, "failed mclk calculation\n");
 129                 return ret;
 130         }
 131
 132         ret = ram_init(fuc, pfb);
 133         if (ret)
 134                 return ret;
 135
 136         /* XXX: where the fuck does 750MHz come from? */
 137         if (freq <= 750000) {
 138                 r004018 = 0x10000000;
 139                 r100760 = 0x22222222;
 140         } else {
 141                 r004018 = 0x00000000;
 142                 r100760 = 0x00000000;
 143         }
 144
 145         ctrl = ram_rd32(fuc, 0x004000);
 146         if (ctrl & 0x00000008) {
 147                 if (mclk.pll) {
 148                         ram_mask(fuc, 0x004128, 0x00000101, 0x00000101);
 149                         ram_wr32(fuc, 0x004004, mclk.pll);
 150                         ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001));
 151                         ram_wr32(fuc, 0x004000, (ctrl &= 0xffffffef));
 152                         ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
 153                         ram_wr32(fuc, 0x004000, (ctrl |= 0x00000010));
 154                         ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
 155                         ram_wr32(fuc, 0x004000, (ctrl |= 0x00000004));
 156                 }
 157         } else {
 158                 u32 ssel = 0x00000101;
 159                 if (mclk.clk)
 160                         ssel |= mclk.clk;
 161                 else
 162                         ssel |= 0x00080000; /* 324MHz, shouldn't matter... */
 163                 ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
 164         }
 165
 166         if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
 167                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
 168         } else {
 169                 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
 170                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
 171         }
 172
 173         if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02))
 174                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
 175         ram_wr32(fuc, 0x611200, 0x00003300);
 176         if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10))
 177                 ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
 178
 179         ram_wr32(fuc, 0x1002d4, 0x00000001);
 180         ram_wr32(fuc, 0x1002d0, 0x00000001);
 181         ram_wr32(fuc, 0x1002d0, 0x00000001);
 182         ram_wr32(fuc, 0x100210, 0x00000000);
 183         ram_wr32(fuc, 0x1002dc, 0x00000001);
 184         ram_nsec(fuc, 2000);
 185
 186         ctrl = ram_rd32(fuc, 0x004000);
 187         if (!(ctrl & 0x00000008) && mclk.pll) {
 188                 ram_wr32(fuc, 0x004000, (ctrl |=  0x00000008));
 189                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 190                 ram_wr32(fuc, 0x004018, 0x00001000);
 191                 ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000001));
 192                 ram_wr32(fuc, 0x004004, mclk.pll);
 193                 ram_wr32(fuc, 0x004000, (ctrl |=  0x00000001));
 194                 udelay(64);
 195                 ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
 196                 udelay(20);
 197         } else
 198         if (!mclk.pll) {
 199                 ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk);
 200                 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008));
 201                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 202                 ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
 203         }
 204
 205         if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) {
 206                 u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) |
 207                               nv_ro08(bios, ramcfg.data + 0x05);
 208                 u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07));
 209                 u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 |
 210                              (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 |
 211                              (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) |
 212                              0x80000000;
 213                 ram_wr32(fuc, 0x1005a0, unk5a0);
 214                 ram_wr32(fuc, 0x1005a4, unk5a4);
 215                 ram_wr32(fuc, 0x10f804, unk804);
 216                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
 217         } else {
 218                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
 219                 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
 220                 ram_mask(fuc, 0x100760, 0x22222222, r100760);
 221                 ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
 222                 ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
 223         }
 224
 225         if (mclk.pll) {
 226                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
 227                 ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000008));
 228         }
 229
 230         /*XXX: LEAVE */
 231         ram_wr32(fuc, 0x1002dc, 0x00000000);
 232         ram_wr32(fuc, 0x1002d4, 0x00000001);
 233         ram_wr32(fuc, 0x100210, 0x80000000);
 234         ram_nsec(fuc, 1000);
 235         ram_nsec(fuc, 1000);
 236
 237         ram_mask(fuc, mr[2], 0x00000000, 0x00000000);
 238         ram_nsec(fuc, 1000);
 239         ram_nuke(fuc, mr[0]);
 240         ram_mask(fuc, mr[0], 0x00000000, 0x00000000);
 241         ram_nsec(fuc, 1000);
 242
 243         ram_mask(fuc, 0x100220[3], 0x00000000, 0x00000000);
 244         ram_mask(fuc, 0x100220[1], 0x00000000, 0x00000000);
 245         ram_mask(fuc, 0x100220[6], 0x00000000, 0x00000000);
 246         ram_mask(fuc, 0x100220[7], 0x00000000, 0x00000000);
 247         ram_mask(fuc, 0x100220[2], 0x00000000, 0x00000000);
 248         ram_mask(fuc, 0x100220[4], 0x00000000, 0x00000000);
 249         ram_mask(fuc, 0x100220[5], 0x00000000, 0x00000000);
 250         ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
 251         ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
 252
 253         data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000;
 254         ram_mask(fuc, 0x100200, 0x00001000, data);
 255
 256         unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
 257         unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
 258         unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
 259         if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20))
 260                 unk714 |= 0xf0000000;
 261         if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04))
 262                 unk714 |= 0x00000010;
 263         ram_wr32(fuc, 0x100714, unk714);
 264
 265         if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01)
 266                 unk71c |= 0x00000100;
 267         ram_wr32(fuc, 0x10071c, unk71c);
 268
 269         if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02)
 270                 unk718 |= 0x00000100;
 271         ram_wr32(fuc, 0x100718, unk718);
 272
 273         if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)
 274                 ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
 275
 276         ram_mask(fuc, mr[0], 0x100, 0x100);
 277         ram_nsec(fuc, 1000);
 278         ram_mask(fuc, mr[0], 0x100, 0x000);
 279         ram_nsec(fuc, 1000);
 280
 281         ram_nsec(fuc, 2000);
 282         ram_nsec(fuc, 12000);
 283
 284         ram_wr32(fuc, 0x611200, 0x00003330);
 285         if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02))
 286                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
 287         if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
 288                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
 289                 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
 290         } else {
 291                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
 292         }
 293
 294         if (mclk.pll) {
 295                 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
 296                 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
 297         } else {
 298                 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
 299                 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
 300                 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int
 307 nva3_ram_prog(struct nouveau_fb *pfb)
 308 {
 309         struct nouveau_device *device = nv_device(pfb);
 310         struct nva3_ram *ram = (void *)pfb->ram;
 311         struct nva3_ramfuc *fuc = &ram->fuc;
 312         ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
 313         return 0;
 314 }
 315
 316 static void
 317 nva3_ram_tidy(struct nouveau_fb *pfb)
 318 {
 319         struct nva3_ram *ram = (void *)pfb->ram;
 320         struct nva3_ramfuc *fuc = &ram->fuc;
 321         ram_exec(fuc, false);
 322 }
 323
 324 static int
 325 nva3_ram_init(struct nouveau_object *object)
 326 {
 327         struct nouveau_fb *pfb = (void *)object->parent;
 328         struct nva3_ram   *ram = (void *)object;
 329         int ret, i;
 330
 331         ret = nouveau_ram_init(&ram->base);
 332         if (ret)
 333                 return ret;
 334
 335         /* prepare for ddr link training, and load training patterns */
 336         switch (ram->base.type) {
 337         case NV_MEM_TYPE_DDR3: {
 338                 if (nv_device(pfb)->chipset == 0xa8) {
 339                         static const u32 pattern[16] = {
 340                                 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
 341                                 0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
 342                                 0x33333333, 0x55555555, 0x77777777, 0x66666666,
 343                                 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
 344                         };
 345
 346                         nv_wr32(pfb, 0x100538, 0x10001ff6); /*XXX*/
 347                         nv_wr32(pfb, 0x1005a8, 0x0000ffff);
 348                         nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001);
 349                         for (i = 0; i < 0x30; i++) {
 350                                 nv_wr32(pfb, 0x10f8c0, (i << 8) | i);
 351                                 nv_wr32(pfb, 0x10f8e0, (i << 8) | i);
 352                                 nv_wr32(pfb, 0x10f900, pattern[i % 16]);
 353                                 nv_wr32(pfb, 0x10f920, pattern[i % 16]);
 354                         }
 355                 }
 356         }
 357                 break;
 358         default:
 359                 break;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static int
 366 nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 367               struct nouveau_oclass *oclass, void *data, u32 datasize,
 368               struct nouveau_object **pobject)
 369 {
 370         struct nva3_ram *ram;
 371         int ret, i;
 372
 373         ret = nv50_ram_create(parent, engine, oclass, &ram);
 374         *pobject = nv_object(ram);
 375         if (ret)
 376                 return ret;
 377
 378         switch (ram->base.type) {
 379         case NV_MEM_TYPE_DDR3:
 380                 ram->base.calc = nva3_ram_calc;
 381                 ram->base.prog = nva3_ram_prog;
 382                 ram->base.tidy = nva3_ram_tidy;
 383                 break;
 384         default:
 385                 nv_warn(ram, "reclocking of this ram type unsupported\n");
 386                 return 0;
 387         }
 388
 389         ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
 390         ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
 391         ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
 392         ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
 393         ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
 394         ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
 395         ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
 396         for (i = 0; i < 9; i++)
 397                 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
 398         ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
 399         ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
 400         ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
 401         ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
 402         ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
 403         ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
 404         ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
 405         ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
 406         ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
 407         ram->fuc.r_0x100760 = ramfuc_reg(0x100760);
 408         ram->fuc.r_0x1007a0 = ramfuc_reg(0x1007a0);
 409         ram->fuc.r_0x1007e0 = ramfuc_reg(0x1007e0);
 410         ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
 411         ram->fuc.r_0x1110e0 = ramfuc_reg(0x1110e0);
 412         ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
 413         ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
 414         ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
 415
 416         if (ram->base.ranks > 1) {
 417                 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
 418                 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
 419                 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
 420                 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
 421         } else {
 422                 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
 423                 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
 424                 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
 425                 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
 426         }
 427
 428         return 0;
 429 }
 430
 431 struct nouveau_oclass
 432 nva3_ram_oclass = {
 433         .ofuncs = &(struct nouveau_ofuncs) {
 434                 .ctor = nva3_ram_ctor,
 435                 .dtor = _nouveau_ram_dtor,
 436                 .init = nva3_ram_init,
 437                 .fini = _nouveau_ram_fini,
 438         },
 439 };