drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/bios.h>
  26 #include <subdev/bios/bit.h>
  27 #include <subdev/bios/pll.h>
  28 #include <subdev/bios/rammap.h>
  29 #include <subdev/bios/timing.h>
  30
  31 #include <subdev/clock/nva3.h>
  32 #include <subdev/clock/pll.h>
  33
  34 #include <core/option.h>
  35
  36 #include "ramfuc.h"
  37
  38 #include "nv50.h"
  39
  40 struct nva3_ramfuc {
  41         struct ramfuc base;
  42         struct ramfuc_reg r_0x004000;
  43         struct ramfuc_reg r_0x004004;
  44         struct ramfuc_reg r_0x004018;
  45         struct ramfuc_reg r_0x004128;
  46         struct ramfuc_reg r_0x004168;
  47         struct ramfuc_reg r_0x100200;
  48         struct ramfuc_reg r_0x100210;
  49         struct ramfuc_reg r_0x100220[9];
  50         struct ramfuc_reg r_0x1002d0;
  51         struct ramfuc_reg r_0x1002d4;
  52         struct ramfuc_reg r_0x1002dc;
  53         struct ramfuc_reg r_0x10053c;
  54         struct ramfuc_reg r_0x1005a0;
  55         struct ramfuc_reg r_0x1005a4;
  56         struct ramfuc_reg r_0x100714;
  57         struct ramfuc_reg r_0x100718;
  58         struct ramfuc_reg r_0x10071c;
  59         struct ramfuc_reg r_0x100760;
  60         struct ramfuc_reg r_0x1007a0;
  61         struct ramfuc_reg r_0x1007e0;
  62         struct ramfuc_reg r_0x10f804;
  63         struct ramfuc_reg r_0x1110e0;
  64         struct ramfuc_reg r_0x111100;
  65         struct ramfuc_reg r_0x111104;
  66         struct ramfuc_reg r_0x611200;
  67         struct ramfuc_reg r_mr[4];
  68 };
  69
  70 struct nva3_ram {
  71         struct nouveau_ram base;
  72         struct nva3_ramfuc fuc;
  73 };
  74
  75 static int
  76 nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
  77 {
  78         struct nouveau_bios *bios = nouveau_bios(pfb);
  79         struct nva3_ram *ram = (void *)pfb->ram;
  80         struct nva3_ramfuc *fuc = &ram->fuc;
  81         struct nva3_clock_info mclk;
  82         struct bit_entry M;
  83         u8  ver, cnt, strap;
  84         u32 data;
  85         struct {
  86                 u32 data;
  87                 u8  size;
  88         } rammap, ramcfg, timing;
  89         u32 r004018, r100760, ctrl;
  90         u32 unk714, unk718, unk71c;
  91         int ret;
  92
  93         /* lookup memory config data relevant to the target frequency */
  94         rammap.data = nvbios_rammap_match(bios, freq / 1000, &ver, &rammap.size,
  95                                          &cnt, &ramcfg.size);
  96         if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
  97                 nv_error(pfb, "invalid/missing rammap entry\n");
  98                 return -EINVAL;
  99         }
 100
 101         /* locate specific data set for the attached memory */
 102         if (bit_entry(bios, 'M', &M) || M.version != 2 || M.length < 3) {
 103                 nv_error(pfb, "invalid/missing memory table\n");
 104                 return -EINVAL;
 105         }
 106
 107         strap = (nv_rd32(pfb, 0x101000) & 0x0000003c) >> 2;
 108         data = nv_ro16(bios, M.offset + 1);
 109         if (data)
 110                 strap = nv_ro08(bios, data + strap);
 111
 112         if (strap >= cnt) {
 113                 nv_error(pfb, "invalid ramcfg strap\n");
 114                 return -EINVAL;
 115         }
 116
 117         ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
 118         if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
 119                 nv_error(pfb, "invalid/missing ramcfg entry\n");
 120                 return -EINVAL;
 121         }
 122
 123         /* lookup memory timings, if bios says they're present */
 124         strap = nv_ro08(bios, ramcfg.data + 0x01);
 125         if (strap != 0xff) {
 126                 timing.data = nvbios_timing_entry(bios, strap, &ver,
 127                                                  &timing.size);
 128                 if (!timing.data || ver != 0x10 || timing.size < 0x19) {
 129                         nv_error(pfb, "invalid/missing timing entry\n");
 130                         return -EINVAL;
 131                 }
 132         } else {
 133                 timing.data = 0;
 134         }
 135
 136         ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
 137         if (ret < 0) {
 138                 nv_error(pfb, "failed mclk calculation\n");
 139                 return ret;
 140         }
 141
 142         ret = ram_init(fuc, pfb);
 143         if (ret)
 144                 return ret;
 145
 146         /* XXX: where the fuck does 750MHz come from? */
 147         if (freq <= 750000) {
 148                 r004018 = 0x10000000;
 149                 r100760 = 0x22222222;
 150         } else {
 151                 r004018 = 0x00000000;
 152                 r100760 = 0x00000000;
 153         }
 154
 155         ctrl = ram_rd32(fuc, 0x004000);
 156         if (ctrl & 0x00000008) {
 157                 if (mclk.pll) {
 158                         ram_mask(fuc, 0x004128, 0x00000101, 0x00000101);
 159                         ram_wr32(fuc, 0x004004, mclk.pll);
 160                         ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001));
 161                         ram_wr32(fuc, 0x004000, (ctrl &= 0xffffffef));
 162                         ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
 163                         ram_wr32(fuc, 0x004000, (ctrl |= 0x00000010));
 164                         ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
 165                         ram_wr32(fuc, 0x004000, (ctrl |= 0x00000004));
 166                 }
 167         } else {
 168                 u32 ssel = 0x00000101;
 169                 if (mclk.clk)
 170                         ssel |= mclk.clk;
 171                 else
 172                         ssel |= 0x00080000; /* 324MHz, shouldn't matter... */
 173                 ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
 174         }
 175
 176         if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
 177                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
 178         } else {
 179                 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
 180                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
 181         }
 182
 183         if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02))
 184                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
 185         ram_wr32(fuc, 0x611200, 0x00003300);
 186         if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10))
 187                 ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
 188
 189         ram_wr32(fuc, 0x1002d4, 0x00000001);
 190         ram_wr32(fuc, 0x1002d0, 0x00000001);
 191         ram_wr32(fuc, 0x1002d0, 0x00000001);
 192         ram_wr32(fuc, 0x100210, 0x00000000);
 193         ram_wr32(fuc, 0x1002dc, 0x00000001);
 194         ram_nsec(fuc, 2000);
 195
 196         ctrl = ram_rd32(fuc, 0x004000);
 197         if (!(ctrl & 0x00000008) && mclk.pll) {
 198                 ram_wr32(fuc, 0x004000, (ctrl |=  0x00000008));
 199                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 200                 ram_wr32(fuc, 0x004018, 0x00001000);
 201                 ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000001));
 202                 ram_wr32(fuc, 0x004004, mclk.pll);
 203                 ram_wr32(fuc, 0x004000, (ctrl |=  0x00000001));
 204                 udelay(64);
 205                 ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
 206                 udelay(20);
 207         } else
 208         if (!mclk.pll) {
 209                 ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk);
 210                 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008));
 211                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 212                 ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
 213         }
 214
 215         if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) {
 216                 u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) |
 217                               nv_ro08(bios, ramcfg.data + 0x05);
 218                 u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07));
 219                 u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 |
 220                              (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 |
 221                              (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) |
 222                              0x80000000;
 223                 ram_wr32(fuc, 0x1005a0, unk5a0);
 224                 ram_wr32(fuc, 0x1005a4, unk5a4);
 225                 ram_wr32(fuc, 0x10f804, unk804);
 226                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
 227         } else {
 228                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
 229                 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
 230                 ram_mask(fuc, 0x100760, 0x22222222, r100760);
 231                 ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
 232                 ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
 233         }
 234
 235         if (mclk.pll) {
 236                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
 237                 ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000008));
 238         }
 239
 240         /*XXX: LEAVE */
 241         ram_wr32(fuc, 0x1002dc, 0x00000000);
 242         ram_wr32(fuc, 0x1002d4, 0x00000001);
 243         ram_wr32(fuc, 0x100210, 0x80000000);
 244         ram_nsec(fuc, 1000);
 245         ram_nsec(fuc, 1000);
 246
 247         ram_mask(fuc, mr[2], 0x00000000, 0x00000000);
 248         ram_nsec(fuc, 1000);
 249         ram_nuke(fuc, mr[0]);
 250         ram_mask(fuc, mr[0], 0x00000000, 0x00000000);
 251         ram_nsec(fuc, 1000);
 252
 253         ram_mask(fuc, 0x100220[3], 0x00000000, 0x00000000);
 254         ram_mask(fuc, 0x100220[1], 0x00000000, 0x00000000);
 255         ram_mask(fuc, 0x100220[6], 0x00000000, 0x00000000);
 256         ram_mask(fuc, 0x100220[7], 0x00000000, 0x00000000);
 257         ram_mask(fuc, 0x100220[2], 0x00000000, 0x00000000);
 258         ram_mask(fuc, 0x100220[4], 0x00000000, 0x00000000);
 259         ram_mask(fuc, 0x100220[5], 0x00000000, 0x00000000);
 260         ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
 261         ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
 262
 263         data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000;
 264         ram_mask(fuc, 0x100200, 0x00001000, data);
 265
 266         unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
 267         unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
 268         unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
 269         if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20))
 270                 unk714 |= 0xf0000000;
 271         if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04))
 272                 unk714 |= 0x00000010;
 273         ram_wr32(fuc, 0x100714, unk714);
 274
 275         if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01)
 276                 unk71c |= 0x00000100;
 277         ram_wr32(fuc, 0x10071c, unk71c);
 278
 279         if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02)
 280                 unk718 |= 0x00000100;
 281         ram_wr32(fuc, 0x100718, unk718);
 282
 283         if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)
 284                 ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
 285
 286         ram_mask(fuc, mr[0], 0x100, 0x100);
 287         ram_nsec(fuc, 1000);
 288         ram_mask(fuc, mr[0], 0x100, 0x000);
 289         ram_nsec(fuc, 1000);
 290
 291         ram_nsec(fuc, 2000);
 292         ram_nsec(fuc, 12000);
 293
 294         ram_wr32(fuc, 0x611200, 0x00003330);
 295         if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02))
 296                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
 297         if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
 298                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
 299                 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
 300         } else {
 301                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
 302         }
 303
 304         if (mclk.pll) {
 305                 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
 306                 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
 307         } else {
 308                 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
 309                 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
 310                 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int
 317 nva3_ram_prog(struct nouveau_fb *pfb)
 318 {
 319         struct nouveau_device *device = nv_device(pfb);
 320         struct nva3_ram *ram = (void *)pfb->ram;
 321         struct nva3_ramfuc *fuc = &ram->fuc;
 322         ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
 323         return 0;
 324 }
 325
 326 static void
 327 nva3_ram_tidy(struct nouveau_fb *pfb)
 328 {
 329         struct nva3_ram *ram = (void *)pfb->ram;
 330         struct nva3_ramfuc *fuc = &ram->fuc;
 331         ram_exec(fuc, false);
 332 }
 333
 334 static int
 335 nva3_ram_init(struct nouveau_object *object)
 336 {
 337         struct nouveau_fb *pfb = (void *)object->parent;
 338         struct nva3_ram   *ram = (void *)object;
 339         int ret, i;
 340
 341         ret = nouveau_ram_init(&ram->base);
 342         if (ret)
 343                 return ret;
 344
 345         /* prepare for ddr link training, and load training patterns */
 346         switch (ram->base.type) {
 347         case NV_MEM_TYPE_DDR3: {
 348                 static const u32 pattern[16] = {
 349                         0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
 350                         0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
 351                         0x33333333, 0x55555555, 0x77777777, 0x66666666,
 352                         0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
 353                 };
 354
 355                 nv_wr32(pfb, 0x100538, 0x10001ff6); /*XXX*/
 356                 nv_wr32(pfb, 0x1005a8, 0x0000ffff);
 357                 nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001);
 358                 for (i = 0; i < 0x30; i++) {
 359                         nv_wr32(pfb, 0x10f8c0, (i << 8) | i);
 360                         nv_wr32(pfb, 0x10f8e0, (i << 8) | i);
 361                         nv_wr32(pfb, 0x10f900, pattern[i % 16]);
 362                         nv_wr32(pfb, 0x10f920, pattern[i % 16]);
 363                 }
 364         }
 365                 break;
 366         default:
 367                 break;
 368         }
 369
 370         return 0;
 371 }
 372
 373 static int
 374 nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 375               struct nouveau_oclass *oclass, void *data, u32 datasize,
 376               struct nouveau_object **pobject)
 377 {
 378         struct nva3_ram *ram;
 379         int ret, i;
 380
 381         ret = nv50_ram_create(parent, engine, oclass, &ram);
 382         *pobject = nv_object(ram);
 383         if (ret)
 384                 return ret;
 385
 386         switch (ram->base.type) {
 387         case NV_MEM_TYPE_DDR3:
 388                 ram->base.calc = nva3_ram_calc;
 389                 ram->base.prog = nva3_ram_prog;
 390                 ram->base.tidy = nva3_ram_tidy;
 391                 break;
 392         default:
 393                 nv_warn(ram, "reclocking of this ram type unsupported\n");
 394                 return 0;
 395         }
 396
 397         ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
 398         ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
 399         ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
 400         ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
 401         ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
 402         ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
 403         ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
 404         for (i = 0; i < 9; i++)
 405                 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
 406         ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
 407         ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
 408         ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
 409         ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
 410         ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
 411         ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
 412         ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
 413         ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
 414         ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
 415         ram->fuc.r_0x100760 = ramfuc_reg(0x100760);
 416         ram->fuc.r_0x1007a0 = ramfuc_reg(0x1007a0);
 417         ram->fuc.r_0x1007e0 = ramfuc_reg(0x1007e0);
 418         ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
 419         ram->fuc.r_0x1110e0 = ramfuc_reg(0x1110e0);
 420         ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
 421         ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
 422         ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
 423
 424         if (ram->base.ranks > 1) {
 425                 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
 426                 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
 427                 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
 428                 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
 429         } else {
 430                 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
 431                 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
 432                 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
 433                 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
 434         }
 435
 436         return 0;
 437 }
 438
 439 struct nouveau_oclass
 440 nva3_ram_oclass = {
 441         .ofuncs = &(struct nouveau_ofuncs) {
 442                 .ctor = nva3_ram_ctor,
 443                 .dtor = _nouveau_ram_dtor,
 444                 .init = nva3_ram_init,
 445                 .fini = _nouveau_ram_fini,
 446         },
 447 };