drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/mc.h>
  26
  27 struct nv44_mc_priv {
  28         struct nouveau_mc base;
  29 };
  30
  31 static int
  32 nv44_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  33              struct nouveau_oclass *oclass, void *data, u32 size,
  34              struct nouveau_object **pobject)
  35 {
  36         struct nv44_mc_priv *priv;
  37         int ret;
  38
  39         ret = nouveau_mc_create(parent, engine, oclass, nv04_mc_intr, &priv);
  40         *pobject = nv_object(priv);
  41         if (ret)
  42                 return ret;
  43
  44         return 0;
  45 }
  46
  47 static int
  48 nv44_mc_init(struct nouveau_object *object)
  49 {
  50         struct nv44_mc_priv *priv = (void *)object;
  51         u32 tmp = nv_rd32(priv, 0x10020c);
  52
  53         nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
  54
  55         nv_wr32(priv, 0x001700, tmp);
  56         nv_wr32(priv, 0x001704, 0);
  57         nv_wr32(priv, 0x001708, 0);
  58         nv_wr32(priv, 0x00170c, tmp);
  59
  60         return nouveau_mc_init(&priv->base);
  61 }
  62
  63 struct nouveau_oclass
  64 nv44_mc_oclass = {
  65         .handle = NV_SUBDEV(MC, 0x44),
  66         .ofuncs = &(struct nouveau_ofuncs) {
  67                 .ctor = nv44_mc_ctor,
  68                 .dtor = _nouveau_mc_dtor,
  69                 .init = nv44_mc_init,
  70                 .fini = _nouveau_mc_fini,
  71         },
  72 };