drivers/gpu/drm/nouveau/include/nvif/class.h

   1 #ifndef __NVIF_CLASS_H__
   2 #define __NVIF_CLASS_H__
   3
   4 /*******************************************************************************
   5  * class identifiers
   6  ******************************************************************************/
   7
   8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
   9 #define NV_DEVICE                                                    0x00000080
  10
  11 #define NV_DMA_FROM_MEMORY                                           0x00000002
  12 #define NV_DMA_TO_MEMORY                                             0x00000003
  13 #define NV_DMA_IN_MEMORY                                             0x0000003d
  14
  15 #define NV04_DISP                                                    0x00000046
  16
  17 #define NV03_CHANNEL_DMA                                             0x0000006b
  18 #define NV10_CHANNEL_DMA                                             0x0000006e
  19 #define NV17_CHANNEL_DMA                                             0x0000176e
  20 #define NV40_CHANNEL_DMA                                             0x0000406e
  21 #define NV50_CHANNEL_DMA                                             0x0000506e
  22 #define G82_CHANNEL_DMA                                              0x0000826e
  23
  24 #define NV50_CHANNEL_GPFIFO                                          0x0000506f
  25 #define G82_CHANNEL_GPFIFO                                           0x0000826f
  26 #define FERMI_CHANNEL_GPFIFO                                         0x0000906f
  27 #define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
  28
  29 #define NV50_DISP                                                    0x00005070
  30 #define G82_DISP                                                     0x00008270
  31 #define GT200_DISP                                                   0x00008370
  32 #define GT214_DISP                                                   0x00008570
  33 #define GT206_DISP                                                   0x00008870
  34 #define GF110_DISP                                                   0x00009070
  35 #define GK104_DISP                                                   0x00009170
  36 #define GK110_DISP                                                   0x00009270
  37 #define GM107_DISP                                                   0x00009470
  38 #define GM204_DISP                                                   0x00009570
  39
  40 #define NV50_DISP_CURSOR                                             0x0000507a
  41 #define G82_DISP_CURSOR                                              0x0000827a
  42 #define GT214_DISP_CURSOR                                            0x0000857a
  43 #define GF110_DISP_CURSOR                                            0x0000907a
  44 #define GK104_DISP_CURSOR                                            0x0000917a
  45
  46 #define NV50_DISP_OVERLAY                                            0x0000507b
  47 #define G82_DISP_OVERLAY                                             0x0000827b
  48 #define GT214_DISP_OVERLAY                                           0x0000857b
  49 #define GF110_DISP_OVERLAY                                           0x0000907b
  50 #define GK104_DISP_OVERLAY                                           0x0000917b
  51
  52 #define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
  53 #define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
  54 #define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
  55 #define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
  56 #define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
  57 #define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
  58 #define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c
  59
  60 #define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
  61 #define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
  62 #define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
  63 #define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
  64 #define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
  65 #define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
  66 #define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
  67 #define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
  68 #define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
  69 #define GM204_DISP_CORE_CHANNEL_DMA                                  0x0000957d
  70
  71 #define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
  72 #define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
  73 #define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
  74 #define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
  75 #define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
  76 #define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e
  77
  78 #define FERMI_A                                                      0x00009097
  79 #define FERMI_B                                                      0x00009197
  80 #define FERMI_C                                                      0x00009297
  81
  82 #define KEPLER_A                                                     0x0000a097
  83 #define KEPLER_B                                                     0x0000a197
  84 #define KEPLER_C                                                     0x0000a297
  85
  86 #define MAXWELL_A                                                    0x0000b097
  87
  88 #define FERMI_COMPUTE_A                                              0x000090c0
  89 #define FERMI_COMPUTE_B                                              0x000091c0
  90
  91 #define KEPLER_COMPUTE_A                                             0x0000a0c0
  92 #define KEPLER_COMPUTE_B                                             0x0000a1c0
  93
  94 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
  95
  96
  97 /*******************************************************************************
  98  * client
  99  ******************************************************************************/
 100
 101 #define NV_CLIENT_DEVLIST                                                  0x00
 102
 103 struct nv_client_devlist_v0 {
 104         __u8  version;
 105         __u8  count;
 106         __u8  pad02[6];
 107         __u64 device[];
 108 };
 109
 110
 111 /*******************************************************************************
 112  * device
 113  ******************************************************************************/
 114
 115 struct nv_device_v0 {
 116         __u8  version;
 117         __u8  pad01[7];
 118         __u64 device;   /* device identifier, ~0 for client default */
 119 #define NV_DEVICE_V0_DISABLE_IDENTIFY                     0x0000000000000001ULL
 120 #define NV_DEVICE_V0_DISABLE_MMIO                         0x0000000000000002ULL
 121 #define NV_DEVICE_V0_DISABLE_VBIOS                        0x0000000000000004ULL
 122 #define NV_DEVICE_V0_DISABLE_CORE                         0x0000000000000008ULL
 123 #define NV_DEVICE_V0_DISABLE_DISP                         0x0000000000010000ULL
 124 #define NV_DEVICE_V0_DISABLE_FIFO                         0x0000000000020000ULL
 125 #define NV_DEVICE_V0_DISABLE_GR                           0x0000000100000000ULL
 126 #define NV_DEVICE_V0_DISABLE_MPEG                         0x0000000200000000ULL
 127 #define NV_DEVICE_V0_DISABLE_ME                           0x0000000400000000ULL
 128 #define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL
 129 #define NV_DEVICE_V0_DISABLE_CIPHER                       0x0000001000000000ULL
 130 #define NV_DEVICE_V0_DISABLE_BSP                          0x0000002000000000ULL
 131 #define NV_DEVICE_V0_DISABLE_MSPPP                        0x0000004000000000ULL
 132 #define NV_DEVICE_V0_DISABLE_CE0                          0x0000008000000000ULL
 133 #define NV_DEVICE_V0_DISABLE_CE1                          0x0000010000000000ULL
 134 #define NV_DEVICE_V0_DISABLE_VIC                          0x0000020000000000ULL
 135 #define NV_DEVICE_V0_DISABLE_VENC                         0x0000040000000000ULL
 136 #define NV_DEVICE_V0_DISABLE_CE2                          0x0000080000000000ULL
 137 #define NV_DEVICE_V0_DISABLE_MSVLD                        0x0000100000000000ULL
 138 #define NV_DEVICE_V0_DISABLE_SEC                          0x0000200000000000ULL
 139         __u64 disable;  /* disable particular subsystems */
 140         __u64 debug0;   /* as above, but *internal* ids, and *NOT* ABI */
 141 };
 142
 143 #define NV_DEVICE_V0_INFO                                                  0x00
 144
 145 struct nv_device_info_v0 {
 146         __u8  version;
 147 #define NV_DEVICE_INFO_V0_IGP                                              0x00
 148 #define NV_DEVICE_INFO_V0_PCI                                              0x01
 149 #define NV_DEVICE_INFO_V0_AGP                                              0x02
 150 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
 151 #define NV_DEVICE_INFO_V0_SOC                                              0x04
 152         __u8  platform;
 153         __u16 chipset;  /* from NV_PMC_BOOT_0 */
 154         __u8  revision; /* from NV_PMC_BOOT_0 */
 155 #define NV_DEVICE_INFO_V0_TNT                                              0x01
 156 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
 157 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
 158 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
 159 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
 160 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
 161 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
 162 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
 163 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
 164         __u8  family;
 165         __u8  pad06[2];
 166         __u64 ram_size;
 167         __u64 ram_user;
 168 };
 169
 170
 171 /*******************************************************************************
 172  * context dma
 173  ******************************************************************************/
 174
 175 struct nv_dma_v0 {
 176         __u8  version;
 177 #define NV_DMA_V0_TARGET_VM                                                0x00
 178 #define NV_DMA_V0_TARGET_VRAM                                              0x01
 179 #define NV_DMA_V0_TARGET_PCI                                               0x02
 180 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
 181 #define NV_DMA_V0_TARGET_AGP                                               0x04
 182         __u8  target;
 183 #define NV_DMA_V0_ACCESS_VM                                                0x00
 184 #define NV_DMA_V0_ACCESS_RD                                                0x01
 185 #define NV_DMA_V0_ACCESS_WR                                                0x02
 186 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
 187         __u8  access;
 188         __u8  pad03[5];
 189         __u64 start;
 190         __u64 limit;
 191         /* ... chipset-specific class data */
 192 };
 193
 194 struct nv50_dma_v0 {
 195         __u8  version;
 196 #define NV50_DMA_V0_PRIV_VM                                                0x00
 197 #define NV50_DMA_V0_PRIV_US                                                0x01
 198 #define NV50_DMA_V0_PRIV__S                                                0x02
 199         __u8  priv;
 200 #define NV50_DMA_V0_PART_VM                                                0x00
 201 #define NV50_DMA_V0_PART_256                                               0x01
 202 #define NV50_DMA_V0_PART_1KB                                               0x02
 203         __u8  part;
 204 #define NV50_DMA_V0_COMP_NONE                                              0x00
 205 #define NV50_DMA_V0_COMP_1                                                 0x01
 206 #define NV50_DMA_V0_COMP_2                                                 0x02
 207 #define NV50_DMA_V0_COMP_VM                                                0x03
 208         __u8  comp;
 209 #define NV50_DMA_V0_KIND_PITCH                                             0x00
 210 #define NV50_DMA_V0_KIND_VM                                                0x7f
 211         __u8  kind;
 212         __u8  pad05[3];
 213 };
 214
 215 struct gf100_dma_v0 {
 216         __u8  version;
 217 #define GF100_DMA_V0_PRIV_VM                                               0x00
 218 #define GF100_DMA_V0_PRIV_US                                               0x01
 219 #define GF100_DMA_V0_PRIV__S                                               0x02
 220         __u8  priv;
 221 #define GF100_DMA_V0_KIND_PITCH                                            0x00
 222 #define GF100_DMA_V0_KIND_VM                                               0xff
 223         __u8  kind;
 224         __u8  pad03[5];
 225 };
 226
 227 struct gf110_dma_v0 {
 228         __u8  version;
 229 #define GF110_DMA_V0_PAGE_LP                                               0x00
 230 #define GF110_DMA_V0_PAGE_SP                                               0x01
 231         __u8  page;
 232 #define GF110_DMA_V0_KIND_PITCH                                            0x00
 233 #define GF110_DMA_V0_KIND_VM                                               0xff
 234         __u8  kind;
 235         __u8  pad03[5];
 236 };
 237
 238
 239 /*******************************************************************************
 240  * perfmon
 241  ******************************************************************************/
 242
 243 struct nvif_perfctr_v0 {
 244         __u8  version;
 245         __u8  pad01[1];
 246         __u16 logic_op;
 247         __u8  pad04[4];
 248         char  name[4][64];
 249 };
 250
 251 #define NVIF_PERFCTR_V0_QUERY                                              0x00
 252 #define NVIF_PERFCTR_V0_SAMPLE                                             0x01
 253 #define NVIF_PERFCTR_V0_READ                                               0x02
 254
 255 struct nvif_perfctr_query_v0 {
 256         __u8  version;
 257         __u8  pad01[3];
 258         __u32 iter;
 259         char  name[64];
 260 };
 261
 262 struct nvif_perfctr_sample {
 263 };
 264
 265 struct nvif_perfctr_read_v0 {
 266         __u8  version;
 267         __u8  pad01[7];
 268         __u32 ctr;
 269         __u32 clk;
 270 };
 271
 272
 273 /*******************************************************************************
 274  * device control
 275  ******************************************************************************/
 276
 277 #define NVIF_CONTROL_PSTATE_INFO                                           0x00
 278 #define NVIF_CONTROL_PSTATE_ATTR                                           0x01
 279 #define NVIF_CONTROL_PSTATE_USER                                           0x02
 280
 281 struct nvif_control_pstate_info_v0 {
 282         __u8  version;
 283         __u8  count; /* out: number of power states */
 284 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
 285 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
 286         __s8  ustate_ac; /* out: target pstate index */
 287         __s8  ustate_dc; /* out: target pstate index */
 288         __s8  pwrsrc; /* out: current power source */
 289 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
 290 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
 291         __s8  pstate; /* out: current pstate index */
 292         __u8  pad06[2];
 293 };
 294
 295 struct nvif_control_pstate_attr_v0 {
 296         __u8  version;
 297 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
 298         __s8  state; /*  in: index of pstate to query
 299                       * out: pstate identifier
 300                       */
 301         __u8  index; /*  in: index of attribute to query
 302                       * out: index of next attribute, or 0 if no more
 303                       */
 304         __u8  pad03[5];
 305         __u32 min;
 306         __u32 max;
 307         char  name[32];
 308         char  unit[16];
 309 };
 310
 311 struct nvif_control_pstate_user_v0 {
 312         __u8  version;
 313 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
 314 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
 315         __s8  ustate; /*  in: pstate identifier */
 316         __s8  pwrsrc; /*  in: target power source */
 317         __u8  pad03[5];
 318 };
 319
 320
 321 /*******************************************************************************
 322  * DMA FIFO channels
 323  ******************************************************************************/
 324
 325 struct nv03_channel_dma_v0 {
 326         __u8  version;
 327         __u8  chid;
 328         __u8  pad02[2];
 329         __u32 pushbuf;
 330         __u64 offset;
 331 };
 332
 333 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00
 334
 335 /*******************************************************************************
 336  * GPFIFO channels
 337  ******************************************************************************/
 338
 339 struct nv50_channel_gpfifo_v0 {
 340         __u8  version;
 341         __u8  chid;
 342         __u8  pad01[6];
 343         __u32 pushbuf;
 344         __u32 ilength;
 345         __u64 ioffset;
 346 };
 347
 348 struct kepler_channel_gpfifo_a_v0 {
 349         __u8  version;
 350 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
 351 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP                               0x02
 352 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
 353 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
 354 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
 355 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
 356 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
 357         __u8  engine;
 358         __u16 chid;
 359         __u8  pad04[4];
 360         __u32 pushbuf;
 361         __u32 ilength;
 362         __u64 ioffset;
 363 };
 364
 365 /*******************************************************************************
 366  * legacy display
 367  ******************************************************************************/
 368
 369 #define NV04_DISP_NTFY_VBLANK                                              0x00
 370 #define NV04_DISP_NTFY_CONN                                                0x01
 371
 372 struct nv04_disp_mthd_v0 {
 373         __u8  version;
 374 #define NV04_DISP_SCANOUTPOS                                               0x00
 375         __u8  method;
 376         __u8  head;
 377         __u8  pad03[5];
 378 };
 379
 380 struct nv04_disp_scanoutpos_v0 {
 381         __u8  version;
 382         __u8  pad01[7];
 383         __s64 time[2];
 384         __u16 vblanks;
 385         __u16 vblanke;
 386         __u16 vtotal;
 387         __u16 vline;
 388         __u16 hblanks;
 389         __u16 hblanke;
 390         __u16 htotal;
 391         __u16 hline;
 392 };
 393
 394 /*******************************************************************************
 395  * display
 396  ******************************************************************************/
 397
 398 #define NV50_DISP_MTHD                                                     0x00
 399
 400 struct nv50_disp_mthd_v0 {
 401         __u8  version;
 402 #define NV50_DISP_SCANOUTPOS                                               0x00
 403         __u8  method;
 404         __u8  head;
 405         __u8  pad03[5];
 406 };
 407
 408 struct nv50_disp_mthd_v1 {
 409         __u8  version;
 410 #define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
 411 #define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
 412 #define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
 413 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
 414 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
 415 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
 416 #define NV50_DISP_MTHD_V1_SOR_DP_PWR                                       0x24
 417 #define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
 418         __u8  method;
 419         __u16 hasht;
 420         __u16 hashm;
 421         __u8  pad06[2];
 422 };
 423
 424 struct nv50_disp_dac_pwr_v0 {
 425         __u8  version;
 426         __u8  state;
 427         __u8  data;
 428         __u8  vsync;
 429         __u8  hsync;
 430         __u8  pad05[3];
 431 };
 432
 433 struct nv50_disp_dac_load_v0 {
 434         __u8  version;
 435         __u8  load;
 436         __u8  pad02[2];
 437         __u32 data;
 438 };
 439
 440 struct nv50_disp_sor_pwr_v0 {
 441         __u8  version;
 442         __u8  state;
 443         __u8  pad02[6];
 444 };
 445
 446 struct nv50_disp_sor_hda_eld_v0 {
 447         __u8  version;
 448         __u8  pad01[7];
 449         __u8  data[];
 450 };
 451
 452 struct nv50_disp_sor_hdmi_pwr_v0 {
 453         __u8  version;
 454         __u8  state;
 455         __u8  max_ac_packet;
 456         __u8  rekey;
 457         __u8  pad04[4];
 458 };
 459
 460 struct nv50_disp_sor_lvds_script_v0 {
 461         __u8  version;
 462         __u8  pad01[1];
 463         __u16 script;
 464         __u8  pad04[4];
 465 };
 466
 467 struct nv50_disp_sor_dp_pwr_v0 {
 468         __u8  version;
 469         __u8  state;
 470         __u8  pad02[6];
 471 };
 472
 473 struct nv50_disp_pior_pwr_v0 {
 474         __u8  version;
 475         __u8  state;
 476         __u8  type;
 477         __u8  pad03[5];
 478 };
 479
 480 /* core */
 481 struct nv50_disp_core_channel_dma_v0 {
 482         __u8  version;
 483         __u8  pad01[3];
 484         __u32 pushbuf;
 485 };
 486
 487 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
 488
 489 /* cursor immediate */
 490 struct nv50_disp_cursor_v0 {
 491         __u8  version;
 492         __u8  head;
 493         __u8  pad02[6];
 494 };
 495
 496 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00
 497
 498 /* base */
 499 struct nv50_disp_base_channel_dma_v0 {
 500         __u8  version;
 501         __u8  pad01[2];
 502         __u8  head;
 503         __u32 pushbuf;
 504 };
 505
 506 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
 507
 508 /* overlay */
 509 struct nv50_disp_overlay_channel_dma_v0 {
 510         __u8  version;
 511         __u8  pad01[2];
 512         __u8  head;
 513         __u32 pushbuf;
 514 };
 515
 516 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00
 517
 518 /* overlay immediate */
 519 struct nv50_disp_overlay_v0 {
 520         __u8  version;
 521         __u8  head;
 522         __u8  pad02[6];
 523 };
 524
 525 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
 526
 527 /*******************************************************************************
 528  * fermi
 529  ******************************************************************************/
 530
 531 #define FERMI_A_ZBC_COLOR                                                  0x00
 532 #define FERMI_A_ZBC_DEPTH                                                  0x01
 533
 534 struct fermi_a_zbc_color_v0 {
 535         __u8  version;
 536 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO                                      0x01
 537 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE                                 0x02
 538 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32                       0x04
 539 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16                           0x08
 540 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16                       0x0c
 541 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16                       0x10
 542 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16                       0x14
 543 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16                       0x16
 544 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8                                  0x18
 545 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8                               0x1c
 546 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10                               0x20
 547 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10                           0x24
 548 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8                                  0x28
 549 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8                               0x2c
 550 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8                              0x30
 551 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8                              0x34
 552 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8                              0x38
 553 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10                               0x3c
 554 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11                              0x40
 555         __u8  format;
 556         __u8  index;
 557         __u8  pad03[5];
 558         __u32 ds[4];
 559         __u32 l2[4];
 560 };
 561
 562 struct fermi_a_zbc_depth_v0 {
 563         __u8  version;
 564 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32                                      0x01
 565         __u8  format;
 566         __u8  index;
 567         __u8  pad03[5];
 568         __u32 ds;
 569         __u32 l2;
 570 };
 571
 572 #endif