drivers/gpu/drm/nouveau/include/nvif/class.h

   1 #ifndef __NVIF_CLASS_H__
   2 #define __NVIF_CLASS_H__
   3
   4 /*******************************************************************************
   5  * class identifiers
   6  ******************************************************************************/
   7
   8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
   9 #define NV_DEVICE                                                    0x00000080
  10
  11 #define NV_DMA_FROM_MEMORY                                           0x00000002
  12 #define NV_DMA_TO_MEMORY                                             0x00000003
  13 #define NV_DMA_IN_MEMORY                                             0x0000003d
  14
  15 #define FERMI_TWOD_A                                                 0x0000902d
  16
  17 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
  18
  19 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
  20 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
  21
  22 #define NV04_DISP                                                    0x00000046
  23
  24 #define NV03_CHANNEL_DMA                                             0x0000006b
  25 #define NV10_CHANNEL_DMA                                             0x0000006e
  26 #define NV17_CHANNEL_DMA                                             0x0000176e
  27 #define NV40_CHANNEL_DMA                                             0x0000406e
  28 #define NV50_CHANNEL_DMA                                             0x0000506e
  29 #define G82_CHANNEL_DMA                                              0x0000826e
  30
  31 #define NV50_CHANNEL_GPFIFO                                          0x0000506f
  32 #define G82_CHANNEL_GPFIFO                                           0x0000826f
  33 #define FERMI_CHANNEL_GPFIFO                                         0x0000906f
  34 #define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
  35 #define MAXWELL_CHANNEL_GPFIFO_A                                     0x0000b06f
  36
  37 #define NV50_DISP                                                    0x00005070
  38 #define G82_DISP                                                     0x00008270
  39 #define GT200_DISP                                                   0x00008370
  40 #define GT214_DISP                                                   0x00008570
  41 #define GT206_DISP                                                   0x00008870
  42 #define GF110_DISP                                                   0x00009070
  43 #define GK104_DISP                                                   0x00009170
  44 #define GK110_DISP                                                   0x00009270
  45 #define GM107_DISP                                                   0x00009470
  46 #define GM204_DISP                                                   0x00009570
  47
  48 #define NV74_VP2                                                     0x00007476
  49
  50 #define NV50_DISP_CURSOR                                             0x0000507a
  51 #define G82_DISP_CURSOR                                              0x0000827a
  52 #define GT214_DISP_CURSOR                                            0x0000857a
  53 #define GF110_DISP_CURSOR                                            0x0000907a
  54 #define GK104_DISP_CURSOR                                            0x0000917a
  55
  56 #define NV50_DISP_OVERLAY                                            0x0000507b
  57 #define G82_DISP_OVERLAY                                             0x0000827b
  58 #define GT214_DISP_OVERLAY                                           0x0000857b
  59 #define GF110_DISP_OVERLAY                                           0x0000907b
  60 #define GK104_DISP_OVERLAY                                           0x0000917b
  61
  62 #define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
  63 #define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
  64 #define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
  65 #define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
  66 #define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
  67 #define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
  68 #define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c
  69
  70 #define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
  71 #define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
  72 #define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
  73 #define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
  74 #define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
  75 #define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
  76 #define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
  77 #define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
  78 #define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
  79 #define GM204_DISP_CORE_CHANNEL_DMA                                  0x0000957d
  80
  81 #define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
  82 #define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
  83 #define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
  84 #define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
  85 #define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
  86 #define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e
  87
  88 #define FERMI_A                                                      0x00009097
  89 #define FERMI_B                                                      0x00009197
  90 #define FERMI_C                                                      0x00009297
  91
  92 #define KEPLER_A                                                     0x0000a097
  93 #define KEPLER_B                                                     0x0000a197
  94 #define KEPLER_C                                                     0x0000a297
  95
  96 #define MAXWELL_A                                                    0x0000b097
  97 #define MAXWELL_B                                                    0x0000b197
  98
  99 #define NV74_BSP                                                     0x000074b0
 100
 101 #define GT212_MSVLD                                                  0x000085b1
 102 #define IGT21A_MSVLD                                                 0x000086b1
 103 #define G98_MSVLD                                                    0x000088b1
 104 #define GF100_MSVLD                                                  0x000090b1
 105 #define GK104_MSVLD                                                  0x000095b1
 106
 107 #define GT212_MSPDEC                                                 0x000085b2
 108 #define G98_MSPDEC                                                   0x000088b2
 109 #define GF100_MSPDEC                                                 0x000090b2
 110 #define GK104_MSPDEC                                                 0x000095b2
 111
 112 #define GT212_MSPPP                                                  0x000085b3
 113 #define G98_MSPPP                                                    0x000088b3
 114 #define GF100_MSPPP                                                  0x000090b3
 115
 116 #define G98_SEC                                                      0x000088b4
 117
 118 #define GT212_DMA                                                    0x000085b5
 119 #define FERMI_DMA                                                    0x000090b5
 120 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
 121 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
 122
 123 #define FERMI_DECOMPRESS                                             0x000090b8
 124
 125 #define FERMI_COMPUTE_A                                              0x000090c0
 126 #define FERMI_COMPUTE_B                                              0x000091c0
 127
 128 #define KEPLER_COMPUTE_A                                             0x0000a0c0
 129 #define KEPLER_COMPUTE_B                                             0x0000a1c0
 130
 131 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
 132 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
 133
 134
 135 /*******************************************************************************
 136  * client
 137  ******************************************************************************/
 138
 139 #define NV_CLIENT_DEVLIST                                                  0x00
 140
 141 struct nv_client_devlist_v0 {
 142         __u8  version;
 143         __u8  count;
 144         __u8  pad02[6];
 145         __u64 device[];
 146 };
 147
 148
 149 /*******************************************************************************
 150  * device
 151  ******************************************************************************/
 152
 153 struct nv_device_v0 {
 154         __u8  version;
 155         __u8  pad01[7];
 156         __u64 device;   /* device identifier, ~0 for client default */
 157 };
 158
 159 #define NV_DEVICE_V0_INFO                                                  0x00
 160 #define NV_DEVICE_V0_TIME                                                  0x01
 161
 162 struct nv_device_info_v0 {
 163         __u8  version;
 164 #define NV_DEVICE_INFO_V0_IGP                                              0x00
 165 #define NV_DEVICE_INFO_V0_PCI                                              0x01
 166 #define NV_DEVICE_INFO_V0_AGP                                              0x02
 167 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
 168 #define NV_DEVICE_INFO_V0_SOC                                              0x04
 169         __u8  platform;
 170         __u16 chipset;  /* from NV_PMC_BOOT_0 */
 171         __u8  revision; /* from NV_PMC_BOOT_0 */
 172 #define NV_DEVICE_INFO_V0_TNT                                              0x01
 173 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
 174 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
 175 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
 176 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
 177 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
 178 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
 179 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
 180 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
 181         __u8  family;
 182         __u8  pad06[2];
 183         __u64 ram_size;
 184         __u64 ram_user;
 185         char  chip[16];
 186         char  name[64];
 187 };
 188
 189 struct nv_device_time_v0 {
 190         __u8  version;
 191         __u8  pad01[7];
 192         __u64 time;
 193 };
 194
 195
 196 /*******************************************************************************
 197  * context dma
 198  ******************************************************************************/
 199
 200 struct nv_dma_v0 {
 201         __u8  version;
 202 #define NV_DMA_V0_TARGET_VM                                                0x00
 203 #define NV_DMA_V0_TARGET_VRAM                                              0x01
 204 #define NV_DMA_V0_TARGET_PCI                                               0x02
 205 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
 206 #define NV_DMA_V0_TARGET_AGP                                               0x04
 207         __u8  target;
 208 #define NV_DMA_V0_ACCESS_VM                                                0x00
 209 #define NV_DMA_V0_ACCESS_RD                                                0x01
 210 #define NV_DMA_V0_ACCESS_WR                                                0x02
 211 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
 212         __u8  access;
 213         __u8  pad03[5];
 214         __u64 start;
 215         __u64 limit;
 216         /* ... chipset-specific class data */
 217 };
 218
 219 struct nv50_dma_v0 {
 220         __u8  version;
 221 #define NV50_DMA_V0_PRIV_VM                                                0x00
 222 #define NV50_DMA_V0_PRIV_US                                                0x01
 223 #define NV50_DMA_V0_PRIV__S                                                0x02
 224         __u8  priv;
 225 #define NV50_DMA_V0_PART_VM                                                0x00
 226 #define NV50_DMA_V0_PART_256                                               0x01
 227 #define NV50_DMA_V0_PART_1KB                                               0x02
 228         __u8  part;
 229 #define NV50_DMA_V0_COMP_NONE                                              0x00
 230 #define NV50_DMA_V0_COMP_1                                                 0x01
 231 #define NV50_DMA_V0_COMP_2                                                 0x02
 232 #define NV50_DMA_V0_COMP_VM                                                0x03
 233         __u8  comp;
 234 #define NV50_DMA_V0_KIND_PITCH                                             0x00
 235 #define NV50_DMA_V0_KIND_VM                                                0x7f
 236         __u8  kind;
 237         __u8  pad05[3];
 238 };
 239
 240 struct gf100_dma_v0 {
 241         __u8  version;
 242 #define GF100_DMA_V0_PRIV_VM                                               0x00
 243 #define GF100_DMA_V0_PRIV_US                                               0x01
 244 #define GF100_DMA_V0_PRIV__S                                               0x02
 245         __u8  priv;
 246 #define GF100_DMA_V0_KIND_PITCH                                            0x00
 247 #define GF100_DMA_V0_KIND_VM                                               0xff
 248         __u8  kind;
 249         __u8  pad03[5];
 250 };
 251
 252 struct gf110_dma_v0 {
 253         __u8  version;
 254 #define GF110_DMA_V0_PAGE_LP                                               0x00
 255 #define GF110_DMA_V0_PAGE_SP                                               0x01
 256         __u8  page;
 257 #define GF110_DMA_V0_KIND_PITCH                                            0x00
 258 #define GF110_DMA_V0_KIND_VM                                               0xff
 259         __u8  kind;
 260         __u8  pad03[5];
 261 };
 262
 263
 264 /*******************************************************************************
 265  * perfmon
 266  ******************************************************************************/
 267
 268 #define NVIF_PERFMON_V0_QUERY_DOMAIN                                       0x00
 269 #define NVIF_PERFMON_V0_QUERY_SIGNAL                                       0x01
 270 #define NVIF_PERFMON_V0_QUERY_SOURCE                                       0x02
 271
 272 struct nvif_perfmon_query_domain_v0 {
 273         __u8  version;
 274         __u8  id;
 275         __u8  counter_nr;
 276         __u8  iter;
 277         __u16 signal_nr;
 278         __u8  pad05[2];
 279         char  name[64];
 280 };
 281
 282 struct nvif_perfmon_query_signal_v0 {
 283         __u8  version;
 284         __u8  domain;
 285         __u16 iter;
 286         __u8  signal;
 287         __u8  source_nr;
 288         __u8  pad05[2];
 289         char  name[64];
 290 };
 291
 292 struct nvif_perfmon_query_source_v0 {
 293         __u8  version;
 294         __u8  domain;
 295         __u8  signal;
 296         __u8  iter;
 297         __u8  pad04[4];
 298         __u32 source;
 299         __u32 mask;
 300         char  name[64];
 301 };
 302
 303
 304 /*******************************************************************************
 305  * perfdom
 306  ******************************************************************************/
 307
 308 struct nvif_perfdom_v0 {
 309         __u8  version;
 310         __u8  domain;
 311         __u8  mode;
 312         __u8  pad03[1];
 313         struct {
 314                 __u8  signal[4];
 315                 __u64 source[4][8];
 316                 __u16 logic_op;
 317         } ctr[4];
 318 };
 319
 320 #define NVIF_PERFDOM_V0_INIT                                               0x00
 321 #define NVIF_PERFDOM_V0_SAMPLE                                             0x01
 322 #define NVIF_PERFDOM_V0_READ                                               0x02
 323
 324 struct nvif_perfdom_init {
 325 };
 326
 327 struct nvif_perfdom_sample {
 328 };
 329
 330 struct nvif_perfdom_read_v0 {
 331         __u8  version;
 332         __u8  pad01[7];
 333         __u32 ctr[4];
 334         __u32 clk;
 335         __u8  pad04[4];
 336 };
 337
 338
 339 /*******************************************************************************
 340  * device control
 341  ******************************************************************************/
 342
 343 #define NVIF_CONTROL_PSTATE_INFO                                           0x00
 344 #define NVIF_CONTROL_PSTATE_ATTR                                           0x01
 345 #define NVIF_CONTROL_PSTATE_USER                                           0x02
 346
 347 struct nvif_control_pstate_info_v0 {
 348         __u8  version;
 349         __u8  count; /* out: number of power states */
 350 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
 351 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
 352         __s8  ustate_ac; /* out: target pstate index */
 353         __s8  ustate_dc; /* out: target pstate index */
 354         __s8  pwrsrc; /* out: current power source */
 355 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
 356 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
 357         __s8  pstate; /* out: current pstate index */
 358         __u8  pad06[2];
 359 };
 360
 361 struct nvif_control_pstate_attr_v0 {
 362         __u8  version;
 363 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
 364         __s8  state; /*  in: index of pstate to query
 365                       * out: pstate identifier
 366                       */
 367         __u8  index; /*  in: index of attribute to query
 368                       * out: index of next attribute, or 0 if no more
 369                       */
 370         __u8  pad03[5];
 371         __u32 min;
 372         __u32 max;
 373         char  name[32];
 374         char  unit[16];
 375 };
 376
 377 struct nvif_control_pstate_user_v0 {
 378         __u8  version;
 379 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
 380 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
 381         __s8  ustate; /*  in: pstate identifier */
 382         __s8  pwrsrc; /*  in: target power source */
 383         __u8  pad03[5];
 384 };
 385
 386
 387 /*******************************************************************************
 388  * DMA FIFO channels
 389  ******************************************************************************/
 390
 391 struct nv03_channel_dma_v0 {
 392         __u8  version;
 393         __u8  chid;
 394         __u8  pad02[2];
 395         __u32 offset;
 396         __u64 pushbuf;
 397 };
 398
 399 struct nv50_channel_dma_v0 {
 400         __u8  version;
 401         __u8  chid;
 402         __u8  pad02[6];
 403         __u64 vm;
 404         __u64 pushbuf;
 405         __u64 offset;
 406 };
 407
 408 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00
 409
 410 /*******************************************************************************
 411  * GPFIFO channels
 412  ******************************************************************************/
 413
 414 struct nv50_channel_gpfifo_v0 {
 415         __u8  version;
 416         __u8  chid;
 417         __u8  pad02[2];
 418         __u32 ilength;
 419         __u64 ioffset;
 420         __u64 pushbuf;
 421         __u64 vm;
 422 };
 423
 424 struct fermi_channel_gpfifo_v0 {
 425         __u8  version;
 426         __u8  chid;
 427         __u8  pad02[2];
 428         __u32 ilength;
 429         __u64 ioffset;
 430         __u64 vm;
 431 };
 432
 433 struct kepler_channel_gpfifo_a_v0 {
 434         __u8  version;
 435 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
 436 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
 437 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
 438 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
 439 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
 440 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
 441 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
 442         __u8  engine;
 443         __u16 chid;
 444         __u32 ilength;
 445         __u64 ioffset;
 446         __u64 vm;
 447 };
 448
 449 /*******************************************************************************
 450  * legacy display
 451  ******************************************************************************/
 452
 453 #define NV04_DISP_NTFY_VBLANK                                              0x00
 454 #define NV04_DISP_NTFY_CONN                                                0x01
 455
 456 struct nv04_disp_mthd_v0 {
 457         __u8  version;
 458 #define NV04_DISP_SCANOUTPOS                                               0x00
 459         __u8  method;
 460         __u8  head;
 461         __u8  pad03[5];
 462 };
 463
 464 struct nv04_disp_scanoutpos_v0 {
 465         __u8  version;
 466         __u8  pad01[7];
 467         __s64 time[2];
 468         __u16 vblanks;
 469         __u16 vblanke;
 470         __u16 vtotal;
 471         __u16 vline;
 472         __u16 hblanks;
 473         __u16 hblanke;
 474         __u16 htotal;
 475         __u16 hline;
 476 };
 477
 478 /*******************************************************************************
 479  * display
 480  ******************************************************************************/
 481
 482 #define NV50_DISP_MTHD                                                     0x00
 483
 484 struct nv50_disp_mthd_v0 {
 485         __u8  version;
 486 #define NV50_DISP_SCANOUTPOS                                               0x00
 487         __u8  method;
 488         __u8  head;
 489         __u8  pad03[5];
 490 };
 491
 492 struct nv50_disp_mthd_v1 {
 493         __u8  version;
 494 #define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
 495 #define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
 496 #define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
 497 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
 498 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
 499 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
 500 #define NV50_DISP_MTHD_V1_SOR_DP_PWR                                       0x24
 501 #define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
 502         __u8  method;
 503         __u16 hasht;
 504         __u16 hashm;
 505         __u8  pad06[2];
 506 };
 507
 508 struct nv50_disp_dac_pwr_v0 {
 509         __u8  version;
 510         __u8  state;
 511         __u8  data;
 512         __u8  vsync;
 513         __u8  hsync;
 514         __u8  pad05[3];
 515 };
 516
 517 struct nv50_disp_dac_load_v0 {
 518         __u8  version;
 519         __u8  load;
 520         __u8  pad02[2];
 521         __u32 data;
 522 };
 523
 524 struct nv50_disp_sor_pwr_v0 {
 525         __u8  version;
 526         __u8  state;
 527         __u8  pad02[6];
 528 };
 529
 530 struct nv50_disp_sor_hda_eld_v0 {
 531         __u8  version;
 532         __u8  pad01[7];
 533         __u8  data[];
 534 };
 535
 536 struct nv50_disp_sor_hdmi_pwr_v0 {
 537         __u8  version;
 538         __u8  state;
 539         __u8  max_ac_packet;
 540         __u8  rekey;
 541         __u8  pad04[4];
 542 };
 543
 544 struct nv50_disp_sor_lvds_script_v0 {
 545         __u8  version;
 546         __u8  pad01[1];
 547         __u16 script;
 548         __u8  pad04[4];
 549 };
 550
 551 struct nv50_disp_sor_dp_pwr_v0 {
 552         __u8  version;
 553         __u8  state;
 554         __u8  pad02[6];
 555 };
 556
 557 struct nv50_disp_pior_pwr_v0 {
 558         __u8  version;
 559         __u8  state;
 560         __u8  type;
 561         __u8  pad03[5];
 562 };
 563
 564 /* core */
 565 struct nv50_disp_core_channel_dma_v0 {
 566         __u8  version;
 567         __u8  pad01[7];
 568         __u64 pushbuf;
 569 };
 570
 571 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
 572
 573 /* cursor immediate */
 574 struct nv50_disp_cursor_v0 {
 575         __u8  version;
 576         __u8  head;
 577         __u8  pad02[6];
 578 };
 579
 580 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00
 581
 582 /* base */
 583 struct nv50_disp_base_channel_dma_v0 {
 584         __u8  version;
 585         __u8  head;
 586         __u8  pad02[6];
 587         __u64 pushbuf;
 588 };
 589
 590 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
 591
 592 /* overlay */
 593 struct nv50_disp_overlay_channel_dma_v0 {
 594         __u8  version;
 595         __u8  head;
 596         __u8  pad02[6];
 597         __u64 pushbuf;
 598 };
 599
 600 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00
 601
 602 /* overlay immediate */
 603 struct nv50_disp_overlay_v0 {
 604         __u8  version;
 605         __u8  head;
 606         __u8  pad02[6];
 607 };
 608
 609 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
 610
 611 /*******************************************************************************
 612  * software
 613  ******************************************************************************/
 614
 615 #define NVSW_NTFY_UEVENT                                                   0x00
 616
 617 #define NV04_NVSW_GET_REF                                                  0x00
 618
 619 struct nv04_nvsw_get_ref_v0 {
 620         __u8  version;
 621         __u8  pad01[3];
 622         __u32 ref;
 623 };
 624
 625 /*******************************************************************************
 626  * fermi
 627  ******************************************************************************/
 628
 629 #define FERMI_A_ZBC_COLOR                                                  0x00
 630 #define FERMI_A_ZBC_DEPTH                                                  0x01
 631
 632 struct fermi_a_zbc_color_v0 {
 633         __u8  version;
 634 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO                                      0x01
 635 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE                                 0x02
 636 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32                       0x04
 637 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16                           0x08
 638 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16                       0x0c
 639 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16                       0x10
 640 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16                       0x14
 641 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16                       0x16
 642 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8                                  0x18
 643 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8                               0x1c
 644 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10                               0x20
 645 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10                           0x24
 646 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8                                  0x28
 647 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8                               0x2c
 648 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8                              0x30
 649 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8                              0x34
 650 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8                              0x38
 651 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10                               0x3c
 652 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11                              0x40
 653         __u8  format;
 654         __u8  index;
 655         __u8  pad03[5];
 656         __u32 ds[4];
 657         __u32 l2[4];
 658 };
 659
 660 struct fermi_a_zbc_depth_v0 {
 661         __u8  version;
 662 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32                                      0x01
 663         __u8  format;
 664         __u8  index;
 665         __u8  pad03[5];
 666         __u32 ds;
 667         __u32 l2;
 668 };
 669
 670 #endif