drm/nouveau/dma: split user classes out from engine implementations
[deliverable/linux.git] / drivers / gpu / drm / nouveau / include / nvkm / core / device.h
1 #ifndef __NVKM_DEVICE_H__
2 #define __NVKM_DEVICE_H__
3 #include <core/engine.h>
4 #include <core/event.h>
5
6 enum nvkm_devidx {
7 NVDEV_SUBDEV_VBIOS,
8
9 /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
10 * *any* of them are initialised. This subdev category is used
11 * for any subdevs that the VBIOS init table parsing may call out
12 * to during POST.
13 */
14 NVDEV_SUBDEV_DEVINIT,
15 NVDEV_SUBDEV_IBUS,
16 NVDEV_SUBDEV_GPIO,
17 NVDEV_SUBDEV_I2C,
18 NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
19
20 /* This grouping of subdevs are initialised right after they've
21 * been created, and are allowed to assume any subdevs in the
22 * list above them exist and have been initialised.
23 */
24 NVDEV_SUBDEV_FUSE,
25 NVDEV_SUBDEV_MXM,
26 NVDEV_SUBDEV_MC,
27 NVDEV_SUBDEV_BUS,
28 NVDEV_SUBDEV_TIMER,
29 NVDEV_SUBDEV_FB,
30 NVDEV_SUBDEV_LTC,
31 NVDEV_SUBDEV_INSTMEM,
32 NVDEV_SUBDEV_MMU,
33 NVDEV_SUBDEV_BAR,
34 NVDEV_SUBDEV_PMU,
35 NVDEV_SUBDEV_VOLT,
36 NVDEV_SUBDEV_THERM,
37 NVDEV_SUBDEV_CLK,
38
39 NVDEV_ENGINE_FIRST,
40 NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
41 NVDEV_ENGINE_IFB,
42 NVDEV_ENGINE_FIFO,
43 NVDEV_ENGINE_SW,
44 NVDEV_ENGINE_GR,
45 NVDEV_ENGINE_MPEG,
46 NVDEV_ENGINE_ME,
47 NVDEV_ENGINE_VP,
48 NVDEV_ENGINE_CIPHER,
49 NVDEV_ENGINE_BSP,
50 NVDEV_ENGINE_MSPPP,
51 NVDEV_ENGINE_CE0,
52 NVDEV_ENGINE_CE1,
53 NVDEV_ENGINE_CE2,
54 NVDEV_ENGINE_VIC,
55 NVDEV_ENGINE_MSENC,
56 NVDEV_ENGINE_DISP,
57 NVDEV_ENGINE_PM,
58 NVDEV_ENGINE_MSVLD,
59 NVDEV_ENGINE_SEC,
60 NVDEV_ENGINE_MSPDEC,
61
62 NVDEV_SUBDEV_NR,
63 };
64
65 struct nvkm_device {
66 struct nvkm_engine engine;
67
68 const struct nvkm_device_func *func;
69 const struct nvkm_device_quirk *quirk;
70 struct device *dev;
71 u64 handle;
72 const char *name;
73 const char *cfgopt;
74 const char *dbgopt;
75
76 struct list_head head;
77 struct mutex mutex;
78 int refcount;
79
80 struct pci_dev *pdev;
81 struct platform_device *platformdev;
82
83 void __iomem *pri;
84
85 struct nvkm_event event;
86
87 u64 disable_mask;
88
89 const struct nvkm_device_chip *chip;
90 enum {
91 NV_04 = 0x04,
92 NV_10 = 0x10,
93 NV_11 = 0x11,
94 NV_20 = 0x20,
95 NV_30 = 0x30,
96 NV_40 = 0x40,
97 NV_50 = 0x50,
98 NV_C0 = 0xc0,
99 NV_E0 = 0xe0,
100 GM100 = 0x110,
101 } card_type;
102 u32 chipset;
103 u8 chiprev;
104 u32 crystal;
105
106 struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
107
108 struct {
109 struct notifier_block nb;
110 } acpi;
111
112 struct nvkm_bar *bar;
113 struct nvkm_bios *bios;
114 struct nvkm_bus *bus;
115 struct nvkm_clk *clk;
116 struct nvkm_devinit *devinit;
117 struct nvkm_fb *fb;
118 struct nvkm_fuse *fuse;
119 struct nvkm_gpio *gpio;
120 struct nvkm_i2c *i2c;
121 struct nvkm_subdev *ibus;
122 struct nvkm_instmem *imem;
123 struct nvkm_ltc *ltc;
124 struct nvkm_mc *mc;
125 struct nvkm_mmu *mmu;
126 struct nvkm_subdev *mxm;
127 struct nvkm_pmu *pmu;
128 struct nvkm_therm *therm;
129 struct nvkm_timer *timer;
130 struct nvkm_volt *volt;
131
132 struct nvkm_engine *bsp;
133 struct nvkm_engine *ce[3];
134 struct nvkm_engine *cipher;
135 struct nvkm_disp *disp;
136 struct nvkm_dma *dma;
137 struct nvkm_fifo *fifo;
138 struct nvkm_gr *gr;
139 struct nvkm_engine *ifb;
140 struct nvkm_engine *me;
141 struct nvkm_engine *mpeg;
142 struct nvkm_engine *msenc;
143 struct nvkm_engine *mspdec;
144 struct nvkm_engine *msppp;
145 struct nvkm_engine *msvld;
146 struct nvkm_pm *pm;
147 struct nvkm_engine *sec;
148 struct nvkm_sw *sw;
149 struct nvkm_engine *vic;
150 struct nvkm_engine *vp;
151
152 struct nouveau_platform_gpu *gpu;
153 };
154
155 struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
156 struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index);
157
158 struct nvkm_device_func {
159 struct nvkm_device_pci *(*pci)(struct nvkm_device *);
160 struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
161 void *(*dtor)(struct nvkm_device *);
162 int (*preinit)(struct nvkm_device *);
163 void (*fini)(struct nvkm_device *, bool suspend);
164 };
165
166 struct nvkm_device_quirk {
167 };
168
169 struct nvkm_device_chip {
170 const char *name;
171
172 int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **);
173 int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **);
174 int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **);
175 int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **);
176 int (*devinit)(struct nvkm_device *, int idx, struct nvkm_devinit **);
177 int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **);
178 int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **);
179 int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **);
180 int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **);
181 int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **);
182 int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **);
183 int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **);
184 int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **);
185 int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **);
186 int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **);
187 int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **);
188 int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **);
189 int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **);
190 int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **);
191
192 int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **);
193 int (*ce[3] )(struct nvkm_device *, int idx, struct nvkm_engine **);
194 int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
195 int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
196 int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **);
197 int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **);
198 int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
199 int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);
200 int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **);
201 int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);
202 int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **);
203 int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
204 int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
205 int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
206 int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
207 int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
208 int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
209 int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
210 int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **);
211 };
212
213 struct nvkm_device *nvkm_device_find(u64 name);
214 int nvkm_device_list(u64 *name, int size);
215
216 /* privileged register interface accessor macros */
217 #define nvkm_rd08(d,a) ioread8((d)->pri + (a))
218 #define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
219 #define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
220 #define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
221 #define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
222 #define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
223 #define nvkm_mask(d,a,m,v) ({ \
224 struct nvkm_device *_device = (d); \
225 u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
226 nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
227 _temp; \
228 })
229
230 struct nvkm_device *nv_device(void *obj);
231
232 static inline bool
233 nv_device_match(struct nvkm_device *device, u16 dev, u16 ven, u16 sub)
234 {
235 return device->pdev->device == dev &&
236 device->pdev->subsystem_vendor == ven &&
237 device->pdev->subsystem_device == sub;
238 }
239
240 static inline bool
241 nv_device_is_pci(struct nvkm_device *device)
242 {
243 return device->pdev != NULL;
244 }
245
246 static inline bool
247 nv_device_is_cpu_coherent(struct nvkm_device *device)
248 {
249 return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device));
250 }
251
252 static inline struct device *
253 nv_device_base(struct nvkm_device *device)
254 {
255 return nv_device_is_pci(device) ? &device->pdev->dev :
256 &device->platformdev->dev;
257 }
258
259 resource_size_t
260 nv_device_resource_start(struct nvkm_device *device, unsigned int bar);
261
262 resource_size_t
263 nv_device_resource_len(struct nvkm_device *device, unsigned int bar);
264
265 int
266 nv_device_get_irq(struct nvkm_device *device, bool stall);
267
268 struct platform_device;
269
270 enum nv_bus_type {
271 NVKM_BUS_PCI,
272 NVKM_BUS_PLATFORM,
273 };
274
275 void nvkm_device_del(struct nvkm_device **);
276
277 struct nvkm_device_oclass {
278 int (*ctor)(struct nvkm_device *, const struct nvkm_oclass *,
279 void *data, u32 size, struct nvkm_object **);
280 struct nvkm_sclass base;
281 };
282
283 extern const struct nvkm_sclass nvkm_udevice_sclass;
284
285 /* device logging */
286 #define nvdev_printk_(d,l,p,f,a...) do { \
287 struct nvkm_device *_device = (d); \
288 if (_device->engine.subdev.debug >= (l)) \
289 dev_##p(_device->dev, f, ##a); \
290 } while(0)
291 #define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
292 #define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL, crit, f, ##a)
293 #define nvdev_error(d,f,a...) nvdev_printk((d), ERROR, err, f, ##a)
294 #define nvdev_warn(d,f,a...) nvdev_printk((d), WARN, notice, f, ##a)
295 #define nvdev_info(d,f,a...) nvdev_printk((d), INFO, info, f, ##a)
296 #define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG, info, f, ##a)
297 #define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE, info, f, ##a)
298 #define nvdev_spam(d,f,a...) nvdev_printk((d), SPAM, dbg, f, ##a)
299 #endif
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