2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_mm.h"
36 #include "nouveau_vm.h"
38 #include <linux/log2.h>
39 #include <linux/slab.h>
42 nouveau_bo_del_ttm(struct ttm_buffer_object
*bo
)
44 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
45 struct drm_device
*dev
= dev_priv
->dev
;
46 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
48 if (unlikely(nvbo
->gem
))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo
);
51 nv10_mem_put_tile_region(dev
, nvbo
->tile
, NULL
);
52 nouveau_vm_put(&nvbo
->vma
);
57 nouveau_bo_fixup_align(struct nouveau_bo
*nvbo
, int *align
, int *size
,
60 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
62 if (dev_priv
->card_type
< NV_50
) {
63 if (nvbo
->tile_mode
) {
64 if (dev_priv
->chipset
>= 0x40) {
66 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
68 } else if (dev_priv
->chipset
>= 0x30) {
70 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
72 } else if (dev_priv
->chipset
>= 0x20) {
74 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
76 } else if (dev_priv
->chipset
>= 0x10) {
78 *size
= roundup(*size
, 32 * nvbo
->tile_mode
);
82 if (likely(dev_priv
->chan_vm
)) {
83 if (*size
> 256 * 1024)
84 *page_shift
= dev_priv
->chan_vm
->lpg_shift
;
86 *page_shift
= dev_priv
->chan_vm
->spg_shift
;
91 *size
= roundup(*size
, (1 << *page_shift
));
92 *align
= max((1 << *page_shift
), *align
);
95 *size
= roundup(*size
, PAGE_SIZE
);
99 nouveau_bo_new(struct drm_device
*dev
, struct nouveau_channel
*chan
,
100 int size
, int align
, uint32_t flags
, uint32_t tile_mode
,
101 uint32_t tile_flags
, bool no_vm
, bool mappable
,
102 struct nouveau_bo
**pnvbo
)
104 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
105 struct nouveau_bo
*nvbo
;
106 int ret
= 0, page_shift
= 0;
108 nvbo
= kzalloc(sizeof(struct nouveau_bo
), GFP_KERNEL
);
111 INIT_LIST_HEAD(&nvbo
->head
);
112 INIT_LIST_HEAD(&nvbo
->entry
);
113 nvbo
->mappable
= mappable
;
115 nvbo
->tile_mode
= tile_mode
;
116 nvbo
->tile_flags
= tile_flags
;
117 nvbo
->bo
.bdev
= &dev_priv
->ttm
.bdev
;
119 nouveau_bo_fixup_align(nvbo
, &align
, &size
, &page_shift
);
120 align
>>= PAGE_SHIFT
;
122 if (!nvbo
->no_vm
&& dev_priv
->chan_vm
) {
123 ret
= nouveau_vm_get(dev_priv
->chan_vm
, size
, page_shift
,
124 NV_MEM_ACCESS_RW
, &nvbo
->vma
);
131 nouveau_bo_placement_set(nvbo
, flags
, 0);
133 nvbo
->channel
= chan
;
134 ret
= ttm_bo_init(&dev_priv
->ttm
.bdev
, &nvbo
->bo
, size
,
135 ttm_bo_type_device
, &nvbo
->placement
, align
, 0,
136 false, NULL
, size
, nouveau_bo_del_ttm
);
138 /* ttm will call nouveau_bo_del_ttm if it fails.. */
141 nvbo
->channel
= NULL
;
143 if (nvbo
->vma
.node
) {
144 if (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
145 nvbo
->bo
.offset
= nvbo
->vma
.offset
;
153 set_placement_list(uint32_t *pl
, unsigned *n
, uint32_t type
, uint32_t flags
)
157 if (type
& TTM_PL_FLAG_VRAM
)
158 pl
[(*n
)++] = TTM_PL_FLAG_VRAM
| flags
;
159 if (type
& TTM_PL_FLAG_TT
)
160 pl
[(*n
)++] = TTM_PL_FLAG_TT
| flags
;
161 if (type
& TTM_PL_FLAG_SYSTEM
)
162 pl
[(*n
)++] = TTM_PL_FLAG_SYSTEM
| flags
;
166 set_placement_range(struct nouveau_bo
*nvbo
, uint32_t type
)
168 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
170 if (dev_priv
->card_type
== NV_10
&&
171 nvbo
->tile_mode
&& (type
& TTM_PL_FLAG_VRAM
)) {
173 * Make sure that the color and depth buffers are handled
174 * by independent memory controller units. Up to a 9x
175 * speed up when alpha-blending and depth-test are enabled
178 int vram_pages
= dev_priv
->vram_size
>> PAGE_SHIFT
;
180 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_ZETA
) {
181 nvbo
->placement
.fpfn
= vram_pages
/ 2;
182 nvbo
->placement
.lpfn
= ~0;
184 nvbo
->placement
.fpfn
= 0;
185 nvbo
->placement
.lpfn
= vram_pages
/ 2;
191 nouveau_bo_placement_set(struct nouveau_bo
*nvbo
, uint32_t type
, uint32_t busy
)
193 struct ttm_placement
*pl
= &nvbo
->placement
;
194 uint32_t flags
= TTM_PL_MASK_CACHING
|
195 (nvbo
->pin_refcnt
? TTM_PL_FLAG_NO_EVICT
: 0);
197 pl
->placement
= nvbo
->placements
;
198 set_placement_list(nvbo
->placements
, &pl
->num_placement
,
201 pl
->busy_placement
= nvbo
->busy_placements
;
202 set_placement_list(nvbo
->busy_placements
, &pl
->num_busy_placement
,
205 set_placement_range(nvbo
, type
);
209 nouveau_bo_pin(struct nouveau_bo
*nvbo
, uint32_t memtype
)
211 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
212 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
215 if (nvbo
->pin_refcnt
&& !(memtype
& (1 << bo
->mem
.mem_type
))) {
216 NV_ERROR(nouveau_bdev(bo
->bdev
)->dev
,
217 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo
,
218 1 << bo
->mem
.mem_type
, memtype
);
222 if (nvbo
->pin_refcnt
++)
225 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
229 nouveau_bo_placement_set(nvbo
, memtype
, 0);
231 ret
= nouveau_bo_validate(nvbo
, false, false, false);
233 switch (bo
->mem
.mem_type
) {
235 dev_priv
->fb_aper_free
-= bo
->mem
.size
;
238 dev_priv
->gart_info
.aper_free
-= bo
->mem
.size
;
244 ttm_bo_unreserve(bo
);
252 nouveau_bo_unpin(struct nouveau_bo
*nvbo
)
254 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
255 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
258 if (--nvbo
->pin_refcnt
)
261 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
265 nouveau_bo_placement_set(nvbo
, bo
->mem
.placement
, 0);
267 ret
= nouveau_bo_validate(nvbo
, false, false, false);
269 switch (bo
->mem
.mem_type
) {
271 dev_priv
->fb_aper_free
+= bo
->mem
.size
;
274 dev_priv
->gart_info
.aper_free
+= bo
->mem
.size
;
281 ttm_bo_unreserve(bo
);
286 nouveau_bo_map(struct nouveau_bo
*nvbo
)
290 ret
= ttm_bo_reserve(&nvbo
->bo
, false, false, false, 0);
294 ret
= ttm_bo_kmap(&nvbo
->bo
, 0, nvbo
->bo
.mem
.num_pages
, &nvbo
->kmap
);
295 ttm_bo_unreserve(&nvbo
->bo
);
300 nouveau_bo_unmap(struct nouveau_bo
*nvbo
)
303 ttm_bo_kunmap(&nvbo
->kmap
);
307 nouveau_bo_validate(struct nouveau_bo
*nvbo
, bool interruptible
,
308 bool no_wait_reserve
, bool no_wait_gpu
)
312 ret
= ttm_bo_validate(&nvbo
->bo
, &nvbo
->placement
, interruptible
,
313 no_wait_reserve
, no_wait_gpu
);
317 if (nvbo
->vma
.node
) {
318 if (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
319 nvbo
->bo
.offset
= nvbo
->vma
.offset
;
326 nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
)
329 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
332 return ioread16_native((void __force __iomem
*)mem
);
338 nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
)
341 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
344 iowrite16_native(val
, (void __force __iomem
*)mem
);
350 nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
)
353 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
356 return ioread32_native((void __force __iomem
*)mem
);
362 nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
)
365 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
368 iowrite32_native(val
, (void __force __iomem
*)mem
);
373 static struct ttm_backend
*
374 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device
*bdev
)
376 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
377 struct drm_device
*dev
= dev_priv
->dev
;
379 switch (dev_priv
->gart_info
.type
) {
381 case NOUVEAU_GART_AGP
:
382 return ttm_agp_backend_init(bdev
, dev
->agp
->bridge
);
384 case NOUVEAU_GART_SGDMA
:
385 return nouveau_sgdma_init_ttm(dev
);
387 NV_ERROR(dev
, "Unknown GART type %d\n",
388 dev_priv
->gart_info
.type
);
396 nouveau_bo_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
398 /* We'll do this from user space. */
403 nouveau_bo_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
404 struct ttm_mem_type_manager
*man
)
406 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
407 struct drm_device
*dev
= dev_priv
->dev
;
411 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
412 man
->available_caching
= TTM_PL_MASK_CACHING
;
413 man
->default_caching
= TTM_PL_FLAG_CACHED
;
416 if (dev_priv
->card_type
>= NV_50
) {
417 man
->func
= &nouveau_vram_manager
;
418 man
->io_reserve_fastpath
= false;
419 man
->use_io_reserve_lru
= true;
421 man
->func
= &ttm_bo_manager_func
;
423 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
424 TTM_MEMTYPE_FLAG_MAPPABLE
;
425 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
427 man
->default_caching
= TTM_PL_FLAG_WC
;
430 man
->func
= &ttm_bo_manager_func
;
431 switch (dev_priv
->gart_info
.type
) {
432 case NOUVEAU_GART_AGP
:
433 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
434 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
436 man
->default_caching
= TTM_PL_FLAG_WC
;
438 case NOUVEAU_GART_SGDMA
:
439 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
|
440 TTM_MEMTYPE_FLAG_CMA
;
441 man
->available_caching
= TTM_PL_MASK_CACHING
;
442 man
->default_caching
= TTM_PL_FLAG_CACHED
;
443 man
->gpu_offset
= dev_priv
->gart_info
.aper_base
;
446 NV_ERROR(dev
, "Unknown GART type: %d\n",
447 dev_priv
->gart_info
.type
);
452 NV_ERROR(dev
, "Unsupported memory type %u\n", (unsigned)type
);
459 nouveau_bo_evict_flags(struct ttm_buffer_object
*bo
, struct ttm_placement
*pl
)
461 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
463 switch (bo
->mem
.mem_type
) {
465 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_TT
,
469 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_SYSTEM
, 0);
473 *pl
= nvbo
->placement
;
477 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
478 * TTM_PL_{VRAM,TT} directly.
482 nouveau_bo_move_accel_cleanup(struct nouveau_channel
*chan
,
483 struct nouveau_bo
*nvbo
, bool evict
,
484 bool no_wait_reserve
, bool no_wait_gpu
,
485 struct ttm_mem_reg
*new_mem
)
487 struct nouveau_fence
*fence
= NULL
;
490 ret
= nouveau_fence_new(chan
, &fence
, true);
494 ret
= ttm_bo_move_accel_cleanup(&nvbo
->bo
, fence
, NULL
, evict
,
495 no_wait_reserve
, no_wait_gpu
, new_mem
);
496 nouveau_fence_unref(&fence
);
500 static inline uint32_t
501 nouveau_bo_mem_ctxdma(struct ttm_buffer_object
*bo
,
502 struct nouveau_channel
*chan
, struct ttm_mem_reg
*mem
)
504 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
507 if (mem
->mem_type
== TTM_PL_TT
)
512 if (mem
->mem_type
== TTM_PL_TT
)
513 return chan
->gart_handle
;
514 return chan
->vram_handle
;
518 nvc0_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
519 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
521 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
522 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
523 u64 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
524 u64 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
525 u32 page_count
= new_mem
->num_pages
;
529 if (old_mem
->mem_type
== TTM_PL_VRAM
)
530 src_offset
= nvbo
->vma
.offset
;
532 src_offset
+= dev_priv
->gart_info
.aper_base
;
534 if (new_mem
->mem_type
== TTM_PL_VRAM
)
535 dst_offset
= nvbo
->vma
.offset
;
537 dst_offset
+= dev_priv
->gart_info
.aper_base
;
540 page_count
= new_mem
->num_pages
;
542 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
544 ret
= RING_SPACE(chan
, 12);
548 BEGIN_NVC0(chan
, 2, NvSubM2MF
, 0x0238, 2);
549 OUT_RING (chan
, upper_32_bits(dst_offset
));
550 OUT_RING (chan
, lower_32_bits(dst_offset
));
551 BEGIN_NVC0(chan
, 2, NvSubM2MF
, 0x030c, 6);
552 OUT_RING (chan
, upper_32_bits(src_offset
));
553 OUT_RING (chan
, lower_32_bits(src_offset
));
554 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
555 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
556 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
557 OUT_RING (chan
, line_count
);
558 BEGIN_NVC0(chan
, 2, NvSubM2MF
, 0x0300, 1);
559 OUT_RING (chan
, 0x00100110);
561 page_count
-= line_count
;
562 src_offset
+= (PAGE_SIZE
* line_count
);
563 dst_offset
+= (PAGE_SIZE
* line_count
);
570 nv50_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
571 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
573 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
574 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
575 u64 length
= (new_mem
->num_pages
<< PAGE_SHIFT
);
576 u64 src_offset
, dst_offset
;
579 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
580 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
582 if (old_mem
->mem_type
== TTM_PL_VRAM
)
583 src_offset
= nvbo
->vma
.offset
;
585 src_offset
+= dev_priv
->gart_info
.aper_base
;
587 if (new_mem
->mem_type
== TTM_PL_VRAM
)
588 dst_offset
= nvbo
->vma
.offset
;
590 dst_offset
+= dev_priv
->gart_info
.aper_base
;
593 ret
= RING_SPACE(chan
, 3);
597 BEGIN_RING(chan
, NvSubM2MF
, 0x0184, 2);
598 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
599 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
602 u32 amount
, stride
, height
;
604 amount
= min(length
, (u64
)(4 * 1024 * 1024));
606 height
= amount
/ stride
;
608 if (new_mem
->mem_type
== TTM_PL_VRAM
&&
609 nouveau_bo_tile_layout(nvbo
)) {
610 ret
= RING_SPACE(chan
, 8);
614 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 7);
617 OUT_RING (chan
, stride
);
618 OUT_RING (chan
, height
);
623 ret
= RING_SPACE(chan
, 2);
627 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 1);
630 if (old_mem
->mem_type
== TTM_PL_VRAM
&&
631 nouveau_bo_tile_layout(nvbo
)) {
632 ret
= RING_SPACE(chan
, 8);
636 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 7);
639 OUT_RING (chan
, stride
);
640 OUT_RING (chan
, height
);
645 ret
= RING_SPACE(chan
, 2);
649 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 1);
653 ret
= RING_SPACE(chan
, 14);
657 BEGIN_RING(chan
, NvSubM2MF
, 0x0238, 2);
658 OUT_RING (chan
, upper_32_bits(src_offset
));
659 OUT_RING (chan
, upper_32_bits(dst_offset
));
660 BEGIN_RING(chan
, NvSubM2MF
, 0x030c, 8);
661 OUT_RING (chan
, lower_32_bits(src_offset
));
662 OUT_RING (chan
, lower_32_bits(dst_offset
));
663 OUT_RING (chan
, stride
);
664 OUT_RING (chan
, stride
);
665 OUT_RING (chan
, stride
);
666 OUT_RING (chan
, height
);
667 OUT_RING (chan
, 0x00000101);
668 OUT_RING (chan
, 0x00000000);
669 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
673 src_offset
+= amount
;
674 dst_offset
+= amount
;
681 nv04_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
682 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
684 u32 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
685 u32 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
686 u32 page_count
= new_mem
->num_pages
;
689 ret
= RING_SPACE(chan
, 3);
693 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE
, 2);
694 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
695 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
697 page_count
= new_mem
->num_pages
;
699 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
701 ret
= RING_SPACE(chan
, 11);
705 BEGIN_RING(chan
, NvSubM2MF
,
706 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
707 OUT_RING (chan
, src_offset
);
708 OUT_RING (chan
, dst_offset
);
709 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
710 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
711 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
712 OUT_RING (chan
, line_count
);
713 OUT_RING (chan
, 0x00000101);
714 OUT_RING (chan
, 0x00000000);
715 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
718 page_count
-= line_count
;
719 src_offset
+= (PAGE_SIZE
* line_count
);
720 dst_offset
+= (PAGE_SIZE
* line_count
);
727 nouveau_bo_move_m2mf(struct ttm_buffer_object
*bo
, int evict
, bool intr
,
728 bool no_wait_reserve
, bool no_wait_gpu
,
729 struct ttm_mem_reg
*new_mem
)
731 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
732 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
733 struct nouveau_channel
*chan
;
736 chan
= nvbo
->channel
;
737 if (!chan
|| nvbo
->no_vm
) {
738 chan
= dev_priv
->channel
;
739 mutex_lock_nested(&chan
->mutex
, NOUVEAU_KCHANNEL_MUTEX
);
742 if (dev_priv
->card_type
< NV_50
)
743 ret
= nv04_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
745 if (dev_priv
->card_type
< NV_C0
)
746 ret
= nv50_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
748 ret
= nvc0_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
750 ret
= nouveau_bo_move_accel_cleanup(chan
, nvbo
, evict
,
752 no_wait_gpu
, new_mem
);
755 if (chan
== dev_priv
->channel
)
756 mutex_unlock(&chan
->mutex
);
761 nouveau_bo_move_flipd(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
762 bool no_wait_reserve
, bool no_wait_gpu
,
763 struct ttm_mem_reg
*new_mem
)
765 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
766 struct ttm_placement placement
;
767 struct ttm_mem_reg tmp_mem
;
770 placement
.fpfn
= placement
.lpfn
= 0;
771 placement
.num_placement
= placement
.num_busy_placement
= 1;
772 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
775 tmp_mem
.mm_node
= NULL
;
776 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
780 ret
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
784 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
788 ret
= ttm_bo_move_ttm(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
790 ttm_bo_mem_put(bo
, &tmp_mem
);
795 nouveau_bo_move_flips(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
796 bool no_wait_reserve
, bool no_wait_gpu
,
797 struct ttm_mem_reg
*new_mem
)
799 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
800 struct ttm_placement placement
;
801 struct ttm_mem_reg tmp_mem
;
804 placement
.fpfn
= placement
.lpfn
= 0;
805 placement
.num_placement
= placement
.num_busy_placement
= 1;
806 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
809 tmp_mem
.mm_node
= NULL
;
810 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
814 ret
= ttm_bo_move_ttm(bo
, evict
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
818 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
823 ttm_bo_mem_put(bo
, &tmp_mem
);
828 nouveau_bo_vm_bind(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
,
829 struct nouveau_tile_reg
**new_tile
)
831 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
832 struct drm_device
*dev
= dev_priv
->dev
;
833 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
836 if (nvbo
->no_vm
|| new_mem
->mem_type
!= TTM_PL_VRAM
) {
842 offset
= new_mem
->start
<< PAGE_SHIFT
;
844 if (dev_priv
->chan_vm
) {
845 nouveau_vm_map(&nvbo
->vma
, new_mem
->mm_node
);
846 } else if (dev_priv
->card_type
>= NV_10
) {
847 *new_tile
= nv10_mem_set_tiling(dev
, offset
, new_mem
->size
,
856 nouveau_bo_vm_cleanup(struct ttm_buffer_object
*bo
,
857 struct nouveau_tile_reg
*new_tile
,
858 struct nouveau_tile_reg
**old_tile
)
860 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
861 struct drm_device
*dev
= dev_priv
->dev
;
863 if (dev_priv
->card_type
>= NV_10
&&
864 dev_priv
->card_type
< NV_50
) {
865 nv10_mem_put_tile_region(dev
, *old_tile
, bo
->sync_obj
);
866 *old_tile
= new_tile
;
871 nouveau_bo_move(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
872 bool no_wait_reserve
, bool no_wait_gpu
,
873 struct ttm_mem_reg
*new_mem
)
875 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
876 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
877 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
878 struct nouveau_tile_reg
*new_tile
= NULL
;
881 ret
= nouveau_bo_vm_bind(bo
, new_mem
, &new_tile
);
886 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& !bo
->ttm
) {
887 BUG_ON(bo
->mem
.mm_node
!= NULL
);
889 new_mem
->mm_node
= NULL
;
893 /* Software copy if the card isn't up and running yet. */
894 if (!dev_priv
->channel
) {
895 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
899 /* Hardware assisted copy. */
900 if (new_mem
->mem_type
== TTM_PL_SYSTEM
)
901 ret
= nouveau_bo_move_flipd(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
902 else if (old_mem
->mem_type
== TTM_PL_SYSTEM
)
903 ret
= nouveau_bo_move_flips(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
905 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
910 /* Fallback to software copy. */
911 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
915 nouveau_bo_vm_cleanup(bo
, NULL
, &new_tile
);
917 nouveau_bo_vm_cleanup(bo
, new_tile
, &nvbo
->tile
);
923 nouveau_bo_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
929 nouveau_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
931 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
932 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
933 struct drm_device
*dev
= dev_priv
->dev
;
936 mem
->bus
.addr
= NULL
;
938 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
940 mem
->bus
.is_iomem
= false;
941 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
943 switch (mem
->mem_type
) {
949 if (dev_priv
->gart_info
.type
== NOUVEAU_GART_AGP
) {
950 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
951 mem
->bus
.base
= dev_priv
->gart_info
.aper_base
;
952 mem
->bus
.is_iomem
= true;
958 struct nouveau_vram
*vram
= mem
->mm_node
;
961 if (!dev_priv
->bar1_vm
) {
962 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
963 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
964 mem
->bus
.is_iomem
= true;
968 if (dev_priv
->card_type
== NV_C0
)
969 page_shift
= vram
->page_shift
;
973 ret
= nouveau_vm_get(dev_priv
->bar1_vm
, mem
->bus
.size
,
974 page_shift
, NV_MEM_ACCESS_RW
,
979 nouveau_vm_map(&vram
->bar_vma
, vram
);
981 nouveau_vm_put(&vram
->bar_vma
);
985 mem
->bus
.offset
= vram
->bar_vma
.offset
;
986 if (dev_priv
->card_type
== NV_50
) /*XXX*/
987 mem
->bus
.offset
-= 0x0020000000ULL
;
988 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
989 mem
->bus
.is_iomem
= true;
999 nouveau_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
1001 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
1002 struct nouveau_vram
*vram
= mem
->mm_node
;
1004 if (!dev_priv
->bar1_vm
|| mem
->mem_type
!= TTM_PL_VRAM
)
1007 if (!vram
->bar_vma
.node
)
1010 nouveau_vm_unmap(&vram
->bar_vma
);
1011 nouveau_vm_put(&vram
->bar_vma
);
1015 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object
*bo
)
1017 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
1018 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1020 /* as long as the bo isn't in vram, and isn't tiled, we've got
1021 * nothing to do here.
1023 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
) {
1024 if (dev_priv
->card_type
< NV_50
||
1025 !nouveau_bo_tile_layout(nvbo
))
1029 /* make sure bo is in mappable vram */
1030 if (bo
->mem
.start
+ bo
->mem
.num_pages
< dev_priv
->fb_mappable_pages
)
1034 nvbo
->placement
.fpfn
= 0;
1035 nvbo
->placement
.lpfn
= dev_priv
->fb_mappable_pages
;
1036 nouveau_bo_placement_set(nvbo
, TTM_PL_VRAM
, 0);
1037 return nouveau_bo_validate(nvbo
, false, true, false);
1041 nouveau_bo_fence(struct nouveau_bo
*nvbo
, struct nouveau_fence
*fence
)
1043 struct nouveau_fence
*old_fence
;
1046 nouveau_fence_ref(fence
);
1048 spin_lock(&nvbo
->bo
.bdev
->fence_lock
);
1049 old_fence
= nvbo
->bo
.sync_obj
;
1050 nvbo
->bo
.sync_obj
= fence
;
1051 spin_unlock(&nvbo
->bo
.bdev
->fence_lock
);
1053 nouveau_fence_unref(&old_fence
);
1056 struct ttm_bo_driver nouveau_bo_driver
= {
1057 .create_ttm_backend_entry
= nouveau_bo_create_ttm_backend_entry
,
1058 .invalidate_caches
= nouveau_bo_invalidate_caches
,
1059 .init_mem_type
= nouveau_bo_init_mem_type
,
1060 .evict_flags
= nouveau_bo_evict_flags
,
1061 .move
= nouveau_bo_move
,
1062 .verify_access
= nouveau_bo_verify_access
,
1063 .sync_obj_signaled
= __nouveau_fence_signalled
,
1064 .sync_obj_wait
= __nouveau_fence_wait
,
1065 .sync_obj_flush
= __nouveau_fence_flush
,
1066 .sync_obj_unref
= __nouveau_fence_unref
,
1067 .sync_obj_ref
= __nouveau_fence_ref
,
1068 .fault_reserve_notify
= &nouveau_ttm_fault_reserve_notify
,
1069 .io_mem_reserve
= &nouveau_ttm_io_mem_reserve
,
1070 .io_mem_free
= &nouveau_ttm_io_mem_free
,