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[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73 };
74
75 struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
87 bool validate_mapped;
88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
96 struct nouveau_tile_reg *tile;
97
98 struct drm_gem_object *gem;
99 int pin_refcnt;
100 };
101
102 #define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
104
105 static inline struct nouveau_bo *
106 nouveau_bo(struct ttm_buffer_object *bo)
107 {
108 return container_of(bo, struct nouveau_bo, bo);
109 }
110
111 static inline struct nouveau_bo *
112 nouveau_gem_object(struct drm_gem_object *gem)
113 {
114 return gem ? gem->driver_private : NULL;
115 }
116
117 /* TODO: submit equivalent to TTM generic API upstream? */
118 static inline void __iomem *
119 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120 {
121 bool is_iomem;
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
125 return ioptr;
126 }
127
128 enum nouveau_flags {
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
131 };
132
133 #define NVOBJ_ENGINE_SW 0
134 #define NVOBJ_ENGINE_GR 1
135 #define NVOBJ_ENGINE_PPP 2
136 #define NVOBJ_ENGINE_COPY 3
137 #define NVOBJ_ENGINE_VP 4
138 #define NVOBJ_ENGINE_CRYPT 5
139 #define NVOBJ_ENGINE_BSP 6
140 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
141 #define NVOBJ_ENGINE_INT 0xdeadbeef
142
143 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
145 struct nouveau_gpuobj {
146 struct drm_device *dev;
147 struct kref refcount;
148 struct list_head list;
149
150 struct drm_mm_node *im_pramin;
151 struct nouveau_bo *im_backing;
152 uint32_t *im_backing_suspend;
153 int im_bound;
154
155 uint32_t flags;
156
157 u32 size;
158 u32 pinst;
159 u32 cinst;
160 u64 vinst;
161
162 uint32_t engine;
163 uint32_t class;
164
165 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
166 void *priv;
167 };
168
169 struct nouveau_channel {
170 struct drm_device *dev;
171 int id;
172
173 /* references to the channel data structure */
174 struct kref ref;
175 /* users of the hardware channel resources, the hardware
176 * context will be kicked off when it reaches zero. */
177 atomic_t users;
178 struct mutex mutex;
179
180 /* owner of this fifo */
181 struct drm_file *file_priv;
182 /* mapping of the fifo itself */
183 struct drm_local_map *map;
184
185 /* mapping of the regs controling the fifo */
186 void __iomem *user;
187 uint32_t user_get;
188 uint32_t user_put;
189
190 /* Fencing */
191 struct {
192 /* lock protects the pending list only */
193 spinlock_t lock;
194 struct list_head pending;
195 uint32_t sequence;
196 uint32_t sequence_ack;
197 atomic_t last_sequence_irq;
198 } fence;
199
200 /* DMA push buffer */
201 struct nouveau_gpuobj *pushbuf;
202 struct nouveau_bo *pushbuf_bo;
203 uint32_t pushbuf_base;
204
205 /* Notifier memory */
206 struct nouveau_bo *notifier_bo;
207 struct drm_mm notifier_heap;
208
209 /* PFIFO context */
210 struct nouveau_gpuobj *ramfc;
211 struct nouveau_gpuobj *cache;
212
213 /* PGRAPH context */
214 /* XXX may be merge 2 pointers as private data ??? */
215 struct nouveau_gpuobj *ramin_grctx;
216 struct nouveau_gpuobj *crypt_ctx;
217 void *pgraph_ctx;
218
219 /* NV50 VM */
220 struct nouveau_gpuobj *vm_pd;
221 struct nouveau_gpuobj *vm_gart_pt;
222 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
223
224 /* Objects */
225 struct nouveau_gpuobj *ramin; /* Private instmem */
226 struct drm_mm ramin_heap; /* Private PRAMIN heap */
227 struct nouveau_ramht *ramht; /* Hash table */
228
229 /* GPU object info for stuff used in-kernel (mm_enabled) */
230 uint32_t m2mf_ntfy;
231 uint32_t vram_handle;
232 uint32_t gart_handle;
233 bool accel_done;
234
235 /* Push buffer state (only for drm's channel on !mm_enabled) */
236 struct {
237 int max;
238 int free;
239 int cur;
240 int put;
241 /* access via pushbuf_bo */
242
243 int ib_base;
244 int ib_max;
245 int ib_free;
246 int ib_put;
247 } dma;
248
249 uint32_t sw_subchannel[8];
250
251 struct {
252 struct nouveau_gpuobj *vblsem;
253 uint32_t vblsem_offset;
254 uint32_t vblsem_rval;
255 struct list_head vbl_wait;
256 } nvsw;
257
258 struct {
259 bool active;
260 char name[32];
261 struct drm_info_list info;
262 } debugfs;
263 };
264
265 struct nouveau_instmem_engine {
266 void *priv;
267
268 int (*init)(struct drm_device *dev);
269 void (*takedown)(struct drm_device *dev);
270 int (*suspend)(struct drm_device *dev);
271 void (*resume)(struct drm_device *dev);
272
273 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
274 u32 *size, u32 align);
275 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
276 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
277 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
278 void (*flush)(struct drm_device *);
279 };
280
281 struct nouveau_mc_engine {
282 int (*init)(struct drm_device *dev);
283 void (*takedown)(struct drm_device *dev);
284 };
285
286 struct nouveau_timer_engine {
287 int (*init)(struct drm_device *dev);
288 void (*takedown)(struct drm_device *dev);
289 uint64_t (*read)(struct drm_device *dev);
290 };
291
292 struct nouveau_fb_engine {
293 int num_tiles;
294
295 int (*init)(struct drm_device *dev);
296 void (*takedown)(struct drm_device *dev);
297
298 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
299 uint32_t size, uint32_t pitch);
300 };
301
302 struct nouveau_fifo_engine {
303 int channels;
304
305 struct nouveau_gpuobj *playlist[2];
306 int cur_playlist;
307
308 int (*init)(struct drm_device *);
309 void (*takedown)(struct drm_device *);
310
311 void (*disable)(struct drm_device *);
312 void (*enable)(struct drm_device *);
313 bool (*reassign)(struct drm_device *, bool enable);
314 bool (*cache_pull)(struct drm_device *dev, bool enable);
315
316 int (*channel_id)(struct drm_device *);
317
318 int (*create_context)(struct nouveau_channel *);
319 void (*destroy_context)(struct nouveau_channel *);
320 int (*load_context)(struct nouveau_channel *);
321 int (*unload_context)(struct drm_device *);
322 void (*tlb_flush)(struct drm_device *dev);
323 };
324
325 struct nouveau_pgraph_engine {
326 bool accel_blocked;
327 bool registered;
328 int grctx_size;
329
330 /* NV2x/NV3x context table (0x400780) */
331 struct nouveau_gpuobj *ctx_table;
332
333 int (*init)(struct drm_device *);
334 void (*takedown)(struct drm_device *);
335
336 void (*fifo_access)(struct drm_device *, bool);
337
338 struct nouveau_channel *(*channel)(struct drm_device *);
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
343 void (*tlb_flush)(struct drm_device *dev);
344
345 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
346 uint32_t size, uint32_t pitch);
347 };
348
349 struct nouveau_display_engine {
350 int (*early_init)(struct drm_device *);
351 void (*late_takedown)(struct drm_device *);
352 int (*create)(struct drm_device *);
353 int (*init)(struct drm_device *);
354 void (*destroy)(struct drm_device *);
355 };
356
357 struct nouveau_gpio_engine {
358 int (*init)(struct drm_device *);
359 void (*takedown)(struct drm_device *);
360
361 int (*get)(struct drm_device *, enum dcb_gpio_tag);
362 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
363
364 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
365 };
366
367 struct nouveau_pm_voltage_level {
368 u8 voltage;
369 u8 vid;
370 };
371
372 struct nouveau_pm_voltage {
373 bool supported;
374 u8 vid_mask;
375
376 struct nouveau_pm_voltage_level *level;
377 int nr_level;
378 };
379
380 #define NOUVEAU_PM_MAX_LEVEL 8
381 struct nouveau_pm_level {
382 struct device_attribute dev_attr;
383 char name[32];
384 int id;
385
386 u32 core;
387 u32 memory;
388 u32 shader;
389 u32 unk05;
390
391 u8 voltage;
392 u8 fanspeed;
393
394 u16 memscript;
395 };
396
397 struct nouveau_pm_temp_sensor_constants {
398 u16 offset_constant;
399 s16 offset_mult;
400 u16 offset_div;
401 u16 slope_mult;
402 u16 slope_div;
403 };
404
405 struct nouveau_pm_threshold_temp {
406 s16 critical;
407 s16 down_clock;
408 s16 fan_boost;
409 };
410
411 struct nouveau_pm_memtiming {
412 u32 reg_100220;
413 u32 reg_100224;
414 u32 reg_100228;
415 u32 reg_10022c;
416 u32 reg_100230;
417 u32 reg_100234;
418 u32 reg_100238;
419 u32 reg_10023c;
420 };
421
422 struct nouveau_pm_memtimings {
423 bool supported;
424 struct nouveau_pm_memtiming *timing;
425 int nr_timing;
426 };
427
428 struct nouveau_pm_engine {
429 struct nouveau_pm_voltage voltage;
430 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
431 int nr_perflvl;
432 struct nouveau_pm_memtimings memtimings;
433 struct nouveau_pm_temp_sensor_constants sensor_constants;
434 struct nouveau_pm_threshold_temp threshold_temp;
435
436 struct nouveau_pm_level boot;
437 struct nouveau_pm_level *cur;
438
439 struct device *hwmon;
440 struct notifier_block acpi_nb;
441
442 int (*clock_get)(struct drm_device *, u32 id);
443 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
444 u32 id, int khz);
445 void (*clock_set)(struct drm_device *, void *);
446 int (*voltage_get)(struct drm_device *);
447 int (*voltage_set)(struct drm_device *, int voltage);
448 int (*fanspeed_get)(struct drm_device *);
449 int (*fanspeed_set)(struct drm_device *, int fanspeed);
450 int (*temp_get)(struct drm_device *);
451 };
452
453 struct nouveau_crypt_engine {
454 bool registered;
455
456 int (*init)(struct drm_device *);
457 void (*takedown)(struct drm_device *);
458 int (*create_context)(struct nouveau_channel *);
459 void (*destroy_context)(struct nouveau_channel *);
460 void (*tlb_flush)(struct drm_device *dev);
461 };
462
463 struct nouveau_engine {
464 struct nouveau_instmem_engine instmem;
465 struct nouveau_mc_engine mc;
466 struct nouveau_timer_engine timer;
467 struct nouveau_fb_engine fb;
468 struct nouveau_pgraph_engine graph;
469 struct nouveau_fifo_engine fifo;
470 struct nouveau_display_engine display;
471 struct nouveau_gpio_engine gpio;
472 struct nouveau_pm_engine pm;
473 struct nouveau_crypt_engine crypt;
474 };
475
476 struct nouveau_pll_vals {
477 union {
478 struct {
479 #ifdef __BIG_ENDIAN
480 uint8_t N1, M1, N2, M2;
481 #else
482 uint8_t M1, N1, M2, N2;
483 #endif
484 };
485 struct {
486 uint16_t NM1, NM2;
487 } __attribute__((packed));
488 };
489 int log2P;
490
491 int refclk;
492 };
493
494 enum nv04_fp_display_regs {
495 FP_DISPLAY_END,
496 FP_TOTAL,
497 FP_CRTC,
498 FP_SYNC_START,
499 FP_SYNC_END,
500 FP_VALID_START,
501 FP_VALID_END
502 };
503
504 struct nv04_crtc_reg {
505 unsigned char MiscOutReg;
506 uint8_t CRTC[0xa0];
507 uint8_t CR58[0x10];
508 uint8_t Sequencer[5];
509 uint8_t Graphics[9];
510 uint8_t Attribute[21];
511 unsigned char DAC[768];
512
513 /* PCRTC regs */
514 uint32_t fb_start;
515 uint32_t crtc_cfg;
516 uint32_t cursor_cfg;
517 uint32_t gpio_ext;
518 uint32_t crtc_830;
519 uint32_t crtc_834;
520 uint32_t crtc_850;
521 uint32_t crtc_eng_ctrl;
522
523 /* PRAMDAC regs */
524 uint32_t nv10_cursync;
525 struct nouveau_pll_vals pllvals;
526 uint32_t ramdac_gen_ctrl;
527 uint32_t ramdac_630;
528 uint32_t ramdac_634;
529 uint32_t tv_setup;
530 uint32_t tv_vtotal;
531 uint32_t tv_vskew;
532 uint32_t tv_vsync_delay;
533 uint32_t tv_htotal;
534 uint32_t tv_hskew;
535 uint32_t tv_hsync_delay;
536 uint32_t tv_hsync_delay2;
537 uint32_t fp_horiz_regs[7];
538 uint32_t fp_vert_regs[7];
539 uint32_t dither;
540 uint32_t fp_control;
541 uint32_t dither_regs[6];
542 uint32_t fp_debug_0;
543 uint32_t fp_debug_1;
544 uint32_t fp_debug_2;
545 uint32_t fp_margin_color;
546 uint32_t ramdac_8c0;
547 uint32_t ramdac_a20;
548 uint32_t ramdac_a24;
549 uint32_t ramdac_a34;
550 uint32_t ctv_regs[38];
551 };
552
553 struct nv04_output_reg {
554 uint32_t output;
555 int head;
556 };
557
558 struct nv04_mode_state {
559 struct nv04_crtc_reg crtc_reg[2];
560 uint32_t pllsel;
561 uint32_t sel_clk;
562 };
563
564 enum nouveau_card_type {
565 NV_04 = 0x00,
566 NV_10 = 0x10,
567 NV_20 = 0x20,
568 NV_30 = 0x30,
569 NV_40 = 0x40,
570 NV_50 = 0x50,
571 NV_C0 = 0xc0,
572 };
573
574 struct drm_nouveau_private {
575 struct drm_device *dev;
576
577 /* the card type, takes NV_* as values */
578 enum nouveau_card_type card_type;
579 /* exact chipset, derived from NV_PMC_BOOT_0 */
580 int chipset;
581 int flags;
582
583 void __iomem *mmio;
584
585 spinlock_t ramin_lock;
586 void __iomem *ramin;
587 u32 ramin_size;
588 u32 ramin_base;
589 bool ramin_available;
590 struct drm_mm ramin_heap;
591 struct list_head gpuobj_list;
592 struct list_head classes;
593
594 struct nouveau_bo *vga_ram;
595
596 struct workqueue_struct *wq;
597 struct work_struct irq_work;
598 struct work_struct hpd_work;
599
600 struct {
601 spinlock_t lock;
602 uint32_t hpd0_bits;
603 uint32_t hpd1_bits;
604 } hpd_state;
605
606 struct list_head vbl_waiting;
607
608 struct {
609 struct drm_global_reference mem_global_ref;
610 struct ttm_bo_global_ref bo_global_ref;
611 struct ttm_bo_device bdev;
612 atomic_t validate_sequence;
613 } ttm;
614
615 struct {
616 spinlock_t lock;
617 struct drm_mm heap;
618 struct nouveau_bo *bo;
619 } fence;
620
621 struct {
622 spinlock_t lock;
623 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
624 } channels;
625
626 struct nouveau_engine engine;
627 struct nouveau_channel *channel;
628
629 /* For PFIFO and PGRAPH. */
630 spinlock_t context_switch_lock;
631
632 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
633 struct nouveau_ramht *ramht;
634 struct nouveau_gpuobj *ramfc;
635 struct nouveau_gpuobj *ramro;
636
637 uint32_t ramin_rsvd_vram;
638
639 struct {
640 enum {
641 NOUVEAU_GART_NONE = 0,
642 NOUVEAU_GART_AGP,
643 NOUVEAU_GART_SGDMA
644 } type;
645 uint64_t aper_base;
646 uint64_t aper_size;
647 uint64_t aper_free;
648
649 struct nouveau_gpuobj *sg_ctxdma;
650 struct page *sg_dummy_page;
651 dma_addr_t sg_dummy_bus;
652 } gart_info;
653
654 /* nv10-nv40 tiling regions */
655 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
656
657 /* VRAM/fb configuration */
658 uint64_t vram_size;
659 uint64_t vram_sys_base;
660 u32 vram_rblock_size;
661
662 uint64_t fb_phys;
663 uint64_t fb_available_size;
664 uint64_t fb_mappable_pages;
665 uint64_t fb_aper_free;
666 int fb_mtrr;
667
668 /* G8x/G9x virtual address space */
669 uint64_t vm_gart_base;
670 uint64_t vm_gart_size;
671 uint64_t vm_vram_base;
672 uint64_t vm_vram_size;
673 uint64_t vm_end;
674 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
675 int vm_vram_pt_nr;
676
677 struct nvbios vbios;
678
679 struct nv04_mode_state mode_reg;
680 struct nv04_mode_state saved_reg;
681 uint32_t saved_vga_font[4][16384];
682 uint32_t crtc_owner;
683 uint32_t dac_users[4];
684
685 struct nouveau_suspend_resume {
686 uint32_t *ramin_copy;
687 } susres;
688
689 struct backlight_device *backlight;
690
691 struct nouveau_channel *evo;
692 struct {
693 struct dcb_entry *dcb;
694 u16 script;
695 u32 pclk;
696 } evo_irq;
697
698 struct {
699 struct dentry *channel_root;
700 } debugfs;
701
702 struct nouveau_fbdev *nfbdev;
703 struct apertures_struct *apertures;
704 };
705
706 static inline struct drm_nouveau_private *
707 nouveau_private(struct drm_device *dev)
708 {
709 return dev->dev_private;
710 }
711
712 static inline struct drm_nouveau_private *
713 nouveau_bdev(struct ttm_bo_device *bd)
714 {
715 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
716 }
717
718 static inline int
719 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
720 {
721 struct nouveau_bo *prev;
722
723 if (!pnvbo)
724 return -EINVAL;
725 prev = *pnvbo;
726
727 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
728 if (prev) {
729 struct ttm_buffer_object *bo = &prev->bo;
730
731 ttm_bo_unref(&bo);
732 }
733
734 return 0;
735 }
736
737 /* nouveau_drv.c */
738 extern int nouveau_agpmode;
739 extern int nouveau_duallink;
740 extern int nouveau_uscript_lvds;
741 extern int nouveau_uscript_tmds;
742 extern int nouveau_vram_pushbuf;
743 extern int nouveau_vram_notify;
744 extern int nouveau_fbpercrtc;
745 extern int nouveau_tv_disable;
746 extern char *nouveau_tv_norm;
747 extern int nouveau_reg_debug;
748 extern char *nouveau_vbios;
749 extern int nouveau_ignorelid;
750 extern int nouveau_nofbaccel;
751 extern int nouveau_noaccel;
752 extern int nouveau_force_post;
753 extern int nouveau_override_conntype;
754 extern char *nouveau_perflvl;
755 extern int nouveau_perflvl_wr;
756
757 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
758 extern int nouveau_pci_resume(struct pci_dev *pdev);
759
760 /* nouveau_state.c */
761 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
762 extern int nouveau_load(struct drm_device *, unsigned long flags);
763 extern int nouveau_firstopen(struct drm_device *);
764 extern void nouveau_lastclose(struct drm_device *);
765 extern int nouveau_unload(struct drm_device *);
766 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
767 struct drm_file *);
768 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
769 struct drm_file *);
770 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
771 uint32_t reg, uint32_t mask, uint32_t val);
772 extern bool nouveau_wait_for_idle(struct drm_device *);
773 extern int nouveau_card_init(struct drm_device *);
774
775 /* nouveau_mem.c */
776 extern int nouveau_mem_vram_init(struct drm_device *);
777 extern void nouveau_mem_vram_fini(struct drm_device *);
778 extern int nouveau_mem_gart_init(struct drm_device *);
779 extern void nouveau_mem_gart_fini(struct drm_device *);
780 extern int nouveau_mem_init_agp(struct drm_device *);
781 extern int nouveau_mem_reset_agp(struct drm_device *);
782 extern void nouveau_mem_close(struct drm_device *);
783 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
784 uint32_t addr,
785 uint32_t size,
786 uint32_t pitch);
787 extern void nv10_mem_expire_tiling(struct drm_device *dev,
788 struct nouveau_tile_reg *tile,
789 struct nouveau_fence *fence);
790 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
791 uint32_t size, uint32_t flags,
792 uint64_t phys);
793 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
794 uint32_t size);
795
796 /* nouveau_notifier.c */
797 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
798 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
799 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
800 int cout, uint32_t *offset);
801 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
802 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
803 struct drm_file *);
804 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
805 struct drm_file *);
806
807 /* nouveau_channel.c */
808 extern struct drm_ioctl_desc nouveau_ioctls[];
809 extern int nouveau_max_ioctl;
810 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
811 extern int nouveau_channel_alloc(struct drm_device *dev,
812 struct nouveau_channel **chan,
813 struct drm_file *file_priv,
814 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
815 extern struct nouveau_channel *
816 nouveau_channel_get_unlocked(struct nouveau_channel *);
817 extern struct nouveau_channel *
818 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
819 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
820 extern void nouveau_channel_put(struct nouveau_channel **);
821 extern void nouveau_channel_ref(struct nouveau_channel *chan,
822 struct nouveau_channel **pchan);
823
824 /* nouveau_object.c */
825 #define NVOBJ_CLASS(d,c,e) do { \
826 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
827 if (ret) \
828 return ret; \
829 } while(0)
830
831 #define NVOBJ_MTHD(d,c,m,e) do { \
832 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
833 if (ret) \
834 return ret; \
835 } while(0)
836
837 extern int nouveau_gpuobj_early_init(struct drm_device *);
838 extern int nouveau_gpuobj_init(struct drm_device *);
839 extern void nouveau_gpuobj_takedown(struct drm_device *);
840 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
841 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
842 extern void nouveau_gpuobj_resume(struct drm_device *dev);
843 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
844 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
845 int (*exec)(struct nouveau_channel *,
846 u32 class, u32 mthd, u32 data));
847 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
848 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
849 uint32_t vram_h, uint32_t tt_h);
850 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
851 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
852 uint32_t size, int align, uint32_t flags,
853 struct nouveau_gpuobj **);
854 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
855 struct nouveau_gpuobj **);
856 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
857 u32 size, u32 flags,
858 struct nouveau_gpuobj **);
859 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
860 uint64_t offset, uint64_t size, int access,
861 int target, struct nouveau_gpuobj **);
862 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
863 uint64_t offset, uint64_t size,
864 int access, struct nouveau_gpuobj **,
865 uint32_t *o_ret);
866 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
867 struct nouveau_gpuobj **);
868 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
869 struct drm_file *);
870 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
871 struct drm_file *);
872
873 /* nouveau_irq.c */
874 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
875 extern void nouveau_irq_preinstall(struct drm_device *);
876 extern int nouveau_irq_postinstall(struct drm_device *);
877 extern void nouveau_irq_uninstall(struct drm_device *);
878
879 /* nouveau_sgdma.c */
880 extern int nouveau_sgdma_init(struct drm_device *);
881 extern void nouveau_sgdma_takedown(struct drm_device *);
882 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
883 uint32_t *page);
884 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
885
886 /* nouveau_debugfs.c */
887 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
888 extern int nouveau_debugfs_init(struct drm_minor *);
889 extern void nouveau_debugfs_takedown(struct drm_minor *);
890 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
891 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
892 #else
893 static inline int
894 nouveau_debugfs_init(struct drm_minor *minor)
895 {
896 return 0;
897 }
898
899 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
900 {
901 }
902
903 static inline int
904 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
905 {
906 return 0;
907 }
908
909 static inline void
910 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
911 {
912 }
913 #endif
914
915 /* nouveau_dma.c */
916 extern void nouveau_dma_pre_init(struct nouveau_channel *);
917 extern int nouveau_dma_init(struct nouveau_channel *);
918 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
919
920 /* nouveau_acpi.c */
921 #define ROM_BIOS_PAGE 4096
922 #if defined(CONFIG_ACPI)
923 void nouveau_register_dsm_handler(void);
924 void nouveau_unregister_dsm_handler(void);
925 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
926 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
927 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
928 #else
929 static inline void nouveau_register_dsm_handler(void) {}
930 static inline void nouveau_unregister_dsm_handler(void) {}
931 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
932 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
933 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
934 #endif
935
936 /* nouveau_backlight.c */
937 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
938 extern int nouveau_backlight_init(struct drm_device *);
939 extern void nouveau_backlight_exit(struct drm_device *);
940 #else
941 static inline int nouveau_backlight_init(struct drm_device *dev)
942 {
943 return 0;
944 }
945
946 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
947 #endif
948
949 /* nouveau_bios.c */
950 extern int nouveau_bios_init(struct drm_device *);
951 extern void nouveau_bios_takedown(struct drm_device *dev);
952 extern int nouveau_run_vbios_init(struct drm_device *);
953 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
954 struct dcb_entry *);
955 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
956 enum dcb_gpio_tag);
957 extern struct dcb_connector_table_entry *
958 nouveau_bios_connector_entry(struct drm_device *, int index);
959 extern u32 get_pll_register(struct drm_device *, enum pll_types);
960 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
961 struct pll_lims *);
962 extern int nouveau_bios_run_display_table(struct drm_device *,
963 struct dcb_entry *,
964 uint32_t script, int pxclk);
965 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
966 int *length);
967 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
968 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
969 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
970 bool *dl, bool *if_is_24bit);
971 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
972 int head, int pxclk);
973 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
974 enum LVDS_script, int pxclk);
975
976 /* nouveau_ttm.c */
977 int nouveau_ttm_global_init(struct drm_nouveau_private *);
978 void nouveau_ttm_global_release(struct drm_nouveau_private *);
979 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
980
981 /* nouveau_dp.c */
982 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
983 uint8_t *data, int data_nr);
984 bool nouveau_dp_detect(struct drm_encoder *);
985 bool nouveau_dp_link_train(struct drm_encoder *);
986
987 /* nv04_fb.c */
988 extern int nv04_fb_init(struct drm_device *);
989 extern void nv04_fb_takedown(struct drm_device *);
990
991 /* nv10_fb.c */
992 extern int nv10_fb_init(struct drm_device *);
993 extern void nv10_fb_takedown(struct drm_device *);
994 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
995 uint32_t, uint32_t);
996
997 /* nv30_fb.c */
998 extern int nv30_fb_init(struct drm_device *);
999 extern void nv30_fb_takedown(struct drm_device *);
1000
1001 /* nv40_fb.c */
1002 extern int nv40_fb_init(struct drm_device *);
1003 extern void nv40_fb_takedown(struct drm_device *);
1004 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
1005 uint32_t, uint32_t);
1006 /* nv50_fb.c */
1007 extern int nv50_fb_init(struct drm_device *);
1008 extern void nv50_fb_takedown(struct drm_device *);
1009 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1010
1011 /* nvc0_fb.c */
1012 extern int nvc0_fb_init(struct drm_device *);
1013 extern void nvc0_fb_takedown(struct drm_device *);
1014
1015 /* nv04_fifo.c */
1016 extern int nv04_fifo_init(struct drm_device *);
1017 extern void nv04_fifo_disable(struct drm_device *);
1018 extern void nv04_fifo_enable(struct drm_device *);
1019 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1020 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1021 extern int nv04_fifo_channel_id(struct drm_device *);
1022 extern int nv04_fifo_create_context(struct nouveau_channel *);
1023 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1024 extern int nv04_fifo_load_context(struct nouveau_channel *);
1025 extern int nv04_fifo_unload_context(struct drm_device *);
1026
1027 /* nv10_fifo.c */
1028 extern int nv10_fifo_init(struct drm_device *);
1029 extern int nv10_fifo_channel_id(struct drm_device *);
1030 extern int nv10_fifo_create_context(struct nouveau_channel *);
1031 extern int nv10_fifo_load_context(struct nouveau_channel *);
1032 extern int nv10_fifo_unload_context(struct drm_device *);
1033
1034 /* nv40_fifo.c */
1035 extern int nv40_fifo_init(struct drm_device *);
1036 extern int nv40_fifo_create_context(struct nouveau_channel *);
1037 extern int nv40_fifo_load_context(struct nouveau_channel *);
1038 extern int nv40_fifo_unload_context(struct drm_device *);
1039
1040 /* nv50_fifo.c */
1041 extern int nv50_fifo_init(struct drm_device *);
1042 extern void nv50_fifo_takedown(struct drm_device *);
1043 extern int nv50_fifo_channel_id(struct drm_device *);
1044 extern int nv50_fifo_create_context(struct nouveau_channel *);
1045 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1046 extern int nv50_fifo_load_context(struct nouveau_channel *);
1047 extern int nv50_fifo_unload_context(struct drm_device *);
1048 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1049
1050 /* nvc0_fifo.c */
1051 extern int nvc0_fifo_init(struct drm_device *);
1052 extern void nvc0_fifo_takedown(struct drm_device *);
1053 extern void nvc0_fifo_disable(struct drm_device *);
1054 extern void nvc0_fifo_enable(struct drm_device *);
1055 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1056 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1057 extern int nvc0_fifo_channel_id(struct drm_device *);
1058 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1059 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1060 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1061 extern int nvc0_fifo_unload_context(struct drm_device *);
1062
1063 /* nv04_graph.c */
1064 extern int nv04_graph_init(struct drm_device *);
1065 extern void nv04_graph_takedown(struct drm_device *);
1066 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1067 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1068 extern int nv04_graph_create_context(struct nouveau_channel *);
1069 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1070 extern int nv04_graph_load_context(struct nouveau_channel *);
1071 extern int nv04_graph_unload_context(struct drm_device *);
1072 extern void nv04_graph_context_switch(struct drm_device *);
1073
1074 /* nv10_graph.c */
1075 extern int nv10_graph_init(struct drm_device *);
1076 extern void nv10_graph_takedown(struct drm_device *);
1077 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1078 extern int nv10_graph_create_context(struct nouveau_channel *);
1079 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1080 extern int nv10_graph_load_context(struct nouveau_channel *);
1081 extern int nv10_graph_unload_context(struct drm_device *);
1082 extern void nv10_graph_context_switch(struct drm_device *);
1083 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1084 uint32_t, uint32_t);
1085
1086 /* nv20_graph.c */
1087 extern int nv20_graph_create_context(struct nouveau_channel *);
1088 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1089 extern int nv20_graph_load_context(struct nouveau_channel *);
1090 extern int nv20_graph_unload_context(struct drm_device *);
1091 extern int nv20_graph_init(struct drm_device *);
1092 extern void nv20_graph_takedown(struct drm_device *);
1093 extern int nv30_graph_init(struct drm_device *);
1094 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1095 uint32_t, uint32_t);
1096
1097 /* nv40_graph.c */
1098 extern int nv40_graph_init(struct drm_device *);
1099 extern void nv40_graph_takedown(struct drm_device *);
1100 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1101 extern int nv40_graph_create_context(struct nouveau_channel *);
1102 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1103 extern int nv40_graph_load_context(struct nouveau_channel *);
1104 extern int nv40_graph_unload_context(struct drm_device *);
1105 extern void nv40_grctx_init(struct nouveau_grctx *);
1106 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1107 uint32_t, uint32_t);
1108
1109 /* nv50_graph.c */
1110 extern int nv50_graph_init(struct drm_device *);
1111 extern void nv50_graph_takedown(struct drm_device *);
1112 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1113 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1114 extern int nv50_graph_create_context(struct nouveau_channel *);
1115 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1116 extern int nv50_graph_load_context(struct nouveau_channel *);
1117 extern int nv50_graph_unload_context(struct drm_device *);
1118 extern void nv50_graph_context_switch(struct drm_device *);
1119 extern int nv50_grctx_init(struct nouveau_grctx *);
1120 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1121 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1122
1123 /* nvc0_graph.c */
1124 extern int nvc0_graph_init(struct drm_device *);
1125 extern void nvc0_graph_takedown(struct drm_device *);
1126 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1127 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1128 extern int nvc0_graph_create_context(struct nouveau_channel *);
1129 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1130 extern int nvc0_graph_load_context(struct nouveau_channel *);
1131 extern int nvc0_graph_unload_context(struct drm_device *);
1132
1133 /* nv84_crypt.c */
1134 extern int nv84_crypt_init(struct drm_device *dev);
1135 extern void nv84_crypt_fini(struct drm_device *dev);
1136 extern int nv84_crypt_create_context(struct nouveau_channel *);
1137 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1138 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1139
1140 /* nv04_instmem.c */
1141 extern int nv04_instmem_init(struct drm_device *);
1142 extern void nv04_instmem_takedown(struct drm_device *);
1143 extern int nv04_instmem_suspend(struct drm_device *);
1144 extern void nv04_instmem_resume(struct drm_device *);
1145 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1146 u32 *size, u32 align);
1147 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1148 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1149 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1150 extern void nv04_instmem_flush(struct drm_device *);
1151
1152 /* nv50_instmem.c */
1153 extern int nv50_instmem_init(struct drm_device *);
1154 extern void nv50_instmem_takedown(struct drm_device *);
1155 extern int nv50_instmem_suspend(struct drm_device *);
1156 extern void nv50_instmem_resume(struct drm_device *);
1157 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1158 u32 *size, u32 align);
1159 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1160 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1161 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1162 extern void nv50_instmem_flush(struct drm_device *);
1163 extern void nv84_instmem_flush(struct drm_device *);
1164 extern void nv50_vm_flush(struct drm_device *, int engine);
1165
1166 /* nvc0_instmem.c */
1167 extern int nvc0_instmem_init(struct drm_device *);
1168 extern void nvc0_instmem_takedown(struct drm_device *);
1169 extern int nvc0_instmem_suspend(struct drm_device *);
1170 extern void nvc0_instmem_resume(struct drm_device *);
1171 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1172 u32 *size, u32 align);
1173 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1174 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1175 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1176 extern void nvc0_instmem_flush(struct drm_device *);
1177
1178 /* nv04_mc.c */
1179 extern int nv04_mc_init(struct drm_device *);
1180 extern void nv04_mc_takedown(struct drm_device *);
1181
1182 /* nv40_mc.c */
1183 extern int nv40_mc_init(struct drm_device *);
1184 extern void nv40_mc_takedown(struct drm_device *);
1185
1186 /* nv50_mc.c */
1187 extern int nv50_mc_init(struct drm_device *);
1188 extern void nv50_mc_takedown(struct drm_device *);
1189
1190 /* nv04_timer.c */
1191 extern int nv04_timer_init(struct drm_device *);
1192 extern uint64_t nv04_timer_read(struct drm_device *);
1193 extern void nv04_timer_takedown(struct drm_device *);
1194
1195 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1196 unsigned long arg);
1197
1198 /* nv04_dac.c */
1199 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1200 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1201 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1202 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1203 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1204
1205 /* nv04_dfp.c */
1206 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1207 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1208 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1209 int head, bool dl);
1210 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1211 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1212
1213 /* nv04_tv.c */
1214 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1215 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1216
1217 /* nv17_tv.c */
1218 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1219
1220 /* nv04_display.c */
1221 extern int nv04_display_early_init(struct drm_device *);
1222 extern void nv04_display_late_takedown(struct drm_device *);
1223 extern int nv04_display_create(struct drm_device *);
1224 extern int nv04_display_init(struct drm_device *);
1225 extern void nv04_display_destroy(struct drm_device *);
1226
1227 /* nv04_crtc.c */
1228 extern int nv04_crtc_create(struct drm_device *, int index);
1229
1230 /* nouveau_bo.c */
1231 extern struct ttm_bo_driver nouveau_bo_driver;
1232 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1233 int size, int align, uint32_t flags,
1234 uint32_t tile_mode, uint32_t tile_flags,
1235 bool no_vm, bool mappable, struct nouveau_bo **);
1236 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1237 extern int nouveau_bo_unpin(struct nouveau_bo *);
1238 extern int nouveau_bo_map(struct nouveau_bo *);
1239 extern void nouveau_bo_unmap(struct nouveau_bo *);
1240 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1241 uint32_t busy);
1242 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1243 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1244 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1245 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1246
1247 /* nouveau_fence.c */
1248 struct nouveau_fence;
1249 extern int nouveau_fence_init(struct drm_device *);
1250 extern void nouveau_fence_fini(struct drm_device *);
1251 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1252 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1253 extern void nouveau_fence_update(struct nouveau_channel *);
1254 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1255 bool emit);
1256 extern int nouveau_fence_emit(struct nouveau_fence *);
1257 extern void nouveau_fence_work(struct nouveau_fence *fence,
1258 void (*work)(void *priv, bool signalled),
1259 void *priv);
1260 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1261 extern bool nouveau_fence_signalled(void *obj, void *arg);
1262 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1263 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1264 extern int nouveau_fence_flush(void *obj, void *arg);
1265 extern void nouveau_fence_unref(void **obj);
1266 extern void *nouveau_fence_ref(void *obj);
1267
1268 /* nouveau_gem.c */
1269 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1270 int size, int align, uint32_t flags,
1271 uint32_t tile_mode, uint32_t tile_flags,
1272 bool no_vm, bool mappable, struct nouveau_bo **);
1273 extern int nouveau_gem_object_new(struct drm_gem_object *);
1274 extern void nouveau_gem_object_del(struct drm_gem_object *);
1275 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1276 struct drm_file *);
1277 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1278 struct drm_file *);
1279 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1280 struct drm_file *);
1281 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1282 struct drm_file *);
1283 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1284 struct drm_file *);
1285
1286 /* nv10_gpio.c */
1287 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1288 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1289
1290 /* nv50_gpio.c */
1291 int nv50_gpio_init(struct drm_device *dev);
1292 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1293 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1294 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1295
1296 /* nv50_calc. */
1297 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1298 int *N1, int *M1, int *N2, int *M2, int *P);
1299 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1300 int clk, int *N, int *fN, int *M, int *P);
1301
1302 #ifndef ioread32_native
1303 #ifdef __BIG_ENDIAN
1304 #define ioread16_native ioread16be
1305 #define iowrite16_native iowrite16be
1306 #define ioread32_native ioread32be
1307 #define iowrite32_native iowrite32be
1308 #else /* def __BIG_ENDIAN */
1309 #define ioread16_native ioread16
1310 #define iowrite16_native iowrite16
1311 #define ioread32_native ioread32
1312 #define iowrite32_native iowrite32
1313 #endif /* def __BIG_ENDIAN else */
1314 #endif /* !ioread32_native */
1315
1316 /* channel control reg access */
1317 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1318 {
1319 return ioread32_native(chan->user + reg);
1320 }
1321
1322 static inline void nvchan_wr32(struct nouveau_channel *chan,
1323 unsigned reg, u32 val)
1324 {
1325 iowrite32_native(val, chan->user + reg);
1326 }
1327
1328 /* register access */
1329 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1330 {
1331 struct drm_nouveau_private *dev_priv = dev->dev_private;
1332 return ioread32_native(dev_priv->mmio + reg);
1333 }
1334
1335 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1336 {
1337 struct drm_nouveau_private *dev_priv = dev->dev_private;
1338 iowrite32_native(val, dev_priv->mmio + reg);
1339 }
1340
1341 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1342 {
1343 u32 tmp = nv_rd32(dev, reg);
1344 nv_wr32(dev, reg, (tmp & ~mask) | val);
1345 return tmp;
1346 }
1347
1348 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1349 {
1350 struct drm_nouveau_private *dev_priv = dev->dev_private;
1351 return ioread8(dev_priv->mmio + reg);
1352 }
1353
1354 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1355 {
1356 struct drm_nouveau_private *dev_priv = dev->dev_private;
1357 iowrite8(val, dev_priv->mmio + reg);
1358 }
1359
1360 #define nv_wait(dev, reg, mask, val) \
1361 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1362
1363 /* PRAMIN access */
1364 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1365 {
1366 struct drm_nouveau_private *dev_priv = dev->dev_private;
1367 return ioread32_native(dev_priv->ramin + offset);
1368 }
1369
1370 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1371 {
1372 struct drm_nouveau_private *dev_priv = dev->dev_private;
1373 iowrite32_native(val, dev_priv->ramin + offset);
1374 }
1375
1376 /* object access */
1377 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1378 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1379
1380 /*
1381 * Logging
1382 * Argument d is (struct drm_device *).
1383 */
1384 #define NV_PRINTK(level, d, fmt, arg...) \
1385 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1386 pci_name(d->pdev), ##arg)
1387 #ifndef NV_DEBUG_NOTRACE
1388 #define NV_DEBUG(d, fmt, arg...) do { \
1389 if (drm_debug & DRM_UT_DRIVER) { \
1390 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1391 __LINE__, ##arg); \
1392 } \
1393 } while (0)
1394 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1395 if (drm_debug & DRM_UT_KMS) { \
1396 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1397 __LINE__, ##arg); \
1398 } \
1399 } while (0)
1400 #else
1401 #define NV_DEBUG(d, fmt, arg...) do { \
1402 if (drm_debug & DRM_UT_DRIVER) \
1403 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1404 } while (0)
1405 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1406 if (drm_debug & DRM_UT_KMS) \
1407 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1408 } while (0)
1409 #endif
1410 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1411 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1412 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1413 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1414 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1415
1416 /* nouveau_reg_debug bitmask */
1417 enum {
1418 NOUVEAU_REG_DEBUG_MC = 0x1,
1419 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1420 NOUVEAU_REG_DEBUG_FB = 0x4,
1421 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1422 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1423 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1424 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1425 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1426 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1427 NOUVEAU_REG_DEBUG_EVO = 0x200,
1428 };
1429
1430 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1431 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1432 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1433 } while (0)
1434
1435 static inline bool
1436 nv_two_heads(struct drm_device *dev)
1437 {
1438 struct drm_nouveau_private *dev_priv = dev->dev_private;
1439 const int impl = dev->pci_device & 0x0ff0;
1440
1441 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1442 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1443 return true;
1444
1445 return false;
1446 }
1447
1448 static inline bool
1449 nv_gf4_disp_arch(struct drm_device *dev)
1450 {
1451 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1452 }
1453
1454 static inline bool
1455 nv_two_reg_pll(struct drm_device *dev)
1456 {
1457 struct drm_nouveau_private *dev_priv = dev->dev_private;
1458 const int impl = dev->pci_device & 0x0ff0;
1459
1460 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1461 return true;
1462 return false;
1463 }
1464
1465 static inline bool
1466 nv_match_device(struct drm_device *dev, unsigned device,
1467 unsigned sub_vendor, unsigned sub_device)
1468 {
1469 return dev->pdev->device == device &&
1470 dev->pdev->subsystem_vendor == sub_vendor &&
1471 dev->pdev->subsystem_device == sub_device;
1472 }
1473
1474 #define NV_SW 0x0000506e
1475 #define NV_SW_DMA_SEMAPHORE 0x00000060
1476 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1477 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1478 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1479 #define NV_SW_YIELD 0x00000080
1480 #define NV_SW_DMA_VBLSEM 0x0000018c
1481 #define NV_SW_VBLSEM_OFFSET 0x00000400
1482 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1483 #define NV_SW_VBLSEM_RELEASE 0x00000408
1484
1485 #endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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