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drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 spinlock_t lock;
50 struct list_head channels;
51 struct nouveau_vm *vm;
52 };
53
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
56 {
57 return file_priv ? file_priv->driver_priv : NULL;
58 }
59
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
61
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
66
67 struct nouveau_grctx;
68 struct nouveau_mem;
69 #include "nouveau_vm.h"
70
71 #define MAX_NUM_DCB_ENTRIES 16
72
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
75
76 struct nouveau_mem {
77 struct drm_device *dev;
78
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
81 u8 page_shift;
82
83 struct drm_mm_node *tag;
84 struct list_head regions;
85 dma_addr_t *pages;
86 u32 memtype;
87 u64 offset;
88 u64 size;
89 };
90
91 struct nouveau_tile_reg {
92 bool used;
93 uint32_t addr;
94 uint32_t limit;
95 uint32_t pitch;
96 uint32_t zcomp;
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
99 };
100
101 struct nouveau_bo {
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
104 u32 valid_domains;
105 u32 placements[3];
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
109
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
113 int pbbo_index;
114 bool validate_mapped;
115
116 struct nouveau_channel *channel;
117
118 struct list_head vma_list;
119 unsigned page_shift;
120
121 uint32_t tile_mode;
122 uint32_t tile_flags;
123 struct nouveau_tile_reg *tile;
124
125 struct drm_gem_object *gem;
126 int pin_refcnt;
127 };
128
129 #define nouveau_bo_tile_layout(nvbo) \
130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
131
132 static inline struct nouveau_bo *
133 nouveau_bo(struct ttm_buffer_object *bo)
134 {
135 return container_of(bo, struct nouveau_bo, bo);
136 }
137
138 static inline struct nouveau_bo *
139 nouveau_gem_object(struct drm_gem_object *gem)
140 {
141 return gem ? gem->driver_private : NULL;
142 }
143
144 /* TODO: submit equivalent to TTM generic API upstream? */
145 static inline void __iomem *
146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
147 {
148 bool is_iomem;
149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
150 &nvbo->kmap, &is_iomem);
151 WARN_ON_ONCE(ioptr && !is_iomem);
152 return ioptr;
153 }
154
155 enum nouveau_flags {
156 NV_NFORCE = 0x10000000,
157 NV_NFORCE2 = 0x20000000
158 };
159
160 #define NVOBJ_ENGINE_SW 0
161 #define NVOBJ_ENGINE_GR 1
162 #define NVOBJ_ENGINE_CRYPT 2
163 #define NVOBJ_ENGINE_COPY0 3
164 #define NVOBJ_ENGINE_COPY1 4
165 #define NVOBJ_ENGINE_MPEG 5
166 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
167 #define NVOBJ_ENGINE_BSP 6
168 #define NVOBJ_ENGINE_VP 7
169 #define NVOBJ_ENGINE_DISPLAY 15
170 #define NVOBJ_ENGINE_NR 16
171
172 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
173 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
174 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
175 #define NVOBJ_FLAG_VM (1 << 3)
176 #define NVOBJ_FLAG_VM_USER (1 << 4)
177
178 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
179
180 struct nouveau_gpuobj {
181 struct drm_device *dev;
182 struct kref refcount;
183 struct list_head list;
184
185 void *node;
186 u32 *suspend;
187
188 uint32_t flags;
189
190 u32 size;
191 u32 pinst; /* PRAMIN BAR offset */
192 u32 cinst; /* Channel offset */
193 u64 vinst; /* VRAM address */
194 u64 linst; /* VM address */
195
196 uint32_t engine;
197 uint32_t class;
198
199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
200 void *priv;
201 };
202
203 struct nouveau_page_flip_state {
204 struct list_head head;
205 struct drm_pending_vblank_event *event;
206 int crtc, bpp, pitch, x, y;
207 uint64_t offset;
208 };
209
210 enum nouveau_channel_mutex_class {
211 NOUVEAU_UCHANNEL_MUTEX,
212 NOUVEAU_KCHANNEL_MUTEX
213 };
214
215 struct nouveau_channel {
216 struct drm_device *dev;
217 struct list_head list;
218 int id;
219
220 /* references to the channel data structure */
221 struct kref ref;
222 /* users of the hardware channel resources, the hardware
223 * context will be kicked off when it reaches zero. */
224 atomic_t users;
225 struct mutex mutex;
226
227 /* owner of this fifo */
228 struct drm_file *file_priv;
229 /* mapping of the fifo itself */
230 struct drm_local_map *map;
231
232 /* mapping of the regs controlling the fifo */
233 void __iomem *user;
234 uint32_t user_get;
235 uint32_t user_get_hi;
236 uint32_t user_put;
237
238 /* Fencing */
239 struct {
240 /* lock protects the pending list only */
241 spinlock_t lock;
242 struct list_head pending;
243 uint32_t sequence;
244 uint32_t sequence_ack;
245 atomic_t last_sequence_irq;
246 struct nouveau_vma vma;
247 } fence;
248
249 /* DMA push buffer */
250 struct nouveau_gpuobj *pushbuf;
251 struct nouveau_bo *pushbuf_bo;
252 struct nouveau_vma pushbuf_vma;
253 uint64_t pushbuf_base;
254
255 /* Notifier memory */
256 struct nouveau_bo *notifier_bo;
257 struct nouveau_vma notifier_vma;
258 struct drm_mm notifier_heap;
259
260 /* PFIFO context */
261 struct nouveau_gpuobj *ramfc;
262 struct nouveau_gpuobj *cache;
263 void *fifo_priv;
264
265 /* Execution engine contexts */
266 void *engctx[NVOBJ_ENGINE_NR];
267
268 /* NV50 VM */
269 struct nouveau_vm *vm;
270 struct nouveau_gpuobj *vm_pd;
271
272 /* Objects */
273 struct nouveau_gpuobj *ramin; /* Private instmem */
274 struct drm_mm ramin_heap; /* Private PRAMIN heap */
275 struct nouveau_ramht *ramht; /* Hash table */
276
277 /* GPU object info for stuff used in-kernel (mm_enabled) */
278 uint32_t m2mf_ntfy;
279 uint32_t vram_handle;
280 uint32_t gart_handle;
281 bool accel_done;
282
283 /* Push buffer state (only for drm's channel on !mm_enabled) */
284 struct {
285 int max;
286 int free;
287 int cur;
288 int put;
289 /* access via pushbuf_bo */
290
291 int ib_base;
292 int ib_max;
293 int ib_free;
294 int ib_put;
295 } dma;
296
297 uint32_t sw_subchannel[8];
298
299 struct nouveau_vma dispc_vma[2];
300 struct {
301 struct nouveau_gpuobj *vblsem;
302 uint32_t vblsem_head;
303 uint32_t vblsem_offset;
304 uint32_t vblsem_rval;
305 struct list_head vbl_wait;
306 struct list_head flip;
307 } nvsw;
308
309 struct {
310 bool active;
311 char name[32];
312 struct drm_info_list info;
313 } debugfs;
314 };
315
316 struct nouveau_exec_engine {
317 void (*destroy)(struct drm_device *, int engine);
318 int (*init)(struct drm_device *, int engine);
319 int (*fini)(struct drm_device *, int engine, bool suspend);
320 int (*context_new)(struct nouveau_channel *, int engine);
321 void (*context_del)(struct nouveau_channel *, int engine);
322 int (*object_new)(struct nouveau_channel *, int engine,
323 u32 handle, u16 class);
324 void (*set_tile_region)(struct drm_device *dev, int i);
325 void (*tlb_flush)(struct drm_device *, int engine);
326 };
327
328 struct nouveau_instmem_engine {
329 void *priv;
330
331 int (*init)(struct drm_device *dev);
332 void (*takedown)(struct drm_device *dev);
333 int (*suspend)(struct drm_device *dev);
334 void (*resume)(struct drm_device *dev);
335
336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
337 u32 size, u32 align);
338 void (*put)(struct nouveau_gpuobj *);
339 int (*map)(struct nouveau_gpuobj *);
340 void (*unmap)(struct nouveau_gpuobj *);
341
342 void (*flush)(struct drm_device *);
343 };
344
345 struct nouveau_mc_engine {
346 int (*init)(struct drm_device *dev);
347 void (*takedown)(struct drm_device *dev);
348 };
349
350 struct nouveau_timer_engine {
351 int (*init)(struct drm_device *dev);
352 void (*takedown)(struct drm_device *dev);
353 uint64_t (*read)(struct drm_device *dev);
354 };
355
356 struct nouveau_fb_engine {
357 int num_tiles;
358 struct drm_mm tag_heap;
359 void *priv;
360
361 int (*init)(struct drm_device *dev);
362 void (*takedown)(struct drm_device *dev);
363
364 void (*init_tile_region)(struct drm_device *dev, int i,
365 uint32_t addr, uint32_t size,
366 uint32_t pitch, uint32_t flags);
367 void (*set_tile_region)(struct drm_device *dev, int i);
368 void (*free_tile_region)(struct drm_device *dev, int i);
369 };
370
371 struct nouveau_fifo_engine {
372 void *priv;
373 int channels;
374
375 struct nouveau_gpuobj *playlist[2];
376 int cur_playlist;
377
378 int (*init)(struct drm_device *);
379 void (*takedown)(struct drm_device *);
380
381 void (*disable)(struct drm_device *);
382 void (*enable)(struct drm_device *);
383 bool (*reassign)(struct drm_device *, bool enable);
384 bool (*cache_pull)(struct drm_device *dev, bool enable);
385
386 int (*channel_id)(struct drm_device *);
387
388 int (*create_context)(struct nouveau_channel *);
389 void (*destroy_context)(struct nouveau_channel *);
390 int (*load_context)(struct nouveau_channel *);
391 int (*unload_context)(struct drm_device *);
392 void (*tlb_flush)(struct drm_device *dev);
393 };
394
395 struct nouveau_display_engine {
396 void *priv;
397 int (*early_init)(struct drm_device *);
398 void (*late_takedown)(struct drm_device *);
399 int (*create)(struct drm_device *);
400 void (*destroy)(struct drm_device *);
401 int (*init)(struct drm_device *);
402 void (*fini)(struct drm_device *);
403
404 struct drm_property *dithering_mode;
405 struct drm_property *dithering_depth;
406 struct drm_property *underscan_property;
407 struct drm_property *underscan_hborder_property;
408 struct drm_property *underscan_vborder_property;
409 };
410
411 struct nouveau_gpio_engine {
412 spinlock_t lock;
413 struct list_head isr;
414 int (*init)(struct drm_device *);
415 void (*fini)(struct drm_device *);
416 int (*drive)(struct drm_device *, int line, int dir, int out);
417 int (*sense)(struct drm_device *, int line);
418 void (*irq_enable)(struct drm_device *, int line, bool);
419 };
420
421 struct nouveau_pm_voltage_level {
422 u32 voltage; /* microvolts */
423 u8 vid;
424 };
425
426 struct nouveau_pm_voltage {
427 bool supported;
428 u8 version;
429 u8 vid_mask;
430
431 struct nouveau_pm_voltage_level *level;
432 int nr_level;
433 };
434
435 /* Exclusive upper limits */
436 #define NV_MEM_CL_DDR2_MAX 8
437 #define NV_MEM_WR_DDR2_MAX 9
438 #define NV_MEM_CL_DDR3_MAX 17
439 #define NV_MEM_WR_DDR3_MAX 17
440 #define NV_MEM_CL_GDDR3_MAX 16
441 #define NV_MEM_WR_GDDR3_MAX 18
442 #define NV_MEM_CL_GDDR5_MAX 21
443 #define NV_MEM_WR_GDDR5_MAX 20
444
445 struct nouveau_pm_memtiming {
446 int id;
447
448 u32 reg[9];
449 u32 mr[4];
450
451 u8 tCWL;
452
453 u8 odt;
454 u8 drive_strength;
455 };
456
457 struct nouveau_pm_tbl_header {
458 u8 version;
459 u8 header_len;
460 u8 entry_cnt;
461 u8 entry_len;
462 };
463
464 struct nouveau_pm_tbl_entry {
465 u8 tWR;
466 u8 tWTR;
467 u8 tCL;
468 u8 tRC;
469 u8 empty_4;
470 u8 tRFC; /* Byte 5 */
471 u8 empty_6;
472 u8 tRAS; /* Byte 7 */
473 u8 empty_8;
474 u8 tRP; /* Byte 9 */
475 u8 tRCDRD;
476 u8 tRCDWR;
477 u8 tRRD;
478 u8 tUNK_13;
479 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
480 u8 empty_15;
481 u8 tUNK_16;
482 u8 empty_17;
483 u8 tUNK_18;
484 u8 tCWL;
485 u8 tUNK_20, tUNK_21;
486 };
487
488 #define NOUVEAU_PM_MAX_LEVEL 8
489 struct nouveau_pm_level {
490 struct device_attribute dev_attr;
491 char name[32];
492 int id;
493
494 u32 core;
495 u32 memory;
496 u32 shader;
497 u32 rop;
498 u32 copy;
499 u32 daemon;
500 u32 vdec;
501 u32 dom6;
502 u32 unka0; /* nva3:nvc0 */
503 u32 hub01; /* nvc0- */
504 u32 hub06; /* nvc0- */
505 u32 hub07; /* nvc0- */
506
507 u32 volt_min; /* microvolts */
508 u32 volt_max;
509 u8 fanspeed;
510
511 u16 memscript;
512 struct nouveau_pm_memtiming *timing;
513 };
514
515 struct nouveau_pm_temp_sensor_constants {
516 u16 offset_constant;
517 s16 offset_mult;
518 s16 offset_div;
519 s16 slope_mult;
520 s16 slope_div;
521 };
522
523 struct nouveau_pm_threshold_temp {
524 s16 critical;
525 s16 down_clock;
526 s16 fan_boost;
527 };
528
529 struct nouveau_pm_memtimings {
530 bool supported;
531 struct nouveau_pm_memtiming boot;
532 struct nouveau_pm_memtiming *timing;
533 int nr_timing;
534 int nr_timing_valid;
535 };
536
537 struct nouveau_pm_fan {
538 u32 percent;
539 u32 min_duty;
540 u32 max_duty;
541 u32 pwm_freq;
542 u32 pwm_divisor;
543 };
544
545 struct nouveau_pm_engine {
546 struct nouveau_pm_voltage voltage;
547 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
548 int nr_perflvl;
549 struct nouveau_pm_memtimings memtimings;
550 struct nouveau_pm_temp_sensor_constants sensor_constants;
551 struct nouveau_pm_threshold_temp threshold_temp;
552 struct nouveau_pm_fan fan;
553
554 struct nouveau_pm_level boot;
555 struct nouveau_pm_level *cur;
556
557 struct device *hwmon;
558 struct notifier_block acpi_nb;
559
560 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
561 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
562 int (*clocks_set)(struct drm_device *, void *);
563
564 int (*voltage_get)(struct drm_device *);
565 int (*voltage_set)(struct drm_device *, int voltage);
566 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
567 int (*pwm_set)(struct drm_device *, int line, u32, u32);
568 int (*temp_get)(struct drm_device *);
569 };
570
571 struct nouveau_vram_engine {
572 struct nouveau_mm mm;
573
574 int (*init)(struct drm_device *);
575 void (*takedown)(struct drm_device *dev);
576 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
577 u32 type, struct nouveau_mem **);
578 void (*put)(struct drm_device *, struct nouveau_mem **);
579
580 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
581 };
582
583 struct nouveau_engine {
584 struct nouveau_instmem_engine instmem;
585 struct nouveau_mc_engine mc;
586 struct nouveau_timer_engine timer;
587 struct nouveau_fb_engine fb;
588 struct nouveau_fifo_engine fifo;
589 struct nouveau_display_engine display;
590 struct nouveau_gpio_engine gpio;
591 struct nouveau_pm_engine pm;
592 struct nouveau_vram_engine vram;
593 };
594
595 struct nouveau_pll_vals {
596 union {
597 struct {
598 #ifdef __BIG_ENDIAN
599 uint8_t N1, M1, N2, M2;
600 #else
601 uint8_t M1, N1, M2, N2;
602 #endif
603 };
604 struct {
605 uint16_t NM1, NM2;
606 } __attribute__((packed));
607 };
608 int log2P;
609
610 int refclk;
611 };
612
613 enum nv04_fp_display_regs {
614 FP_DISPLAY_END,
615 FP_TOTAL,
616 FP_CRTC,
617 FP_SYNC_START,
618 FP_SYNC_END,
619 FP_VALID_START,
620 FP_VALID_END
621 };
622
623 struct nv04_crtc_reg {
624 unsigned char MiscOutReg;
625 uint8_t CRTC[0xa0];
626 uint8_t CR58[0x10];
627 uint8_t Sequencer[5];
628 uint8_t Graphics[9];
629 uint8_t Attribute[21];
630 unsigned char DAC[768];
631
632 /* PCRTC regs */
633 uint32_t fb_start;
634 uint32_t crtc_cfg;
635 uint32_t cursor_cfg;
636 uint32_t gpio_ext;
637 uint32_t crtc_830;
638 uint32_t crtc_834;
639 uint32_t crtc_850;
640 uint32_t crtc_eng_ctrl;
641
642 /* PRAMDAC regs */
643 uint32_t nv10_cursync;
644 struct nouveau_pll_vals pllvals;
645 uint32_t ramdac_gen_ctrl;
646 uint32_t ramdac_630;
647 uint32_t ramdac_634;
648 uint32_t tv_setup;
649 uint32_t tv_vtotal;
650 uint32_t tv_vskew;
651 uint32_t tv_vsync_delay;
652 uint32_t tv_htotal;
653 uint32_t tv_hskew;
654 uint32_t tv_hsync_delay;
655 uint32_t tv_hsync_delay2;
656 uint32_t fp_horiz_regs[7];
657 uint32_t fp_vert_regs[7];
658 uint32_t dither;
659 uint32_t fp_control;
660 uint32_t dither_regs[6];
661 uint32_t fp_debug_0;
662 uint32_t fp_debug_1;
663 uint32_t fp_debug_2;
664 uint32_t fp_margin_color;
665 uint32_t ramdac_8c0;
666 uint32_t ramdac_a20;
667 uint32_t ramdac_a24;
668 uint32_t ramdac_a34;
669 uint32_t ctv_regs[38];
670 };
671
672 struct nv04_output_reg {
673 uint32_t output;
674 int head;
675 };
676
677 struct nv04_mode_state {
678 struct nv04_crtc_reg crtc_reg[2];
679 uint32_t pllsel;
680 uint32_t sel_clk;
681 };
682
683 enum nouveau_card_type {
684 NV_04 = 0x00,
685 NV_10 = 0x10,
686 NV_20 = 0x20,
687 NV_30 = 0x30,
688 NV_40 = 0x40,
689 NV_50 = 0x50,
690 NV_C0 = 0xc0,
691 NV_D0 = 0xd0
692 };
693
694 struct drm_nouveau_private {
695 struct drm_device *dev;
696 bool noaccel;
697
698 /* the card type, takes NV_* as values */
699 enum nouveau_card_type card_type;
700 /* exact chipset, derived from NV_PMC_BOOT_0 */
701 int chipset;
702 int flags;
703 u32 crystal;
704
705 void __iomem *mmio;
706
707 spinlock_t ramin_lock;
708 void __iomem *ramin;
709 u32 ramin_size;
710 u32 ramin_base;
711 bool ramin_available;
712 struct drm_mm ramin_heap;
713 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
714 struct list_head gpuobj_list;
715 struct list_head classes;
716
717 struct nouveau_bo *vga_ram;
718
719 /* interrupt handling */
720 void (*irq_handler[32])(struct drm_device *);
721 bool msi_enabled;
722
723 struct list_head vbl_waiting;
724
725 struct {
726 struct drm_global_reference mem_global_ref;
727 struct ttm_bo_global_ref bo_global_ref;
728 struct ttm_bo_device bdev;
729 atomic_t validate_sequence;
730 } ttm;
731
732 struct {
733 spinlock_t lock;
734 struct drm_mm heap;
735 struct nouveau_bo *bo;
736 } fence;
737
738 struct {
739 spinlock_t lock;
740 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
741 } channels;
742
743 struct nouveau_engine engine;
744 struct nouveau_channel *channel;
745
746 /* For PFIFO and PGRAPH. */
747 spinlock_t context_switch_lock;
748
749 /* VM/PRAMIN flush, legacy PRAMIN aperture */
750 spinlock_t vm_lock;
751
752 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
753 struct nouveau_ramht *ramht;
754 struct nouveau_gpuobj *ramfc;
755 struct nouveau_gpuobj *ramro;
756
757 uint32_t ramin_rsvd_vram;
758
759 struct {
760 enum {
761 NOUVEAU_GART_NONE = 0,
762 NOUVEAU_GART_AGP, /* AGP */
763 NOUVEAU_GART_PDMA, /* paged dma object */
764 NOUVEAU_GART_HW /* on-chip gart/vm */
765 } type;
766 uint64_t aper_base;
767 uint64_t aper_size;
768 uint64_t aper_free;
769
770 struct ttm_backend_func *func;
771
772 struct {
773 struct page *page;
774 dma_addr_t addr;
775 } dummy;
776
777 struct nouveau_gpuobj *sg_ctxdma;
778 } gart_info;
779
780 /* nv10-nv40 tiling regions */
781 struct {
782 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
783 spinlock_t lock;
784 } tile;
785
786 /* VRAM/fb configuration */
787 enum {
788 NV_MEM_TYPE_UNKNOWN = 0,
789 NV_MEM_TYPE_STOLEN,
790 NV_MEM_TYPE_SGRAM,
791 NV_MEM_TYPE_SDRAM,
792 NV_MEM_TYPE_DDR1,
793 NV_MEM_TYPE_DDR2,
794 NV_MEM_TYPE_DDR3,
795 NV_MEM_TYPE_GDDR2,
796 NV_MEM_TYPE_GDDR3,
797 NV_MEM_TYPE_GDDR4,
798 NV_MEM_TYPE_GDDR5
799 } vram_type;
800 uint64_t vram_size;
801 uint64_t vram_sys_base;
802 bool vram_rank_B;
803
804 uint64_t fb_available_size;
805 uint64_t fb_mappable_pages;
806 uint64_t fb_aper_free;
807 int fb_mtrr;
808
809 /* BAR control (NV50-) */
810 struct nouveau_vm *bar1_vm;
811 struct nouveau_vm *bar3_vm;
812
813 /* G8x/G9x virtual address space */
814 struct nouveau_vm *chan_vm;
815
816 struct nvbios vbios;
817 u8 *mxms;
818 struct list_head i2c_ports;
819
820 struct nv04_mode_state mode_reg;
821 struct nv04_mode_state saved_reg;
822 uint32_t saved_vga_font[4][16384];
823 uint32_t crtc_owner;
824 uint32_t dac_users[4];
825
826 struct backlight_device *backlight;
827
828 struct {
829 struct dentry *channel_root;
830 } debugfs;
831
832 struct nouveau_fbdev *nfbdev;
833 struct apertures_struct *apertures;
834 };
835
836 static inline struct drm_nouveau_private *
837 nouveau_private(struct drm_device *dev)
838 {
839 return dev->dev_private;
840 }
841
842 static inline struct drm_nouveau_private *
843 nouveau_bdev(struct ttm_bo_device *bd)
844 {
845 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
846 }
847
848 static inline int
849 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
850 {
851 struct nouveau_bo *prev;
852
853 if (!pnvbo)
854 return -EINVAL;
855 prev = *pnvbo;
856
857 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
858 if (prev) {
859 struct ttm_buffer_object *bo = &prev->bo;
860
861 ttm_bo_unref(&bo);
862 }
863
864 return 0;
865 }
866
867 /* nouveau_drv.c */
868 extern int nouveau_modeset;
869 extern int nouveau_agpmode;
870 extern int nouveau_duallink;
871 extern int nouveau_uscript_lvds;
872 extern int nouveau_uscript_tmds;
873 extern int nouveau_vram_pushbuf;
874 extern int nouveau_vram_notify;
875 extern char *nouveau_vram_type;
876 extern int nouveau_fbpercrtc;
877 extern int nouveau_tv_disable;
878 extern char *nouveau_tv_norm;
879 extern int nouveau_reg_debug;
880 extern char *nouveau_vbios;
881 extern int nouveau_ignorelid;
882 extern int nouveau_nofbaccel;
883 extern int nouveau_noaccel;
884 extern int nouveau_force_post;
885 extern int nouveau_override_conntype;
886 extern char *nouveau_perflvl;
887 extern int nouveau_perflvl_wr;
888 extern int nouveau_msi;
889 extern int nouveau_ctxfw;
890 extern int nouveau_mxmdcb;
891
892 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
893 extern int nouveau_pci_resume(struct pci_dev *pdev);
894
895 /* nouveau_state.c */
896 extern int nouveau_open(struct drm_device *, struct drm_file *);
897 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
898 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
899 extern int nouveau_load(struct drm_device *, unsigned long flags);
900 extern int nouveau_firstopen(struct drm_device *);
901 extern void nouveau_lastclose(struct drm_device *);
902 extern int nouveau_unload(struct drm_device *);
903 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
904 struct drm_file *);
905 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
906 struct drm_file *);
907 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
908 uint32_t reg, uint32_t mask, uint32_t val);
909 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
910 uint32_t reg, uint32_t mask, uint32_t val);
911 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
912 bool (*cond)(void *), void *);
913 extern bool nouveau_wait_for_idle(struct drm_device *);
914 extern int nouveau_card_init(struct drm_device *);
915
916 /* nouveau_mem.c */
917 extern int nouveau_mem_vram_init(struct drm_device *);
918 extern void nouveau_mem_vram_fini(struct drm_device *);
919 extern int nouveau_mem_gart_init(struct drm_device *);
920 extern void nouveau_mem_gart_fini(struct drm_device *);
921 extern int nouveau_mem_init_agp(struct drm_device *);
922 extern int nouveau_mem_reset_agp(struct drm_device *);
923 extern void nouveau_mem_close(struct drm_device *);
924 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
925 extern int nouveau_mem_vbios_type(struct drm_device *);
926 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
927 struct drm_device *dev, uint32_t addr, uint32_t size,
928 uint32_t pitch, uint32_t flags);
929 extern void nv10_mem_put_tile_region(struct drm_device *dev,
930 struct nouveau_tile_reg *tile,
931 struct nouveau_fence *fence);
932 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
933 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
934
935 /* nouveau_notifier.c */
936 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
937 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
938 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
939 int cout, uint32_t start, uint32_t end,
940 uint32_t *offset);
941 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
942 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
943 struct drm_file *);
944 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
945 struct drm_file *);
946
947 /* nouveau_channel.c */
948 extern struct drm_ioctl_desc nouveau_ioctls[];
949 extern int nouveau_max_ioctl;
950 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
951 extern int nouveau_channel_alloc(struct drm_device *dev,
952 struct nouveau_channel **chan,
953 struct drm_file *file_priv,
954 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
955 extern struct nouveau_channel *
956 nouveau_channel_get_unlocked(struct nouveau_channel *);
957 extern struct nouveau_channel *
958 nouveau_channel_get(struct drm_file *, int id);
959 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
960 extern void nouveau_channel_put(struct nouveau_channel **);
961 extern void nouveau_channel_ref(struct nouveau_channel *chan,
962 struct nouveau_channel **pchan);
963 extern void nouveau_channel_idle(struct nouveau_channel *chan);
964
965 /* nouveau_object.c */
966 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
967 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
968 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
969 } while (0)
970
971 #define NVOBJ_ENGINE_DEL(d, e) do { \
972 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
973 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
974 } while (0)
975
976 #define NVOBJ_CLASS(d, c, e) do { \
977 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
978 if (ret) \
979 return ret; \
980 } while (0)
981
982 #define NVOBJ_MTHD(d, c, m, e) do { \
983 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
984 if (ret) \
985 return ret; \
986 } while (0)
987
988 extern int nouveau_gpuobj_early_init(struct drm_device *);
989 extern int nouveau_gpuobj_init(struct drm_device *);
990 extern void nouveau_gpuobj_takedown(struct drm_device *);
991 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
992 extern void nouveau_gpuobj_resume(struct drm_device *dev);
993 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
994 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
995 int (*exec)(struct nouveau_channel *,
996 u32 class, u32 mthd, u32 data));
997 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
998 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
999 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
1000 uint32_t vram_h, uint32_t tt_h);
1001 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
1002 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
1003 uint32_t size, int align, uint32_t flags,
1004 struct nouveau_gpuobj **);
1005 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
1006 struct nouveau_gpuobj **);
1007 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
1008 u32 size, u32 flags,
1009 struct nouveau_gpuobj **);
1010 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
1011 uint64_t offset, uint64_t size, int access,
1012 int target, struct nouveau_gpuobj **);
1013 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
1014 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
1015 u64 size, int target, int access, u32 type,
1016 u32 comp, struct nouveau_gpuobj **pobj);
1017 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
1018 int class, u64 base, u64 size, int target,
1019 int access, u32 type, u32 comp);
1020 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
1021 struct drm_file *);
1022 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
1023 struct drm_file *);
1024
1025 /* nouveau_irq.c */
1026 extern int nouveau_irq_init(struct drm_device *);
1027 extern void nouveau_irq_fini(struct drm_device *);
1028 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1029 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1030 void (*)(struct drm_device *));
1031 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1032 extern void nouveau_irq_preinstall(struct drm_device *);
1033 extern int nouveau_irq_postinstall(struct drm_device *);
1034 extern void nouveau_irq_uninstall(struct drm_device *);
1035
1036 /* nouveau_sgdma.c */
1037 extern int nouveau_sgdma_init(struct drm_device *);
1038 extern void nouveau_sgdma_takedown(struct drm_device *);
1039 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1040 uint32_t offset);
1041 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1042 unsigned long size,
1043 uint32_t page_flags,
1044 struct page *dummy_read_page);
1045
1046 /* nouveau_debugfs.c */
1047 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1048 extern int nouveau_debugfs_init(struct drm_minor *);
1049 extern void nouveau_debugfs_takedown(struct drm_minor *);
1050 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1051 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1052 #else
1053 static inline int
1054 nouveau_debugfs_init(struct drm_minor *minor)
1055 {
1056 return 0;
1057 }
1058
1059 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1060 {
1061 }
1062
1063 static inline int
1064 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1065 {
1066 return 0;
1067 }
1068
1069 static inline void
1070 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1071 {
1072 }
1073 #endif
1074
1075 /* nouveau_dma.c */
1076 extern void nouveau_dma_pre_init(struct nouveau_channel *);
1077 extern int nouveau_dma_init(struct nouveau_channel *);
1078 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1079
1080 /* nouveau_acpi.c */
1081 #define ROM_BIOS_PAGE 4096
1082 #if defined(CONFIG_ACPI)
1083 void nouveau_register_dsm_handler(void);
1084 void nouveau_unregister_dsm_handler(void);
1085 void nouveau_switcheroo_optimus_dsm(void);
1086 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1087 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1088 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1089 #else
1090 static inline void nouveau_register_dsm_handler(void) {}
1091 static inline void nouveau_unregister_dsm_handler(void) {}
1092 static inline void nouveau_switcheroo_optimus_dsm(void) {}
1093 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1094 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1095 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1096 #endif
1097
1098 /* nouveau_backlight.c */
1099 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1100 extern int nouveau_backlight_init(struct drm_device *);
1101 extern void nouveau_backlight_exit(struct drm_device *);
1102 #else
1103 static inline int nouveau_backlight_init(struct drm_device *dev)
1104 {
1105 return 0;
1106 }
1107
1108 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1109 #endif
1110
1111 /* nouveau_bios.c */
1112 extern int nouveau_bios_init(struct drm_device *);
1113 extern void nouveau_bios_takedown(struct drm_device *dev);
1114 extern int nouveau_run_vbios_init(struct drm_device *);
1115 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1116 struct dcb_entry *, int crtc);
1117 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1118 extern struct dcb_connector_table_entry *
1119 nouveau_bios_connector_entry(struct drm_device *, int index);
1120 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1121 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1122 struct pll_lims *);
1123 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1124 struct dcb_entry *, int crtc);
1125 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1126 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1127 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1128 bool *dl, bool *if_is_24bit);
1129 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1130 int head, int pxclk);
1131 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1132 enum LVDS_script, int pxclk);
1133 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1134
1135 /* nouveau_mxm.c */
1136 int nouveau_mxm_init(struct drm_device *dev);
1137 void nouveau_mxm_fini(struct drm_device *dev);
1138
1139 /* nouveau_ttm.c */
1140 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1141 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1142 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1143
1144 /* nouveau_hdmi.c */
1145 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1146
1147 /* nouveau_dp.c */
1148 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1149 uint8_t *data, int data_nr);
1150 bool nouveau_dp_detect(struct drm_encoder *);
1151 bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
1152 void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
1153 u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
1154
1155 /* nv04_fb.c */
1156 extern int nv04_fb_vram_init(struct drm_device *);
1157 extern int nv04_fb_init(struct drm_device *);
1158 extern void nv04_fb_takedown(struct drm_device *);
1159
1160 /* nv10_fb.c */
1161 extern int nv10_fb_vram_init(struct drm_device *dev);
1162 extern int nv1a_fb_vram_init(struct drm_device *dev);
1163 extern int nv10_fb_init(struct drm_device *);
1164 extern void nv10_fb_takedown(struct drm_device *);
1165 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1166 uint32_t addr, uint32_t size,
1167 uint32_t pitch, uint32_t flags);
1168 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1169 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1170
1171 /* nv20_fb.c */
1172 extern int nv20_fb_vram_init(struct drm_device *dev);
1173 extern int nv20_fb_init(struct drm_device *);
1174 extern void nv20_fb_takedown(struct drm_device *);
1175 extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1176 uint32_t addr, uint32_t size,
1177 uint32_t pitch, uint32_t flags);
1178 extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1179 extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1180
1181 /* nv30_fb.c */
1182 extern int nv30_fb_init(struct drm_device *);
1183 extern void nv30_fb_takedown(struct drm_device *);
1184 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1185 uint32_t addr, uint32_t size,
1186 uint32_t pitch, uint32_t flags);
1187 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1188
1189 /* nv40_fb.c */
1190 extern int nv40_fb_vram_init(struct drm_device *dev);
1191 extern int nv40_fb_init(struct drm_device *);
1192 extern void nv40_fb_takedown(struct drm_device *);
1193 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1194
1195 /* nv50_fb.c */
1196 extern int nv50_fb_init(struct drm_device *);
1197 extern void nv50_fb_takedown(struct drm_device *);
1198 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1199
1200 /* nvc0_fb.c */
1201 extern int nvc0_fb_init(struct drm_device *);
1202 extern void nvc0_fb_takedown(struct drm_device *);
1203
1204 /* nv04_fifo.c */
1205 extern int nv04_fifo_init(struct drm_device *);
1206 extern void nv04_fifo_fini(struct drm_device *);
1207 extern void nv04_fifo_disable(struct drm_device *);
1208 extern void nv04_fifo_enable(struct drm_device *);
1209 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1210 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1211 extern int nv04_fifo_channel_id(struct drm_device *);
1212 extern int nv04_fifo_create_context(struct nouveau_channel *);
1213 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1214 extern int nv04_fifo_load_context(struct nouveau_channel *);
1215 extern int nv04_fifo_unload_context(struct drm_device *);
1216 extern void nv04_fifo_isr(struct drm_device *);
1217
1218 /* nv10_fifo.c */
1219 extern int nv10_fifo_init(struct drm_device *);
1220 extern int nv10_fifo_channel_id(struct drm_device *);
1221 extern int nv10_fifo_create_context(struct nouveau_channel *);
1222 extern int nv10_fifo_load_context(struct nouveau_channel *);
1223 extern int nv10_fifo_unload_context(struct drm_device *);
1224
1225 /* nv40_fifo.c */
1226 extern int nv40_fifo_init(struct drm_device *);
1227 extern int nv40_fifo_create_context(struct nouveau_channel *);
1228 extern int nv40_fifo_load_context(struct nouveau_channel *);
1229 extern int nv40_fifo_unload_context(struct drm_device *);
1230
1231 /* nv50_fifo.c */
1232 extern int nv50_fifo_init(struct drm_device *);
1233 extern void nv50_fifo_takedown(struct drm_device *);
1234 extern int nv50_fifo_channel_id(struct drm_device *);
1235 extern int nv50_fifo_create_context(struct nouveau_channel *);
1236 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1237 extern int nv50_fifo_load_context(struct nouveau_channel *);
1238 extern int nv50_fifo_unload_context(struct drm_device *);
1239 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1240
1241 /* nvc0_fifo.c */
1242 extern int nvc0_fifo_init(struct drm_device *);
1243 extern void nvc0_fifo_takedown(struct drm_device *);
1244 extern void nvc0_fifo_disable(struct drm_device *);
1245 extern void nvc0_fifo_enable(struct drm_device *);
1246 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1247 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1248 extern int nvc0_fifo_channel_id(struct drm_device *);
1249 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1250 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1251 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1252 extern int nvc0_fifo_unload_context(struct drm_device *);
1253
1254 /* nv04_graph.c */
1255 extern int nv04_graph_create(struct drm_device *);
1256 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1257 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1258 u32 class, u32 mthd, u32 data);
1259 extern struct nouveau_bitfield nv04_graph_nsource[];
1260
1261 /* nv10_graph.c */
1262 extern int nv10_graph_create(struct drm_device *);
1263 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1264 extern struct nouveau_bitfield nv10_graph_intr[];
1265 extern struct nouveau_bitfield nv10_graph_nstatus[];
1266
1267 /* nv20_graph.c */
1268 extern int nv20_graph_create(struct drm_device *);
1269
1270 /* nv40_graph.c */
1271 extern int nv40_graph_create(struct drm_device *);
1272 extern void nv40_grctx_init(struct nouveau_grctx *);
1273
1274 /* nv50_graph.c */
1275 extern int nv50_graph_create(struct drm_device *);
1276 extern int nv50_grctx_init(struct nouveau_grctx *);
1277 extern struct nouveau_enum nv50_data_error_names[];
1278 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1279
1280 /* nvc0_graph.c */
1281 extern int nvc0_graph_create(struct drm_device *);
1282 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1283
1284 /* nv84_crypt.c */
1285 extern int nv84_crypt_create(struct drm_device *);
1286
1287 /* nv98_crypt.c */
1288 extern int nv98_crypt_create(struct drm_device *dev);
1289
1290 /* nva3_copy.c */
1291 extern int nva3_copy_create(struct drm_device *dev);
1292
1293 /* nvc0_copy.c */
1294 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1295
1296 /* nv31_mpeg.c */
1297 extern int nv31_mpeg_create(struct drm_device *dev);
1298
1299 /* nv50_mpeg.c */
1300 extern int nv50_mpeg_create(struct drm_device *dev);
1301
1302 /* nv84_bsp.c */
1303 /* nv98_bsp.c */
1304 extern int nv84_bsp_create(struct drm_device *dev);
1305
1306 /* nv84_vp.c */
1307 /* nv98_vp.c */
1308 extern int nv84_vp_create(struct drm_device *dev);
1309
1310 /* nv98_ppp.c */
1311 extern int nv98_ppp_create(struct drm_device *dev);
1312
1313 /* nv04_instmem.c */
1314 extern int nv04_instmem_init(struct drm_device *);
1315 extern void nv04_instmem_takedown(struct drm_device *);
1316 extern int nv04_instmem_suspend(struct drm_device *);
1317 extern void nv04_instmem_resume(struct drm_device *);
1318 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1319 u32 size, u32 align);
1320 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1321 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1322 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1323 extern void nv04_instmem_flush(struct drm_device *);
1324
1325 /* nv50_instmem.c */
1326 extern int nv50_instmem_init(struct drm_device *);
1327 extern void nv50_instmem_takedown(struct drm_device *);
1328 extern int nv50_instmem_suspend(struct drm_device *);
1329 extern void nv50_instmem_resume(struct drm_device *);
1330 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1331 u32 size, u32 align);
1332 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1333 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1334 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1335 extern void nv50_instmem_flush(struct drm_device *);
1336 extern void nv84_instmem_flush(struct drm_device *);
1337
1338 /* nvc0_instmem.c */
1339 extern int nvc0_instmem_init(struct drm_device *);
1340 extern void nvc0_instmem_takedown(struct drm_device *);
1341 extern int nvc0_instmem_suspend(struct drm_device *);
1342 extern void nvc0_instmem_resume(struct drm_device *);
1343
1344 /* nv04_mc.c */
1345 extern int nv04_mc_init(struct drm_device *);
1346 extern void nv04_mc_takedown(struct drm_device *);
1347
1348 /* nv40_mc.c */
1349 extern int nv40_mc_init(struct drm_device *);
1350 extern void nv40_mc_takedown(struct drm_device *);
1351
1352 /* nv50_mc.c */
1353 extern int nv50_mc_init(struct drm_device *);
1354 extern void nv50_mc_takedown(struct drm_device *);
1355
1356 /* nv04_timer.c */
1357 extern int nv04_timer_init(struct drm_device *);
1358 extern uint64_t nv04_timer_read(struct drm_device *);
1359 extern void nv04_timer_takedown(struct drm_device *);
1360
1361 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1362 unsigned long arg);
1363
1364 /* nv04_dac.c */
1365 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1366 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1367 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1368 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1369 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1370
1371 /* nv04_dfp.c */
1372 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1373 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1374 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1375 int head, bool dl);
1376 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1377 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1378
1379 /* nv04_tv.c */
1380 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1381 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1382
1383 /* nv17_tv.c */
1384 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1385
1386 /* nv04_display.c */
1387 extern int nv04_display_early_init(struct drm_device *);
1388 extern void nv04_display_late_takedown(struct drm_device *);
1389 extern int nv04_display_create(struct drm_device *);
1390 extern void nv04_display_destroy(struct drm_device *);
1391 extern int nv04_display_init(struct drm_device *);
1392 extern void nv04_display_fini(struct drm_device *);
1393
1394 /* nvd0_display.c */
1395 extern int nvd0_display_create(struct drm_device *);
1396 extern void nvd0_display_destroy(struct drm_device *);
1397 extern int nvd0_display_init(struct drm_device *);
1398 extern void nvd0_display_fini(struct drm_device *);
1399 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1400 void nvd0_display_flip_stop(struct drm_crtc *);
1401 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1402 struct nouveau_channel *, u32 swap_interval);
1403
1404 /* nv04_crtc.c */
1405 extern int nv04_crtc_create(struct drm_device *, int index);
1406
1407 /* nouveau_bo.c */
1408 extern struct ttm_bo_driver nouveau_bo_driver;
1409 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1410 uint32_t flags, uint32_t tile_mode,
1411 uint32_t tile_flags, struct nouveau_bo **);
1412 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1413 extern int nouveau_bo_unpin(struct nouveau_bo *);
1414 extern int nouveau_bo_map(struct nouveau_bo *);
1415 extern void nouveau_bo_unmap(struct nouveau_bo *);
1416 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1417 uint32_t busy);
1418 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1419 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1420 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1421 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1422 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1423 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1424 bool no_wait_reserve, bool no_wait_gpu);
1425
1426 extern struct nouveau_vma *
1427 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1428 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1429 struct nouveau_vma *);
1430 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1431
1432 /* nouveau_fence.c */
1433 struct nouveau_fence;
1434 extern int nouveau_fence_init(struct drm_device *);
1435 extern void nouveau_fence_fini(struct drm_device *);
1436 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1437 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1438 extern void nouveau_fence_update(struct nouveau_channel *);
1439 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1440 bool emit);
1441 extern int nouveau_fence_emit(struct nouveau_fence *);
1442 extern void nouveau_fence_work(struct nouveau_fence *fence,
1443 void (*work)(void *priv, bool signalled),
1444 void *priv);
1445 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1446
1447 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1448 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1449 extern int __nouveau_fence_flush(void *obj, void *arg);
1450 extern void __nouveau_fence_unref(void **obj);
1451 extern void *__nouveau_fence_ref(void *obj);
1452
1453 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1454 {
1455 return __nouveau_fence_signalled(obj, NULL);
1456 }
1457 static inline int
1458 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1459 {
1460 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1461 }
1462 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1463 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1464 {
1465 return __nouveau_fence_flush(obj, NULL);
1466 }
1467 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1468 {
1469 __nouveau_fence_unref((void **)obj);
1470 }
1471 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1472 {
1473 return __nouveau_fence_ref(obj);
1474 }
1475
1476 /* nouveau_gem.c */
1477 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1478 uint32_t domain, uint32_t tile_mode,
1479 uint32_t tile_flags, struct nouveau_bo **);
1480 extern int nouveau_gem_object_new(struct drm_gem_object *);
1481 extern void nouveau_gem_object_del(struct drm_gem_object *);
1482 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1483 extern void nouveau_gem_object_close(struct drm_gem_object *,
1484 struct drm_file *);
1485 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1486 struct drm_file *);
1487 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1488 struct drm_file *);
1489 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1490 struct drm_file *);
1491 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1492 struct drm_file *);
1493 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1494 struct drm_file *);
1495
1496 /* nouveau_display.c */
1497 int nouveau_display_create(struct drm_device *dev);
1498 void nouveau_display_destroy(struct drm_device *dev);
1499 int nouveau_display_init(struct drm_device *dev);
1500 void nouveau_display_fini(struct drm_device *dev);
1501 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1502 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1503 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1504 struct drm_pending_vblank_event *event);
1505 int nouveau_finish_page_flip(struct nouveau_channel *,
1506 struct nouveau_page_flip_state *);
1507 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1508 struct drm_mode_create_dumb *args);
1509 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1510 uint32_t handle, uint64_t *offset);
1511 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1512 uint32_t handle);
1513
1514 /* nv10_gpio.c */
1515 int nv10_gpio_init(struct drm_device *dev);
1516 void nv10_gpio_fini(struct drm_device *dev);
1517 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1518 int nv10_gpio_sense(struct drm_device *dev, int line);
1519 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1520
1521 /* nv50_gpio.c */
1522 int nv50_gpio_init(struct drm_device *dev);
1523 void nv50_gpio_fini(struct drm_device *dev);
1524 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1525 int nv50_gpio_sense(struct drm_device *dev, int line);
1526 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1527 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1528 int nvd0_gpio_sense(struct drm_device *dev, int line);
1529
1530 /* nv50_calc.c */
1531 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1532 int *N1, int *M1, int *N2, int *M2, int *P);
1533 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1534 int clk, int *N, int *fN, int *M, int *P);
1535
1536 #ifndef ioread32_native
1537 #ifdef __BIG_ENDIAN
1538 #define ioread16_native ioread16be
1539 #define iowrite16_native iowrite16be
1540 #define ioread32_native ioread32be
1541 #define iowrite32_native iowrite32be
1542 #else /* def __BIG_ENDIAN */
1543 #define ioread16_native ioread16
1544 #define iowrite16_native iowrite16
1545 #define ioread32_native ioread32
1546 #define iowrite32_native iowrite32
1547 #endif /* def __BIG_ENDIAN else */
1548 #endif /* !ioread32_native */
1549
1550 /* channel control reg access */
1551 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1552 {
1553 return ioread32_native(chan->user + reg);
1554 }
1555
1556 static inline void nvchan_wr32(struct nouveau_channel *chan,
1557 unsigned reg, u32 val)
1558 {
1559 iowrite32_native(val, chan->user + reg);
1560 }
1561
1562 /* register access */
1563 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1564 {
1565 struct drm_nouveau_private *dev_priv = dev->dev_private;
1566 return ioread32_native(dev_priv->mmio + reg);
1567 }
1568
1569 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1570 {
1571 struct drm_nouveau_private *dev_priv = dev->dev_private;
1572 iowrite32_native(val, dev_priv->mmio + reg);
1573 }
1574
1575 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1576 {
1577 u32 tmp = nv_rd32(dev, reg);
1578 nv_wr32(dev, reg, (tmp & ~mask) | val);
1579 return tmp;
1580 }
1581
1582 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1583 {
1584 struct drm_nouveau_private *dev_priv = dev->dev_private;
1585 return ioread8(dev_priv->mmio + reg);
1586 }
1587
1588 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1589 {
1590 struct drm_nouveau_private *dev_priv = dev->dev_private;
1591 iowrite8(val, dev_priv->mmio + reg);
1592 }
1593
1594 #define nv_wait(dev, reg, mask, val) \
1595 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1596 #define nv_wait_ne(dev, reg, mask, val) \
1597 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1598 #define nv_wait_cb(dev, func, data) \
1599 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1600
1601 /* PRAMIN access */
1602 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1603 {
1604 struct drm_nouveau_private *dev_priv = dev->dev_private;
1605 return ioread32_native(dev_priv->ramin + offset);
1606 }
1607
1608 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1609 {
1610 struct drm_nouveau_private *dev_priv = dev->dev_private;
1611 iowrite32_native(val, dev_priv->ramin + offset);
1612 }
1613
1614 /* object access */
1615 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1616 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1617
1618 /*
1619 * Logging
1620 * Argument d is (struct drm_device *).
1621 */
1622 #define NV_PRINTK(level, d, fmt, arg...) \
1623 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1624 pci_name(d->pdev), ##arg)
1625 #ifndef NV_DEBUG_NOTRACE
1626 #define NV_DEBUG(d, fmt, arg...) do { \
1627 if (drm_debug & DRM_UT_DRIVER) { \
1628 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1629 __LINE__, ##arg); \
1630 } \
1631 } while (0)
1632 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1633 if (drm_debug & DRM_UT_KMS) { \
1634 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1635 __LINE__, ##arg); \
1636 } \
1637 } while (0)
1638 #else
1639 #define NV_DEBUG(d, fmt, arg...) do { \
1640 if (drm_debug & DRM_UT_DRIVER) \
1641 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1642 } while (0)
1643 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1644 if (drm_debug & DRM_UT_KMS) \
1645 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1646 } while (0)
1647 #endif
1648 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1649 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1650 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1651 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1652 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1653 #define NV_WARNONCE(d, fmt, arg...) do { \
1654 static int _warned = 0; \
1655 if (!_warned) { \
1656 NV_WARN(d, fmt, ##arg); \
1657 _warned = 1; \
1658 } \
1659 } while(0)
1660
1661 /* nouveau_reg_debug bitmask */
1662 enum {
1663 NOUVEAU_REG_DEBUG_MC = 0x1,
1664 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1665 NOUVEAU_REG_DEBUG_FB = 0x4,
1666 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1667 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1668 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1669 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1670 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1671 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1672 NOUVEAU_REG_DEBUG_EVO = 0x200,
1673 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1674 };
1675
1676 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1677 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1678 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1679 } while (0)
1680
1681 static inline bool
1682 nv_two_heads(struct drm_device *dev)
1683 {
1684 struct drm_nouveau_private *dev_priv = dev->dev_private;
1685 const int impl = dev->pci_device & 0x0ff0;
1686
1687 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1688 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1689 return true;
1690
1691 return false;
1692 }
1693
1694 static inline bool
1695 nv_gf4_disp_arch(struct drm_device *dev)
1696 {
1697 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1698 }
1699
1700 static inline bool
1701 nv_two_reg_pll(struct drm_device *dev)
1702 {
1703 struct drm_nouveau_private *dev_priv = dev->dev_private;
1704 const int impl = dev->pci_device & 0x0ff0;
1705
1706 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1707 return true;
1708 return false;
1709 }
1710
1711 static inline bool
1712 nv_match_device(struct drm_device *dev, unsigned device,
1713 unsigned sub_vendor, unsigned sub_device)
1714 {
1715 return dev->pdev->device == device &&
1716 dev->pdev->subsystem_vendor == sub_vendor &&
1717 dev->pdev->subsystem_device == sub_device;
1718 }
1719
1720 static inline void *
1721 nv_engine(struct drm_device *dev, int engine)
1722 {
1723 struct drm_nouveau_private *dev_priv = dev->dev_private;
1724 return (void *)dev_priv->eng[engine];
1725 }
1726
1727 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1728 * helpful to determine a number of other hardware features
1729 */
1730 static inline int
1731 nv44_graph_class(struct drm_device *dev)
1732 {
1733 struct drm_nouveau_private *dev_priv = dev->dev_private;
1734
1735 if ((dev_priv->chipset & 0xf0) == 0x60)
1736 return 1;
1737
1738 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1739 }
1740
1741 /* memory type/access flags, do not match hardware values */
1742 #define NV_MEM_ACCESS_RO 1
1743 #define NV_MEM_ACCESS_WO 2
1744 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1745 #define NV_MEM_ACCESS_SYS 4
1746 #define NV_MEM_ACCESS_VM 8
1747
1748 #define NV_MEM_TARGET_VRAM 0
1749 #define NV_MEM_TARGET_PCI 1
1750 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1751 #define NV_MEM_TARGET_VM 3
1752 #define NV_MEM_TARGET_GART 4
1753
1754 #define NV_MEM_TYPE_VM 0x7f
1755 #define NV_MEM_COMP_VM 0x03
1756
1757 /* NV_SW object class */
1758 #define NV_SW 0x0000506e
1759 #define NV_SW_DMA_SEMAPHORE 0x00000060
1760 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1761 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1762 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1763 #define NV_SW_YIELD 0x00000080
1764 #define NV_SW_DMA_VBLSEM 0x0000018c
1765 #define NV_SW_VBLSEM_OFFSET 0x00000400
1766 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1767 #define NV_SW_VBLSEM_RELEASE 0x00000408
1768 #define NV_SW_PAGE_FLIP 0x00000500
1769
1770 #endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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