2 * Copyright (C) 2006 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Ben Skeggs <darktama@iinet.net.au>
35 #include "nouveau_drm.h"
36 #include "nouveau_drv.h"
37 #include "nouveau_reg.h"
38 #include "nouveau_ramht.h"
39 #include <linux/ratelimit.h>
41 /* needed for hotplug irq */
42 #include "nouveau_connector.h"
43 #include "nv50_display.h"
46 nouveau_irq_preinstall(struct drm_device
*dev
)
48 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
51 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, 0);
53 if (dev_priv
->card_type
>= NV_50
) {
54 INIT_WORK(&dev_priv
->irq_work
, nv50_display_irq_handler_bh
);
55 INIT_WORK(&dev_priv
->hpd_work
, nv50_display_irq_hotplug_bh
);
56 INIT_LIST_HEAD(&dev_priv
->vbl_waiting
);
61 nouveau_irq_postinstall(struct drm_device
*dev
)
64 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, NV_PMC_INTR_EN_0_MASTER_ENABLE
);
69 nouveau_irq_uninstall(struct drm_device
*dev
)
72 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, 0);
76 nouveau_call_method(struct nouveau_channel
*chan
, int class, int mthd
, int data
)
78 struct drm_nouveau_private
*dev_priv
= chan
->dev
->dev_private
;
79 struct nouveau_pgraph_object_method
*grm
;
80 struct nouveau_pgraph_object_class
*grc
;
82 grc
= dev_priv
->engine
.graph
.grclass
;
89 if (grc
->id
!= class || !grc
->methods
)
95 return grm
->exec(chan
, class, mthd
, data
);
103 nouveau_fifo_swmthd(struct nouveau_channel
*chan
, uint32_t addr
, uint32_t data
)
105 struct drm_device
*dev
= chan
->dev
;
106 const int subc
= (addr
>> 13) & 0x7;
107 const int mthd
= addr
& 0x1ffc;
109 if (mthd
== 0x0000) {
110 struct nouveau_gpuobj
*gpuobj
;
112 gpuobj
= nouveau_ramht_find(chan
, data
);
116 if (gpuobj
->engine
!= NVOBJ_ENGINE_SW
)
119 chan
->sw_subchannel
[subc
] = gpuobj
->class;
120 nv_wr32(dev
, NV04_PFIFO_CACHE1_ENGINE
, nv_rd32(dev
,
121 NV04_PFIFO_CACHE1_ENGINE
) & ~(0xf << subc
* 4));
126 if (nv_rd32(dev
, NV04_PFIFO_CACHE1_ENGINE
) & (1 << (subc
*4)))
129 if (nouveau_call_method(chan
, chan
->sw_subchannel
[subc
], mthd
, data
))
136 nouveau_fifo_irq_handler(struct drm_device
*dev
)
138 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
139 struct nouveau_engine
*engine
= &dev_priv
->engine
;
140 uint32_t status
, reassign
;
143 reassign
= nv_rd32(dev
, NV03_PFIFO_CACHES
) & 1;
144 while ((status
= nv_rd32(dev
, NV03_PFIFO_INTR_0
)) && (cnt
++ < 100)) {
145 struct nouveau_channel
*chan
= NULL
;
148 nv_wr32(dev
, NV03_PFIFO_CACHES
, 0);
150 chid
= engine
->fifo
.channel_id(dev
);
151 if (chid
>= 0 && chid
< engine
->fifo
.channels
)
152 chan
= dev_priv
->fifos
[chid
];
153 get
= nv_rd32(dev
, NV03_PFIFO_CACHE1_GET
);
155 if (status
& NV_PFIFO_INTR_CACHE_ERROR
) {
159 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
160 * wrapping on my G80 chips, but CACHE1 isn't big
161 * enough for this much data.. Tests show that it
162 * wraps around to the start at GET=0x800.. No clue
165 ptr
= (get
& 0x7ff) >> 2;
167 if (dev_priv
->card_type
< NV_40
) {
169 NV04_PFIFO_CACHE1_METHOD(ptr
));
171 NV04_PFIFO_CACHE1_DATA(ptr
));
174 NV40_PFIFO_CACHE1_METHOD(ptr
));
176 NV40_PFIFO_CACHE1_DATA(ptr
));
179 if (!chan
|| !nouveau_fifo_swmthd(chan
, mthd
, data
)) {
180 NV_INFO(dev
, "PFIFO_CACHE_ERROR - Ch %d/%d "
181 "Mthd 0x%04x Data 0x%08x\n",
182 chid
, (mthd
>> 13) & 7, mthd
& 0x1ffc,
186 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_PUSH
, 0);
187 nv_wr32(dev
, NV03_PFIFO_INTR_0
,
188 NV_PFIFO_INTR_CACHE_ERROR
);
190 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH0
,
191 nv_rd32(dev
, NV03_PFIFO_CACHE1_PUSH0
) & ~1);
192 nv_wr32(dev
, NV03_PFIFO_CACHE1_GET
, get
+ 4);
193 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH0
,
194 nv_rd32(dev
, NV03_PFIFO_CACHE1_PUSH0
) | 1);
195 nv_wr32(dev
, NV04_PFIFO_CACHE1_HASH
, 0);
197 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_PUSH
,
198 nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_PUSH
) | 1);
199 nv_wr32(dev
, NV04_PFIFO_CACHE1_PULL0
, 1);
201 status
&= ~NV_PFIFO_INTR_CACHE_ERROR
;
204 if (status
& NV_PFIFO_INTR_DMA_PUSHER
) {
205 u32 get
= nv_rd32(dev
, 0x003244);
206 u32 put
= nv_rd32(dev
, 0x003240);
207 u32 push
= nv_rd32(dev
, 0x003220);
208 u32 state
= nv_rd32(dev
, 0x003228);
210 if (dev_priv
->card_type
== NV_50
) {
211 u32 ho_get
= nv_rd32(dev
, 0x003328);
212 u32 ho_put
= nv_rd32(dev
, 0x003320);
213 u32 ib_get
= nv_rd32(dev
, 0x003334);
214 u32 ib_put
= nv_rd32(dev
, 0x003330);
216 NV_INFO(dev
, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
217 "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
218 "State 0x%08x Push 0x%08x\n",
219 chid
, ho_get
, get
, ho_put
, put
, ib_get
, ib_put
,
222 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
223 nv_wr32(dev
, 0x003364, 0x00000000);
224 if (get
!= put
|| ho_get
!= ho_put
) {
225 nv_wr32(dev
, 0x003244, put
);
226 nv_wr32(dev
, 0x003328, ho_put
);
228 if (ib_get
!= ib_put
) {
229 nv_wr32(dev
, 0x003334, ib_put
);
232 NV_INFO(dev
, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
233 "Put 0x%08x State 0x%08x Push 0x%08x\n",
234 chid
, get
, put
, state
, push
);
237 nv_wr32(dev
, 0x003244, put
);
240 nv_wr32(dev
, 0x003228, 0x00000000);
241 nv_wr32(dev
, 0x003220, 0x00000001);
242 nv_wr32(dev
, 0x002100, NV_PFIFO_INTR_DMA_PUSHER
);
243 status
&= ~NV_PFIFO_INTR_DMA_PUSHER
;
246 if (status
& NV_PFIFO_INTR_SEMAPHORE
) {
249 status
&= ~NV_PFIFO_INTR_SEMAPHORE
;
250 nv_wr32(dev
, NV03_PFIFO_INTR_0
,
251 NV_PFIFO_INTR_SEMAPHORE
);
253 sem
= nv_rd32(dev
, NV10_PFIFO_CACHE1_SEMAPHORE
);
254 nv_wr32(dev
, NV10_PFIFO_CACHE1_SEMAPHORE
, sem
| 0x1);
256 nv_wr32(dev
, NV03_PFIFO_CACHE1_GET
, get
+ 4);
257 nv_wr32(dev
, NV04_PFIFO_CACHE1_PULL0
, 1);
260 if (dev_priv
->card_type
== NV_50
) {
261 if (status
& 0x00000010) {
262 nv50_fb_vm_trap(dev
, 1, "PFIFO_BAR_FAULT");
263 status
&= ~0x00000010;
264 nv_wr32(dev
, 0x002100, 0x00000010);
269 NV_INFO(dev
, "PFIFO_INTR 0x%08x - Ch %d\n",
271 nv_wr32(dev
, NV03_PFIFO_INTR_0
, status
);
275 nv_wr32(dev
, NV03_PFIFO_CACHES
, reassign
);
279 NV_INFO(dev
, "PFIFO still angry after %d spins, halt\n", cnt
);
280 nv_wr32(dev
, 0x2140, 0);
281 nv_wr32(dev
, 0x140, 0);
284 nv_wr32(dev
, NV03_PMC_INTR_0
, NV_PMC_INTR_0_PFIFO_PENDING
);
287 struct nouveau_bitfield_names
{
292 static struct nouveau_bitfield_names nstatus_names
[] =
294 { NV04_PGRAPH_NSTATUS_STATE_IN_USE
, "STATE_IN_USE" },
295 { NV04_PGRAPH_NSTATUS_INVALID_STATE
, "INVALID_STATE" },
296 { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT
, "BAD_ARGUMENT" },
297 { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT
, "PROTECTION_FAULT" }
300 static struct nouveau_bitfield_names nstatus_names_nv10
[] =
302 { NV10_PGRAPH_NSTATUS_STATE_IN_USE
, "STATE_IN_USE" },
303 { NV10_PGRAPH_NSTATUS_INVALID_STATE
, "INVALID_STATE" },
304 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT
, "BAD_ARGUMENT" },
305 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT
, "PROTECTION_FAULT" }
308 static struct nouveau_bitfield_names nsource_names
[] =
310 { NV03_PGRAPH_NSOURCE_NOTIFICATION
, "NOTIFICATION" },
311 { NV03_PGRAPH_NSOURCE_DATA_ERROR
, "DATA_ERROR" },
312 { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR
, "PROTECTION_ERROR" },
313 { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION
, "RANGE_EXCEPTION" },
314 { NV03_PGRAPH_NSOURCE_LIMIT_COLOR
, "LIMIT_COLOR" },
315 { NV03_PGRAPH_NSOURCE_LIMIT_ZETA
, "LIMIT_ZETA" },
316 { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD
, "ILLEGAL_MTHD" },
317 { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION
, "DMA_R_PROTECTION" },
318 { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION
, "DMA_W_PROTECTION" },
319 { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION
, "FORMAT_EXCEPTION" },
320 { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION
, "PATCH_EXCEPTION" },
321 { NV03_PGRAPH_NSOURCE_STATE_INVALID
, "STATE_INVALID" },
322 { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY
, "DOUBLE_NOTIFY" },
323 { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE
, "NOTIFY_IN_USE" },
324 { NV03_PGRAPH_NSOURCE_METHOD_CNT
, "METHOD_CNT" },
325 { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION
, "BFR_NOTIFICATION" },
326 { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION
, "DMA_VTX_PROTECTION" },
327 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A
, "DMA_WIDTH_A" },
328 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B
, "DMA_WIDTH_B" },
332 nouveau_print_bitfield_names_(uint32_t value
,
333 const struct nouveau_bitfield_names
*namelist
,
334 const int namelist_len
)
337 * Caller must have already printed the KERN_* log level for us.
338 * Also the caller is responsible for adding the newline.
341 for (i
= 0; i
< namelist_len
; ++i
) {
342 uint32_t mask
= namelist
[i
].mask
;
344 printk(" %s", namelist
[i
].name
);
349 printk(" (unknown bits 0x%08x)", value
);
351 #define nouveau_print_bitfield_names(val, namelist) \
352 nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist))
354 struct nouveau_enum_names
{
360 nouveau_print_enum_names_(uint32_t value
,
361 const struct nouveau_enum_names
*namelist
,
362 const int namelist_len
)
365 * Caller must have already printed the KERN_* log level for us.
366 * Also the caller is responsible for adding the newline.
369 for (i
= 0; i
< namelist_len
; ++i
) {
370 if (value
== namelist
[i
].value
) {
371 printk("%s", namelist
[i
].name
);
375 printk("unknown value 0x%08x", value
);
377 #define nouveau_print_enum_names(val, namelist) \
378 nouveau_print_enum_names_((val), (namelist), ARRAY_SIZE(namelist))
381 nouveau_graph_chid_from_grctx(struct drm_device
*dev
)
383 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
387 if (dev_priv
->card_type
< NV_40
)
388 return dev_priv
->engine
.fifo
.channels
;
390 if (dev_priv
->card_type
< NV_50
) {
391 inst
= (nv_rd32(dev
, 0x40032c) & 0xfffff) << 4;
393 for (i
= 0; i
< dev_priv
->engine
.fifo
.channels
; i
++) {
394 struct nouveau_channel
*chan
= dev_priv
->fifos
[i
];
396 if (!chan
|| !chan
->ramin_grctx
)
399 if (inst
== chan
->ramin_grctx
->pinst
)
403 inst
= (nv_rd32(dev
, 0x40032c) & 0xfffff) << 12;
405 for (i
= 0; i
< dev_priv
->engine
.fifo
.channels
; i
++) {
406 struct nouveau_channel
*chan
= dev_priv
->fifos
[i
];
408 if (!chan
|| !chan
->ramin
)
411 if (inst
== chan
->ramin
->vinst
)
421 nouveau_graph_trapped_channel(struct drm_device
*dev
, int *channel_ret
)
423 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
424 struct nouveau_engine
*engine
= &dev_priv
->engine
;
427 if (dev_priv
->card_type
< NV_10
)
428 channel
= (nv_rd32(dev
, NV04_PGRAPH_TRAPPED_ADDR
) >> 24) & 0xf;
430 if (dev_priv
->card_type
< NV_40
)
431 channel
= (nv_rd32(dev
, NV04_PGRAPH_TRAPPED_ADDR
) >> 20) & 0x1f;
433 channel
= nouveau_graph_chid_from_grctx(dev
);
435 if (channel
>= engine
->fifo
.channels
|| !dev_priv
->fifos
[channel
]) {
436 NV_ERROR(dev
, "AIII, invalid/inactive channel id %d\n", channel
);
440 *channel_ret
= channel
;
444 struct nouveau_pgraph_trap
{
447 int subc
, mthd
, size
;
448 uint32_t data
, data2
;
449 uint32_t nsource
, nstatus
;
453 nouveau_graph_trap_info(struct drm_device
*dev
,
454 struct nouveau_pgraph_trap
*trap
)
456 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
459 trap
->nsource
= trap
->nstatus
= 0;
460 if (dev_priv
->card_type
< NV_50
) {
461 trap
->nsource
= nv_rd32(dev
, NV03_PGRAPH_NSOURCE
);
462 trap
->nstatus
= nv_rd32(dev
, NV03_PGRAPH_NSTATUS
);
465 if (nouveau_graph_trapped_channel(dev
, &trap
->channel
))
467 address
= nv_rd32(dev
, NV04_PGRAPH_TRAPPED_ADDR
);
469 trap
->mthd
= address
& 0x1FFC;
470 trap
->data
= nv_rd32(dev
, NV04_PGRAPH_TRAPPED_DATA
);
471 if (dev_priv
->card_type
< NV_10
) {
472 trap
->subc
= (address
>> 13) & 0x7;
474 trap
->subc
= (address
>> 16) & 0x7;
475 trap
->data2
= nv_rd32(dev
, NV10_PGRAPH_TRAPPED_DATA_HIGH
);
478 if (dev_priv
->card_type
< NV_10
)
479 trap
->class = nv_rd32(dev
, 0x400180 + trap
->subc
*4) & 0xFF;
480 else if (dev_priv
->card_type
< NV_40
)
481 trap
->class = nv_rd32(dev
, 0x400160 + trap
->subc
*4) & 0xFFF;
482 else if (dev_priv
->card_type
< NV_50
)
483 trap
->class = nv_rd32(dev
, 0x400160 + trap
->subc
*4) & 0xFFFF;
485 trap
->class = nv_rd32(dev
, 0x400814);
489 nouveau_graph_dump_trap_info(struct drm_device
*dev
, const char *id
,
490 struct nouveau_pgraph_trap
*trap
)
492 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
493 uint32_t nsource
= trap
->nsource
, nstatus
= trap
->nstatus
;
495 if (dev_priv
->card_type
< NV_50
) {
496 NV_INFO(dev
, "%s - nSource:", id
);
497 nouveau_print_bitfield_names(nsource
, nsource_names
);
498 printk(", nStatus:");
499 if (dev_priv
->card_type
< NV_10
)
500 nouveau_print_bitfield_names(nstatus
, nstatus_names
);
502 nouveau_print_bitfield_names(nstatus
, nstatus_names_nv10
);
506 NV_INFO(dev
, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
507 "Data 0x%08x:0x%08x\n",
508 id
, trap
->channel
, trap
->subc
,
509 trap
->class, trap
->mthd
,
510 trap
->data2
, trap
->data
);
514 nouveau_pgraph_intr_swmthd(struct drm_device
*dev
,
515 struct nouveau_pgraph_trap
*trap
)
517 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
519 if (trap
->channel
< 0 ||
520 trap
->channel
>= dev_priv
->engine
.fifo
.channels
||
521 !dev_priv
->fifos
[trap
->channel
])
524 return nouveau_call_method(dev_priv
->fifos
[trap
->channel
],
525 trap
->class, trap
->mthd
, trap
->data
);
529 nouveau_pgraph_intr_notify(struct drm_device
*dev
, uint32_t nsource
)
531 struct nouveau_pgraph_trap trap
;
534 nouveau_graph_trap_info(dev
, &trap
);
536 if (nsource
& NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD
) {
537 if (nouveau_pgraph_intr_swmthd(dev
, &trap
))
544 nouveau_graph_dump_trap_info(dev
, "PGRAPH_NOTIFY", &trap
);
547 static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state
, 3 * HZ
, 20);
549 static int nouveau_ratelimit(void)
551 return __ratelimit(&nouveau_ratelimit_state
);
556 nouveau_pgraph_intr_error(struct drm_device
*dev
, uint32_t nsource
)
558 struct nouveau_pgraph_trap trap
;
561 nouveau_graph_trap_info(dev
, &trap
);
562 trap
.nsource
= nsource
;
564 if (nsource
& NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD
) {
565 if (nouveau_pgraph_intr_swmthd(dev
, &trap
))
567 } else if (nsource
& NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION
) {
568 uint32_t v
= nv_rd32(dev
, 0x402000);
569 nv_wr32(dev
, 0x402000, v
);
571 /* dump the error anyway for now: it's useful for
572 Gallium development */
578 if (unhandled
&& nouveau_ratelimit())
579 nouveau_graph_dump_trap_info(dev
, "PGRAPH_ERROR", &trap
);
583 nouveau_pgraph_intr_context_switch(struct drm_device
*dev
)
585 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
586 struct nouveau_engine
*engine
= &dev_priv
->engine
;
589 chid
= engine
->fifo
.channel_id(dev
);
590 NV_DEBUG(dev
, "PGRAPH context switch interrupt channel %x\n", chid
);
592 switch (dev_priv
->card_type
) {
594 nv04_graph_context_switch(dev
);
597 nv10_graph_context_switch(dev
);
600 NV_ERROR(dev
, "Context switch not implemented\n");
606 nouveau_pgraph_irq_handler(struct drm_device
*dev
)
610 while ((status
= nv_rd32(dev
, NV03_PGRAPH_INTR
))) {
611 uint32_t nsource
= nv_rd32(dev
, NV03_PGRAPH_NSOURCE
);
613 if (status
& NV_PGRAPH_INTR_NOTIFY
) {
614 nouveau_pgraph_intr_notify(dev
, nsource
);
616 status
&= ~NV_PGRAPH_INTR_NOTIFY
;
617 nv_wr32(dev
, NV03_PGRAPH_INTR
, NV_PGRAPH_INTR_NOTIFY
);
620 if (status
& NV_PGRAPH_INTR_ERROR
) {
621 nouveau_pgraph_intr_error(dev
, nsource
);
623 status
&= ~NV_PGRAPH_INTR_ERROR
;
624 nv_wr32(dev
, NV03_PGRAPH_INTR
, NV_PGRAPH_INTR_ERROR
);
627 if (status
& NV_PGRAPH_INTR_CONTEXT_SWITCH
) {
628 status
&= ~NV_PGRAPH_INTR_CONTEXT_SWITCH
;
629 nv_wr32(dev
, NV03_PGRAPH_INTR
,
630 NV_PGRAPH_INTR_CONTEXT_SWITCH
);
632 nouveau_pgraph_intr_context_switch(dev
);
636 NV_INFO(dev
, "Unhandled PGRAPH_INTR - 0x%08x\n", status
);
637 nv_wr32(dev
, NV03_PGRAPH_INTR
, status
);
640 if ((nv_rd32(dev
, NV04_PGRAPH_FIFO
) & (1 << 0)) == 0)
641 nv_wr32(dev
, NV04_PGRAPH_FIFO
, 1);
644 nv_wr32(dev
, NV03_PMC_INTR_0
, NV_PMC_INTR_0_PGRAPH_PENDING
);
647 static struct nouveau_enum_names nv50_mp_exec_error_names
[] =
649 { 3, "STACK_UNDERFLOW" },
650 { 4, "QUADON_ACTIVE" },
652 { 0x10, "INVALID_OPCODE" },
653 { 0x40, "BREAKPOINT" },
657 nv50_pgraph_mp_trap(struct drm_device
*dev
, int tpid
, int display
)
659 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
660 uint32_t units
= nv_rd32(dev
, 0x1540);
661 uint32_t addr
, mp10
, status
, pc
, oplow
, ophigh
;
664 for (i
= 0; i
< 4; i
++) {
665 if (!(units
& 1 << (i
+24)))
667 if (dev_priv
->chipset
< 0xa0)
668 addr
= 0x408200 + (tpid
<< 12) + (i
<< 7);
670 addr
= 0x408100 + (tpid
<< 11) + (i
<< 7);
671 mp10
= nv_rd32(dev
, addr
+ 0x10);
672 status
= nv_rd32(dev
, addr
+ 0x14);
676 nv_rd32(dev
, addr
+ 0x20);
677 pc
= nv_rd32(dev
, addr
+ 0x24);
678 oplow
= nv_rd32(dev
, addr
+ 0x70);
679 ophigh
= nv_rd32(dev
, addr
+ 0x74);
680 NV_INFO(dev
, "PGRAPH_TRAP_MP_EXEC - "
681 "TP %d MP %d: ", tpid
, i
);
682 nouveau_print_enum_names(status
,
683 nv50_mp_exec_error_names
);
684 printk(" at %06x warp %d, opcode %08x %08x\n",
685 pc
&0xffffff, pc
>> 24,
688 nv_wr32(dev
, addr
+ 0x10, mp10
);
689 nv_wr32(dev
, addr
+ 0x14, 0);
693 NV_INFO(dev
, "PGRAPH_TRAP_MP_EXEC - TP %d: "
694 "No MPs claiming errors?\n", tpid
);
698 nv50_pgraph_tp_trap(struct drm_device
*dev
, int type
, uint32_t ustatus_old
,
699 uint32_t ustatus_new
, int display
, const char *name
)
701 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
703 uint32_t units
= nv_rd32(dev
, 0x1540);
705 uint32_t ustatus_addr
, ustatus
;
706 for (i
= 0; i
< 16; i
++) {
707 if (!(units
& (1 << i
)))
709 if (dev_priv
->chipset
< 0xa0)
710 ustatus_addr
= ustatus_old
+ (i
<< 12);
712 ustatus_addr
= ustatus_new
+ (i
<< 11);
713 ustatus
= nv_rd32(dev
, ustatus_addr
) & 0x7fffffff;
718 case 6: /* texture error... unknown for now */
719 nv50_fb_vm_trap(dev
, display
, name
);
721 NV_ERROR(dev
, "magic set %d:\n", i
);
722 for (r
= ustatus_addr
+ 4; r
<= ustatus_addr
+ 0x10; r
+= 4)
723 NV_ERROR(dev
, "\t0x%08x: 0x%08x\n", r
,
727 case 7: /* MP error */
728 if (ustatus
& 0x00010000) {
729 nv50_pgraph_mp_trap(dev
, i
, display
);
730 ustatus
&= ~0x00010000;
733 case 8: /* TPDMA error */
735 uint32_t e0c
= nv_rd32(dev
, ustatus_addr
+ 4);
736 uint32_t e10
= nv_rd32(dev
, ustatus_addr
+ 8);
737 uint32_t e14
= nv_rd32(dev
, ustatus_addr
+ 0xc);
738 uint32_t e18
= nv_rd32(dev
, ustatus_addr
+ 0x10);
739 uint32_t e1c
= nv_rd32(dev
, ustatus_addr
+ 0x14);
740 uint32_t e20
= nv_rd32(dev
, ustatus_addr
+ 0x18);
741 uint32_t e24
= nv_rd32(dev
, ustatus_addr
+ 0x1c);
742 nv50_fb_vm_trap(dev
, display
, name
);
743 /* 2d engine destination */
744 if (ustatus
& 0x00000010) {
746 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
748 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
749 i
, e0c
, e18
, e1c
, e20
, e24
);
751 ustatus
&= ~0x00000010;
754 if (ustatus
& 0x00000040) {
756 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
758 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
759 i
, e0c
, e18
, e1c
, e20
, e24
);
761 ustatus
&= ~0x00000040;
763 /* CUDA memory: l[], g[] or stack. */
764 if (ustatus
& 0x00000080) {
766 if (e18
& 0x80000000) {
767 /* g[] read fault? */
768 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
769 i
, e14
, e10
| ((e18
>> 24) & 0x1f));
771 } else if (e18
& 0xc) {
772 /* g[] write fault? */
773 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
774 i
, e14
, e10
| ((e18
>> 7) & 0x1f));
777 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
780 NV_INFO(dev
, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
781 i
, e0c
, e18
, e1c
, e20
, e24
);
783 ustatus
&= ~0x00000080;
790 NV_INFO(dev
, "%s - TP%d: Unhandled ustatus 0x%08x\n", name
, i
, ustatus
);
792 nv_wr32(dev
, ustatus_addr
, 0xc0000000);
796 NV_INFO(dev
, "%s - No TPs claiming errors?\n", name
);
800 nv50_pgraph_trap_handler(struct drm_device
*dev
)
802 struct nouveau_pgraph_trap trap
;
803 uint32_t status
= nv_rd32(dev
, 0x400108);
805 int display
= nouveau_ratelimit();
808 if (!status
&& display
) {
809 nouveau_graph_trap_info(dev
, &trap
);
810 nouveau_graph_dump_trap_info(dev
, "PGRAPH_TRAP", &trap
);
811 NV_INFO(dev
, "PGRAPH_TRAP - no units reporting traps?\n");
814 /* DISPATCH: Relays commands to other units and handles NOTIFY,
815 * COND, QUERY. If you get a trap from it, the command is still stuck
816 * in DISPATCH and you need to do something about it. */
817 if (status
& 0x001) {
818 ustatus
= nv_rd32(dev
, 0x400804) & 0x7fffffff;
819 if (!ustatus
&& display
) {
820 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
823 /* Known to be triggered by screwed up NOTIFY and COND... */
824 if (ustatus
& 0x00000001) {
825 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_DISPATCH_FAULT");
826 nv_wr32(dev
, 0x400500, 0);
827 if (nv_rd32(dev
, 0x400808) & 0x80000000) {
829 if (nouveau_graph_trapped_channel(dev
, &trap
.channel
))
831 trap
.class = nv_rd32(dev
, 0x400814);
832 trap
.mthd
= nv_rd32(dev
, 0x400808) & 0x1ffc;
833 trap
.subc
= (nv_rd32(dev
, 0x400808) >> 16) & 0x7;
834 trap
.data
= nv_rd32(dev
, 0x40080c);
835 trap
.data2
= nv_rd32(dev
, 0x400810);
836 nouveau_graph_dump_trap_info(dev
,
837 "PGRAPH_TRAP_DISPATCH_FAULT", &trap
);
838 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev
, 0x400808));
839 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev
, 0x400848));
841 nv_wr32(dev
, 0x400808, 0);
842 } else if (display
) {
843 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
845 nv_wr32(dev
, 0x4008e8, nv_rd32(dev
, 0x4008e8) & 3);
846 nv_wr32(dev
, 0x400848, 0);
847 ustatus
&= ~0x00000001;
849 if (ustatus
& 0x00000002) {
850 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_DISPATCH_QUERY");
851 nv_wr32(dev
, 0x400500, 0);
852 if (nv_rd32(dev
, 0x40084c) & 0x80000000) {
854 if (nouveau_graph_trapped_channel(dev
, &trap
.channel
))
856 trap
.class = nv_rd32(dev
, 0x400814);
857 trap
.mthd
= nv_rd32(dev
, 0x40084c) & 0x1ffc;
858 trap
.subc
= (nv_rd32(dev
, 0x40084c) >> 16) & 0x7;
859 trap
.data
= nv_rd32(dev
, 0x40085c);
861 nouveau_graph_dump_trap_info(dev
,
862 "PGRAPH_TRAP_DISPATCH_QUERY", &trap
);
863 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev
, 0x40084c));
865 nv_wr32(dev
, 0x40084c, 0);
866 } else if (display
) {
867 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
869 ustatus
&= ~0x00000002;
871 if (ustatus
&& display
)
872 NV_INFO(dev
, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus
);
873 nv_wr32(dev
, 0x400804, 0xc0000000);
874 nv_wr32(dev
, 0x400108, 0x001);
878 /* TRAPs other than dispatch use the "normal" trap regs. */
879 if (status
&& display
) {
880 nouveau_graph_trap_info(dev
, &trap
);
881 nouveau_graph_dump_trap_info(dev
,
882 "PGRAPH_TRAP", &trap
);
885 /* M2MF: Memory to memory copy engine. */
886 if (status
& 0x002) {
887 ustatus
= nv_rd32(dev
, 0x406800) & 0x7fffffff;
888 if (!ustatus
&& display
) {
889 NV_INFO(dev
, "PGRAPH_TRAP_M2MF - no ustatus?\n");
891 if (ustatus
& 0x00000001) {
892 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_M2MF_NOTIFY");
893 ustatus
&= ~0x00000001;
895 if (ustatus
& 0x00000002) {
896 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_M2MF_IN");
897 ustatus
&= ~0x00000002;
899 if (ustatus
& 0x00000004) {
900 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_M2MF_OUT");
901 ustatus
&= ~0x00000004;
903 NV_INFO (dev
, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
904 nv_rd32(dev
, 0x406804),
905 nv_rd32(dev
, 0x406808),
906 nv_rd32(dev
, 0x40680c),
907 nv_rd32(dev
, 0x406810));
908 if (ustatus
&& display
)
909 NV_INFO(dev
, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus
);
910 /* No sane way found yet -- just reset the bugger. */
911 nv_wr32(dev
, 0x400040, 2);
912 nv_wr32(dev
, 0x400040, 0);
913 nv_wr32(dev
, 0x406800, 0xc0000000);
914 nv_wr32(dev
, 0x400108, 0x002);
918 /* VFETCH: Fetches data from vertex buffers. */
919 if (status
& 0x004) {
920 ustatus
= nv_rd32(dev
, 0x400c04) & 0x7fffffff;
921 if (!ustatus
&& display
) {
922 NV_INFO(dev
, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
924 if (ustatus
& 0x00000001) {
925 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_VFETCH_FAULT");
926 NV_INFO (dev
, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
927 nv_rd32(dev
, 0x400c00),
928 nv_rd32(dev
, 0x400c08),
929 nv_rd32(dev
, 0x400c0c),
930 nv_rd32(dev
, 0x400c10));
931 ustatus
&= ~0x00000001;
933 if (ustatus
&& display
)
934 NV_INFO(dev
, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus
);
935 nv_wr32(dev
, 0x400c04, 0xc0000000);
936 nv_wr32(dev
, 0x400108, 0x004);
940 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
941 if (status
& 0x008) {
942 ustatus
= nv_rd32(dev
, 0x401800) & 0x7fffffff;
943 if (!ustatus
&& display
) {
944 NV_INFO(dev
, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
946 if (ustatus
& 0x00000001) {
947 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_STRMOUT_FAULT");
948 NV_INFO (dev
, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
949 nv_rd32(dev
, 0x401804),
950 nv_rd32(dev
, 0x401808),
951 nv_rd32(dev
, 0x40180c),
952 nv_rd32(dev
, 0x401810));
953 ustatus
&= ~0x00000001;
955 if (ustatus
&& display
)
956 NV_INFO(dev
, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus
);
957 /* No sane way found yet -- just reset the bugger. */
958 nv_wr32(dev
, 0x400040, 0x80);
959 nv_wr32(dev
, 0x400040, 0);
960 nv_wr32(dev
, 0x401800, 0xc0000000);
961 nv_wr32(dev
, 0x400108, 0x008);
965 /* CCACHE: Handles code and c[] caches and fills them. */
966 if (status
& 0x010) {
967 ustatus
= nv_rd32(dev
, 0x405018) & 0x7fffffff;
968 if (!ustatus
&& display
) {
969 NV_INFO(dev
, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
971 if (ustatus
& 0x00000001) {
972 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_CCACHE_FAULT");
973 NV_INFO (dev
, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
974 nv_rd32(dev
, 0x405800),
975 nv_rd32(dev
, 0x405804),
976 nv_rd32(dev
, 0x405808),
977 nv_rd32(dev
, 0x40580c),
978 nv_rd32(dev
, 0x405810),
979 nv_rd32(dev
, 0x405814),
980 nv_rd32(dev
, 0x40581c));
981 ustatus
&= ~0x00000001;
983 if (ustatus
&& display
)
984 NV_INFO(dev
, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus
);
985 nv_wr32(dev
, 0x405018, 0xc0000000);
986 nv_wr32(dev
, 0x400108, 0x010);
990 /* Unknown, not seen yet... 0x402000 is the only trap status reg
991 * remaining, so try to handle it anyway. Perhaps related to that
992 * unknown DMA slot on tesla? */
994 nv50_fb_vm_trap(dev
, display
, "PGRAPH_TRAP_UNKC04");
995 ustatus
= nv_rd32(dev
, 0x402000) & 0x7fffffff;
997 NV_INFO(dev
, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus
);
998 nv_wr32(dev
, 0x402000, 0xc0000000);
999 /* no status modifiction on purpose */
1002 /* TEXTURE: CUDA texturing units */
1003 if (status
& 0x040) {
1004 nv50_pgraph_tp_trap (dev
, 6, 0x408900, 0x408600, display
,
1005 "PGRAPH_TRAP_TEXTURE");
1006 nv_wr32(dev
, 0x400108, 0x040);
1010 /* MP: CUDA execution engines. */
1011 if (status
& 0x080) {
1012 nv50_pgraph_tp_trap (dev
, 7, 0x408314, 0x40831c, display
,
1014 nv_wr32(dev
, 0x400108, 0x080);
1018 /* TPDMA: Handles TP-initiated uncached memory accesses:
1019 * l[], g[], stack, 2d surfaces, render targets. */
1020 if (status
& 0x100) {
1021 nv50_pgraph_tp_trap (dev
, 8, 0x408e08, 0x408708, display
,
1022 "PGRAPH_TRAP_TPDMA");
1023 nv_wr32(dev
, 0x400108, 0x100);
1029 NV_INFO(dev
, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
1031 nv_wr32(dev
, 0x400108, status
);
1035 /* There must be a *lot* of these. Will take some time to gather them up. */
1036 static struct nouveau_enum_names nv50_data_error_names
[] =
1038 { 4, "INVALID_VALUE" },
1039 { 5, "INVALID_ENUM" },
1040 { 8, "INVALID_OBJECT" },
1041 { 0xc, "INVALID_BITFIELD" },
1042 { 0x28, "MP_NO_REG_SPACE" },
1043 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
1047 nv50_pgraph_irq_handler(struct drm_device
*dev
)
1049 struct nouveau_pgraph_trap trap
;
1053 while ((status
= nv_rd32(dev
, NV03_PGRAPH_INTR
))) {
1054 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
1055 if (status
& 0x00000001) {
1056 nouveau_graph_trap_info(dev
, &trap
);
1057 if (nouveau_ratelimit())
1058 nouveau_graph_dump_trap_info(dev
,
1059 "PGRAPH_NOTIFY", &trap
);
1060 status
&= ~0x00000001;
1061 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00000001);
1064 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
1065 * when you write 0x200 to 0x50c0 method 0x31c. */
1066 if (status
& 0x00000002) {
1067 nouveau_graph_trap_info(dev
, &trap
);
1068 if (nouveau_ratelimit())
1069 nouveau_graph_dump_trap_info(dev
,
1070 "PGRAPH_COMPUTE_QUERY", &trap
);
1071 status
&= ~0x00000002;
1072 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00000002);
1075 /* Unknown, never seen: 0x4 */
1077 /* ILLEGAL_MTHD: You used a wrong method for this class. */
1078 if (status
& 0x00000010) {
1079 nouveau_graph_trap_info(dev
, &trap
);
1080 if (nouveau_pgraph_intr_swmthd(dev
, &trap
))
1082 if (unhandled
&& nouveau_ratelimit())
1083 nouveau_graph_dump_trap_info(dev
,
1084 "PGRAPH_ILLEGAL_MTHD", &trap
);
1085 status
&= ~0x00000010;
1086 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00000010);
1089 /* ILLEGAL_CLASS: You used a wrong class. */
1090 if (status
& 0x00000020) {
1091 nouveau_graph_trap_info(dev
, &trap
);
1092 if (nouveau_ratelimit())
1093 nouveau_graph_dump_trap_info(dev
,
1094 "PGRAPH_ILLEGAL_CLASS", &trap
);
1095 status
&= ~0x00000020;
1096 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00000020);
1099 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
1100 if (status
& 0x00000040) {
1101 nouveau_graph_trap_info(dev
, &trap
);
1102 if (nouveau_ratelimit())
1103 nouveau_graph_dump_trap_info(dev
,
1104 "PGRAPH_DOUBLE_NOTIFY", &trap
);
1105 status
&= ~0x00000040;
1106 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00000040);
1109 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
1110 if (status
& 0x00001000) {
1111 nv_wr32(dev
, 0x400500, 0x00000000);
1112 nv_wr32(dev
, NV03_PGRAPH_INTR
,
1113 NV_PGRAPH_INTR_CONTEXT_SWITCH
);
1114 nv_wr32(dev
, NV40_PGRAPH_INTR_EN
, nv_rd32(dev
,
1115 NV40_PGRAPH_INTR_EN
) &
1116 ~NV_PGRAPH_INTR_CONTEXT_SWITCH
);
1117 nv_wr32(dev
, 0x400500, 0x00010001);
1119 nv50_graph_context_switch(dev
);
1121 status
&= ~NV_PGRAPH_INTR_CONTEXT_SWITCH
;
1124 /* BUFFER_NOTIFY: Your m2mf transfer finished */
1125 if (status
& 0x00010000) {
1126 nouveau_graph_trap_info(dev
, &trap
);
1127 if (nouveau_ratelimit())
1128 nouveau_graph_dump_trap_info(dev
,
1129 "PGRAPH_BUFFER_NOTIFY", &trap
);
1130 status
&= ~0x00010000;
1131 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00010000);
1134 /* DATA_ERROR: Invalid value for this method, or invalid
1135 * state in current PGRAPH context for this operation */
1136 if (status
& 0x00100000) {
1137 nouveau_graph_trap_info(dev
, &trap
);
1138 if (nouveau_ratelimit()) {
1139 nouveau_graph_dump_trap_info(dev
,
1140 "PGRAPH_DATA_ERROR", &trap
);
1141 NV_INFO (dev
, "PGRAPH_DATA_ERROR - ");
1142 nouveau_print_enum_names(nv_rd32(dev
, 0x400110),
1143 nv50_data_error_names
);
1146 status
&= ~0x00100000;
1147 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00100000);
1150 /* TRAP: Something bad happened in the middle of command
1151 * execution. Has a billion types, subtypes, and even
1153 if (status
& 0x00200000) {
1154 nv50_pgraph_trap_handler(dev
);
1155 status
&= ~0x00200000;
1156 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x00200000);
1159 /* Unknown, never seen: 0x00400000 */
1161 /* SINGLE_STEP: Happens on every method if you turned on
1162 * single stepping in 40008c */
1163 if (status
& 0x01000000) {
1164 nouveau_graph_trap_info(dev
, &trap
);
1165 if (nouveau_ratelimit())
1166 nouveau_graph_dump_trap_info(dev
,
1167 "PGRAPH_SINGLE_STEP", &trap
);
1168 status
&= ~0x01000000;
1169 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0x01000000);
1172 /* 0x02000000 happens when you pause a ctxprog...
1173 * but the only way this can happen that I know is by
1174 * poking the relevant MMIO register, and we don't
1178 NV_INFO(dev
, "Unhandled PGRAPH_INTR - 0x%08x\n",
1180 nv_wr32(dev
, NV03_PGRAPH_INTR
, status
);
1184 const int isb
= (1 << 16) | (1 << 0);
1186 if ((nv_rd32(dev
, 0x400500) & isb
) != isb
)
1187 nv_wr32(dev
, 0x400500,
1188 nv_rd32(dev
, 0x400500) | isb
);
1192 nv_wr32(dev
, NV03_PMC_INTR_0
, NV_PMC_INTR_0_PGRAPH_PENDING
);
1193 if (nv_rd32(dev
, 0x400824) & (1 << 31))
1194 nv_wr32(dev
, 0x400824, nv_rd32(dev
, 0x400824) & ~(1 << 31));
1198 nouveau_crtc_irq_handler(struct drm_device
*dev
, int crtc
)
1201 nv_wr32(dev
, NV_CRTC0_INTSTAT
, NV_CRTC_INTR_VBLANK
);
1204 nv_wr32(dev
, NV_CRTC1_INTSTAT
, NV_CRTC_INTR_VBLANK
);
1208 nouveau_irq_handler(DRM_IRQ_ARGS
)
1210 struct drm_device
*dev
= (struct drm_device
*)arg
;
1211 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1213 unsigned long flags
;
1215 status
= nv_rd32(dev
, NV03_PMC_INTR_0
);
1219 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
1221 if (status
& NV_PMC_INTR_0_PFIFO_PENDING
) {
1222 nouveau_fifo_irq_handler(dev
);
1223 status
&= ~NV_PMC_INTR_0_PFIFO_PENDING
;
1226 if (status
& NV_PMC_INTR_0_PGRAPH_PENDING
) {
1227 if (dev_priv
->card_type
>= NV_50
)
1228 nv50_pgraph_irq_handler(dev
);
1230 nouveau_pgraph_irq_handler(dev
);
1232 status
&= ~NV_PMC_INTR_0_PGRAPH_PENDING
;
1235 if (status
& NV_PMC_INTR_0_CRTCn_PENDING
) {
1236 nouveau_crtc_irq_handler(dev
, (status
>>24)&3);
1237 status
&= ~NV_PMC_INTR_0_CRTCn_PENDING
;
1240 if (status
& (NV_PMC_INTR_0_NV50_DISPLAY_PENDING
|
1241 NV_PMC_INTR_0_NV50_I2C_PENDING
)) {
1242 nv50_display_irq_handler(dev
);
1243 status
&= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING
|
1244 NV_PMC_INTR_0_NV50_I2C_PENDING
);
1248 NV_ERROR(dev
, "Unhandled PMC INTR status bits 0x%08x\n", status
);
1250 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);