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Merge remote branch 'alsa/devel' into topic/misc
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_object.c
1 /*
2 * Copyright (C) 2006 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /*
29 * Authors:
30 * Ben Skeggs <darktama@iinet.net.au>
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37
38 /* NVidia uses context objects to drive drawing operations.
39
40 Context objects can be selected into 8 subchannels in the FIFO,
41 and then used via DMA command buffers.
42
43 A context object is referenced by a user defined handle (CARD32). The HW
44 looks up graphics objects in a hash table in the instance RAM.
45
46 An entry in the hash table consists of 2 CARD32. The first CARD32 contains
47 the handle, the second one a bitfield, that contains the address of the
48 object in instance RAM.
49
50 The format of the second CARD32 seems to be:
51
52 NV4 to NV30:
53
54 15: 0 instance_addr >> 4
55 17:16 engine (here uses 1 = graphics)
56 28:24 channel id (here uses 0)
57 31 valid (use 1)
58
59 NV40:
60
61 15: 0 instance_addr >> 4 (maybe 19-0)
62 21:20 engine (here uses 1 = graphics)
63 I'm unsure about the other bits, but using 0 seems to work.
64
65 The key into the hash table depends on the object handle and channel id and
66 is given as:
67 */
68 static uint32_t
69 nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
70 {
71 struct drm_nouveau_private *dev_priv = dev->dev_private;
72 uint32_t hash = 0;
73 int i;
74
75 NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);
76
77 for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
78 hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
79 handle >>= dev_priv->ramht_bits;
80 }
81
82 if (dev_priv->card_type < NV_50)
83 hash ^= channel << (dev_priv->ramht_bits - 4);
84 hash <<= 3;
85
86 NV_DEBUG(dev, "hash=0x%08x\n", hash);
87 return hash;
88 }
89
90 static int
91 nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
92 uint32_t offset)
93 {
94 struct drm_nouveau_private *dev_priv = dev->dev_private;
95 uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);
96
97 if (dev_priv->card_type < NV_40)
98 return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
99 return (ctx != 0);
100 }
101
102 static int
103 nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
104 {
105 struct drm_nouveau_private *dev_priv = dev->dev_private;
106 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
107 struct nouveau_channel *chan = ref->channel;
108 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
109 uint32_t ctx, co, ho;
110
111 if (!ramht) {
112 NV_ERROR(dev, "No hash table!\n");
113 return -EINVAL;
114 }
115
116 if (dev_priv->card_type < NV_40) {
117 ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
118 (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
119 (ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
120 } else
121 if (dev_priv->card_type < NV_50) {
122 ctx = (ref->instance >> 4) |
123 (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
124 (ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
125 } else {
126 if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
127 ctx = (ref->instance << 10) | 2;
128 } else {
129 ctx = (ref->instance >> 4) |
130 ((ref->gpuobj->engine <<
131 NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
132 }
133 }
134
135 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
136 do {
137 if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
138 NV_DEBUG(dev,
139 "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
140 chan->id, co, ref->handle, ctx);
141 nv_wo32(dev, ramht, (co + 0)/4, ref->handle);
142 nv_wo32(dev, ramht, (co + 4)/4, ctx);
143
144 list_add_tail(&ref->list, &chan->ramht_refs);
145 instmem->flush(dev);
146 return 0;
147 }
148 NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
149 chan->id, co, nv_ro32(dev, ramht, co/4));
150
151 co += 8;
152 if (co >= dev_priv->ramht_size)
153 co = 0;
154 } while (co != ho);
155
156 NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
157 return -ENOMEM;
158 }
159
160 static void
161 nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
162 {
163 struct drm_nouveau_private *dev_priv = dev->dev_private;
164 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
165 struct nouveau_channel *chan = ref->channel;
166 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
167 uint32_t co, ho;
168
169 if (!ramht) {
170 NV_ERROR(dev, "No hash table!\n");
171 return;
172 }
173
174 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
175 do {
176 if (nouveau_ramht_entry_valid(dev, ramht, co) &&
177 (ref->handle == nv_ro32(dev, ramht, (co/4)))) {
178 NV_DEBUG(dev,
179 "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
180 chan->id, co, ref->handle,
181 nv_ro32(dev, ramht, (co + 4)));
182 nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);
183 nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
184
185 list_del(&ref->list);
186 instmem->flush(dev);
187 return;
188 }
189
190 co += 8;
191 if (co >= dev_priv->ramht_size)
192 co = 0;
193 } while (co != ho);
194 list_del(&ref->list);
195
196 NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
197 chan->id, ref->handle);
198 }
199
200 int
201 nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
202 uint32_t size, int align, uint32_t flags,
203 struct nouveau_gpuobj **gpuobj_ret)
204 {
205 struct drm_nouveau_private *dev_priv = dev->dev_private;
206 struct nouveau_engine *engine = &dev_priv->engine;
207 struct nouveau_gpuobj *gpuobj;
208 struct drm_mm *pramin = NULL;
209 int ret;
210
211 NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
212 chan ? chan->id : -1, size, align, flags);
213
214 if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
215 return -EINVAL;
216
217 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
218 if (!gpuobj)
219 return -ENOMEM;
220 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
221 gpuobj->flags = flags;
222 gpuobj->im_channel = chan;
223
224 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
225
226 /* Choose between global instmem heap, and per-channel private
227 * instmem heap. On <NV50 allow requests for private instmem
228 * to be satisfied from global heap if no per-channel area
229 * available.
230 */
231 if (chan) {
232 NV_DEBUG(dev, "channel heap\n");
233 pramin = &chan->ramin_heap;
234 } else {
235 NV_DEBUG(dev, "global heap\n");
236 pramin = &dev_priv->ramin_heap;
237
238 ret = engine->instmem.populate(dev, gpuobj, &size);
239 if (ret) {
240 nouveau_gpuobj_del(dev, &gpuobj);
241 return ret;
242 }
243 }
244
245 /* Allocate a chunk of the PRAMIN aperture */
246 gpuobj->im_pramin = drm_mm_search_free(pramin, size, align, 0);
247 if (gpuobj->im_pramin)
248 gpuobj->im_pramin = drm_mm_get_block(gpuobj->im_pramin, size, align);
249
250 if (!gpuobj->im_pramin) {
251 nouveau_gpuobj_del(dev, &gpuobj);
252 return -ENOMEM;
253 }
254
255 if (!chan) {
256 ret = engine->instmem.bind(dev, gpuobj);
257 if (ret) {
258 nouveau_gpuobj_del(dev, &gpuobj);
259 return ret;
260 }
261 }
262
263 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
264 int i;
265
266 for (i = 0; i < gpuobj->im_pramin->size; i += 4)
267 nv_wo32(dev, gpuobj, i/4, 0);
268 engine->instmem.flush(dev);
269 }
270
271 *gpuobj_ret = gpuobj;
272 return 0;
273 }
274
275 int
276 nouveau_gpuobj_early_init(struct drm_device *dev)
277 {
278 struct drm_nouveau_private *dev_priv = dev->dev_private;
279
280 NV_DEBUG(dev, "\n");
281
282 INIT_LIST_HEAD(&dev_priv->gpuobj_list);
283
284 return 0;
285 }
286
287 int
288 nouveau_gpuobj_init(struct drm_device *dev)
289 {
290 struct drm_nouveau_private *dev_priv = dev->dev_private;
291 int ret;
292
293 NV_DEBUG(dev, "\n");
294
295 if (dev_priv->card_type < NV_50) {
296 ret = nouveau_gpuobj_new_fake(dev,
297 dev_priv->ramht_offset, ~0, dev_priv->ramht_size,
298 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ALLOW_NO_REFS,
299 &dev_priv->ramht, NULL);
300 if (ret)
301 return ret;
302 }
303
304 return 0;
305 }
306
307 void
308 nouveau_gpuobj_takedown(struct drm_device *dev)
309 {
310 struct drm_nouveau_private *dev_priv = dev->dev_private;
311
312 NV_DEBUG(dev, "\n");
313
314 nouveau_gpuobj_del(dev, &dev_priv->ramht);
315 }
316
317 void
318 nouveau_gpuobj_late_takedown(struct drm_device *dev)
319 {
320 struct drm_nouveau_private *dev_priv = dev->dev_private;
321 struct nouveau_gpuobj *gpuobj = NULL;
322 struct list_head *entry, *tmp;
323
324 NV_DEBUG(dev, "\n");
325
326 list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) {
327 gpuobj = list_entry(entry, struct nouveau_gpuobj, list);
328
329 NV_ERROR(dev, "gpuobj %p still exists at takedown, refs=%d\n",
330 gpuobj, gpuobj->refcount);
331 gpuobj->refcount = 0;
332 nouveau_gpuobj_del(dev, &gpuobj);
333 }
334 }
335
336 int
337 nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj)
338 {
339 struct drm_nouveau_private *dev_priv = dev->dev_private;
340 struct nouveau_engine *engine = &dev_priv->engine;
341 struct nouveau_gpuobj *gpuobj;
342 int i;
343
344 NV_DEBUG(dev, "gpuobj %p\n", pgpuobj ? *pgpuobj : NULL);
345
346 if (!dev_priv || !pgpuobj || !(*pgpuobj))
347 return -EINVAL;
348 gpuobj = *pgpuobj;
349
350 if (gpuobj->refcount != 0) {
351 NV_ERROR(dev, "gpuobj refcount is %d\n", gpuobj->refcount);
352 return -EINVAL;
353 }
354
355 if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
356 for (i = 0; i < gpuobj->im_pramin->size; i += 4)
357 nv_wo32(dev, gpuobj, i/4, 0);
358 engine->instmem.flush(dev);
359 }
360
361 if (gpuobj->dtor)
362 gpuobj->dtor(dev, gpuobj);
363
364 if (gpuobj->im_backing && !(gpuobj->flags & NVOBJ_FLAG_FAKE))
365 engine->instmem.clear(dev, gpuobj);
366
367 if (gpuobj->im_pramin) {
368 if (gpuobj->flags & NVOBJ_FLAG_FAKE)
369 kfree(gpuobj->im_pramin);
370 else
371 drm_mm_put_block(gpuobj->im_pramin);
372 }
373
374 list_del(&gpuobj->list);
375
376 *pgpuobj = NULL;
377 kfree(gpuobj);
378 return 0;
379 }
380
381 static int
382 nouveau_gpuobj_instance_get(struct drm_device *dev,
383 struct nouveau_channel *chan,
384 struct nouveau_gpuobj *gpuobj, uint32_t *inst)
385 {
386 struct drm_nouveau_private *dev_priv = dev->dev_private;
387 struct nouveau_gpuobj *cpramin;
388
389 /* <NV50 use PRAMIN address everywhere */
390 if (dev_priv->card_type < NV_50) {
391 *inst = gpuobj->im_pramin->start;
392 return 0;
393 }
394
395 if (chan && gpuobj->im_channel != chan) {
396 NV_ERROR(dev, "Channel mismatch: obj %d, ref %d\n",
397 gpuobj->im_channel->id, chan->id);
398 return -EINVAL;
399 }
400
401 /* NV50 channel-local instance */
402 if (chan) {
403 cpramin = chan->ramin->gpuobj;
404 *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start;
405 return 0;
406 }
407
408 /* NV50 global (VRAM) instance */
409 if (!gpuobj->im_channel) {
410 /* ...from global heap */
411 if (!gpuobj->im_backing) {
412 NV_ERROR(dev, "AII, no VRAM backing gpuobj\n");
413 return -EINVAL;
414 }
415 *inst = gpuobj->im_backing_start;
416 return 0;
417 } else {
418 /* ...from local heap */
419 cpramin = gpuobj->im_channel->ramin->gpuobj;
420 *inst = cpramin->im_backing_start +
421 (gpuobj->im_pramin->start - cpramin->im_pramin->start);
422 return 0;
423 }
424
425 return -EINVAL;
426 }
427
428 int
429 nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan,
430 uint32_t handle, struct nouveau_gpuobj *gpuobj,
431 struct nouveau_gpuobj_ref **ref_ret)
432 {
433 struct drm_nouveau_private *dev_priv = dev->dev_private;
434 struct nouveau_gpuobj_ref *ref;
435 uint32_t instance;
436 int ret;
437
438 NV_DEBUG(dev, "ch%d h=0x%08x gpuobj=%p\n",
439 chan ? chan->id : -1, handle, gpuobj);
440
441 if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL))
442 return -EINVAL;
443
444 if (!chan && !ref_ret)
445 return -EINVAL;
446
447 if (gpuobj->engine == NVOBJ_ENGINE_SW && !gpuobj->im_pramin) {
448 /* sw object */
449 instance = 0x40;
450 } else {
451 ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance);
452 if (ret)
453 return ret;
454 }
455
456 ref = kzalloc(sizeof(*ref), GFP_KERNEL);
457 if (!ref)
458 return -ENOMEM;
459 INIT_LIST_HEAD(&ref->list);
460 ref->gpuobj = gpuobj;
461 ref->channel = chan;
462 ref->instance = instance;
463
464 if (!ref_ret) {
465 ref->handle = handle;
466
467 ret = nouveau_ramht_insert(dev, ref);
468 if (ret) {
469 kfree(ref);
470 return ret;
471 }
472 } else {
473 ref->handle = ~0;
474 *ref_ret = ref;
475 }
476
477 ref->gpuobj->refcount++;
478 return 0;
479 }
480
481 int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **pref)
482 {
483 struct nouveau_gpuobj_ref *ref;
484
485 NV_DEBUG(dev, "ref %p\n", pref ? *pref : NULL);
486
487 if (!dev || !pref || *pref == NULL)
488 return -EINVAL;
489 ref = *pref;
490
491 if (ref->handle != ~0)
492 nouveau_ramht_remove(dev, ref);
493
494 if (ref->gpuobj) {
495 ref->gpuobj->refcount--;
496
497 if (ref->gpuobj->refcount == 0) {
498 if (!(ref->gpuobj->flags & NVOBJ_FLAG_ALLOW_NO_REFS))
499 nouveau_gpuobj_del(dev, &ref->gpuobj);
500 }
501 }
502
503 *pref = NULL;
504 kfree(ref);
505 return 0;
506 }
507
508 int
509 nouveau_gpuobj_new_ref(struct drm_device *dev,
510 struct nouveau_channel *oc, struct nouveau_channel *rc,
511 uint32_t handle, uint32_t size, int align,
512 uint32_t flags, struct nouveau_gpuobj_ref **ref)
513 {
514 struct nouveau_gpuobj *gpuobj = NULL;
515 int ret;
516
517 ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj);
518 if (ret)
519 return ret;
520
521 ret = nouveau_gpuobj_ref_add(dev, rc, handle, gpuobj, ref);
522 if (ret) {
523 nouveau_gpuobj_del(dev, &gpuobj);
524 return ret;
525 }
526
527 return 0;
528 }
529
530 int
531 nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle,
532 struct nouveau_gpuobj_ref **ref_ret)
533 {
534 struct nouveau_gpuobj_ref *ref;
535 struct list_head *entry, *tmp;
536
537 list_for_each_safe(entry, tmp, &chan->ramht_refs) {
538 ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
539
540 if (ref->handle == handle) {
541 if (ref_ret)
542 *ref_ret = ref;
543 return 0;
544 }
545 }
546
547 return -EINVAL;
548 }
549
550 int
551 nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset,
552 uint32_t b_offset, uint32_t size,
553 uint32_t flags, struct nouveau_gpuobj **pgpuobj,
554 struct nouveau_gpuobj_ref **pref)
555 {
556 struct drm_nouveau_private *dev_priv = dev->dev_private;
557 struct nouveau_gpuobj *gpuobj = NULL;
558 int i;
559
560 NV_DEBUG(dev,
561 "p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n",
562 p_offset, b_offset, size, flags);
563
564 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
565 if (!gpuobj)
566 return -ENOMEM;
567 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
568 gpuobj->im_channel = NULL;
569 gpuobj->flags = flags | NVOBJ_FLAG_FAKE;
570
571 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
572
573 if (p_offset != ~0) {
574 gpuobj->im_pramin = kzalloc(sizeof(struct drm_mm_node),
575 GFP_KERNEL);
576 if (!gpuobj->im_pramin) {
577 nouveau_gpuobj_del(dev, &gpuobj);
578 return -ENOMEM;
579 }
580 gpuobj->im_pramin->start = p_offset;
581 gpuobj->im_pramin->size = size;
582 }
583
584 if (b_offset != ~0) {
585 gpuobj->im_backing = (struct nouveau_bo *)-1;
586 gpuobj->im_backing_start = b_offset;
587 }
588
589 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
590 for (i = 0; i < gpuobj->im_pramin->size; i += 4)
591 nv_wo32(dev, gpuobj, i/4, 0);
592 dev_priv->engine.instmem.flush(dev);
593 }
594
595 if (pref) {
596 i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref);
597 if (i) {
598 nouveau_gpuobj_del(dev, &gpuobj);
599 return i;
600 }
601 }
602
603 if (pgpuobj)
604 *pgpuobj = gpuobj;
605 return 0;
606 }
607
608
609 static uint32_t
610 nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
611 {
612 struct drm_nouveau_private *dev_priv = dev->dev_private;
613
614 /*XXX: dodgy hack for now */
615 if (dev_priv->card_type >= NV_50)
616 return 24;
617 if (dev_priv->card_type >= NV_40)
618 return 32;
619 return 16;
620 }
621
622 /*
623 DMA objects are used to reference a piece of memory in the
624 framebuffer, PCI or AGP address space. Each object is 16 bytes big
625 and looks as follows:
626
627 entry[0]
628 11:0 class (seems like I can always use 0 here)
629 12 page table present?
630 13 page entry linear?
631 15:14 access: 0 rw, 1 ro, 2 wo
632 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
633 31:20 dma adjust (bits 0-11 of the address)
634 entry[1]
635 dma limit (size of transfer)
636 entry[X]
637 1 0 readonly, 1 readwrite
638 31:12 dma frame address of the page (bits 12-31 of the address)
639 entry[N]
640 page table terminator, same value as the first pte, as does nvidia
641 rivatv uses 0xffffffff
642
643 Non linear page tables need a list of frame addresses afterwards,
644 the rivatv project has some info on this.
645
646 The method below creates a DMA object in instance RAM and returns a handle
647 to it that can be used to set up context objects.
648 */
649 int
650 nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
651 uint64_t offset, uint64_t size, int access,
652 int target, struct nouveau_gpuobj **gpuobj)
653 {
654 struct drm_device *dev = chan->dev;
655 struct drm_nouveau_private *dev_priv = dev->dev_private;
656 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
657 int ret;
658
659 NV_DEBUG(dev, "ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
660 chan->id, class, offset, size);
661 NV_DEBUG(dev, "access=%d target=%d\n", access, target);
662
663 switch (target) {
664 case NV_DMA_TARGET_AGP:
665 offset += dev_priv->gart_info.aper_base;
666 break;
667 default:
668 break;
669 }
670
671 ret = nouveau_gpuobj_new(dev, chan,
672 nouveau_gpuobj_class_instmem_size(dev, class),
673 16, NVOBJ_FLAG_ZERO_ALLOC |
674 NVOBJ_FLAG_ZERO_FREE, gpuobj);
675 if (ret) {
676 NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
677 return ret;
678 }
679
680 if (dev_priv->card_type < NV_50) {
681 uint32_t frame, adjust, pte_flags = 0;
682
683 if (access != NV_DMA_ACCESS_RO)
684 pte_flags |= (1<<1);
685 adjust = offset & 0x00000fff;
686 frame = offset & ~0x00000fff;
687
688 nv_wo32(dev, *gpuobj, 0, ((1<<12) | (1<<13) |
689 (adjust << 20) |
690 (access << 14) |
691 (target << 16) |
692 class));
693 nv_wo32(dev, *gpuobj, 1, size - 1);
694 nv_wo32(dev, *gpuobj, 2, frame | pte_flags);
695 nv_wo32(dev, *gpuobj, 3, frame | pte_flags);
696 } else {
697 uint64_t limit = offset + size - 1;
698 uint32_t flags0, flags5;
699
700 if (target == NV_DMA_TARGET_VIDMEM) {
701 flags0 = 0x00190000;
702 flags5 = 0x00010000;
703 } else {
704 flags0 = 0x7fc00000;
705 flags5 = 0x00080000;
706 }
707
708 nv_wo32(dev, *gpuobj, 0, flags0 | class);
709 nv_wo32(dev, *gpuobj, 1, lower_32_bits(limit));
710 nv_wo32(dev, *gpuobj, 2, lower_32_bits(offset));
711 nv_wo32(dev, *gpuobj, 3, ((upper_32_bits(limit) & 0xff) << 24) |
712 (upper_32_bits(offset) & 0xff));
713 nv_wo32(dev, *gpuobj, 5, flags5);
714 }
715
716 instmem->flush(dev);
717
718 (*gpuobj)->engine = NVOBJ_ENGINE_SW;
719 (*gpuobj)->class = class;
720 return 0;
721 }
722
723 int
724 nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
725 uint64_t offset, uint64_t size, int access,
726 struct nouveau_gpuobj **gpuobj,
727 uint32_t *o_ret)
728 {
729 struct drm_device *dev = chan->dev;
730 struct drm_nouveau_private *dev_priv = dev->dev_private;
731 int ret;
732
733 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
734 (dev_priv->card_type >= NV_50 &&
735 dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
736 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
737 offset + dev_priv->vm_gart_base,
738 size, access, NV_DMA_TARGET_AGP,
739 gpuobj);
740 if (o_ret)
741 *o_ret = 0;
742 } else
743 if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
744 *gpuobj = dev_priv->gart_info.sg_ctxdma;
745 if (offset & ~0xffffffffULL) {
746 NV_ERROR(dev, "obj offset exceeds 32-bits\n");
747 return -EINVAL;
748 }
749 if (o_ret)
750 *o_ret = (uint32_t)offset;
751 ret = (*gpuobj != NULL) ? 0 : -EINVAL;
752 } else {
753 NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
754 return -EINVAL;
755 }
756
757 return ret;
758 }
759
760 /* Context objects in the instance RAM have the following structure.
761 * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
762
763 NV4 - NV30:
764
765 entry[0]
766 11:0 class
767 12 chroma key enable
768 13 user clip enable
769 14 swizzle enable
770 17:15 patch config:
771 scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
772 18 synchronize enable
773 19 endian: 1 big, 0 little
774 21:20 dither mode
775 23 single step enable
776 24 patch status: 0 invalid, 1 valid
777 25 context_surface 0: 1 valid
778 26 context surface 1: 1 valid
779 27 context pattern: 1 valid
780 28 context rop: 1 valid
781 29,30 context beta, beta4
782 entry[1]
783 7:0 mono format
784 15:8 color format
785 31:16 notify instance address
786 entry[2]
787 15:0 dma 0 instance address
788 31:16 dma 1 instance address
789 entry[3]
790 dma method traps
791
792 NV40:
793 No idea what the exact format is. Here's what can be deducted:
794
795 entry[0]:
796 11:0 class (maybe uses more bits here?)
797 17 user clip enable
798 21:19 patch config
799 25 patch status valid ?
800 entry[1]:
801 15:0 DMA notifier (maybe 20:0)
802 entry[2]:
803 15:0 DMA 0 instance (maybe 20:0)
804 24 big endian
805 entry[3]:
806 15:0 DMA 1 instance (maybe 20:0)
807 entry[4]:
808 entry[5]:
809 set to 0?
810 */
811 int
812 nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
813 struct nouveau_gpuobj **gpuobj)
814 {
815 struct drm_device *dev = chan->dev;
816 struct drm_nouveau_private *dev_priv = dev->dev_private;
817 int ret;
818
819 NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
820
821 ret = nouveau_gpuobj_new(dev, chan,
822 nouveau_gpuobj_class_instmem_size(dev, class),
823 16,
824 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
825 gpuobj);
826 if (ret) {
827 NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
828 return ret;
829 }
830
831 if (dev_priv->card_type >= NV_50) {
832 nv_wo32(dev, *gpuobj, 0, class);
833 nv_wo32(dev, *gpuobj, 5, 0x00010000);
834 } else {
835 switch (class) {
836 case NV_CLASS_NULL:
837 nv_wo32(dev, *gpuobj, 0, 0x00001030);
838 nv_wo32(dev, *gpuobj, 1, 0xFFFFFFFF);
839 break;
840 default:
841 if (dev_priv->card_type >= NV_40) {
842 nv_wo32(dev, *gpuobj, 0, class);
843 #ifdef __BIG_ENDIAN
844 nv_wo32(dev, *gpuobj, 2, 0x01000000);
845 #endif
846 } else {
847 #ifdef __BIG_ENDIAN
848 nv_wo32(dev, *gpuobj, 0, class | 0x00080000);
849 #else
850 nv_wo32(dev, *gpuobj, 0, class);
851 #endif
852 }
853 }
854 }
855 dev_priv->engine.instmem.flush(dev);
856
857 (*gpuobj)->engine = NVOBJ_ENGINE_GR;
858 (*gpuobj)->class = class;
859 return 0;
860 }
861
862 int
863 nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
864 struct nouveau_gpuobj **gpuobj_ret)
865 {
866 struct drm_nouveau_private *dev_priv;
867 struct nouveau_gpuobj *gpuobj;
868
869 if (!chan || !gpuobj_ret || *gpuobj_ret != NULL)
870 return -EINVAL;
871 dev_priv = chan->dev->dev_private;
872
873 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
874 if (!gpuobj)
875 return -ENOMEM;
876 gpuobj->engine = NVOBJ_ENGINE_SW;
877 gpuobj->class = class;
878
879 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
880 *gpuobj_ret = gpuobj;
881 return 0;
882 }
883
884 static int
885 nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
886 {
887 struct drm_device *dev = chan->dev;
888 struct drm_nouveau_private *dev_priv = dev->dev_private;
889 struct nouveau_gpuobj *pramin = NULL;
890 uint32_t size;
891 uint32_t base;
892 int ret;
893
894 NV_DEBUG(dev, "ch%d\n", chan->id);
895
896 /* Base amount for object storage (4KiB enough?) */
897 size = 0x1000;
898 base = 0;
899
900 /* PGRAPH context */
901 size += dev_priv->engine.graph.grctx_size;
902
903 if (dev_priv->card_type == NV_50) {
904 /* Various fixed table thingos */
905 size += 0x1400; /* mostly unknown stuff */
906 size += 0x4000; /* vm pd */
907 base = 0x6000;
908 /* RAMHT, not sure about setting size yet, 32KiB to be safe */
909 size += 0x8000;
910 /* RAMFC */
911 size += 0x1000;
912 }
913
914 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0,
915 &chan->ramin);
916 if (ret) {
917 NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
918 return ret;
919 }
920 pramin = chan->ramin->gpuobj;
921
922 ret = drm_mm_init(&chan->ramin_heap, pramin->im_pramin->start + base, size);
923 if (ret) {
924 NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
925 nouveau_gpuobj_ref_del(dev, &chan->ramin);
926 return ret;
927 }
928
929 return 0;
930 }
931
932 int
933 nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
934 uint32_t vram_h, uint32_t tt_h)
935 {
936 struct drm_device *dev = chan->dev;
937 struct drm_nouveau_private *dev_priv = dev->dev_private;
938 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
939 struct nouveau_gpuobj *vram = NULL, *tt = NULL;
940 int ret, i;
941
942 INIT_LIST_HEAD(&chan->ramht_refs);
943
944 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
945
946 /* Allocate a chunk of memory for per-channel object storage */
947 ret = nouveau_gpuobj_channel_init_pramin(chan);
948 if (ret) {
949 NV_ERROR(dev, "init pramin\n");
950 return ret;
951 }
952
953 /* NV50 VM
954 * - Allocate per-channel page-directory
955 * - Map GART and VRAM into the channel's address space at the
956 * locations determined during init.
957 */
958 if (dev_priv->card_type >= NV_50) {
959 uint32_t vm_offset, pde;
960
961 vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;
962 vm_offset += chan->ramin->gpuobj->im_pramin->start;
963
964 ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000,
965 0, &chan->vm_pd, NULL);
966 if (ret)
967 return ret;
968 for (i = 0; i < 0x4000; i += 8) {
969 nv_wo32(dev, chan->vm_pd, (i+0)/4, 0x00000000);
970 nv_wo32(dev, chan->vm_pd, (i+4)/4, 0xdeadcafe);
971 }
972
973 pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 2;
974 ret = nouveau_gpuobj_ref_add(dev, NULL, 0,
975 dev_priv->gart_info.sg_ctxdma,
976 &chan->vm_gart_pt);
977 if (ret)
978 return ret;
979 nv_wo32(dev, chan->vm_pd, pde++,
980 chan->vm_gart_pt->instance | 0x03);
981 nv_wo32(dev, chan->vm_pd, pde++, 0x00000000);
982
983 pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 2;
984 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
985 ret = nouveau_gpuobj_ref_add(dev, NULL, 0,
986 dev_priv->vm_vram_pt[i],
987 &chan->vm_vram_pt[i]);
988 if (ret)
989 return ret;
990
991 nv_wo32(dev, chan->vm_pd, pde++,
992 chan->vm_vram_pt[i]->instance | 0x61);
993 nv_wo32(dev, chan->vm_pd, pde++, 0x00000000);
994 }
995
996 instmem->flush(dev);
997 }
998
999 /* RAMHT */
1000 if (dev_priv->card_type < NV_50) {
1001 ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->ramht,
1002 &chan->ramht);
1003 if (ret)
1004 return ret;
1005 } else {
1006 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0,
1007 0x8000, 16,
1008 NVOBJ_FLAG_ZERO_ALLOC,
1009 &chan->ramht);
1010 if (ret)
1011 return ret;
1012 }
1013
1014 /* VRAM ctxdma */
1015 if (dev_priv->card_type >= NV_50) {
1016 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
1017 0, dev_priv->vm_end,
1018 NV_DMA_ACCESS_RW,
1019 NV_DMA_TARGET_AGP, &vram);
1020 if (ret) {
1021 NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
1022 return ret;
1023 }
1024 } else {
1025 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
1026 0, dev_priv->fb_available_size,
1027 NV_DMA_ACCESS_RW,
1028 NV_DMA_TARGET_VIDMEM, &vram);
1029 if (ret) {
1030 NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
1031 return ret;
1032 }
1033 }
1034
1035 ret = nouveau_gpuobj_ref_add(dev, chan, vram_h, vram, NULL);
1036 if (ret) {
1037 NV_ERROR(dev, "Error referencing VRAM ctxdma: %d\n", ret);
1038 return ret;
1039 }
1040
1041 /* TT memory ctxdma */
1042 if (dev_priv->card_type >= NV_50) {
1043 tt = vram;
1044 } else
1045 if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
1046 ret = nouveau_gpuobj_gart_dma_new(chan, 0,
1047 dev_priv->gart_info.aper_size,
1048 NV_DMA_ACCESS_RW, &tt, NULL);
1049 } else {
1050 NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
1051 ret = -EINVAL;
1052 }
1053
1054 if (ret) {
1055 NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
1056 return ret;
1057 }
1058
1059 ret = nouveau_gpuobj_ref_add(dev, chan, tt_h, tt, NULL);
1060 if (ret) {
1061 NV_ERROR(dev, "Error referencing TT ctxdma: %d\n", ret);
1062 return ret;
1063 }
1064
1065 return 0;
1066 }
1067
1068 void
1069 nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
1070 {
1071 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
1072 struct drm_device *dev = chan->dev;
1073 struct list_head *entry, *tmp;
1074 struct nouveau_gpuobj_ref *ref;
1075 int i;
1076
1077 NV_DEBUG(dev, "ch%d\n", chan->id);
1078
1079 if (!chan->ramht_refs.next)
1080 return;
1081
1082 list_for_each_safe(entry, tmp, &chan->ramht_refs) {
1083 ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
1084
1085 nouveau_gpuobj_ref_del(dev, &ref);
1086 }
1087
1088 nouveau_gpuobj_ref_del(dev, &chan->ramht);
1089
1090 nouveau_gpuobj_del(dev, &chan->vm_pd);
1091 nouveau_gpuobj_ref_del(dev, &chan->vm_gart_pt);
1092 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
1093 nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]);
1094
1095 if (chan->ramin_heap.free_stack.next)
1096 drm_mm_takedown(&chan->ramin_heap);
1097 if (chan->ramin)
1098 nouveau_gpuobj_ref_del(dev, &chan->ramin);
1099
1100 }
1101
1102 int
1103 nouveau_gpuobj_suspend(struct drm_device *dev)
1104 {
1105 struct drm_nouveau_private *dev_priv = dev->dev_private;
1106 struct nouveau_gpuobj *gpuobj;
1107 int i;
1108
1109 if (dev_priv->card_type < NV_50) {
1110 dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram);
1111 if (!dev_priv->susres.ramin_copy)
1112 return -ENOMEM;
1113
1114 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
1115 dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i);
1116 return 0;
1117 }
1118
1119 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
1120 if (!gpuobj->im_backing || (gpuobj->flags & NVOBJ_FLAG_FAKE))
1121 continue;
1122
1123 gpuobj->im_backing_suspend = vmalloc(gpuobj->im_pramin->size);
1124 if (!gpuobj->im_backing_suspend) {
1125 nouveau_gpuobj_resume(dev);
1126 return -ENOMEM;
1127 }
1128
1129 for (i = 0; i < gpuobj->im_pramin->size / 4; i++)
1130 gpuobj->im_backing_suspend[i] = nv_ro32(dev, gpuobj, i);
1131 }
1132
1133 return 0;
1134 }
1135
1136 void
1137 nouveau_gpuobj_suspend_cleanup(struct drm_device *dev)
1138 {
1139 struct drm_nouveau_private *dev_priv = dev->dev_private;
1140 struct nouveau_gpuobj *gpuobj;
1141
1142 if (dev_priv->card_type < NV_50) {
1143 vfree(dev_priv->susres.ramin_copy);
1144 dev_priv->susres.ramin_copy = NULL;
1145 return;
1146 }
1147
1148 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
1149 if (!gpuobj->im_backing_suspend)
1150 continue;
1151
1152 vfree(gpuobj->im_backing_suspend);
1153 gpuobj->im_backing_suspend = NULL;
1154 }
1155 }
1156
1157 void
1158 nouveau_gpuobj_resume(struct drm_device *dev)
1159 {
1160 struct drm_nouveau_private *dev_priv = dev->dev_private;
1161 struct nouveau_gpuobj *gpuobj;
1162 int i;
1163
1164 if (dev_priv->card_type < NV_50) {
1165 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
1166 nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]);
1167 nouveau_gpuobj_suspend_cleanup(dev);
1168 return;
1169 }
1170
1171 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
1172 if (!gpuobj->im_backing_suspend)
1173 continue;
1174
1175 for (i = 0; i < gpuobj->im_pramin->size / 4; i++)
1176 nv_wo32(dev, gpuobj, i, gpuobj->im_backing_suspend[i]);
1177 dev_priv->engine.instmem.flush(dev);
1178 }
1179
1180 nouveau_gpuobj_suspend_cleanup(dev);
1181 }
1182
1183 int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
1184 struct drm_file *file_priv)
1185 {
1186 struct drm_nouveau_private *dev_priv = dev->dev_private;
1187 struct drm_nouveau_grobj_alloc *init = data;
1188 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
1189 struct nouveau_pgraph_object_class *grc;
1190 struct nouveau_gpuobj *gr = NULL;
1191 struct nouveau_channel *chan;
1192 int ret;
1193
1194 NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
1195
1196 if (init->handle == ~0)
1197 return -EINVAL;
1198
1199 grc = pgraph->grclass;
1200 while (grc->id) {
1201 if (grc->id == init->class)
1202 break;
1203 grc++;
1204 }
1205
1206 if (!grc->id) {
1207 NV_ERROR(dev, "Illegal object class: 0x%x\n", init->class);
1208 return -EPERM;
1209 }
1210
1211 if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) == 0)
1212 return -EEXIST;
1213
1214 if (!grc->software)
1215 ret = nouveau_gpuobj_gr_new(chan, grc->id, &gr);
1216 else
1217 ret = nouveau_gpuobj_sw_new(chan, grc->id, &gr);
1218
1219 if (ret) {
1220 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
1221 ret, init->channel, init->handle);
1222 return ret;
1223 }
1224
1225 ret = nouveau_gpuobj_ref_add(dev, chan, init->handle, gr, NULL);
1226 if (ret) {
1227 NV_ERROR(dev, "Error referencing object: %d (%d/0x%08x)\n",
1228 ret, init->channel, init->handle);
1229 nouveau_gpuobj_del(dev, &gr);
1230 return ret;
1231 }
1232
1233 return 0;
1234 }
1235
1236 int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
1237 struct drm_file *file_priv)
1238 {
1239 struct drm_nouveau_gpuobj_free *objfree = data;
1240 struct nouveau_gpuobj_ref *ref;
1241 struct nouveau_channel *chan;
1242 int ret;
1243
1244 NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan);
1245
1246 ret = nouveau_gpuobj_ref_find(chan, objfree->handle, &ref);
1247 if (ret)
1248 return ret;
1249 nouveau_gpuobj_ref_del(dev, &ref);
1250
1251 return 0;
1252 }
Linux kernel - Deliverables
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