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drm/nouveau/fb: merge fb/vram and port to subdev interfaces
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_state.c
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include <nouveau_drm.h>
37 #include "nouveau_fbcon.h"
38 #include <core/ramht.h>
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
41 #include <engine/fifo.h>
42 #include "nouveau_fence.h"
43 #include "nouveau_software.h"
44
45 static void nouveau_stub_takedown(struct drm_device *dev) {}
46 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
47
48 static int nouveau_init_engine_ptrs(struct drm_device *dev)
49 {
50 struct drm_nouveau_private *dev_priv = dev->dev_private;
51 struct nouveau_engine *engine = &dev_priv->engine;
52
53 switch (dev_priv->chipset & 0xf0) {
54 case 0x00:
55 engine->instmem.init = nv04_instmem_init;
56 engine->instmem.takedown = nv04_instmem_takedown;
57 engine->instmem.suspend = nv04_instmem_suspend;
58 engine->instmem.resume = nv04_instmem_resume;
59 engine->instmem.get = nv04_instmem_get;
60 engine->instmem.put = nv04_instmem_put;
61 engine->instmem.map = nv04_instmem_map;
62 engine->instmem.unmap = nv04_instmem_unmap;
63 engine->instmem.flush = nv04_instmem_flush;
64 engine->display.early_init = nv04_display_early_init;
65 engine->display.late_takedown = nv04_display_late_takedown;
66 engine->display.create = nv04_display_create;
67 engine->display.destroy = nv04_display_destroy;
68 engine->display.init = nv04_display_init;
69 engine->display.fini = nv04_display_fini;
70 engine->pm.clocks_get = nv04_pm_clocks_get;
71 engine->pm.clocks_pre = nv04_pm_clocks_pre;
72 engine->pm.clocks_set = nv04_pm_clocks_set;
73 break;
74 case 0x10:
75 engine->instmem.init = nv04_instmem_init;
76 engine->instmem.takedown = nv04_instmem_takedown;
77 engine->instmem.suspend = nv04_instmem_suspend;
78 engine->instmem.resume = nv04_instmem_resume;
79 engine->instmem.get = nv04_instmem_get;
80 engine->instmem.put = nv04_instmem_put;
81 engine->instmem.map = nv04_instmem_map;
82 engine->instmem.unmap = nv04_instmem_unmap;
83 engine->instmem.flush = nv04_instmem_flush;
84 engine->display.early_init = nv04_display_early_init;
85 engine->display.late_takedown = nv04_display_late_takedown;
86 engine->display.create = nv04_display_create;
87 engine->display.destroy = nv04_display_destroy;
88 engine->display.init = nv04_display_init;
89 engine->display.fini = nv04_display_fini;
90 engine->pm.clocks_get = nv04_pm_clocks_get;
91 engine->pm.clocks_pre = nv04_pm_clocks_pre;
92 engine->pm.clocks_set = nv04_pm_clocks_set;
93 break;
94 case 0x20:
95 engine->instmem.init = nv04_instmem_init;
96 engine->instmem.takedown = nv04_instmem_takedown;
97 engine->instmem.suspend = nv04_instmem_suspend;
98 engine->instmem.resume = nv04_instmem_resume;
99 engine->instmem.get = nv04_instmem_get;
100 engine->instmem.put = nv04_instmem_put;
101 engine->instmem.map = nv04_instmem_map;
102 engine->instmem.unmap = nv04_instmem_unmap;
103 engine->instmem.flush = nv04_instmem_flush;
104 engine->display.early_init = nv04_display_early_init;
105 engine->display.late_takedown = nv04_display_late_takedown;
106 engine->display.create = nv04_display_create;
107 engine->display.destroy = nv04_display_destroy;
108 engine->display.init = nv04_display_init;
109 engine->display.fini = nv04_display_fini;
110 engine->pm.clocks_get = nv04_pm_clocks_get;
111 engine->pm.clocks_pre = nv04_pm_clocks_pre;
112 engine->pm.clocks_set = nv04_pm_clocks_set;
113 break;
114 case 0x30:
115 engine->instmem.init = nv04_instmem_init;
116 engine->instmem.takedown = nv04_instmem_takedown;
117 engine->instmem.suspend = nv04_instmem_suspend;
118 engine->instmem.resume = nv04_instmem_resume;
119 engine->instmem.get = nv04_instmem_get;
120 engine->instmem.put = nv04_instmem_put;
121 engine->instmem.map = nv04_instmem_map;
122 engine->instmem.unmap = nv04_instmem_unmap;
123 engine->instmem.flush = nv04_instmem_flush;
124 engine->display.early_init = nv04_display_early_init;
125 engine->display.late_takedown = nv04_display_late_takedown;
126 engine->display.create = nv04_display_create;
127 engine->display.destroy = nv04_display_destroy;
128 engine->display.init = nv04_display_init;
129 engine->display.fini = nv04_display_fini;
130 engine->pm.clocks_get = nv04_pm_clocks_get;
131 engine->pm.clocks_pre = nv04_pm_clocks_pre;
132 engine->pm.clocks_set = nv04_pm_clocks_set;
133 engine->pm.voltage_get = nouveau_voltage_gpio_get;
134 engine->pm.voltage_set = nouveau_voltage_gpio_set;
135 break;
136 case 0x40:
137 case 0x60:
138 engine->instmem.init = nv04_instmem_init;
139 engine->instmem.takedown = nv04_instmem_takedown;
140 engine->instmem.suspend = nv04_instmem_suspend;
141 engine->instmem.resume = nv04_instmem_resume;
142 engine->instmem.get = nv04_instmem_get;
143 engine->instmem.put = nv04_instmem_put;
144 engine->instmem.map = nv04_instmem_map;
145 engine->instmem.unmap = nv04_instmem_unmap;
146 engine->instmem.flush = nv04_instmem_flush;
147 engine->display.early_init = nv04_display_early_init;
148 engine->display.late_takedown = nv04_display_late_takedown;
149 engine->display.create = nv04_display_create;
150 engine->display.destroy = nv04_display_destroy;
151 engine->display.init = nv04_display_init;
152 engine->display.fini = nv04_display_fini;
153 engine->pm.clocks_get = nv40_pm_clocks_get;
154 engine->pm.clocks_pre = nv40_pm_clocks_pre;
155 engine->pm.clocks_set = nv40_pm_clocks_set;
156 engine->pm.voltage_get = nouveau_voltage_gpio_get;
157 engine->pm.voltage_set = nouveau_voltage_gpio_set;
158 engine->pm.temp_get = nv40_temp_get;
159 engine->pm.pwm_get = nv40_pm_pwm_get;
160 engine->pm.pwm_set = nv40_pm_pwm_set;
161 break;
162 case 0x50:
163 case 0x80: /* gotta love NVIDIA's consistency.. */
164 case 0x90:
165 case 0xa0:
166 engine->instmem.init = nv50_instmem_init;
167 engine->instmem.takedown = nv50_instmem_takedown;
168 engine->instmem.suspend = nv50_instmem_suspend;
169 engine->instmem.resume = nv50_instmem_resume;
170 engine->instmem.get = nv50_instmem_get;
171 engine->instmem.put = nv50_instmem_put;
172 engine->instmem.map = nv50_instmem_map;
173 engine->instmem.unmap = nv50_instmem_unmap;
174 if (dev_priv->chipset == 0x50)
175 engine->instmem.flush = nv50_instmem_flush;
176 else
177 engine->instmem.flush = nv84_instmem_flush;
178 engine->display.early_init = nv50_display_early_init;
179 engine->display.late_takedown = nv50_display_late_takedown;
180 engine->display.create = nv50_display_create;
181 engine->display.destroy = nv50_display_destroy;
182 engine->display.init = nv50_display_init;
183 engine->display.fini = nv50_display_fini;
184 switch (dev_priv->chipset) {
185 case 0x84:
186 case 0x86:
187 case 0x92:
188 case 0x94:
189 case 0x96:
190 case 0x98:
191 case 0xa0:
192 case 0xaa:
193 case 0xac:
194 case 0x50:
195 engine->pm.clocks_get = nv50_pm_clocks_get;
196 engine->pm.clocks_pre = nv50_pm_clocks_pre;
197 engine->pm.clocks_set = nv50_pm_clocks_set;
198 break;
199 default:
200 engine->pm.clocks_get = nva3_pm_clocks_get;
201 engine->pm.clocks_pre = nva3_pm_clocks_pre;
202 engine->pm.clocks_set = nva3_pm_clocks_set;
203 break;
204 }
205 engine->pm.voltage_get = nouveau_voltage_gpio_get;
206 engine->pm.voltage_set = nouveau_voltage_gpio_set;
207 if (dev_priv->chipset >= 0x84)
208 engine->pm.temp_get = nv84_temp_get;
209 else
210 engine->pm.temp_get = nv40_temp_get;
211 engine->pm.pwm_get = nv50_pm_pwm_get;
212 engine->pm.pwm_set = nv50_pm_pwm_set;
213 break;
214 case 0xc0:
215 engine->instmem.init = nvc0_instmem_init;
216 engine->instmem.takedown = nvc0_instmem_takedown;
217 engine->instmem.suspend = nvc0_instmem_suspend;
218 engine->instmem.resume = nvc0_instmem_resume;
219 engine->instmem.get = nv50_instmem_get;
220 engine->instmem.put = nv50_instmem_put;
221 engine->instmem.map = nv50_instmem_map;
222 engine->instmem.unmap = nv50_instmem_unmap;
223 engine->instmem.flush = nv84_instmem_flush;
224 engine->display.early_init = nv50_display_early_init;
225 engine->display.late_takedown = nv50_display_late_takedown;
226 engine->display.create = nv50_display_create;
227 engine->display.destroy = nv50_display_destroy;
228 engine->display.init = nv50_display_init;
229 engine->display.fini = nv50_display_fini;
230 engine->pm.temp_get = nv84_temp_get;
231 engine->pm.clocks_get = nvc0_pm_clocks_get;
232 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
233 engine->pm.clocks_set = nvc0_pm_clocks_set;
234 engine->pm.voltage_get = nouveau_voltage_gpio_get;
235 engine->pm.voltage_set = nouveau_voltage_gpio_set;
236 engine->pm.pwm_get = nv50_pm_pwm_get;
237 engine->pm.pwm_set = nv50_pm_pwm_set;
238 break;
239 case 0xd0:
240 engine->instmem.init = nvc0_instmem_init;
241 engine->instmem.takedown = nvc0_instmem_takedown;
242 engine->instmem.suspend = nvc0_instmem_suspend;
243 engine->instmem.resume = nvc0_instmem_resume;
244 engine->instmem.get = nv50_instmem_get;
245 engine->instmem.put = nv50_instmem_put;
246 engine->instmem.map = nv50_instmem_map;
247 engine->instmem.unmap = nv50_instmem_unmap;
248 engine->instmem.flush = nv84_instmem_flush;
249 engine->display.early_init = nouveau_stub_init;
250 engine->display.late_takedown = nouveau_stub_takedown;
251 engine->display.create = nvd0_display_create;
252 engine->display.destroy = nvd0_display_destroy;
253 engine->display.init = nvd0_display_init;
254 engine->display.fini = nvd0_display_fini;
255 engine->pm.temp_get = nv84_temp_get;
256 engine->pm.clocks_get = nvc0_pm_clocks_get;
257 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
258 engine->pm.clocks_set = nvc0_pm_clocks_set;
259 engine->pm.voltage_get = nouveau_voltage_gpio_get;
260 engine->pm.voltage_set = nouveau_voltage_gpio_set;
261 break;
262 case 0xe0:
263 engine->instmem.init = nvc0_instmem_init;
264 engine->instmem.takedown = nvc0_instmem_takedown;
265 engine->instmem.suspend = nvc0_instmem_suspend;
266 engine->instmem.resume = nvc0_instmem_resume;
267 engine->instmem.get = nv50_instmem_get;
268 engine->instmem.put = nv50_instmem_put;
269 engine->instmem.map = nv50_instmem_map;
270 engine->instmem.unmap = nv50_instmem_unmap;
271 engine->instmem.flush = nv84_instmem_flush;
272 engine->display.early_init = nouveau_stub_init;
273 engine->display.late_takedown = nouveau_stub_takedown;
274 engine->display.create = nvd0_display_create;
275 engine->display.destroy = nvd0_display_destroy;
276 engine->display.init = nvd0_display_init;
277 engine->display.fini = nvd0_display_fini;
278 break;
279 default:
280 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
281 return 1;
282 }
283
284 /* headless mode */
285 if (nouveau_modeset == 2) {
286 engine->display.early_init = nouveau_stub_init;
287 engine->display.late_takedown = nouveau_stub_takedown;
288 engine->display.create = nouveau_stub_init;
289 engine->display.init = nouveau_stub_init;
290 engine->display.destroy = nouveau_stub_takedown;
291 }
292
293 return 0;
294 }
295
296 static unsigned int
297 nouveau_vga_set_decode(void *priv, bool state)
298 {
299 struct drm_device *dev = priv;
300 struct drm_nouveau_private *dev_priv = dev->dev_private;
301
302 if (dev_priv->chipset >= 0x40)
303 nv_wr32(dev, 0x88054, state);
304 else
305 nv_wr32(dev, 0x1854, state);
306
307 if (state)
308 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
309 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
310 else
311 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
312 }
313
314 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
315 enum vga_switcheroo_state state)
316 {
317 struct drm_device *dev = pci_get_drvdata(pdev);
318 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
319 if (state == VGA_SWITCHEROO_ON) {
320 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
321 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
322 nouveau_pci_resume(pdev);
323 drm_kms_helper_poll_enable(dev);
324 dev->switch_power_state = DRM_SWITCH_POWER_ON;
325 } else {
326 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
327 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
328 drm_kms_helper_poll_disable(dev);
329 nouveau_switcheroo_optimus_dsm();
330 nouveau_pci_suspend(pdev, pmm);
331 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
332 }
333 }
334
335 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
336 {
337 struct drm_device *dev = pci_get_drvdata(pdev);
338 nouveau_fbcon_output_poll_changed(dev);
339 }
340
341 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
342 {
343 struct drm_device *dev = pci_get_drvdata(pdev);
344 bool can_switch;
345
346 spin_lock(&dev->count_lock);
347 can_switch = (dev->open_count == 0);
348 spin_unlock(&dev->count_lock);
349 return can_switch;
350 }
351
352 static void
353 nouveau_card_channel_fini(struct drm_device *dev)
354 {
355 struct drm_nouveau_private *dev_priv = dev->dev_private;
356
357 if (dev_priv->channel)
358 nouveau_channel_put_unlocked(&dev_priv->channel);
359 }
360
361 static int
362 nouveau_card_channel_init(struct drm_device *dev)
363 {
364 struct drm_nouveau_private *dev_priv = dev->dev_private;
365 struct nouveau_channel *chan;
366 int ret;
367
368 ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
369 dev_priv->channel = chan;
370 if (ret)
371 return ret;
372 mutex_unlock(&dev_priv->channel->mutex);
373
374 nouveau_bo_move_init(chan);
375 return 0;
376 }
377
378 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
379 .set_gpu_state = nouveau_switcheroo_set_state,
380 .reprobe = nouveau_switcheroo_reprobe,
381 .can_switch = nouveau_switcheroo_can_switch,
382 };
383
384 int
385 nouveau_card_init(struct drm_device *dev)
386 {
387 struct drm_nouveau_private *dev_priv = dev->dev_private;
388 struct nouveau_engine *engine;
389 int ret, e = 0;
390
391 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
392 vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
393
394 /* Initialise internal driver API hooks */
395 ret = nouveau_init_engine_ptrs(dev);
396 if (ret)
397 goto out;
398 engine = &dev_priv->engine;
399 spin_lock_init(&dev_priv->channels.lock);
400 spin_lock_init(&dev_priv->tile.lock);
401 spin_lock_init(&dev_priv->context_switch_lock);
402 spin_lock_init(&dev_priv->vm_lock);
403
404 /* Make the CRTCs and I2C buses accessible */
405 ret = engine->display.early_init(dev);
406 if (ret)
407 goto out;
408
409 /* Parse BIOS tables / Run init tables if card not POSTed */
410 ret = nouveau_bios_init(dev);
411 if (ret)
412 goto out_display_early;
413
414 /* workaround an odd issue on nvc1 by disabling the device's
415 * nosnoop capability. hopefully won't cause issues until a
416 * better fix is found - assuming there is one...
417 */
418 if (dev_priv->chipset == 0xc1) {
419 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
420 }
421
422 ret = nouveau_gpuobj_init(dev);
423 if (ret)
424 goto out_bios;
425
426 ret = engine->instmem.init(dev);
427 if (ret)
428 goto out_gpuobj;
429
430 ret = nouveau_mem_vram_init(dev);
431 if (ret)
432 goto out_instmem;
433
434 ret = nouveau_mem_gart_init(dev);
435 if (ret)
436 goto out_ttmvram;
437
438 if (!dev_priv->noaccel) {
439 switch (dev_priv->card_type) {
440 case NV_04:
441 nv04_fifo_create(dev);
442 break;
443 case NV_10:
444 case NV_20:
445 case NV_30:
446 if (dev_priv->chipset < 0x17)
447 nv10_fifo_create(dev);
448 else
449 nv17_fifo_create(dev);
450 break;
451 case NV_40:
452 nv40_fifo_create(dev);
453 break;
454 case NV_50:
455 if (dev_priv->chipset == 0x50)
456 nv50_fifo_create(dev);
457 else
458 nv84_fifo_create(dev);
459 break;
460 case NV_C0:
461 case NV_D0:
462 nvc0_fifo_create(dev);
463 break;
464 case NV_E0:
465 nve0_fifo_create(dev);
466 break;
467 default:
468 break;
469 }
470
471 switch (dev_priv->card_type) {
472 case NV_04:
473 nv04_fence_create(dev);
474 break;
475 case NV_10:
476 case NV_20:
477 case NV_30:
478 case NV_40:
479 case NV_50:
480 if (dev_priv->chipset < 0x84)
481 nv10_fence_create(dev);
482 else
483 nv84_fence_create(dev);
484 break;
485 case NV_C0:
486 case NV_D0:
487 case NV_E0:
488 nvc0_fence_create(dev);
489 break;
490 default:
491 break;
492 }
493
494 switch (dev_priv->card_type) {
495 case NV_04:
496 case NV_10:
497 case NV_20:
498 case NV_30:
499 case NV_40:
500 nv04_software_create(dev);
501 break;
502 case NV_50:
503 nv50_software_create(dev);
504 break;
505 case NV_C0:
506 case NV_D0:
507 case NV_E0:
508 nvc0_software_create(dev);
509 break;
510 default:
511 break;
512 }
513
514 switch (dev_priv->card_type) {
515 case NV_04:
516 nv04_graph_create(dev);
517 break;
518 case NV_10:
519 nv10_graph_create(dev);
520 break;
521 case NV_20:
522 case NV_30:
523 nv20_graph_create(dev);
524 break;
525 case NV_40:
526 nv40_graph_create(dev);
527 break;
528 case NV_50:
529 nv50_graph_create(dev);
530 break;
531 case NV_C0:
532 case NV_D0:
533 nvc0_graph_create(dev);
534 break;
535 case NV_E0:
536 nve0_graph_create(dev);
537 break;
538 default:
539 break;
540 }
541
542 switch (dev_priv->chipset) {
543 case 0x84:
544 case 0x86:
545 case 0x92:
546 case 0x94:
547 case 0x96:
548 case 0xa0:
549 nv84_crypt_create(dev);
550 break;
551 case 0x98:
552 case 0xaa:
553 case 0xac:
554 nv98_crypt_create(dev);
555 break;
556 }
557
558 switch (dev_priv->card_type) {
559 case NV_50:
560 switch (dev_priv->chipset) {
561 case 0xa3:
562 case 0xa5:
563 case 0xa8:
564 nva3_copy_create(dev);
565 break;
566 }
567 break;
568 case NV_C0:
569 if (!(nv_rd32(dev, 0x022500) & 0x00000200))
570 nvc0_copy_create(dev, 1);
571 case NV_D0:
572 if (!(nv_rd32(dev, 0x022500) & 0x00000100))
573 nvc0_copy_create(dev, 0);
574 break;
575 default:
576 break;
577 }
578
579 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
580 nv84_bsp_create(dev);
581 nv84_vp_create(dev);
582 nv98_ppp_create(dev);
583 } else
584 if (dev_priv->chipset >= 0x84) {
585 nv50_mpeg_create(dev);
586 nv84_bsp_create(dev);
587 nv84_vp_create(dev);
588 } else
589 if (dev_priv->chipset >= 0x50) {
590 nv50_mpeg_create(dev);
591 } else
592 if (dev_priv->card_type == NV_40 ||
593 dev_priv->chipset == 0x31 ||
594 dev_priv->chipset == 0x34 ||
595 dev_priv->chipset == 0x36) {
596 nv31_mpeg_create(dev);
597 }
598
599 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
600 if (dev_priv->eng[e]) {
601 ret = dev_priv->eng[e]->init(dev, e);
602 if (ret)
603 goto out_engine;
604 }
605 }
606 }
607
608 ret = nouveau_irq_init(dev);
609 if (ret)
610 goto out_engine;
611
612 ret = nouveau_display_create(dev);
613 if (ret)
614 goto out_irq;
615
616 nouveau_backlight_init(dev);
617 nouveau_pm_init(dev);
618
619 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
620 ret = nouveau_card_channel_init(dev);
621 if (ret)
622 goto out_pm;
623 }
624
625 if (dev->mode_config.num_crtc) {
626 ret = nouveau_display_init(dev);
627 if (ret)
628 goto out_chan;
629
630 nouveau_fbcon_init(dev);
631 }
632
633 return 0;
634
635 out_chan:
636 nouveau_card_channel_fini(dev);
637 out_pm:
638 nouveau_pm_fini(dev);
639 nouveau_backlight_exit(dev);
640 nouveau_display_destroy(dev);
641 out_irq:
642 nouveau_irq_fini(dev);
643 out_engine:
644 if (!dev_priv->noaccel) {
645 for (e = e - 1; e >= 0; e--) {
646 if (!dev_priv->eng[e])
647 continue;
648 dev_priv->eng[e]->fini(dev, e, false);
649 dev_priv->eng[e]->destroy(dev,e );
650 }
651 }
652 nouveau_mem_gart_fini(dev);
653 out_ttmvram:
654 nouveau_mem_vram_fini(dev);
655 out_instmem:
656 engine->instmem.takedown(dev);
657 out_gpuobj:
658 nouveau_gpuobj_takedown(dev);
659 out_bios:
660 nouveau_bios_takedown(dev);
661 out_display_early:
662 engine->display.late_takedown(dev);
663 out:
664 vga_switcheroo_unregister_client(dev->pdev);
665 vga_client_register(dev->pdev, NULL, NULL, NULL);
666 return ret;
667 }
668
669 static void nouveau_card_takedown(struct drm_device *dev)
670 {
671 struct drm_nouveau_private *dev_priv = dev->dev_private;
672 struct nouveau_engine *engine = &dev_priv->engine;
673 int e;
674
675 if (dev->mode_config.num_crtc) {
676 nouveau_fbcon_fini(dev);
677 nouveau_display_fini(dev);
678 }
679
680 nouveau_card_channel_fini(dev);
681 nouveau_pm_fini(dev);
682 nouveau_backlight_exit(dev);
683 nouveau_display_destroy(dev);
684
685 if (!dev_priv->noaccel) {
686 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
687 if (dev_priv->eng[e]) {
688 dev_priv->eng[e]->fini(dev, e, false);
689 dev_priv->eng[e]->destroy(dev,e );
690 }
691 }
692 }
693
694 if (dev_priv->vga_ram) {
695 nouveau_bo_unpin(dev_priv->vga_ram);
696 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
697 }
698
699 mutex_lock(&dev->struct_mutex);
700 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
701 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
702 mutex_unlock(&dev->struct_mutex);
703 nouveau_mem_gart_fini(dev);
704 nouveau_mem_vram_fini(dev);
705
706 engine->instmem.takedown(dev);
707 nouveau_gpuobj_takedown(dev);
708
709 nouveau_bios_takedown(dev);
710 engine->display.late_takedown(dev);
711
712 nouveau_irq_fini(dev);
713
714 vga_switcheroo_unregister_client(dev->pdev);
715 vga_client_register(dev->pdev, NULL, NULL, NULL);
716 }
717
718 int
719 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
720 {
721 struct drm_nouveau_private *dev_priv = dev->dev_private;
722 struct nouveau_fpriv *fpriv;
723 int ret;
724
725 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
726 if (unlikely(!fpriv))
727 return -ENOMEM;
728
729 spin_lock_init(&fpriv->lock);
730 INIT_LIST_HEAD(&fpriv->channels);
731
732 if (dev_priv->card_type == NV_50) {
733 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
734 &fpriv->vm);
735 if (ret) {
736 kfree(fpriv);
737 return ret;
738 }
739 } else
740 if (dev_priv->card_type >= NV_C0) {
741 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
742 &fpriv->vm);
743 if (ret) {
744 kfree(fpriv);
745 return ret;
746 }
747 }
748
749 file_priv->driver_priv = fpriv;
750 return 0;
751 }
752
753 /* here a client dies, release the stuff that was allocated for its
754 * file_priv */
755 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
756 {
757 nouveau_channel_cleanup(dev, file_priv);
758 }
759
760 void
761 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
762 {
763 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
764 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
765 kfree(fpriv);
766 }
767
768 /* first module load, setup the mmio/fb mapping */
769 /* KMS: we need mmio at load time, not when the first drm client opens. */
770 int nouveau_firstopen(struct drm_device *dev)
771 {
772 return 0;
773 }
774
775 /* if we have an OF card, copy vbios to RAMIN */
776 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
777 {
778 #if defined(__powerpc__)
779 int size, i;
780 const uint32_t *bios;
781 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
782 if (!dn) {
783 NV_INFO(dev, "Unable to get the OF node\n");
784 return;
785 }
786
787 bios = of_get_property(dn, "NVDA,BMP", &size);
788 if (bios) {
789 for (i = 0; i < size; i += 4)
790 nv_wi32(dev, i, bios[i/4]);
791 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
792 } else {
793 NV_INFO(dev, "Unable to get the OF bios\n");
794 }
795 #endif
796 }
797
798 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
799 {
800 struct pci_dev *pdev = dev->pdev;
801 struct apertures_struct *aper = alloc_apertures(3);
802 if (!aper)
803 return NULL;
804
805 aper->ranges[0].base = pci_resource_start(pdev, 1);
806 aper->ranges[0].size = pci_resource_len(pdev, 1);
807 aper->count = 1;
808
809 if (pci_resource_len(pdev, 2)) {
810 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
811 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
812 aper->count++;
813 }
814
815 if (pci_resource_len(pdev, 3)) {
816 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
817 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
818 aper->count++;
819 }
820
821 return aper;
822 }
823
824 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
825 {
826 struct drm_nouveau_private *dev_priv = dev->dev_private;
827 bool primary = false;
828 dev_priv->apertures = nouveau_get_apertures(dev);
829 if (!dev_priv->apertures)
830 return -ENOMEM;
831
832 #ifdef CONFIG_X86
833 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
834 #endif
835
836 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
837 return 0;
838 }
839
840 void *
841 nouveau_newpriv(struct drm_device *dev)
842 {
843 struct drm_nouveau_private *dev_priv = dev->dev_private;
844 return dev_priv->newpriv;
845 }
846
847 int nouveau_load(struct drm_device *dev, unsigned long flags)
848 {
849 struct drm_nouveau_private *dev_priv;
850 uint32_t reg0 = ~0, strap;
851 int ret;
852
853 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
854 if (!dev_priv) {
855 ret = -ENOMEM;
856 goto err_out;
857 }
858 dev_priv->newpriv = dev->dev_private;
859 dev->dev_private = dev_priv;
860 dev_priv->dev = dev;
861
862 dev_priv->flags = flags & NOUVEAU_FLAGS;
863
864 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
865 dev->pci_vendor, dev->pci_device, dev->pdev->class);
866
867 /* determine chipset and derive architecture from it */
868 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
869 if ((reg0 & 0x0f000000) > 0) {
870 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
871 switch (dev_priv->chipset & 0xf0) {
872 case 0x10:
873 case 0x20:
874 case 0x30:
875 dev_priv->card_type = dev_priv->chipset & 0xf0;
876 break;
877 case 0x40:
878 case 0x60:
879 dev_priv->card_type = NV_40;
880 break;
881 case 0x50:
882 case 0x80:
883 case 0x90:
884 case 0xa0:
885 dev_priv->card_type = NV_50;
886 break;
887 case 0xc0:
888 dev_priv->card_type = NV_C0;
889 break;
890 case 0xd0:
891 dev_priv->card_type = NV_D0;
892 break;
893 case 0xe0:
894 dev_priv->card_type = NV_E0;
895 break;
896 default:
897 break;
898 }
899 } else
900 if ((reg0 & 0xff00fff0) == 0x20004000) {
901 if (reg0 & 0x00f00000)
902 dev_priv->chipset = 0x05;
903 else
904 dev_priv->chipset = 0x04;
905 dev_priv->card_type = NV_04;
906 }
907
908 if (!dev_priv->card_type) {
909 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
910 ret = -EINVAL;
911 goto err_priv;
912 }
913
914 NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
915 dev_priv->card_type, reg0);
916
917 /* determine frequency of timing crystal */
918 strap = nv_rd32(dev, 0x101000);
919 if ( dev_priv->chipset < 0x17 ||
920 (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
921 strap &= 0x00000040;
922 else
923 strap &= 0x00400040;
924
925 switch (strap) {
926 case 0x00000000: dev_priv->crystal = 13500; break;
927 case 0x00000040: dev_priv->crystal = 14318; break;
928 case 0x00400000: dev_priv->crystal = 27000; break;
929 case 0x00400040: dev_priv->crystal = 25000; break;
930 }
931
932 NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
933
934 /* Determine whether we'll attempt acceleration or not, some
935 * cards are disabled by default here due to them being known
936 * non-functional, or never been tested due to lack of hw.
937 */
938 dev_priv->noaccel = !!nouveau_noaccel;
939 if (nouveau_noaccel == -1) {
940 switch (dev_priv->chipset) {
941 case 0xd9: /* known broken */
942 case 0xe4: /* needs binary driver firmware */
943 case 0xe7: /* needs binary driver firmware */
944 NV_INFO(dev, "acceleration disabled by default, pass "
945 "noaccel=0 to force enable\n");
946 dev_priv->noaccel = true;
947 break;
948 default:
949 dev_priv->noaccel = false;
950 break;
951 }
952 }
953
954 ret = nouveau_remove_conflicting_drivers(dev);
955 if (ret)
956 goto err_priv;
957
958 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
959 if (dev_priv->card_type >= NV_40) {
960 int ramin_bar = 2;
961 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
962 ramin_bar = 3;
963
964 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
965 dev_priv->ramin =
966 ioremap(pci_resource_start(dev->pdev, ramin_bar),
967 dev_priv->ramin_size);
968 if (!dev_priv->ramin) {
969 NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
970 ret = -ENOMEM;
971 goto err_priv;
972 }
973 } else {
974 dev_priv->ramin_size = 1 * 1024 * 1024;
975 dev_priv->ramin = ioremap(pci_resource_start(dev->pdev, 0),
976 dev_priv->ramin_size);
977 if (!dev_priv->ramin) {
978 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
979 ret = -ENOMEM;
980 goto err_priv;
981 }
982 }
983
984 nouveau_OF_copy_vbios_to_ramin(dev);
985
986 /* Special flags */
987 if (dev->pci_device == 0x01a0)
988 dev_priv->flags |= NV_NFORCE;
989 else if (dev->pci_device == 0x01f0)
990 dev_priv->flags |= NV_NFORCE2;
991
992 /* For kernel modesetting, init card now and bring up fbcon */
993 ret = nouveau_card_init(dev);
994 if (ret)
995 goto err_ramin;
996
997 return 0;
998
999 err_ramin:
1000 iounmap(dev_priv->ramin);
1001 err_priv:
1002 dev->dev_private = dev_priv->newpriv;
1003 kfree(dev_priv);
1004 err_out:
1005 return ret;
1006 }
1007
1008 void nouveau_lastclose(struct drm_device *dev)
1009 {
1010 vga_switcheroo_process_delayed_switch();
1011 }
1012
1013 int nouveau_unload(struct drm_device *dev)
1014 {
1015 struct drm_nouveau_private *dev_priv = dev->dev_private;
1016
1017 nouveau_card_takedown(dev);
1018
1019 iounmap(dev_priv->ramin);
1020
1021 dev->dev_private = dev_priv->newpriv;
1022 kfree(dev_priv);
1023 return 0;
1024 }
1025
1026 /* Waits for PGRAPH to go completely idle */
1027 bool nouveau_wait_for_idle(struct drm_device *dev)
1028 {
1029 struct drm_nouveau_private *dev_priv = dev->dev_private;
1030 uint32_t mask = ~0;
1031
1032 if (dev_priv->card_type == NV_40)
1033 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1034
1035 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1036 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1037 nv_rd32(dev, NV04_PGRAPH_STATUS));
1038 return false;
1039 }
1040
1041 return true;
1042 }
1043
Linux kernel - Deliverables
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