2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "nv50_display.h"
28 #include "nouveau_crtc.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_connector.h"
31 #include "nouveau_fb.h"
32 #include "nouveau_fbcon.h"
33 #include "nouveau_ramht.h"
34 #include "drm_crtc_helper.h"
37 nv50_sor_nr(struct drm_device
*dev
)
39 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
41 if (dev_priv
->chipset
< 0x90 ||
42 dev_priv
->chipset
== 0x92 ||
43 dev_priv
->chipset
== 0xa0)
50 nv50_evo_channel_del(struct nouveau_channel
**pchan
)
52 struct nouveau_channel
*chan
= *pchan
;
58 nouveau_gpuobj_channel_takedown(chan
);
59 nouveau_bo_unmap(chan
->pushbuf_bo
);
60 nouveau_bo_ref(NULL
, &chan
->pushbuf_bo
);
69 nv50_evo_dmaobj_new(struct nouveau_channel
*evo
, uint32_t class, uint32_t name
,
70 uint32_t tile_flags
, uint32_t magic_flags
,
71 uint32_t offset
, uint32_t limit
)
73 struct drm_nouveau_private
*dev_priv
= evo
->dev
->dev_private
;
74 struct drm_device
*dev
= evo
->dev
;
75 struct nouveau_gpuobj
*obj
= NULL
;
78 ret
= nouveau_gpuobj_new(dev
, evo
, 6*4, 32, 0, &obj
);
81 obj
->engine
= NVOBJ_ENGINE_DISPLAY
;
83 nv_wo32(obj
, 0, (tile_flags
<< 22) | (magic_flags
<< 16) | class);
84 nv_wo32(obj
, 4, limit
);
85 nv_wo32(obj
, 8, offset
);
86 nv_wo32(obj
, 12, 0x00000000);
87 nv_wo32(obj
, 16, 0x00000000);
88 if (dev_priv
->card_type
< NV_C0
)
89 nv_wo32(obj
, 20, 0x00010000);
91 nv_wo32(obj
, 20, 0x00020000);
92 dev_priv
->engine
.instmem
.flush(dev
);
94 ret
= nouveau_ramht_insert(evo
, name
, obj
);
95 nouveau_gpuobj_ref(NULL
, &obj
);
104 nv50_evo_channel_new(struct drm_device
*dev
, struct nouveau_channel
**pchan
)
106 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
107 struct nouveau_gpuobj
*ramht
= NULL
;
108 struct nouveau_channel
*chan
;
111 chan
= kzalloc(sizeof(struct nouveau_channel
), GFP_KERNEL
);
121 ret
= nouveau_gpuobj_new(dev
, NULL
, 32768, 0x1000,
122 NVOBJ_FLAG_ZERO_ALLOC
, &chan
->ramin
);
124 NV_ERROR(dev
, "Error allocating EVO channel memory: %d\n", ret
);
125 nv50_evo_channel_del(pchan
);
129 ret
= drm_mm_init(&chan
->ramin_heap
, 0, 32768);
131 NV_ERROR(dev
, "Error initialising EVO PRAMIN heap: %d\n", ret
);
132 nv50_evo_channel_del(pchan
);
136 ret
= nouveau_gpuobj_new(dev
, chan
, 4096, 16, 0, &ramht
);
138 NV_ERROR(dev
, "Unable to allocate EVO RAMHT: %d\n", ret
);
139 nv50_evo_channel_del(pchan
);
143 ret
= nouveau_ramht_new(dev
, ramht
, &chan
->ramht
);
144 nouveau_gpuobj_ref(NULL
, &ramht
);
146 nv50_evo_channel_del(pchan
);
150 if (dev_priv
->chipset
!= 0x50) {
151 ret
= nv50_evo_dmaobj_new(chan
, 0x3d, NvEvoFB16
, 0x70, 0x19,
154 nv50_evo_channel_del(pchan
);
159 ret
= nv50_evo_dmaobj_new(chan
, 0x3d, NvEvoFB32
, 0x7a, 0x19,
162 nv50_evo_channel_del(pchan
);
167 ret
= nv50_evo_dmaobj_new(chan
, 0x3d, NvEvoVRAM
, 0, 0x19,
168 0, dev_priv
->vram_size
);
170 nv50_evo_channel_del(pchan
);
174 ret
= nouveau_bo_new(dev
, NULL
, 4096, 0, TTM_PL_FLAG_VRAM
, 0, 0,
175 false, true, &chan
->pushbuf_bo
);
177 ret
= nouveau_bo_pin(chan
->pushbuf_bo
, TTM_PL_FLAG_VRAM
);
179 NV_ERROR(dev
, "Error creating EVO DMA push buffer: %d\n", ret
);
180 nv50_evo_channel_del(pchan
);
184 ret
= nouveau_bo_map(chan
->pushbuf_bo
);
186 NV_ERROR(dev
, "Error mapping EVO DMA push buffer: %d\n", ret
);
187 nv50_evo_channel_del(pchan
);
191 chan
->user
= ioremap(pci_resource_start(dev
->pdev
, 0) +
192 NV50_PDISPLAY_USER(0), PAGE_SIZE
);
194 NV_ERROR(dev
, "Error mapping EVO control regs.\n");
195 nv50_evo_channel_del(pchan
);
203 nv50_display_early_init(struct drm_device
*dev
)
209 nv50_display_late_takedown(struct drm_device
*dev
)
214 nv50_display_init(struct drm_device
*dev
)
216 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
217 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
218 struct nouveau_gpio_engine
*pgpio
= &dev_priv
->engine
.gpio
;
219 struct nouveau_channel
*evo
= dev_priv
->evo
;
220 struct drm_connector
*connector
;
225 NV_DEBUG_KMS(dev
, "\n");
227 nv_wr32(dev
, 0x00610184, nv_rd32(dev
, 0x00614004));
229 * I think the 0x006101XX range is some kind of main control area
230 * that enables things.
233 for (i
= 0; i
< 2; i
++) {
234 val
= nv_rd32(dev
, 0x00616100 + (i
* 0x800));
235 nv_wr32(dev
, 0x00610190 + (i
* 0x10), val
);
236 val
= nv_rd32(dev
, 0x00616104 + (i
* 0x800));
237 nv_wr32(dev
, 0x00610194 + (i
* 0x10), val
);
238 val
= nv_rd32(dev
, 0x00616108 + (i
* 0x800));
239 nv_wr32(dev
, 0x00610198 + (i
* 0x10), val
);
240 val
= nv_rd32(dev
, 0x0061610c + (i
* 0x800));
241 nv_wr32(dev
, 0x0061019c + (i
* 0x10), val
);
244 for (i
= 0; i
< 3; i
++) {
245 val
= nv_rd32(dev
, 0x0061a000 + (i
* 0x800));
246 nv_wr32(dev
, 0x006101d0 + (i
* 0x04), val
);
249 for (i
= 0; i
< nv50_sor_nr(dev
); i
++) {
250 val
= nv_rd32(dev
, 0x0061c000 + (i
* 0x800));
251 nv_wr32(dev
, 0x006101e0 + (i
* 0x04), val
);
254 for (i
= 0; i
< 3; i
++) {
255 val
= nv_rd32(dev
, 0x0061e000 + (i
* 0x800));
256 nv_wr32(dev
, 0x006101f0 + (i
* 0x04), val
);
259 for (i
= 0; i
< 3; i
++) {
260 nv_wr32(dev
, NV50_PDISPLAY_DAC_DPMS_CTRL(i
), 0x00550000 |
261 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING
);
262 nv_wr32(dev
, NV50_PDISPLAY_DAC_CLK_CTRL1(i
), 0x00000001);
265 /* The precise purpose is unknown, i suspect it has something to do
268 if (nv_rd32(dev
, NV50_PDISPLAY_INTR_1
) & 0x100) {
269 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, 0x100);
270 nv_wr32(dev
, 0x006194e8, nv_rd32(dev
, 0x006194e8) & ~1);
271 if (!nv_wait(dev
, 0x006194e8, 2, 0)) {
272 NV_ERROR(dev
, "timeout: (0x6194e8 & 2) != 0\n");
273 NV_ERROR(dev
, "0x6194e8 = 0x%08x\n",
274 nv_rd32(dev
, 0x6194e8));
279 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
280 * stuck in some unspecified state
282 start
= ptimer
->read(dev
);
283 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
284 while ((val
= nv_rd32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
285 if ((val
& 0x9f0000) == 0x20000)
286 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0),
289 if ((val
& 0x3f0000) == 0x30000)
290 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0),
293 if (ptimer
->read(dev
) - start
> 1000000000ULL) {
294 NV_ERROR(dev
, "timeout: (0x610200 & 0x1e0000) != 0\n");
295 NV_ERROR(dev
, "0x610200 = 0x%08x\n", val
);
300 nv_wr32(dev
, NV50_PDISPLAY_CTRL_STATE
, NV50_PDISPLAY_CTRL_STATE_ENABLE
);
301 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
302 if (!nv_wait(dev
, NV50_PDISPLAY_CHANNEL_STAT(0),
303 0x40000000, 0x40000000)) {
304 NV_ERROR(dev
, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
305 NV_ERROR(dev
, "0x610200 = 0x%08x\n",
306 nv_rd32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0)));
310 for (i
= 0; i
< 2; i
++) {
311 nv_wr32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
), 0x2000);
312 if (!nv_wait(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
313 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS
, 0)) {
314 NV_ERROR(dev
, "timeout: CURSOR_CTRL2_STATUS == 0\n");
315 NV_ERROR(dev
, "CURSOR_CTRL2 = 0x%08x\n",
316 nv_rd32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
)));
320 nv_wr32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
321 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON
);
322 if (!nv_wait(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
323 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS
,
324 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE
)) {
325 NV_ERROR(dev
, "timeout: "
326 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i
);
327 NV_ERROR(dev
, "CURSOR_CTRL2(%d) = 0x%08x\n", i
,
328 nv_rd32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
)));
333 nv_wr32(dev
, NV50_PDISPLAY_OBJECTS
, (evo
->ramin
->vinst
>> 8) | 9);
335 /* initialise fifo */
336 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
337 ((evo
->pushbuf_bo
->bo
.mem
.start
<< PAGE_SHIFT
) >> 8) |
338 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM
|
339 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID
);
340 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
341 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
342 if (!nv_wait(dev
, 0x610200, 0x80000000, 0x00000000)) {
343 NV_ERROR(dev
, "timeout: (0x610200 & 0x80000000) == 0\n");
344 NV_ERROR(dev
, "0x610200 = 0x%08x\n", nv_rd32(dev
, 0x610200));
347 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0),
348 (nv_rd32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
349 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED
);
350 nv_wr32(dev
, NV50_PDISPLAY_USER_PUT(0), 0);
351 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
352 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED
);
353 nv_wr32(dev
, 0x610300, nv_rd32(dev
, 0x610300) & ~1);
355 evo
->dma
.max
= (4096/4) - 2;
357 evo
->dma
.cur
= evo
->dma
.put
;
358 evo
->dma
.free
= evo
->dma
.max
- evo
->dma
.cur
;
360 ret
= RING_SPACE(evo
, NOUVEAU_DMA_SKIPS
);
364 for (i
= 0; i
< NOUVEAU_DMA_SKIPS
; i
++)
367 ret
= RING_SPACE(evo
, 11);
370 BEGIN_RING(evo
, 0, NV50_EVO_UNK84
, 2);
371 OUT_RING(evo
, NV50_EVO_UNK84_NOTIFY_DISABLED
);
372 OUT_RING(evo
, NV50_EVO_DMA_NOTIFY_HANDLE_NONE
);
373 BEGIN_RING(evo
, 0, NV50_EVO_CRTC(0, FB_DMA
), 1);
374 OUT_RING(evo
, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE
);
375 BEGIN_RING(evo
, 0, NV50_EVO_CRTC(0, UNK0800
), 1);
377 BEGIN_RING(evo
, 0, NV50_EVO_CRTC(0, DISPLAY_START
), 1);
379 BEGIN_RING(evo
, 0, NV50_EVO_CRTC(0, UNK082C
), 1);
382 if (!nv_wait(dev
, 0x640004, 0xffffffff, evo
->dma
.put
<< 2))
383 NV_ERROR(dev
, "evo pushbuf stalled\n");
385 /* enable clock change interrupts. */
386 nv_wr32(dev
, 0x610028, 0x00010001);
387 nv_wr32(dev
, NV50_PDISPLAY_INTR_EN
, (NV50_PDISPLAY_INTR_EN_CLK_UNK10
|
388 NV50_PDISPLAY_INTR_EN_CLK_UNK20
|
389 NV50_PDISPLAY_INTR_EN_CLK_UNK40
));
391 /* enable hotplug interrupts */
392 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
393 struct nouveau_connector
*conn
= nouveau_connector(connector
);
395 if (conn
->dcb
->gpio_tag
== 0xff)
398 pgpio
->irq_enable(dev
, conn
->dcb
->gpio_tag
, true);
404 static int nv50_display_disable(struct drm_device
*dev
)
406 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
407 struct drm_crtc
*drm_crtc
;
410 NV_DEBUG_KMS(dev
, "\n");
412 list_for_each_entry(drm_crtc
, &dev
->mode_config
.crtc_list
, head
) {
413 struct nouveau_crtc
*crtc
= nouveau_crtc(drm_crtc
);
415 nv50_crtc_blank(crtc
, true);
418 ret
= RING_SPACE(dev_priv
->evo
, 2);
420 BEGIN_RING(dev_priv
->evo
, 0, NV50_EVO_UPDATE
, 1);
421 OUT_RING(dev_priv
->evo
, 0);
423 FIRE_RING(dev_priv
->evo
);
425 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
428 list_for_each_entry(drm_crtc
, &dev
->mode_config
.crtc_list
, head
) {
429 struct nouveau_crtc
*crtc
= nouveau_crtc(drm_crtc
);
430 uint32_t mask
= NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc
->index
);
432 if (!crtc
->base
.enabled
)
435 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, mask
);
436 if (!nv_wait(dev
, NV50_PDISPLAY_INTR_1
, mask
, mask
)) {
437 NV_ERROR(dev
, "timeout: (0x610024 & 0x%08x) == "
438 "0x%08x\n", mask
, mask
);
439 NV_ERROR(dev
, "0x610024 = 0x%08x\n",
440 nv_rd32(dev
, NV50_PDISPLAY_INTR_1
));
444 nv_wr32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
445 nv_wr32(dev
, NV50_PDISPLAY_CTRL_STATE
, 0);
446 if (!nv_wait(dev
, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
447 NV_ERROR(dev
, "timeout: (0x610200 & 0x1e0000) == 0\n");
448 NV_ERROR(dev
, "0x610200 = 0x%08x\n",
449 nv_rd32(dev
, NV50_PDISPLAY_CHANNEL_STAT(0)));
452 for (i
= 0; i
< 3; i
++) {
453 if (!nv_wait(dev
, NV50_PDISPLAY_SOR_DPMS_STATE(i
),
454 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT
, 0)) {
455 NV_ERROR(dev
, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i
);
456 NV_ERROR(dev
, "SOR_DPMS_STATE(%d) = 0x%08x\n", i
,
457 nv_rd32(dev
, NV50_PDISPLAY_SOR_DPMS_STATE(i
)));
461 /* disable interrupts. */
462 nv_wr32(dev
, NV50_PDISPLAY_INTR_EN
, 0x00000000);
464 /* disable hotplug interrupts */
465 nv_wr32(dev
, 0xe054, 0xffffffff);
466 nv_wr32(dev
, 0xe050, 0x00000000);
467 if (dev_priv
->chipset
>= 0x90) {
468 nv_wr32(dev
, 0xe074, 0xffffffff);
469 nv_wr32(dev
, 0xe070, 0x00000000);
474 int nv50_display_create(struct drm_device
*dev
)
476 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
477 struct dcb_table
*dcb
= &dev_priv
->vbios
.dcb
;
478 struct drm_connector
*connector
, *ct
;
481 NV_DEBUG_KMS(dev
, "\n");
483 /* init basic kernel modesetting */
484 drm_mode_config_init(dev
);
486 /* Initialise some optional connector properties. */
487 drm_mode_create_scaling_mode_property(dev
);
488 drm_mode_create_dithering_property(dev
);
490 dev
->mode_config
.min_width
= 0;
491 dev
->mode_config
.min_height
= 0;
493 dev
->mode_config
.funcs
= (void *)&nouveau_mode_config_funcs
;
495 dev
->mode_config
.max_width
= 8192;
496 dev
->mode_config
.max_height
= 8192;
498 dev
->mode_config
.fb_base
= dev_priv
->fb_phys
;
500 /* Create EVO channel */
501 ret
= nv50_evo_channel_new(dev
, &dev_priv
->evo
);
503 NV_ERROR(dev
, "Error creating EVO channel: %d\n", ret
);
507 /* Create CRTC objects */
508 for (i
= 0; i
< 2; i
++)
509 nv50_crtc_create(dev
, i
);
511 /* We setup the encoders from the BIOS table */
512 for (i
= 0 ; i
< dcb
->entries
; i
++) {
513 struct dcb_entry
*entry
= &dcb
->entry
[i
];
515 if (entry
->location
!= DCB_LOC_ON_CHIP
) {
516 NV_WARN(dev
, "Off-chip encoder %d/%d unsupported\n",
517 entry
->type
, ffs(entry
->or) - 1);
521 connector
= nouveau_connector_create(dev
, entry
->connector
);
522 if (IS_ERR(connector
))
525 switch (entry
->type
) {
529 nv50_sor_create(connector
, entry
);
532 nv50_dac_create(connector
, entry
);
535 NV_WARN(dev
, "DCB encoder %d unknown\n", entry
->type
);
540 list_for_each_entry_safe(connector
, ct
,
541 &dev
->mode_config
.connector_list
, head
) {
542 if (!connector
->encoder_ids
[0]) {
543 NV_WARN(dev
, "%s has no encoders, removing\n",
544 drm_get_connector_name(connector
));
545 connector
->funcs
->destroy(connector
);
549 ret
= nv50_display_init(dev
);
551 nv50_display_destroy(dev
);
559 nv50_display_destroy(struct drm_device
*dev
)
561 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
563 NV_DEBUG_KMS(dev
, "\n");
565 drm_mode_config_cleanup(dev
);
567 nv50_display_disable(dev
);
568 nv50_evo_channel_del(&dev_priv
->evo
);
572 nv50_display_script_select(struct drm_device
*dev
, struct dcb_entry
*dcb
,
575 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
576 struct nouveau_connector
*nv_connector
= NULL
;
577 struct drm_encoder
*encoder
;
578 struct nvbios
*bios
= &dev_priv
->vbios
;
581 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
582 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
584 if (nv_encoder
->dcb
!= dcb
)
587 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
591 or = ffs(dcb
->or) - 1;
594 script
= (mc
>> 8) & 0xf;
595 if (bios
->fp_no_ddc
) {
596 if (bios
->fp
.dual_link
)
598 if (bios
->fp
.if_is_24bit
)
601 if (pxclk
>= bios
->fp
.duallink_transition_clk
) {
603 if (bios
->fp
.strapless_is_24bit
& 2)
606 if (bios
->fp
.strapless_is_24bit
& 1)
609 if (nv_connector
&& nv_connector
->edid
&&
610 (nv_connector
->edid
->revision
>= 4) &&
611 (nv_connector
->edid
->input
& 0x70) >= 0x20)
615 if (nouveau_uscript_lvds
>= 0) {
616 NV_INFO(dev
, "override script 0x%04x with 0x%04x "
617 "for output LVDS-%d\n", script
,
618 nouveau_uscript_lvds
, or);
619 script
= nouveau_uscript_lvds
;
623 script
= (mc
>> 8) & 0xf;
627 if (nouveau_uscript_tmds
>= 0) {
628 NV_INFO(dev
, "override script 0x%04x with 0x%04x "
629 "for output TMDS-%d\n", script
,
630 nouveau_uscript_tmds
, or);
631 script
= nouveau_uscript_tmds
;
635 script
= (mc
>> 8) & 0xf;
641 NV_ERROR(dev
, "modeset on unsupported output type!\n");
649 nv50_display_vblank_crtc_handler(struct drm_device
*dev
, int crtc
)
651 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
652 struct nouveau_channel
*chan
;
653 struct list_head
*entry
, *tmp
;
655 list_for_each_safe(entry
, tmp
, &dev_priv
->vbl_waiting
) {
656 chan
= list_entry(entry
, struct nouveau_channel
, nvsw
.vbl_wait
);
658 nouveau_bo_wr32(chan
->notifier_bo
, chan
->nvsw
.vblsem_offset
,
659 chan
->nvsw
.vblsem_rval
);
660 list_del(&chan
->nvsw
.vbl_wait
);
665 nv50_display_vblank_handler(struct drm_device
*dev
, uint32_t intr
)
667 intr
&= NV50_PDISPLAY_INTR_1_VBLANK_CRTC
;
669 if (intr
& NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0
)
670 nv50_display_vblank_crtc_handler(dev
, 0);
672 if (intr
& NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1
)
673 nv50_display_vblank_crtc_handler(dev
, 1);
675 nv_wr32(dev
, NV50_PDISPLAY_INTR_EN
, nv_rd32(dev
,
676 NV50_PDISPLAY_INTR_EN
) & ~intr
);
677 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, intr
);
681 nv50_display_unk10_handler(struct drm_device
*dev
)
683 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
684 u32 unk30
= nv_rd32(dev
, 0x610030), mc
;
685 int i
, crtc
, or, type
= OUTPUT_ANY
;
687 NV_DEBUG_KMS(dev
, "0x610030: 0x%08x\n", unk30
);
688 dev_priv
->evo_irq
.dcb
= NULL
;
690 nv_wr32(dev
, 0x619494, nv_rd32(dev
, 0x619494) & ~8);
692 /* Determine which CRTC we're dealing with, only 1 ever will be
693 * signalled at the same time with the current nouveau code.
695 crtc
= ffs((unk30
& 0x00000060) >> 5) - 1;
699 /* Nothing needs to be done for the encoder */
700 crtc
= ffs((unk30
& 0x00000180) >> 7) - 1;
704 /* Find which encoder was connected to the CRTC */
705 for (i
= 0; type
== OUTPUT_ANY
&& i
< 3; i
++) {
706 mc
= nv_rd32(dev
, NV50_PDISPLAY_DAC_MODE_CTRL_C(i
));
707 NV_DEBUG_KMS(dev
, "DAC-%d mc: 0x%08x\n", i
, mc
);
708 if (!(mc
& (1 << crtc
)))
711 switch ((mc
& 0x00000f00) >> 8) {
712 case 0: type
= OUTPUT_ANALOG
; break;
713 case 1: type
= OUTPUT_TV
; break;
715 NV_ERROR(dev
, "invalid mc, DAC-%d: 0x%08x\n", i
, mc
);
722 for (i
= 0; type
== OUTPUT_ANY
&& i
< nv50_sor_nr(dev
); i
++) {
723 if (dev_priv
->chipset
< 0x90 ||
724 dev_priv
->chipset
== 0x92 ||
725 dev_priv
->chipset
== 0xa0)
726 mc
= nv_rd32(dev
, NV50_PDISPLAY_SOR_MODE_CTRL_C(i
));
728 mc
= nv_rd32(dev
, NV90_PDISPLAY_SOR_MODE_CTRL_C(i
));
730 NV_DEBUG_KMS(dev
, "SOR-%d mc: 0x%08x\n", i
, mc
);
731 if (!(mc
& (1 << crtc
)))
734 switch ((mc
& 0x00000f00) >> 8) {
735 case 0: type
= OUTPUT_LVDS
; break;
736 case 1: type
= OUTPUT_TMDS
; break;
737 case 2: type
= OUTPUT_TMDS
; break;
738 case 5: type
= OUTPUT_TMDS
; break;
739 case 8: type
= OUTPUT_DP
; break;
740 case 9: type
= OUTPUT_DP
; break;
742 NV_ERROR(dev
, "invalid mc, SOR-%d: 0x%08x\n", i
, mc
);
749 /* There was no encoder to disable */
750 if (type
== OUTPUT_ANY
)
753 /* Disable the encoder */
754 for (i
= 0; i
< dev_priv
->vbios
.dcb
.entries
; i
++) {
755 struct dcb_entry
*dcb
= &dev_priv
->vbios
.dcb
.entry
[i
];
757 if (dcb
->type
== type
&& (dcb
->or & (1 << or))) {
758 nouveau_bios_run_display_table(dev
, dcb
, 0, -1);
759 dev_priv
->evo_irq
.dcb
= dcb
;
764 NV_ERROR(dev
, "no dcb for %d %d 0x%08x\n", or, type
, mc
);
766 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_CLK_UNK10
);
767 nv_wr32(dev
, 0x610030, 0x80000000);
771 nv50_display_unk20_dp_hack(struct drm_device
*dev
, struct dcb_entry
*dcb
)
773 int or = ffs(dcb
->or) - 1, link
= !(dcb
->dpconf
.sor
.link
& 1);
774 struct drm_encoder
*encoder
;
775 uint32_t tmp
, unk0
= 0, unk1
= 0;
777 if (dcb
->type
!= OUTPUT_DP
)
780 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
781 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
783 if (nv_encoder
->dcb
== dcb
) {
784 unk0
= nv_encoder
->dp
.unk0
;
785 unk1
= nv_encoder
->dp
.unk1
;
791 tmp
= nv_rd32(dev
, NV50_SOR_DP_CTRL(or, link
));
793 nv_wr32(dev
, NV50_SOR_DP_CTRL(or, link
), tmp
| unk0
);
795 tmp
= nv_rd32(dev
, NV50_SOR_DP_UNK128(or, link
));
797 nv_wr32(dev
, NV50_SOR_DP_UNK128(or, link
), tmp
| unk1
);
802 nv50_display_unk20_handler(struct drm_device
*dev
)
804 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
805 u32 unk30
= nv_rd32(dev
, 0x610030), tmp
, pclk
, script
, mc
;
806 struct dcb_entry
*dcb
;
807 int i
, crtc
, or, type
= OUTPUT_ANY
;
809 NV_DEBUG_KMS(dev
, "0x610030: 0x%08x\n", unk30
);
810 dcb
= dev_priv
->evo_irq
.dcb
;
812 nouveau_bios_run_display_table(dev
, dcb
, 0, -2);
813 dev_priv
->evo_irq
.dcb
= NULL
;
816 /* CRTC clock change requested? */
817 crtc
= ffs((unk30
& 0x00000600) >> 9) - 1;
819 pclk
= nv_rd32(dev
, NV50_PDISPLAY_CRTC_P(crtc
, CLOCK
));
822 nv50_crtc_set_clock(dev
, crtc
, pclk
);
824 tmp
= nv_rd32(dev
, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc
));
826 nv_wr32(dev
, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc
), tmp
);
829 /* Nothing needs to be done for the encoder */
830 crtc
= ffs((unk30
& 0x00000180) >> 7) - 1;
833 pclk
= nv_rd32(dev
, NV50_PDISPLAY_CRTC_P(crtc
, CLOCK
)) & 0x003fffff;
835 /* Find which encoder is connected to the CRTC */
836 for (i
= 0; type
== OUTPUT_ANY
&& i
< 3; i
++) {
837 mc
= nv_rd32(dev
, NV50_PDISPLAY_DAC_MODE_CTRL_P(i
));
838 NV_DEBUG_KMS(dev
, "DAC-%d mc: 0x%08x\n", i
, mc
);
839 if (!(mc
& (1 << crtc
)))
842 switch ((mc
& 0x00000f00) >> 8) {
843 case 0: type
= OUTPUT_ANALOG
; break;
844 case 1: type
= OUTPUT_TV
; break;
846 NV_ERROR(dev
, "invalid mc, DAC-%d: 0x%08x\n", i
, mc
);
853 for (i
= 0; type
== OUTPUT_ANY
&& i
< nv50_sor_nr(dev
); i
++) {
854 if (dev_priv
->chipset
< 0x90 ||
855 dev_priv
->chipset
== 0x92 ||
856 dev_priv
->chipset
== 0xa0)
857 mc
= nv_rd32(dev
, NV50_PDISPLAY_SOR_MODE_CTRL_P(i
));
859 mc
= nv_rd32(dev
, NV90_PDISPLAY_SOR_MODE_CTRL_P(i
));
861 NV_DEBUG_KMS(dev
, "SOR-%d mc: 0x%08x\n", i
, mc
);
862 if (!(mc
& (1 << crtc
)))
865 switch ((mc
& 0x00000f00) >> 8) {
866 case 0: type
= OUTPUT_LVDS
; break;
867 case 1: type
= OUTPUT_TMDS
; break;
868 case 2: type
= OUTPUT_TMDS
; break;
869 case 5: type
= OUTPUT_TMDS
; break;
870 case 8: type
= OUTPUT_DP
; break;
871 case 9: type
= OUTPUT_DP
; break;
873 NV_ERROR(dev
, "invalid mc, SOR-%d: 0x%08x\n", i
, mc
);
880 if (type
== OUTPUT_ANY
)
883 /* Enable the encoder */
884 for (i
= 0; i
< dev_priv
->vbios
.dcb
.entries
; i
++) {
885 dcb
= &dev_priv
->vbios
.dcb
.entry
[i
];
886 if (dcb
->type
== type
&& (dcb
->or & (1 << or)))
890 if (i
== dev_priv
->vbios
.dcb
.entries
) {
891 NV_ERROR(dev
, "no dcb for %d %d 0x%08x\n", or, type
, mc
);
895 script
= nv50_display_script_select(dev
, dcb
, mc
, pclk
);
896 nouveau_bios_run_display_table(dev
, dcb
, script
, pclk
);
898 nv50_display_unk20_dp_hack(dev
, dcb
);
900 if (dcb
->type
!= OUTPUT_ANALOG
) {
901 tmp
= nv_rd32(dev
, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
905 nv_wr32(dev
, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp
);
907 nv_wr32(dev
, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
910 dev_priv
->evo_irq
.dcb
= dcb
;
911 dev_priv
->evo_irq
.pclk
= pclk
;
912 dev_priv
->evo_irq
.script
= script
;
915 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_CLK_UNK20
);
916 nv_wr32(dev
, 0x610030, 0x80000000);
919 /* If programming a TMDS output on a SOR that can also be configured for
920 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
922 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
923 * the VBIOS scripts on at least one board I have only switch it off on
924 * link 0, causing a blank display if the output has previously been
925 * programmed for DisplayPort.
928 nv50_display_unk40_dp_set_tmds(struct drm_device
*dev
, struct dcb_entry
*dcb
)
930 int or = ffs(dcb
->or) - 1, link
= !(dcb
->dpconf
.sor
.link
& 1);
931 struct drm_encoder
*encoder
;
934 if (dcb
->type
!= OUTPUT_TMDS
)
937 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
938 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
940 if (nv_encoder
->dcb
->type
== OUTPUT_DP
&&
941 nv_encoder
->dcb
->or & (1 << or)) {
942 tmp
= nv_rd32(dev
, NV50_SOR_DP_CTRL(or, link
));
943 tmp
&= ~NV50_SOR_DP_CTRL_ENABLED
;
944 nv_wr32(dev
, NV50_SOR_DP_CTRL(or, link
), tmp
);
951 nv50_display_unk40_handler(struct drm_device
*dev
)
953 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
954 struct dcb_entry
*dcb
= dev_priv
->evo_irq
.dcb
;
955 u16 script
= dev_priv
->evo_irq
.script
;
956 u32 unk30
= nv_rd32(dev
, 0x610030), pclk
= dev_priv
->evo_irq
.pclk
;
958 NV_DEBUG_KMS(dev
, "0x610030: 0x%08x\n", unk30
);
959 dev_priv
->evo_irq
.dcb
= NULL
;
963 nouveau_bios_run_display_table(dev
, dcb
, script
, -pclk
);
964 nv50_display_unk40_dp_set_tmds(dev
, dcb
);
967 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_CLK_UNK40
);
968 nv_wr32(dev
, 0x610030, 0x80000000);
969 nv_wr32(dev
, 0x619494, nv_rd32(dev
, 0x619494) | 8);
973 nv50_display_irq_handler_bh(struct work_struct
*work
)
975 struct drm_nouveau_private
*dev_priv
=
976 container_of(work
, struct drm_nouveau_private
, irq_work
);
977 struct drm_device
*dev
= dev_priv
->dev
;
980 uint32_t intr0
= nv_rd32(dev
, NV50_PDISPLAY_INTR_0
);
981 uint32_t intr1
= nv_rd32(dev
, NV50_PDISPLAY_INTR_1
);
983 NV_DEBUG_KMS(dev
, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0
, intr1
);
985 if (intr1
& NV50_PDISPLAY_INTR_1_CLK_UNK10
)
986 nv50_display_unk10_handler(dev
);
988 if (intr1
& NV50_PDISPLAY_INTR_1_CLK_UNK20
)
989 nv50_display_unk20_handler(dev
);
991 if (intr1
& NV50_PDISPLAY_INTR_1_CLK_UNK40
)
992 nv50_display_unk40_handler(dev
);
997 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, 1);
1001 nv50_display_error_handler(struct drm_device
*dev
)
1003 uint32_t addr
, data
;
1005 nv_wr32(dev
, NV50_PDISPLAY_INTR_0
, 0x00010000);
1006 addr
= nv_rd32(dev
, NV50_PDISPLAY_TRAPPED_ADDR
);
1007 data
= nv_rd32(dev
, NV50_PDISPLAY_TRAPPED_DATA
);
1009 NV_ERROR(dev
, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
1010 0, addr
& 0xffc, data
, addr
>> 16, (addr
>> 12) & 0xf);
1012 nv_wr32(dev
, NV50_PDISPLAY_TRAPPED_ADDR
, 0x90000000);
1016 nv50_display_irq_hotplug_bh(struct work_struct
*work
)
1018 struct drm_nouveau_private
*dev_priv
=
1019 container_of(work
, struct drm_nouveau_private
, hpd_work
);
1020 struct drm_device
*dev
= dev_priv
->dev
;
1021 struct drm_connector
*connector
;
1022 const uint32_t gpio_reg
[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1023 uint32_t unplug_mask
, plug_mask
, change_mask
;
1024 uint32_t hpd0
, hpd1
;
1026 spin_lock_irq(&dev_priv
->hpd_state
.lock
);
1027 hpd0
= dev_priv
->hpd_state
.hpd0_bits
;
1028 dev_priv
->hpd_state
.hpd0_bits
= 0;
1029 hpd1
= dev_priv
->hpd_state
.hpd1_bits
;
1030 dev_priv
->hpd_state
.hpd1_bits
= 0;
1031 spin_unlock_irq(&dev_priv
->hpd_state
.lock
);
1033 hpd0
&= nv_rd32(dev
, 0xe050);
1034 if (dev_priv
->chipset
>= 0x90)
1035 hpd1
&= nv_rd32(dev
, 0xe070);
1037 plug_mask
= (hpd0
& 0x0000ffff) | (hpd1
<< 16);
1038 unplug_mask
= (hpd0
>> 16) | (hpd1
& 0xffff0000);
1039 change_mask
= plug_mask
| unplug_mask
;
1041 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1042 struct drm_encoder_helper_funcs
*helper
;
1043 struct nouveau_connector
*nv_connector
=
1044 nouveau_connector(connector
);
1045 struct nouveau_encoder
*nv_encoder
;
1046 struct dcb_gpio_entry
*gpio
;
1050 if (!nv_connector
->dcb
)
1053 gpio
= nouveau_bios_gpio_entry(dev
, nv_connector
->dcb
->gpio_tag
);
1054 if (!gpio
|| !(change_mask
& (1 << gpio
->line
)))
1057 reg
= nv_rd32(dev
, gpio_reg
[gpio
->line
>> 3]);
1058 plugged
= !!(reg
& (4 << ((gpio
->line
& 7) << 2)));
1059 NV_INFO(dev
, "%splugged %s\n", plugged
? "" : "un",
1060 drm_get_connector_name(connector
)) ;
1062 if (!connector
->encoder
|| !connector
->encoder
->crtc
||
1063 !connector
->encoder
->crtc
->enabled
)
1065 nv_encoder
= nouveau_encoder(connector
->encoder
);
1066 helper
= connector
->encoder
->helper_private
;
1068 if (nv_encoder
->dcb
->type
!= OUTPUT_DP
)
1072 helper
->dpms(connector
->encoder
, DRM_MODE_DPMS_ON
);
1074 helper
->dpms(connector
->encoder
, DRM_MODE_DPMS_OFF
);
1077 drm_helper_hpd_irq_event(dev
);
1081 nv50_display_irq_handler(struct drm_device
*dev
)
1083 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1084 uint32_t delayed
= 0;
1086 if (nv_rd32(dev
, NV50_PMC_INTR_0
) & NV50_PMC_INTR_0_HOTPLUG
) {
1087 uint32_t hpd0_bits
, hpd1_bits
= 0;
1089 hpd0_bits
= nv_rd32(dev
, 0xe054);
1090 nv_wr32(dev
, 0xe054, hpd0_bits
);
1092 if (dev_priv
->chipset
>= 0x90) {
1093 hpd1_bits
= nv_rd32(dev
, 0xe074);
1094 nv_wr32(dev
, 0xe074, hpd1_bits
);
1097 spin_lock(&dev_priv
->hpd_state
.lock
);
1098 dev_priv
->hpd_state
.hpd0_bits
|= hpd0_bits
;
1099 dev_priv
->hpd_state
.hpd1_bits
|= hpd1_bits
;
1100 spin_unlock(&dev_priv
->hpd_state
.lock
);
1102 queue_work(dev_priv
->wq
, &dev_priv
->hpd_work
);
1105 while (nv_rd32(dev
, NV50_PMC_INTR_0
) & NV50_PMC_INTR_0_DISPLAY
) {
1106 uint32_t intr0
= nv_rd32(dev
, NV50_PDISPLAY_INTR_0
);
1107 uint32_t intr1
= nv_rd32(dev
, NV50_PDISPLAY_INTR_1
);
1110 NV_DEBUG_KMS(dev
, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0
, intr1
);
1112 if (!intr0
&& !(intr1
& ~delayed
))
1115 if (intr0
& 0x00010000) {
1116 nv50_display_error_handler(dev
);
1117 intr0
&= ~0x00010000;
1120 if (intr1
& NV50_PDISPLAY_INTR_1_VBLANK_CRTC
) {
1121 nv50_display_vblank_handler(dev
, intr1
);
1122 intr1
&= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC
;
1125 clock
= (intr1
& (NV50_PDISPLAY_INTR_1_CLK_UNK10
|
1126 NV50_PDISPLAY_INTR_1_CLK_UNK20
|
1127 NV50_PDISPLAY_INTR_1_CLK_UNK40
));
1129 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, 0);
1130 if (!work_pending(&dev_priv
->irq_work
))
1131 queue_work(dev_priv
->wq
, &dev_priv
->irq_work
);
1137 NV_ERROR(dev
, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0
);
1138 nv_wr32(dev
, NV50_PDISPLAY_INTR_0
, intr0
);
1143 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1
);
1144 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, intr1
);