2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
28 #include "nv50_display.h"
29 #include "nouveau_crtc.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_fb.h"
33 #include "nouveau_fbcon.h"
34 #include "nouveau_ramht.h"
35 #include "drm_crtc_helper.h"
37 static void nv50_display_isr(struct drm_device
*);
38 static void nv50_display_bh(unsigned long);
41 nv50_sor_nr(struct drm_device
*dev
)
43 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
45 if (dev_priv
->chipset
< 0x90 ||
46 dev_priv
->chipset
== 0x92 ||
47 dev_priv
->chipset
== 0xa0)
54 nv50_display_active_crtcs(struct drm_device
*dev
)
56 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
60 if (dev_priv
->chipset
< 0x90 ||
61 dev_priv
->chipset
== 0x92 ||
62 dev_priv
->chipset
== 0xa0) {
63 for (i
= 0; i
< 2; i
++)
64 mask
|= nv_rd32(dev
, NV50_PDISPLAY_SOR_MODE_CTRL_C(i
));
66 for (i
= 0; i
< 4; i
++)
67 mask
|= nv_rd32(dev
, NV90_PDISPLAY_SOR_MODE_CTRL_C(i
));
70 for (i
= 0; i
< 3; i
++)
71 mask
|= nv_rd32(dev
, NV50_PDISPLAY_DAC_MODE_CTRL_C(i
));
77 evo_icmd(struct drm_device
*dev
, int ch
, u32 mthd
, u32 data
)
80 nv_mask(dev
, 0x610300 + (ch
* 0x08), 0x00000001, 0x00000001);
81 nv_wr32(dev
, 0x610304 + (ch
* 0x08), data
);
82 nv_wr32(dev
, 0x610300 + (ch
* 0x08), 0x80000001 | mthd
);
83 if (!nv_wait(dev
, 0x610300 + (ch
* 0x08), 0x80000000, 0x00000000))
85 if (ret
|| (nouveau_reg_debug
& NOUVEAU_REG_DEBUG_EVO
))
86 NV_INFO(dev
, "EvoPIO: %d 0x%04x 0x%08x\n", ch
, mthd
, data
);
87 nv_mask(dev
, 0x610300 + (ch
* 0x08), 0x00000001, 0x00000000);
92 nv50_display_early_init(struct drm_device
*dev
)
94 u32 ctrl
= nv_rd32(dev
, 0x610200);
97 /* check if master evo channel is already active, a good a sign as any
98 * that the display engine is in a weird state (hibernate/kexec), if
99 * it is, do our best to reset the display engine...
101 if ((ctrl
& 0x00000003) == 0x00000003) {
102 NV_INFO(dev
, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl
);
104 /* deactivate both heads first, PDISP will disappear forever
105 * (well, until you power cycle) on some boards as soon as
106 * PMC_ENABLE is hit unless they are..
108 for (i
= 0; i
< 2; i
++) {
109 evo_icmd(dev
, 0, 0x0880 + (i
* 0x400), 0x05000000);
110 evo_icmd(dev
, 0, 0x089c + (i
* 0x400), 0);
111 evo_icmd(dev
, 0, 0x0840 + (i
* 0x400), 0);
112 evo_icmd(dev
, 0, 0x0844 + (i
* 0x400), 0);
113 evo_icmd(dev
, 0, 0x085c + (i
* 0x400), 0);
114 evo_icmd(dev
, 0, 0x0874 + (i
* 0x400), 0);
116 evo_icmd(dev
, 0, 0x0080, 0);
119 nv_mask(dev
, 0x000200, 0x40000000, 0x00000000);
120 nv_mask(dev
, 0x000200, 0x40000000, 0x40000000);
127 nv50_display_late_takedown(struct drm_device
*dev
)
132 nv50_display_sync(struct drm_device
*dev
)
134 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
135 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
136 struct nv50_display
*disp
= nv50_display(dev
);
137 struct nouveau_channel
*evo
= disp
->master
;
141 ret
= RING_SPACE(evo
, 6);
143 BEGIN_NV04(evo
, 0, 0x0084, 1);
144 OUT_RING (evo
, 0x80000000);
145 BEGIN_NV04(evo
, 0, 0x0080, 1);
147 BEGIN_NV04(evo
, 0, 0x0084, 1);
148 OUT_RING (evo
, 0x00000000);
150 nv_wo32(disp
->ntfy
, 0x000, 0x00000000);
153 start
= ptimer
->read(dev
);
155 if (nv_ro32(disp
->ntfy
, 0x000))
157 } while (ptimer
->read(dev
) - start
< 2000000000ULL);
164 nv50_display_init(struct drm_device
*dev
)
166 struct nouveau_channel
*evo
;
170 NV_DEBUG_KMS(dev
, "\n");
172 nv_wr32(dev
, 0x00610184, nv_rd32(dev
, 0x00614004));
175 * I think the 0x006101XX range is some kind of main control area
176 * that enables things.
179 for (i
= 0; i
< 2; i
++) {
180 val
= nv_rd32(dev
, 0x00616100 + (i
* 0x800));
181 nv_wr32(dev
, 0x00610190 + (i
* 0x10), val
);
182 val
= nv_rd32(dev
, 0x00616104 + (i
* 0x800));
183 nv_wr32(dev
, 0x00610194 + (i
* 0x10), val
);
184 val
= nv_rd32(dev
, 0x00616108 + (i
* 0x800));
185 nv_wr32(dev
, 0x00610198 + (i
* 0x10), val
);
186 val
= nv_rd32(dev
, 0x0061610c + (i
* 0x800));
187 nv_wr32(dev
, 0x0061019c + (i
* 0x10), val
);
191 for (i
= 0; i
< 3; i
++) {
192 val
= nv_rd32(dev
, 0x0061a000 + (i
* 0x800));
193 nv_wr32(dev
, 0x006101d0 + (i
* 0x04), val
);
197 for (i
= 0; i
< nv50_sor_nr(dev
); i
++) {
198 val
= nv_rd32(dev
, 0x0061c000 + (i
* 0x800));
199 nv_wr32(dev
, 0x006101e0 + (i
* 0x04), val
);
203 for (i
= 0; i
< 3; i
++) {
204 val
= nv_rd32(dev
, 0x0061e000 + (i
* 0x800));
205 nv_wr32(dev
, 0x006101f0 + (i
* 0x04), val
);
208 for (i
= 0; i
< 3; i
++) {
209 nv_wr32(dev
, NV50_PDISPLAY_DAC_DPMS_CTRL(i
), 0x00550000 |
210 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING
);
211 nv_wr32(dev
, NV50_PDISPLAY_DAC_CLK_CTRL1(i
), 0x00000001);
214 /* The precise purpose is unknown, i suspect it has something to do
217 if (nv_rd32(dev
, NV50_PDISPLAY_INTR_1
) & 0x100) {
218 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, 0x100);
219 nv_wr32(dev
, 0x006194e8, nv_rd32(dev
, 0x006194e8) & ~1);
220 if (!nv_wait(dev
, 0x006194e8, 2, 0)) {
221 NV_ERROR(dev
, "timeout: (0x6194e8 & 2) != 0\n");
222 NV_ERROR(dev
, "0x6194e8 = 0x%08x\n",
223 nv_rd32(dev
, 0x6194e8));
228 for (i
= 0; i
< 2; i
++) {
229 nv_wr32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
), 0x2000);
230 if (!nv_wait(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
231 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS
, 0)) {
232 NV_ERROR(dev
, "timeout: CURSOR_CTRL2_STATUS == 0\n");
233 NV_ERROR(dev
, "CURSOR_CTRL2 = 0x%08x\n",
234 nv_rd32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
)));
238 nv_wr32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
239 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON
);
240 if (!nv_wait(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
241 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS
,
242 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE
)) {
243 NV_ERROR(dev
, "timeout: "
244 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i
);
245 NV_ERROR(dev
, "CURSOR_CTRL2(%d) = 0x%08x\n", i
,
246 nv_rd32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
)));
251 nv_wr32(dev
, NV50_PDISPLAY_PIO_CTRL
, 0x00000000);
252 nv_mask(dev
, NV50_PDISPLAY_INTR_0
, 0x00000000, 0x00000000);
253 nv_wr32(dev
, NV50_PDISPLAY_INTR_EN_0
, 0x00000000);
254 nv_mask(dev
, NV50_PDISPLAY_INTR_1
, 0x00000000, 0x00000000);
255 nv_wr32(dev
, NV50_PDISPLAY_INTR_EN_1
,
256 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10
|
257 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20
|
258 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40
);
260 ret
= nv50_evo_init(dev
);
263 evo
= nv50_display(dev
)->master
;
265 nv_wr32(dev
, NV50_PDISPLAY_OBJECTS
, (evo
->ramin
->vinst
>> 8) | 9);
267 ret
= RING_SPACE(evo
, 3);
270 BEGIN_NV04(evo
, 0, NV50_EVO_UNK84
, 2);
271 OUT_RING (evo
, NV50_EVO_UNK84_NOTIFY_DISABLED
);
272 OUT_RING (evo
, NvEvoSync
);
274 return nv50_display_sync(dev
);
278 nv50_display_fini(struct drm_device
*dev
)
280 struct nv50_display
*disp
= nv50_display(dev
);
281 struct nouveau_channel
*evo
= disp
->master
;
282 struct drm_crtc
*drm_crtc
;
285 NV_DEBUG_KMS(dev
, "\n");
287 list_for_each_entry(drm_crtc
, &dev
->mode_config
.crtc_list
, head
) {
288 struct nouveau_crtc
*crtc
= nouveau_crtc(drm_crtc
);
290 nv50_crtc_blank(crtc
, true);
293 ret
= RING_SPACE(evo
, 2);
295 BEGIN_NV04(evo
, 0, NV50_EVO_UPDATE
, 1);
300 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
303 list_for_each_entry(drm_crtc
, &dev
->mode_config
.crtc_list
, head
) {
304 struct nouveau_crtc
*crtc
= nouveau_crtc(drm_crtc
);
305 uint32_t mask
= NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc
->index
);
307 if (!crtc
->base
.enabled
)
310 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, mask
);
311 if (!nv_wait(dev
, NV50_PDISPLAY_INTR_1
, mask
, mask
)) {
312 NV_ERROR(dev
, "timeout: (0x610024 & 0x%08x) == "
313 "0x%08x\n", mask
, mask
);
314 NV_ERROR(dev
, "0x610024 = 0x%08x\n",
315 nv_rd32(dev
, NV50_PDISPLAY_INTR_1
));
319 for (i
= 0; i
< 2; i
++) {
320 nv_wr32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
), 0);
321 if (!nv_wait(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
),
322 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS
, 0)) {
323 NV_ERROR(dev
, "timeout: CURSOR_CTRL2_STATUS == 0\n");
324 NV_ERROR(dev
, "CURSOR_CTRL2 = 0x%08x\n",
325 nv_rd32(dev
, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i
)));
331 for (i
= 0; i
< 3; i
++) {
332 if (!nv_wait(dev
, NV50_PDISPLAY_SOR_DPMS_STATE(i
),
333 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT
, 0)) {
334 NV_ERROR(dev
, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i
);
335 NV_ERROR(dev
, "SOR_DPMS_STATE(%d) = 0x%08x\n", i
,
336 nv_rd32(dev
, NV50_PDISPLAY_SOR_DPMS_STATE(i
)));
340 /* disable interrupts. */
341 nv_wr32(dev
, NV50_PDISPLAY_INTR_EN_1
, 0x00000000);
345 nv50_display_create(struct drm_device
*dev
)
347 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
348 struct dcb_table
*dcb
= &dev_priv
->vbios
.dcb
;
349 struct drm_connector
*connector
, *ct
;
350 struct nv50_display
*priv
;
353 NV_DEBUG_KMS(dev
, "\n");
355 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
358 dev_priv
->engine
.display
.priv
= priv
;
360 /* Create CRTC objects */
361 for (i
= 0; i
< 2; i
++) {
362 ret
= nv50_crtc_create(dev
, i
);
367 /* We setup the encoders from the BIOS table */
368 for (i
= 0 ; i
< dcb
->entries
; i
++) {
369 struct dcb_entry
*entry
= &dcb
->entry
[i
];
371 if (entry
->location
!= DCB_LOC_ON_CHIP
) {
372 NV_WARN(dev
, "Off-chip encoder %d/%d unsupported\n",
373 entry
->type
, ffs(entry
->or) - 1);
377 connector
= nouveau_connector_create(dev
, entry
->connector
);
378 if (IS_ERR(connector
))
381 switch (entry
->type
) {
385 nv50_sor_create(connector
, entry
);
388 nv50_dac_create(connector
, entry
);
391 NV_WARN(dev
, "DCB encoder %d unknown\n", entry
->type
);
396 list_for_each_entry_safe(connector
, ct
,
397 &dev
->mode_config
.connector_list
, head
) {
398 if (!connector
->encoder_ids
[0]) {
399 NV_WARN(dev
, "%s has no encoders, removing\n",
400 drm_get_connector_name(connector
));
401 connector
->funcs
->destroy(connector
);
405 tasklet_init(&priv
->tasklet
, nv50_display_bh
, (unsigned long)dev
);
406 nouveau_irq_register(dev
, 26, nv50_display_isr
);
408 ret
= nv50_evo_create(dev
);
410 nv50_display_destroy(dev
);
418 nv50_display_destroy(struct drm_device
*dev
)
420 struct nv50_display
*disp
= nv50_display(dev
);
422 NV_DEBUG_KMS(dev
, "\n");
424 nv50_evo_destroy(dev
);
425 nouveau_irq_unregister(dev
, 26);
430 nv50_display_flip_stop(struct drm_crtc
*crtc
)
432 struct nv50_display
*disp
= nv50_display(crtc
->dev
);
433 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
434 struct nv50_display_crtc
*dispc
= &disp
->crtc
[nv_crtc
->index
];
435 struct nouveau_channel
*evo
= dispc
->sync
;
438 ret
= RING_SPACE(evo
, 8);
444 BEGIN_NV04(evo
, 0, 0x0084, 1);
445 OUT_RING (evo
, 0x00000000);
446 BEGIN_NV04(evo
, 0, 0x0094, 1);
447 OUT_RING (evo
, 0x00000000);
448 BEGIN_NV04(evo
, 0, 0x00c0, 1);
449 OUT_RING (evo
, 0x00000000);
450 BEGIN_NV04(evo
, 0, 0x0080, 1);
451 OUT_RING (evo
, 0x00000000);
456 nv50_display_flip_next(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
457 struct nouveau_channel
*chan
)
459 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
460 struct nouveau_framebuffer
*nv_fb
= nouveau_framebuffer(fb
);
461 struct nv50_display
*disp
= nv50_display(crtc
->dev
);
462 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
463 struct nv50_display_crtc
*dispc
= &disp
->crtc
[nv_crtc
->index
];
464 struct nouveau_channel
*evo
= dispc
->sync
;
467 ret
= RING_SPACE(evo
, chan
? 25 : 27);
471 /* synchronise with the rendering channel, if necessary */
473 ret
= RING_SPACE(chan
, 10);
479 if (dev_priv
->chipset
< 0xc0) {
480 BEGIN_NV04(chan
, 0, 0x0060, 2);
481 OUT_RING (chan
, NvEvoSema0
+ nv_crtc
->index
);
482 OUT_RING (chan
, dispc
->sem
.offset
);
483 BEGIN_NV04(chan
, 0, 0x006c, 1);
484 OUT_RING (chan
, 0xf00d0000 | dispc
->sem
.value
);
485 BEGIN_NV04(chan
, 0, 0x0064, 2);
486 OUT_RING (chan
, dispc
->sem
.offset
^ 0x10);
487 OUT_RING (chan
, 0x74b1e000);
488 BEGIN_NV04(chan
, 0, 0x0060, 1);
489 if (dev_priv
->chipset
< 0x84)
490 OUT_RING (chan
, NvSema
);
492 OUT_RING (chan
, chan
->vram_handle
);
494 u64 offset
= chan
->dispc_vma
[nv_crtc
->index
].offset
;
495 offset
+= dispc
->sem
.offset
;
496 BEGIN_NVC0(chan
, 0, 0x0010, 4);
497 OUT_RING (chan
, upper_32_bits(offset
));
498 OUT_RING (chan
, lower_32_bits(offset
));
499 OUT_RING (chan
, 0xf00d0000 | dispc
->sem
.value
);
500 OUT_RING (chan
, 0x1002);
501 BEGIN_NVC0(chan
, 0, 0x0010, 4);
502 OUT_RING (chan
, upper_32_bits(offset
));
503 OUT_RING (chan
, lower_32_bits(offset
^ 0x10));
504 OUT_RING (chan
, 0x74b1e000);
505 OUT_RING (chan
, 0x1001);
509 nouveau_bo_wr32(dispc
->sem
.bo
, dispc
->sem
.offset
/ 4,
510 0xf00d0000 | dispc
->sem
.value
);
513 /* queue the flip on the crtc's "display sync" channel */
514 BEGIN_NV04(evo
, 0, 0x0100, 1);
515 OUT_RING (evo
, 0xfffe0000);
517 BEGIN_NV04(evo
, 0, 0x0084, 1);
518 OUT_RING (evo
, 0x00000100);
520 BEGIN_NV04(evo
, 0, 0x0084, 1);
521 OUT_RING (evo
, 0x00000010);
522 /* allows gamma somehow, PDISP will bitch at you if
523 * you don't wait for vblank before changing this..
525 BEGIN_NV04(evo
, 0, 0x00e0, 1);
526 OUT_RING (evo
, 0x40000000);
528 BEGIN_NV04(evo
, 0, 0x0088, 4);
529 OUT_RING (evo
, dispc
->sem
.offset
);
530 OUT_RING (evo
, 0xf00d0000 | dispc
->sem
.value
);
531 OUT_RING (evo
, 0x74b1e000);
532 OUT_RING (evo
, NvEvoSync
);
533 BEGIN_NV04(evo
, 0, 0x00a0, 2);
534 OUT_RING (evo
, 0x00000000);
535 OUT_RING (evo
, 0x00000000);
536 BEGIN_NV04(evo
, 0, 0x00c0, 1);
537 OUT_RING (evo
, nv_fb
->r_dma
);
538 BEGIN_NV04(evo
, 0, 0x0110, 2);
539 OUT_RING (evo
, 0x00000000);
540 OUT_RING (evo
, 0x00000000);
541 BEGIN_NV04(evo
, 0, 0x0800, 5);
542 OUT_RING (evo
, nv_fb
->nvbo
->bo
.offset
>> 8);
544 OUT_RING (evo
, (fb
->height
<< 16) | fb
->width
);
545 OUT_RING (evo
, nv_fb
->r_pitch
);
546 OUT_RING (evo
, nv_fb
->r_format
);
547 BEGIN_NV04(evo
, 0, 0x0080, 1);
548 OUT_RING (evo
, 0x00000000);
551 dispc
->sem
.offset
^= 0x10;
557 nv50_display_script_select(struct drm_device
*dev
, struct dcb_entry
*dcb
,
560 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
561 struct nouveau_connector
*nv_connector
= NULL
;
562 struct drm_encoder
*encoder
;
563 struct nvbios
*bios
= &dev_priv
->vbios
;
566 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
567 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
569 if (nv_encoder
->dcb
!= dcb
)
572 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
576 or = ffs(dcb
->or) - 1;
579 script
= (mc
>> 8) & 0xf;
580 if (bios
->fp_no_ddc
) {
581 if (bios
->fp
.dual_link
)
583 if (bios
->fp
.if_is_24bit
)
586 /* determine number of lvds links */
587 if (nv_connector
&& nv_connector
->edid
&&
588 nv_connector
->type
== DCB_CONNECTOR_LVDS_SPWG
) {
589 /* http://www.spwg.org */
590 if (((u8
*)nv_connector
->edid
)[121] == 2)
593 if (pxclk
>= bios
->fp
.duallink_transition_clk
) {
597 /* determine panel depth */
598 if (script
& 0x0100) {
599 if (bios
->fp
.strapless_is_24bit
& 2)
602 if (bios
->fp
.strapless_is_24bit
& 1)
606 if (nv_connector
&& nv_connector
->edid
&&
607 (nv_connector
->edid
->revision
>= 4) &&
608 (nv_connector
->edid
->input
& 0x70) >= 0x20)
612 if (nouveau_uscript_lvds
>= 0) {
613 NV_INFO(dev
, "override script 0x%04x with 0x%04x "
614 "for output LVDS-%d\n", script
,
615 nouveau_uscript_lvds
, or);
616 script
= nouveau_uscript_lvds
;
620 script
= (mc
>> 8) & 0xf;
624 if (nouveau_uscript_tmds
>= 0) {
625 NV_INFO(dev
, "override script 0x%04x with 0x%04x "
626 "for output TMDS-%d\n", script
,
627 nouveau_uscript_tmds
, or);
628 script
= nouveau_uscript_tmds
;
632 script
= (mc
>> 8) & 0xf;
638 NV_ERROR(dev
, "modeset on unsupported output type!\n");
646 nv50_display_vblank_crtc_handler(struct drm_device
*dev
, int crtc
)
648 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
649 struct nouveau_channel
*chan
, *tmp
;
651 list_for_each_entry_safe(chan
, tmp
, &dev_priv
->vbl_waiting
,
653 if (chan
->nvsw
.vblsem_head
!= crtc
)
656 nouveau_bo_wr32(chan
->notifier_bo
, chan
->nvsw
.vblsem_offset
,
657 chan
->nvsw
.vblsem_rval
);
658 list_del(&chan
->nvsw
.vbl_wait
);
659 drm_vblank_put(dev
, crtc
);
662 drm_handle_vblank(dev
, crtc
);
666 nv50_display_vblank_handler(struct drm_device
*dev
, uint32_t intr
)
668 if (intr
& NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0
)
669 nv50_display_vblank_crtc_handler(dev
, 0);
671 if (intr
& NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1
)
672 nv50_display_vblank_crtc_handler(dev
, 1);
674 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_VBLANK_CRTC
);
678 nv50_display_unk10_handler(struct drm_device
*dev
)
680 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
681 struct nv50_display
*disp
= nv50_display(dev
);
682 u32 unk30
= nv_rd32(dev
, 0x610030), mc
;
683 int i
, crtc
, or = 0, type
= OUTPUT_ANY
;
685 NV_DEBUG_KMS(dev
, "0x610030: 0x%08x\n", unk30
);
686 disp
->irq
.dcb
= NULL
;
688 nv_wr32(dev
, 0x619494, nv_rd32(dev
, 0x619494) & ~8);
690 /* Determine which CRTC we're dealing with, only 1 ever will be
691 * signalled at the same time with the current nouveau code.
693 crtc
= ffs((unk30
& 0x00000060) >> 5) - 1;
697 /* Nothing needs to be done for the encoder */
698 crtc
= ffs((unk30
& 0x00000180) >> 7) - 1;
702 /* Find which encoder was connected to the CRTC */
703 for (i
= 0; type
== OUTPUT_ANY
&& i
< 3; i
++) {
704 mc
= nv_rd32(dev
, NV50_PDISPLAY_DAC_MODE_CTRL_C(i
));
705 NV_DEBUG_KMS(dev
, "DAC-%d mc: 0x%08x\n", i
, mc
);
706 if (!(mc
& (1 << crtc
)))
709 switch ((mc
& 0x00000f00) >> 8) {
710 case 0: type
= OUTPUT_ANALOG
; break;
711 case 1: type
= OUTPUT_TV
; break;
713 NV_ERROR(dev
, "invalid mc, DAC-%d: 0x%08x\n", i
, mc
);
720 for (i
= 0; type
== OUTPUT_ANY
&& i
< nv50_sor_nr(dev
); i
++) {
721 if (dev_priv
->chipset
< 0x90 ||
722 dev_priv
->chipset
== 0x92 ||
723 dev_priv
->chipset
== 0xa0)
724 mc
= nv_rd32(dev
, NV50_PDISPLAY_SOR_MODE_CTRL_C(i
));
726 mc
= nv_rd32(dev
, NV90_PDISPLAY_SOR_MODE_CTRL_C(i
));
728 NV_DEBUG_KMS(dev
, "SOR-%d mc: 0x%08x\n", i
, mc
);
729 if (!(mc
& (1 << crtc
)))
732 switch ((mc
& 0x00000f00) >> 8) {
733 case 0: type
= OUTPUT_LVDS
; break;
734 case 1: type
= OUTPUT_TMDS
; break;
735 case 2: type
= OUTPUT_TMDS
; break;
736 case 5: type
= OUTPUT_TMDS
; break;
737 case 8: type
= OUTPUT_DP
; break;
738 case 9: type
= OUTPUT_DP
; break;
740 NV_ERROR(dev
, "invalid mc, SOR-%d: 0x%08x\n", i
, mc
);
747 /* There was no encoder to disable */
748 if (type
== OUTPUT_ANY
)
751 /* Disable the encoder */
752 for (i
= 0; i
< dev_priv
->vbios
.dcb
.entries
; i
++) {
753 struct dcb_entry
*dcb
= &dev_priv
->vbios
.dcb
.entry
[i
];
755 if (dcb
->type
== type
&& (dcb
->or & (1 << or))) {
756 nouveau_bios_run_display_table(dev
, 0, -1, dcb
, -1);
762 NV_ERROR(dev
, "no dcb for %d %d 0x%08x\n", or, type
, mc
);
764 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_CLK_UNK10
);
765 nv_wr32(dev
, 0x610030, 0x80000000);
769 nv50_display_unk20_handler(struct drm_device
*dev
)
771 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
772 struct nv50_display
*disp
= nv50_display(dev
);
773 u32 unk30
= nv_rd32(dev
, 0x610030), tmp
, pclk
, script
, mc
= 0;
774 struct dcb_entry
*dcb
;
775 int i
, crtc
, or = 0, type
= OUTPUT_ANY
;
777 NV_DEBUG_KMS(dev
, "0x610030: 0x%08x\n", unk30
);
780 nouveau_bios_run_display_table(dev
, 0, -2, dcb
, -1);
781 disp
->irq
.dcb
= NULL
;
784 /* CRTC clock change requested? */
785 crtc
= ffs((unk30
& 0x00000600) >> 9) - 1;
787 pclk
= nv_rd32(dev
, NV50_PDISPLAY_CRTC_P(crtc
, CLOCK
));
790 nv50_crtc_set_clock(dev
, crtc
, pclk
);
792 tmp
= nv_rd32(dev
, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc
));
794 nv_wr32(dev
, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc
), tmp
);
797 /* Nothing needs to be done for the encoder */
798 crtc
= ffs((unk30
& 0x00000180) >> 7) - 1;
801 pclk
= nv_rd32(dev
, NV50_PDISPLAY_CRTC_P(crtc
, CLOCK
)) & 0x003fffff;
803 /* Find which encoder is connected to the CRTC */
804 for (i
= 0; type
== OUTPUT_ANY
&& i
< 3; i
++) {
805 mc
= nv_rd32(dev
, NV50_PDISPLAY_DAC_MODE_CTRL_P(i
));
806 NV_DEBUG_KMS(dev
, "DAC-%d mc: 0x%08x\n", i
, mc
);
807 if (!(mc
& (1 << crtc
)))
810 switch ((mc
& 0x00000f00) >> 8) {
811 case 0: type
= OUTPUT_ANALOG
; break;
812 case 1: type
= OUTPUT_TV
; break;
814 NV_ERROR(dev
, "invalid mc, DAC-%d: 0x%08x\n", i
, mc
);
821 for (i
= 0; type
== OUTPUT_ANY
&& i
< nv50_sor_nr(dev
); i
++) {
822 if (dev_priv
->chipset
< 0x90 ||
823 dev_priv
->chipset
== 0x92 ||
824 dev_priv
->chipset
== 0xa0)
825 mc
= nv_rd32(dev
, NV50_PDISPLAY_SOR_MODE_CTRL_P(i
));
827 mc
= nv_rd32(dev
, NV90_PDISPLAY_SOR_MODE_CTRL_P(i
));
829 NV_DEBUG_KMS(dev
, "SOR-%d mc: 0x%08x\n", i
, mc
);
830 if (!(mc
& (1 << crtc
)))
833 switch ((mc
& 0x00000f00) >> 8) {
834 case 0: type
= OUTPUT_LVDS
; break;
835 case 1: type
= OUTPUT_TMDS
; break;
836 case 2: type
= OUTPUT_TMDS
; break;
837 case 5: type
= OUTPUT_TMDS
; break;
838 case 8: type
= OUTPUT_DP
; break;
839 case 9: type
= OUTPUT_DP
; break;
841 NV_ERROR(dev
, "invalid mc, SOR-%d: 0x%08x\n", i
, mc
);
848 if (type
== OUTPUT_ANY
)
851 /* Enable the encoder */
852 for (i
= 0; i
< dev_priv
->vbios
.dcb
.entries
; i
++) {
853 dcb
= &dev_priv
->vbios
.dcb
.entry
[i
];
854 if (dcb
->type
== type
&& (dcb
->or & (1 << or)))
858 if (i
== dev_priv
->vbios
.dcb
.entries
) {
859 NV_ERROR(dev
, "no dcb for %d %d 0x%08x\n", or, type
, mc
);
863 script
= nv50_display_script_select(dev
, dcb
, mc
, pclk
);
864 nouveau_bios_run_display_table(dev
, script
, pclk
, dcb
, -1);
866 if (type
== OUTPUT_DP
) {
867 int link
= !(dcb
->dpconf
.sor
.link
& 1);
868 if ((mc
& 0x000f0000) == 0x00020000)
869 nv50_sor_dp_calc_tu(dev
, or, link
, pclk
, 18);
871 nv50_sor_dp_calc_tu(dev
, or, link
, pclk
, 24);
874 if (dcb
->type
!= OUTPUT_ANALOG
) {
875 tmp
= nv_rd32(dev
, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
879 nv_wr32(dev
, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp
);
881 nv_wr32(dev
, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
885 disp
->irq
.pclk
= pclk
;
886 disp
->irq
.script
= script
;
889 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_CLK_UNK20
);
890 nv_wr32(dev
, 0x610030, 0x80000000);
893 /* If programming a TMDS output on a SOR that can also be configured for
894 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
896 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
897 * the VBIOS scripts on at least one board I have only switch it off on
898 * link 0, causing a blank display if the output has previously been
899 * programmed for DisplayPort.
902 nv50_display_unk40_dp_set_tmds(struct drm_device
*dev
, struct dcb_entry
*dcb
)
904 int or = ffs(dcb
->or) - 1, link
= !(dcb
->dpconf
.sor
.link
& 1);
905 struct drm_encoder
*encoder
;
908 if (dcb
->type
!= OUTPUT_TMDS
)
911 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
912 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
914 if (nv_encoder
->dcb
->type
== OUTPUT_DP
&&
915 nv_encoder
->dcb
->or & (1 << or)) {
916 tmp
= nv_rd32(dev
, NV50_SOR_DP_CTRL(or, link
));
917 tmp
&= ~NV50_SOR_DP_CTRL_ENABLED
;
918 nv_wr32(dev
, NV50_SOR_DP_CTRL(or, link
), tmp
);
925 nv50_display_unk40_handler(struct drm_device
*dev
)
927 struct nv50_display
*disp
= nv50_display(dev
);
928 struct dcb_entry
*dcb
= disp
->irq
.dcb
;
929 u16 script
= disp
->irq
.script
;
930 u32 unk30
= nv_rd32(dev
, 0x610030), pclk
= disp
->irq
.pclk
;
932 NV_DEBUG_KMS(dev
, "0x610030: 0x%08x\n", unk30
);
933 disp
->irq
.dcb
= NULL
;
937 nouveau_bios_run_display_table(dev
, script
, -pclk
, dcb
, -1);
938 nv50_display_unk40_dp_set_tmds(dev
, dcb
);
941 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, NV50_PDISPLAY_INTR_1_CLK_UNK40
);
942 nv_wr32(dev
, 0x610030, 0x80000000);
943 nv_wr32(dev
, 0x619494, nv_rd32(dev
, 0x619494) | 8);
947 nv50_display_bh(unsigned long data
)
949 struct drm_device
*dev
= (struct drm_device
*)data
;
952 uint32_t intr0
= nv_rd32(dev
, NV50_PDISPLAY_INTR_0
);
953 uint32_t intr1
= nv_rd32(dev
, NV50_PDISPLAY_INTR_1
);
955 NV_DEBUG_KMS(dev
, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0
, intr1
);
957 if (intr1
& NV50_PDISPLAY_INTR_1_CLK_UNK10
)
958 nv50_display_unk10_handler(dev
);
960 if (intr1
& NV50_PDISPLAY_INTR_1_CLK_UNK20
)
961 nv50_display_unk20_handler(dev
);
963 if (intr1
& NV50_PDISPLAY_INTR_1_CLK_UNK40
)
964 nv50_display_unk40_handler(dev
);
969 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, 1);
973 nv50_display_error_handler(struct drm_device
*dev
)
975 u32 channels
= (nv_rd32(dev
, NV50_PDISPLAY_INTR_0
) & 0x001f0000) >> 16;
979 for (chid
= 0; chid
< 5; chid
++) {
980 if (!(channels
& (1 << chid
)))
983 nv_wr32(dev
, NV50_PDISPLAY_INTR_0
, 0x00010000 << chid
);
984 addr
= nv_rd32(dev
, NV50_PDISPLAY_TRAPPED_ADDR(chid
));
985 data
= nv_rd32(dev
, NV50_PDISPLAY_TRAPPED_DATA(chid
));
986 NV_ERROR(dev
, "EvoCh %d Mthd 0x%04x Data 0x%08x "
987 "(0x%04x 0x%02x)\n", chid
,
988 addr
& 0xffc, data
, addr
>> 16, (addr
>> 12) & 0xf);
990 nv_wr32(dev
, NV50_PDISPLAY_TRAPPED_ADDR(chid
), 0x90000000);
995 nv50_display_isr(struct drm_device
*dev
)
997 struct nv50_display
*disp
= nv50_display(dev
);
998 uint32_t delayed
= 0;
1000 while (nv_rd32(dev
, NV50_PMC_INTR_0
) & NV50_PMC_INTR_0_DISPLAY
) {
1001 uint32_t intr0
= nv_rd32(dev
, NV50_PDISPLAY_INTR_0
);
1002 uint32_t intr1
= nv_rd32(dev
, NV50_PDISPLAY_INTR_1
);
1005 NV_DEBUG_KMS(dev
, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0
, intr1
);
1007 if (!intr0
&& !(intr1
& ~delayed
))
1010 if (intr0
& 0x001f0000) {
1011 nv50_display_error_handler(dev
);
1012 intr0
&= ~0x001f0000;
1015 if (intr1
& NV50_PDISPLAY_INTR_1_VBLANK_CRTC
) {
1016 nv50_display_vblank_handler(dev
, intr1
);
1017 intr1
&= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC
;
1020 clock
= (intr1
& (NV50_PDISPLAY_INTR_1_CLK_UNK10
|
1021 NV50_PDISPLAY_INTR_1_CLK_UNK20
|
1022 NV50_PDISPLAY_INTR_1_CLK_UNK40
));
1024 nv_wr32(dev
, NV03_PMC_INTR_EN_0
, 0);
1025 tasklet_schedule(&disp
->tasklet
);
1031 NV_ERROR(dev
, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0
);
1032 nv_wr32(dev
, NV50_PDISPLAY_INTR_0
, intr0
);
1037 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1
);
1038 nv_wr32(dev
, NV50_PDISPLAY_INTR_1
, intr1
);